From fad9c7e35cb5bba78ec0f4b0141a4cf3b6c9b05f Mon Sep 17 00:00:00 2001 From: Andrei Vlad LUTAS Date: Tue, 20 Feb 2024 13:39:22 +0200 Subject: [PATCH] BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. --- .gitignore | 8 + CHANGELOG.md | 54 + CMakeLists.txt | 88 +- Dockerfile.fuzzing | 118 + README.md | 16 +- bddisasm.sln | 12 +- bddisasm/Makefile | 2 +- bddisasm/bddisasm.vcxproj | 45 +- bddisasm/bddisasm.vcxproj.filters | 96 +- bddisasm/{crt.c => bddisasm_crt.c} | 2 +- bddisasm/{bddisasm.c => bdx86_decoder.c} | 2470 +- bddisasm/{bdformat.c => bdx86_formatter.c} | 285 +- bddisasm/{bdhelpers.c => bdx86_helpers.c} | 2 +- bddisasm/include/{nd_crt.h => bddisasm_crt.h} | 2 +- bddisasm/include/bdx86_instructions.h | 114205 +++++++++++++++ .../{mnemonics.h => bdx86_mnemonics.h} | 193 +- .../include/{prefixes.h => bdx86_prefixes.h} | 8 +- bddisasm/include/bdx86_table_evex.h | 38359 +++++ bddisasm/include/bdx86_table_root.h | 16820 +++ bddisasm/include/bdx86_table_vex.h | 13464 ++ bddisasm/include/bdx86_table_xop.h | 1557 + .../{tabledefs.h => bdx86_tabledefs.h} | 265 +- bddisasm/include/instructions.h | 46975 ------ bddisasm/include/table_evex.h | 15250 -- bddisasm/include/table_root.h | 16694 --- bddisasm/include/table_vex.h | 13047 -- bddisasm/include/table_xop.h | 1550 - bddisasm_test/README.md | 2 +- bddisasm_test/x86/apx/apx1_64.result | 102913 +++++++++++++ bddisasm_test/x86/apx/apx1_64.test | Bin 0 -> 32309 bytes bddisasm_test/x86/apx/apx2_64.result | 224 + bddisasm_test/x86/apx/apx2_64.test | 1 + bddisasm_test/x86/apx/evex_bad_64_skip.asm | 16 + bddisasm_test/x86/apx/evex_bad_64_skip.result | 7 + bddisasm_test/x86/apx/evex_bad_64_skip.test | Bin 0 -> 112 bytes bddisasm_test/x86/apx/rex2_bad_64_skip.asm | 25 + bddisasm_test/x86/apx/rex2_bad_64_skip.result | 14 + bddisasm_test/x86/apx/rex2_bad_64_skip.test | Bin 0 -> 224 bytes bddisasm_test/x86/apx/rex2_valid_64.asm | 32 + bddisasm_test/x86/apx/rex2_valid_64.result | 301 + bddisasm_test/x86/apx/rex2_valid_64.test | Bin 0 -> 71 bytes .../x86/cmpccxadd/cmpccxadd_64.result | 64 +- bddisasm_test/x86/fred/fred_64.result | 10 +- bddisasm_test/x86/special/invalid_64_skip.asm | 4 +- .../x86/special/invalid_64_skip.result | 9 +- .../x86/special/invalid_64_skip.test | 2 +- bddisasm_test/x86/usermsr/rex2_valid_64.asm | 11 + .../x86/usermsr/rex2_valid_64.result | 68 + bddisasm_test/x86/usermsr/rex2_valid_64.test | 1 + bdshemu/Makefile | 5 +- bdshemu/bdshemu.c | 3208 +- bdshemu/bdshemu.vcxproj | 5 +- bdshemu/bdshemu.vcxproj.filters | 30 +- bdshemu/bdshemu_x86.c | 3568 + bdshemu/include/bdshemu_common.h | 172 + bdshemu_fuzz/CMakeLists.txt | 20 + bdshemu_fuzz/README.md | 49 - bdshemu_fuzz/bdshemu_fuzzer.c | 70 +- bdshemu_fuzz/fuzzing_image_entrypoint.sh | 21 + bdshemu_test/README.md | 2 +- bdshemu_test/bdshemu_test.zip | Bin 97496 -> 0 bytes bdshemu_test/test_all.py | 234 +- bdshemu_test/x86/bdshemu_test_x86.zip | Bin 0 -> 164049 bytes bindings/pybddisasm/pybddisasm/pybddisasm.c | 2 +- bindings/pybddisasm/pybddisasm/pybddisasm.i | 15 +- bindings/pybddisasm/setup.py | 13 +- bindings/rsbddisasm/Cargo.toml | 3 + bindings/rsbddisasm/bddisasm-sys/Cargo.toml | 2 +- bindings/rsbddisasm/bddisasm-sys/build.rs | 8 +- bindings/rsbddisasm/bddisasm-sys/src/lib.rs | 11 +- bindings/rsbddisasm/bddisasm/CHANGELOG.md | 18 +- bindings/rsbddisasm/bddisasm/Cargo.toml | 6 +- bindings/rsbddisasm/bddisasm/src/cpu_modes.rs | 4 + .../rsbddisasm/bddisasm/src/decode_error.rs | 9 +- .../bddisasm/src/decoded_instruction.rs | 328 +- bindings/rsbddisasm/bddisasm/src/decoder.rs | 24 +- bindings/rsbddisasm/bddisasm/src/fpu_flags.rs | 2 + .../bddisasm/src/instruction_category.rs | 7 +- bindings/rsbddisasm/bddisasm/src/isa_set.rs | 9 +- bindings/rsbddisasm/bddisasm/src/lib.rs | 7 +- bindings/rsbddisasm/bddisasm/src/mnemonic.rs | 69 +- bindings/rsbddisasm/bddisasm/src/operand.rs | 156 +- bindings/rsbddisasm/update_ins.py | 198 + disasmtool/CMakeLists.txt | 8 +- disasmtool/disasmtool.c | 803 +- disasmtool/disasmtool.h | 38 +- disasmtool_lix/CMakeLists.txt | 65 - disasmtool_lix/Makefile | 39 - disasmtool_lix/disasm.hpp | 66 - disasmtool_lix/disasmtool.cpp | 927 - disasmtool_lix/dumpers.cpp | 2119 - disasmtool_lix/dumpers.cpp.bak | 1933 - disasmtool_lix/external/argparse.h | 566 - disasmtool_lix/rapidjson.cpp | 1209 - inc/bddisasm.h | 1662 +- inc/{disasmstatus.h => bddisasm_status.h} | 7 +- inc/{disasmtypes.h => bddisasm_types.h} | 34 +- inc/bddisasm_version.h | 16 + inc/bdshemu.h | 465 +- inc/bdshemu_x86.h | 92 + inc/{constants.h => bdx86_constants.h} | 47 +- inc/bdx86_core.h | 1675 + inc/{cpuidflags.h => bdx86_cpuidflags.h} | 9 +- inc/{registers.h => bdx86_registers.h} | 16 +- inc/version.h | 17 - isagenerator/CMakeLists.txt | 4 +- isagenerator/disasmlib.py | 1493 +- isagenerator/generate_tables.py | 1903 +- isagenerator/instructions/cpuid.dat | 2 + isagenerator/instructions/table_0F_38.dat | 148 - isagenerator/instructions/table_0F_3A.dat | 74 - isagenerator/instructions/table_3dnow.dat | 52 +- .../{table_evex1.dat => table_evex_1.dat} | 468 +- .../{table_evex2.dat => table_evex_2.dat} | 654 +- .../{table_evex3.dat => table_evex_3.dat} | 200 +- isagenerator/instructions/table_evex_4.dat | 1342 + .../{table_evex5.dat => table_evex_5.dat} | 104 +- .../{table_evex6.dat => table_evex_6.dat} | 96 +- isagenerator/instructions/table_evex_7.dat | 7 + .../{table_base.dat => table_legacy_0.dat} | 459 +- .../{table_0F.dat => table_legacy_1.dat} | 1075 +- isagenerator/instructions/table_legacy_2.dat | 148 + isagenerator/instructions/table_legacy_3.dat | 74 + .../{table_fpu.dat => table_legacy_fpu.dat} | 76 +- .../{table_vex1.dat => table_vex_1.dat} | 516 +- .../{table_vex2.dat => table_vex_2.dat} | 414 +- .../{table_vex3.dat => table_vex_3.dat} | 202 +- isagenerator/instructions/table_vex_7.dat | 7 + isagenerator/instructions/table_xop.dat | 170 +- isagenerator/isagenerator.vcxproj | 35 +- isagenerator/isagenerator.vcxproj.filters | 117 +- prepare_fuzzing_image.sh | 15 + 132 files changed, 303165 insertions(+), 112069 deletions(-) create mode 100644 CHANGELOG.md create mode 100644 Dockerfile.fuzzing rename bddisasm/{crt.c => bddisasm_crt.c} (97%) rename bddisasm/{bddisasm.c => bdx86_decoder.c} (67%) rename bddisasm/{bdformat.c => bdx86_formatter.c} (83%) rename bddisasm/{bdhelpers.c => bdx86_helpers.c} (99%) rename bddisasm/include/{nd_crt.h => bddisasm_crt.h} (97%) create mode 100644 bddisasm/include/bdx86_instructions.h rename bddisasm/include/{mnemonics.h => bdx86_mnemonics.h} (70%) rename bddisasm/include/{prefixes.h => bdx86_prefixes.h} (89%) create mode 100644 bddisasm/include/bdx86_table_evex.h create mode 100644 bddisasm/include/bdx86_table_root.h create mode 100644 bddisasm/include/bdx86_table_vex.h create mode 100644 bddisasm/include/bdx86_table_xop.h rename bddisasm/include/{tabledefs.h => bdx86_tabledefs.h} (76%) delete mode 100644 bddisasm/include/instructions.h delete mode 100644 bddisasm/include/table_evex.h delete mode 100644 bddisasm/include/table_root.h delete mode 100644 bddisasm/include/table_vex.h delete mode 100644 bddisasm/include/table_xop.h create mode 100644 bddisasm_test/x86/apx/apx1_64.result create mode 100644 bddisasm_test/x86/apx/apx1_64.test create mode 100644 bddisasm_test/x86/apx/apx2_64.result create mode 100644 bddisasm_test/x86/apx/apx2_64.test create mode 100644 bddisasm_test/x86/apx/evex_bad_64_skip.asm create mode 100644 bddisasm_test/x86/apx/evex_bad_64_skip.result create mode 100644 bddisasm_test/x86/apx/evex_bad_64_skip.test create mode 100644 bddisasm_test/x86/apx/rex2_bad_64_skip.asm create mode 100644 bddisasm_test/x86/apx/rex2_bad_64_skip.result create mode 100644 bddisasm_test/x86/apx/rex2_bad_64_skip.test create mode 100644 bddisasm_test/x86/apx/rex2_valid_64.asm create mode 100644 bddisasm_test/x86/apx/rex2_valid_64.result create mode 100644 bddisasm_test/x86/apx/rex2_valid_64.test create mode 100644 bddisasm_test/x86/usermsr/rex2_valid_64.asm create mode 100644 bddisasm_test/x86/usermsr/rex2_valid_64.result create mode 100644 bddisasm_test/x86/usermsr/rex2_valid_64.test create mode 100644 bdshemu/bdshemu_x86.c create mode 100644 bdshemu/include/bdshemu_common.h delete mode 100644 bdshemu_fuzz/README.md create mode 100644 bdshemu_fuzz/fuzzing_image_entrypoint.sh delete mode 100644 bdshemu_test/bdshemu_test.zip create mode 100644 bdshemu_test/x86/bdshemu_test_x86.zip create mode 100644 bindings/rsbddisasm/update_ins.py delete mode 100644 disasmtool_lix/CMakeLists.txt delete mode 100644 disasmtool_lix/Makefile delete mode 100644 disasmtool_lix/disasm.hpp delete mode 100644 disasmtool_lix/disasmtool.cpp delete mode 100644 disasmtool_lix/dumpers.cpp delete mode 100644 disasmtool_lix/dumpers.cpp.bak delete mode 100644 disasmtool_lix/external/argparse.h delete mode 100644 disasmtool_lix/rapidjson.cpp rename inc/{disasmstatus.h => bddisasm_status.h} (95%) rename inc/{disasmtypes.h => bddisasm_types.h} (69%) create mode 100644 inc/bddisasm_version.h create mode 100644 inc/bdshemu_x86.h rename inc/{constants.h => bdx86_constants.h} (98%) create mode 100644 inc/bdx86_core.h rename inc/{cpuidflags.h => bdx86_cpuidflags.h} (97%) rename inc/{registers.h => bdx86_registers.h} (80%) delete mode 100644 inc/version.h delete mode 100644 isagenerator/instructions/table_0F_38.dat delete mode 100644 isagenerator/instructions/table_0F_3A.dat rename isagenerator/instructions/{table_evex1.dat => table_evex_1.dat} (52%) rename isagenerator/instructions/{table_evex2.dat => table_evex_2.dat} (50%) rename isagenerator/instructions/{table_evex3.dat => table_evex_3.dat} (57%) create mode 100644 isagenerator/instructions/table_evex_4.dat rename isagenerator/instructions/{table_evex5.dat => table_evex_5.dat} (60%) rename isagenerator/instructions/{table_evex6.dat => table_evex_6.dat} (59%) create mode 100644 isagenerator/instructions/table_evex_7.dat rename isagenerator/instructions/{table_base.dat => table_legacy_0.dat} (71%) rename isagenerator/instructions/{table_0F.dat => table_legacy_1.dat} (54%) create mode 100644 isagenerator/instructions/table_legacy_2.dat create mode 100644 isagenerator/instructions/table_legacy_3.dat rename isagenerator/instructions/{table_fpu.dat => table_legacy_fpu.dat} (86%) rename isagenerator/instructions/{table_vex1.dat => table_vex_1.dat} (54%) rename isagenerator/instructions/{table_vex2.dat => table_vex_2.dat} (58%) rename isagenerator/instructions/{table_vex3.dat => table_vex_3.dat} (53%) create mode 100644 isagenerator/instructions/table_vex_7.dat create mode 100644 prepare_fuzzing_image.sh diff --git a/.gitignore b/.gitignore index 815b04d..afbf0b0 100644 --- a/.gitignore +++ b/.gitignore @@ -57,7 +57,9 @@ compile_commands.json pydis/.eggs bdshemu_fuzz/out bdshemu_fuzz/shfuzz +bdshemu_fuzz/in-32 bdshemu_fuzz/out-32 +bdshemu_fuzz/in-64 bdshemu_fuzz/out-64 docs/build libbddisasm.pc @@ -67,3 +69,9 @@ disasmtool_lix/_build bindings/rsbddisasm/target bindings/rsbddisasm/Cargo.lock bindings/pybddisasm/pybddisasm.egg-info +bindings/rsbddisasm/bddisasm/target +bindings/pybddisasm/pybddisasm/pybddisasm.py +bindings/pybddisasm/pybddisasm/pybddisasm_wrap.c + +bddfuzz.tar +bindings/pybddisasm/.eggs diff --git a/CHANGELOG.md b/CHANGELOG.md new file mode 100644 index 0000000..923482e --- /dev/null +++ b/CHANGELOG.md @@ -0,0 +1,54 @@ +# Changelog + +All notable (user-facing) changes to this project will be documented in this file. + +The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/). + + + +## [2.1.0] - 2024-02-20 + +### Added +- Support in bddisasm for Intel REX2 prefix. +- Support in bddisasm for Intel APX extensions. +- Support in bddisasm for Intel USERMSR extensions. +- Support in bddisasm for prefix activation fields inside `INSTRUX` - these fields can be consulted to determine whether a particular prefix is present, accepted & active. +- New feature in bdshemu: `SHEMU_OPT_DIRECT_MAPPED_SHELL` - allows emulation with a smaller `IntBuff` at the cost of not having `WRITE_SELF` detections. The shellcode can be provided directly from its original location, without the need to allocate it in a dedicated memory region. +- New feature in bdshemu: `SHEMU_OPT_TRACK_LOOPS` - loops can now be tracked by bdshemu. `SHEMU_OPT_TRACE_LOOPS` can be used to log loop information. +- Support in bdshemu for APX instructions (both REX2 and EVEX encoded instructions) - the new `SHEMU_OPT_SUPPORT_APX` must be set in order to enable APX emulation. + +### Changed +- Reduced the size of the `INSTRUX` structure from 856 bytes to 488 bytes (almost -43%!). +- Increased decoding performance from average 300 clocks/instruction to average 235 clocks/instruction (almost +20%!). +- New decode options - do not decode implicit operands - this further increases performance from average 235 clocks/instruction to 200 clocks/instruction (almost +15%!). +- Re-worked the Python scripts - both `disasmlib.py` and `generate_tables.py` have been significantly reworked, improving readability, and making them more efficient. +- `disasmtool` builds on Linux. + +### Removed +- Support for Cyrix & VIA instructions - only current Intel & AMD instructions remain supported. +- disasmtool_lix has been removed. `disasmtool` is available on Linux as well. + +### Breaking changes + +#### Inside INSTRUX +- Removed `Iclass` field - it was aliased over `Instruction` field, which must be used from now on. +- Removed `OperandsEncodingMap` field - one can consult the `Encoding` field in each operand to determine the encoding. +- Removed `ExceptionClass` field - only `ExceptionType` remains, which contains an enum with all the exception types. +- Removed `Predicate` field - only `Condition` remains, which was aliased over `Predicate`. +- Removed `HasImm3`, `Immediate3`, `Imm3Length` and `Imm3Offset` fields, as they were not used/needed. +- Removed `Bhint`, `SseCondition`, `SignDisp` fields, as they were not used. +- Moved `FlagsAccess.RegAccess` outside and renamed it to `RflAccess`, to save more space. +- Switched from `char Mnemonic[32]` to `const char *Mnemonic` - this decreases INSTRUX size by almost 32 bytes, and increases perf. + +#### Inside ND_OPERAND +- Removed `RawSize` - in most cases, `Size` and `RawSize` are identical; the only case where they might differ is for `Immediate` and `RelativeOffset` operands - in that case, one can consult the `RawSize` field in `Immediate` or `RelativeOffset`. + +#### Inside ND_OPERAND_DECORATOR +- Removed `Broadcast` field, moved it inside `ND_OPDESC_MEMORY`. +- Removed `HasSae`, `HasEr` - they are per instruction, not per operand, and can be consulted directly inside `INSTRUX`. +- Moved `Msk` one level up, inside the `ND_OPERAND_DECORATOR` structure. + +#### Defines & constants +- Removed `ND_PRED_*` defines - search & replace them with `ND_COND_*`. +- Removed `ND_HAS_PREDICATE` - use `ND_HAS_CONDITION` instead. +- Removed `ND_VEND_GEODE` and `ND_VEND_CYRIX`. diff --git a/CMakeLists.txt b/CMakeLists.txt index f891f50..0d8dd93 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,16 +1,18 @@ cmake_minimum_required(VERSION 3.16) option(BDD_INCLUDE_TOOL "Include the disasmtool executable" ON) -option(BDD_INCLUDE_ISAGENERATOR "Include the isagenerator target (if a python interpreter is found)" ON) +option(BDD_INCLUDE_ISAGENERATOR_X86 "Include the x86 isagenerator target (if a python interpreter is found)" ON) option(BDD_INCLUDE_FUZZERS "Include the bdshemu fuzzer" OFF) option(BDD_USE_EXTERNAL_VSNPRINTF "Expect nd_vsnprintf_s implementation from the integrator" OFF) option(BDD_USE_EXTERNAL_MEMSET "Expect nd_memset implementation from the integrator" OFF) +option(BDD_ASAN "Build with ASAN" OFF) +option(BDD_UBSAN "Build with UBSAN" OFF) -set(BDD_VER_FILE ${CMAKE_CURRENT_LIST_DIR}/inc/version.h) +set(BDD_VER_FILE ${CMAKE_CURRENT_LIST_DIR}/inc/bddisasm_version.h) -file(STRINGS ${BDD_VER_FILE} disasm_ver_major REGEX "DISASM_VERSION_MAJOR") -file(STRINGS ${BDD_VER_FILE} disasm_ver_minor REGEX "DISASM_VERSION_MINOR") -file(STRINGS ${BDD_VER_FILE} disasm_ver_patch REGEX "DISASM_VERSION_REVISION") +file(STRINGS ${BDD_VER_FILE} disasm_ver_major REGEX "#define DISASM_VERSION_MAJOR") +file(STRINGS ${BDD_VER_FILE} disasm_ver_minor REGEX "#define DISASM_VERSION_MINOR") +file(STRINGS ${BDD_VER_FILE} disasm_ver_patch REGEX "#define DISASM_VERSION_REVISION") string(REGEX REPLACE "#define DISASM_VERSION_MAJOR[ \t\r\n]*" "" disasm_ver_major ${disasm_ver_major}) string(REGEX REPLACE "#define DISASM_VERSION_MINOR[ \t\r\n]*" "" disasm_ver_minor ${disasm_ver_minor}) @@ -25,7 +27,7 @@ project( LANGUAGES C HOMEPAGE_URL https://github.com/bitdefender/bddisasm) -# Use Release as the build type if no build type was specified and we're not using a multi-config generator . +# Use Release as the build type if no build type was specified and we're not using a multi-config generator. if (NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) message(STATUS "No build type given. Will use 'Release'") set(CMAKE_BUILD_TYPE @@ -79,12 +81,17 @@ endif () set(BDDISASM_PUBLIC_HEADERS "inc/bddisasm.h" - "inc/constants.h" - "inc/cpuidflags.h" - "inc/disasmstatus.h" - "inc/disasmtypes.h" - "inc/registers.h" - "inc/version.h") + "inc/bddisasm_status.h" + "inc/bddisasm_types.h" + "inc/bddisasm_version.h" + "inc/bdx86_constants.h" + "inc/bdx86_core.h" + "inc/bdx86_cpuidflags.h" + "inc/bdx86_registers.h") + +set(BDSHEMU_PUBLIC_HEADERS + "inc/bdshemu_x86.h" + "inc/bdshemu.h") include(GNUInstallDirs) @@ -100,20 +107,20 @@ include(CheckCCompilerFlag) add_library( bddisasm STATIC - bddisasm/crt.c - bddisasm/bddisasm.c - bddisasm/bdformat.c - bddisasm/bdhelpers.c + bddisasm/bddisasm_crt.c + bddisasm/bdx86_decoder.c + bddisasm/bdx86_formatter.c + bddisasm/bdx86_helpers.c # Add the headers so they will show up in IDEs. - bddisasm/include/instructions.h - bddisasm/include/mnemonics.h - bddisasm/include/nd_crt.h - bddisasm/include/prefixes.h - bddisasm/include/table_evex.h - bddisasm/include/table_root.h - bddisasm/include/table_vex.h - bddisasm/include/table_xop.h - bddisasm/include/tabledefs.h + bddisasm/include/bddisasm_crt.h + bddisasm/include/bdx86_instructions.h + bddisasm/include/bdx86_mnemonics.h + bddisasm/include/bdx86_prefixes.h + bddisasm/include/bdx86_tabledefs.h + bddisasm/include/bdx86_table_evex.h + bddisasm/include/bdx86_table_root.h + bddisasm/include/bdx86_table_vex.h + bddisasm/include/bdx86_table_xop.h "${BDDISASM_PUBLIC_HEADERS}") if (NOT BDD_USE_EXTERNAL_VSNPRINTF) @@ -154,6 +161,20 @@ set_target_properties( VERSION ${CMAKE_PROJECT_VERSION} SOVERSION ${CMAKE_PROJECT_VERSION_MAJOR}) +if (BDD_ASAN) + target_compile_options(bddisasm PUBLIC "-fsanitize=address") + target_link_libraries(bddisasm PUBLIC "-fsanitize=address") +endif () + +if (BDD_UBSAN) + target_compile_options(bddisasm PUBLIC + "-fsanitize=undefined" + "-fno-sanitize=alignment") + target_link_libraries(bddisasm PUBLIC + "-fsanitize=undefined" + "-fno-sanitize=alignment") +endif () + add_library(bddisasm::bddisasm ALIAS bddisasm) # -- bdshemu -- @@ -161,8 +182,10 @@ add_library(bddisasm::bddisasm ALIAS bddisasm) add_library( bdshemu STATIC bdshemu/bdshemu.c + bdshemu/bdshemu_x86.c # Add the headers so they will show up in IDEs. - inc/bdshemu.h) + bdshemu/include/bdshemu_common.h + "${BDSHEMU_PUBLIC_HEADERS}") set_target_properties( bdshemu @@ -185,7 +208,7 @@ endif () set_target_properties( bdshemu - PROPERTIES PUBLIC_HEADER "inc/bdshemu.h" + PROPERTIES PUBLIC_HEADER "${BDSHEMU_PUBLIC_HEADERS}" VERSION ${CMAKE_PROJECT_VERSION} SOVERSION ${CMAKE_PROJECT_VERSION_MAJOR}) @@ -193,19 +216,14 @@ add_library(bddisasm::bdshemu ALIAS bdshemu) # If this is the master project (and if the user requested it) add disasmtool. if ((${CMAKE_PROJECT_NAME} STREQUAL ${PROJECT_NAME}) AND BDD_INCLUDE_TOOL) - if (WIN32) - add_subdirectory(disasmtool) - else () - add_subdirectory(disasmtool_lix) - endif () + add_subdirectory(disasmtool) endif () # If this is the master project (and if the user requested it) add isagenerator. -if ((${CMAKE_PROJECT_NAME} STREQUAL ${PROJECT_NAME}) AND BDD_INCLUDE_ISAGENERATOR) +if ((${CMAKE_PROJECT_NAME} STREQUAL ${PROJECT_NAME}) AND BDD_INCLUDE_ISAGENERATOR_X86) add_subdirectory(isagenerator) endif () -# If this is the master project (and if the user requested it) add the fuzzer. if ((${CMAKE_PROJECT_NAME} STREQUAL ${PROJECT_NAME}) AND BDD_INCLUDE_FUZZERS) add_subdirectory(bdshemu_fuzz) endif () @@ -236,7 +254,7 @@ if (${CMAKE_PROJECT_NAME} STREQUAL ${PROJECT_NAME}) COMPONENT bddisasm_Runtime NAMELINK_COMPONENT bddisasm_Development ARCHIVE DESTINATION ${CMAKE_INSTALL_LIBDIR} COMPONENT bddisasm_Development) - + if (BDD_INCLUDE_TOOL) install( TARGETS disasmtool diff --git a/Dockerfile.fuzzing b/Dockerfile.fuzzing new file mode 100644 index 0000000..f8dbd4f --- /dev/null +++ b/Dockerfile.fuzzing @@ -0,0 +1,118 @@ +FROM ubuntu:22.04 as build + +WORKDIR /bddfuzz + +# Install everything we need to build AFL++ and honggfuzz and bdshemu +# We install both clang-13 and clang-15 because honggfuzz does not support newer versions of clang, but AFL++ wants +# the latest version so it is what it is +RUN apt-get update && apt-get install -y \ + cmake make git \ + binutils-dev \ + libunwind-dev \ + libblocksruntime-dev \ + clang-13 \ + clang-15 \ + llvm-15 llvm-15-dev llvm-15-linker-tools llvm-15-runtime llvm-15-tools lld-15 + +# Cleanup +RUN apt-get clean && rm -rf /var/lib/apt/lists/* + +RUN mkdir /bddfuzz/fuzzers + +# Build and install AFL++ +RUN cd /bddfuzz/fuzzers && git clone https://github.com/AFLplusplus/AFLplusplus.git +RUN cd /bddfuzz/fuzzers/AFLplusplus && \ + CC=clang-15 CXX=clang++-15 make source-only install LLVM_CONFIG=llvm-config-15 NO_NYX=1 + +# Build and install honggfuzz +RUN cd /bddfuzz/fuzzers && git clone --depth 1 --branch 2.5 https://github.com/google/honggfuzz.git +RUN cd /bddfuzz/fuzzers/honggfuzz && make install + +# Remove the fuzzer source files as we no longer need them +RUN cd /bddfuzz/fuzzers/AFLplusplus && git clean -dxf && git clean -dXf && rm -rf /bddfuzz/fuzzers/AFLplusplus +RUN rm -rf /bddfuzz/fuzzers/honggfuzz +RUN rm -rf /bddfuzz/fuzzers/ + +ENV SRC /bddfuzz/src/ + +# Copy the relevant bddisasm sources +RUN mkdir "${SRC}" + +COPY CMakeLists.txt "${SRC}"/CMakeLists.txt +COPY bddisasm.pc.in "${SRC}"/bddisasm.pc.in +COPY bddisasmConfig.cmake "${SRC}"/bddisasmConfig.cmake +COPY bddisasm "${SRC}"/bddisasm +COPY bdshemu "${SRC}"/bdshemu +COPY bdshemu_fuzz "${SRC}"/bdshemu_fuzz +COPY inc "${SRC}"/inc + +# Now build all the variants +RUN mkdir build + +# Build for AFL++ with afl-clang-lto +RUN mkdir /bddfuzz/build/afllto && cd /bddfuzz/build/afllto && \ + cmake "${SRC}" -DCMAKE_C_COMPILER=afl-clang-lto -DCMAKE_CXX_COMPILER=afl-clang-lto++ \ + -DCMAKE_BUILD_TYPE=Releaase \ + -DBDD_INCLUDE_TOOL=OFF -DBDD_INCLUDE_ISAGENERATOR_X86=OFF \ + -DBDD_INCLUDE_FUZZERS=ON && \ + make shfuzz + +# Build for honggfuzz +RUN mkdir /bddfuzz/build/hfuzz && cd /bddfuzz/build/hfuzz && \ + cmake "${SRC}" -DCMAKE_C_COMPILER=hfuzz-clang -DCMAKE_CXX_COMPILER=hfuzz-clang++ \ + -DCMAKE_BUILD_TYPE=Releaase \ + -DBDD_INCLUDE_TOOL=OFF -DBDD_INCLUDE_ISAGENERATOR_X86=OFF \ + -DBDD_INCLUDE_FUZZERS=ON && \ + make shfuzz + +# Build for libfuzzer with ASAN and UBSAN +RUN mkdir /bddfuzz/build/san && cd /bddfuzz/build/san && \ + cmake "${SRC}" -DCMAKE_C_COMPILER=clang-15 -DCMAKE_CXX_COMPILER=clang-15++ \ + -DCMAKE_BUILD_TYPE=Releaase \ + -DBDD_INCLUDE_TOOL=OFF -DBDD_INCLUDE_ISAGENERATOR_X86=OFF \ + -DBDD_INCLUDE_FUZZERS=ON -DBDD_FUZZ_WITH_LOGS=ON \ + -DBDD_ASAN=ON -DBDD_UBSAN=ON && \ + make shfuzz + +RUN rm -rf "${SRC}" + +# Save the fuzzers +RUN mkdir /bddfuzz/shf && cd /bddfuzz/shf && \ + for d in /bddfuzz/build/*; do \ + mkdir ./`basename "${d}"` && \ + cp -v "${d}"/bdshemu_fuzz/shfuzz* ./`basename "${d}"`; \ + done + +# Remove the build directory +RUN rm -rf build + +FROM ubuntu:22.04 as run + +WORKDIR /bddfuzz + +# Copy the fuzzers from the build stage +COPY --from=build /bddfuzz/shf /bddfuzz/shf + +# Copy AFL++ and honggfuzz binaries +COPY --from=build /usr/local/bin/afl-* /usr/local/bin/ +COPY --from=build /usr/local/bin/hfuzz-* /usr/local/bin/ +COPY --from=build /usr/local/bin/honggfuzz /usr/local/bin/ + +RUN mkdir /bddfuzz/inputs +COPY bdshemu_fuzz/in-32 /bddfuzz/inputs/in-32 +COPY bdshemu_fuzz/in-64 /bddfuzz/inputs/in-64 + +# Runtime dependencies for honggfuzz +RUN apt-get update && apt-get install -y binutils-dev libunwind-dev libblocksruntime-dev + +# Cleanup +RUN apt-get clean && rm -rf /var/lib/apt/lists/* + +# So we can share files between the host and the container (we don't want to loose the results when we stop the +# container). +ENV SHARE_DIR share + +COPY bdshemu_fuzz/fuzzing_image_entrypoint.sh /bddfuzz/fuzzing_image_entrypoint.sh +RUN chmod +x /bddfuzz/fuzzing_image_entrypoint.sh + +ENTRYPOINT ["/bddfuzz/fuzzing_image_entrypoint.sh"] diff --git a/README.md b/README.md index 56b5ef0..75f6e74 100644 --- a/README.md +++ b/README.md @@ -5,12 +5,10 @@ The Bitdefender disassembler (bddisasm) is a lightweight, x86/x64 only instructi ## Projects 1. [bddisasm](https://github.com/bitdefender/bddisasm/tree/master/bddisasm) - this is the main disassembler project. In order to use the Bitdefender disassembler, all you have to do is build this project, and link with the output library. The only headers you need are located inside the `inc` folder. -2. [bdshemu](https://github.com/bitdefender/bddisasm/tree/master/bdshemu) - this project makes use of the main bddisasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can -emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. In addition, the only supported memory accesses are inside the shellcode itself, and on the emulated stack. -3. [isagenerator](https://github.com/bitdefender/bddisasm/tree/master/isagenerator) - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. You will need Python 3 to run the generation scripts. +2. [bdshemu](https://github.com/bitdefender/bddisasm/tree/master/bdshemu) - this project makes use of the main bddisasm lib in order to build a simple, lightweight, fast, instructions emulator, designated to target shellcodes. This project is also integrated inside the disasmtool, so you can emulate raw binary files, and see their output. Note that this simple emulator supports basic x86/x64 instructions, and does not support emulating any kind of API call. In addition, the only supported memory accesses are inside the shellcode itself, and on the emulated stack. +3. [isagenerator_x86](https://github.com/bitdefender/bddisasm/tree/master/isagenerator) - this project contains the instruction definitions and the scripts required to generate the disassembly tables. If you wish to add support for a new instruction, this is the place. This project will automatically generate several header files (instructions.h, mnemonics.h, constants.h, table_\*.h), so please make sure you don't manually edit any of these files. You will need Python 3 to run the generation scripts. 4. [disasmtool](https://github.com/bitdefender/bddisasm/tree/master/disasmtool) - this project is a command line disassembler tool, used mainly as an example of how to integrate the bddisasm and bdshemu libraries. -5. [disasmtool_lix](https://github.com/bitdefender/bddisasm/tree/master/disasmtool_lix) - like disasmtool, but for Linux. -6. [bindings](https://github.com/bitdefender/bddisasm/tree/master/bindings) - bindings for [python](https://github.com/bitdefender/bddisasm/tree/master/bindings/pybddisasm), and [Rust](https://github.com/bitdefender/bddisasm/tree/master/bindings/rsbddisasm). +5. [bindings](https://github.com/bitdefender/bddisasm/tree/master/bindings) - bindings for [python](https://github.com/bitdefender/bddisasm/tree/master/bindings/pybddisasm), and [Rust](https://github.com/bitdefender/bddisasm/tree/master/bindings/rsbddisasm). ## Objectives @@ -161,13 +159,13 @@ The results will be in the bin directory in the root of the repository. [nd_vsnprintf_s and nd_memset](#nd_vsnprintf_s-and-nd_memset) will not be defined by `bddisasm`, integrators must provide these functions. -## Decoding instructions +## Decoding x86 instructions ### Decoding API There are 4 decoding functions, but internally, they all do the same, albeit some of them with implicit arguments: -- `NDSTATUS NdDecode(INSTRUX *Instrux, const uint8_t *Code, uint8_t DefCode, uint8_t DefData)` - this API should be used only if you don't care about the length of the input buffer; +- `NDSTATUS NdDecode(INSTRUX *Instrux, const uint8_t *Code, uint8_t DefCode, uint8_t DefData)` - this API should be used only if you don't care about the length of the input buffer; - `NDSTATUS NdDecodeEx(INSTRUX *Instrux, const uint8_t *Code, size_t Size, uint8_t DefCode, uint8_t DefData);` - decode instruction from a buffer with maximum length `Size`; - `NDSTATUS NdDecodeEx2(INSTRUX *Instrux, const uint8_t *Code, size_t Size, uint8_t DefCode, uint8_t DefData, uint8_t DefStack, uint8_t PreferedVendor);` - decode instructions with a preferred vendor; - `NDSTATUS NdDecodeWithContext(INSTRUX *Instrux, const uint8_t *Code, size_t Size, ND_CONTEXT *Context);` - base decode API; the input parameters - `DefCode`, `DefData`, `DefStack`, `VendMode` and `FeatMode` must all be filled in the `Context` structure before calling this function. The Context structure should also be initialized using `NdInitContext` before the first decode call. @@ -277,10 +275,10 @@ Working with the extended API is also trivial: INSTRUX ix; ND_CONTEXT ctx; uint8_t code[] = { 0x48, 0x8B, 0x48, 0x28 }; - + // This has to be done only once. NdInitContext(&ctx); - + ctx.DefCode = ND_CODE_64; ctx.DefData = ND_DATA_64; ctx.DefStack = ND_STACK_64; diff --git a/bddisasm.sln b/bddisasm.sln index 0e0d022..f76c78d 100644 --- a/bddisasm.sln +++ b/bddisasm.sln @@ -15,7 +15,11 @@ Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "bdshemu", "bdshemu\bdshemu. {3653AA19-048B-410E-B5C4-FF78E1D84C12} = {3653AA19-048B-410E-B5C4-FF78E1D84C12} EndProjectSection EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "isagenerator", "isagenerator\isagenerator.vcxproj", "{0E9D2957-34FA-40EE-B4B2-0D008D2FE317}" +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "isagenerator_x86", "isagenerator\isagenerator.vcxproj", "{0E9D2957-34FA-40EE-B4B2-0D008D2FE317}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "core", "core", "{3114F0D4-BEBA-4574-A349-D03477C64C60}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "tools", "tools", "{1F8BBB39-7787-4A50-8170-27EB5FA104D0}" EndProject Global GlobalSection(SolutionConfigurationPlatforms) = preSolution @@ -85,6 +89,12 @@ Global GlobalSection(SolutionProperties) = preSolution HideSolutionNode = FALSE EndGlobalSection + GlobalSection(NestedProjects) = preSolution + {94F1B65D-3305-4CCB-9DF1-50B56900D867} = {1F8BBB39-7787-4A50-8170-27EB5FA104D0} + {3653AA19-048B-410E-B5C4-FF78E1D84C12} = {3114F0D4-BEBA-4574-A349-D03477C64C60} + {3C9B2CA7-CF4F-471B-BB72-6490C476CDCA} = {3114F0D4-BEBA-4574-A349-D03477C64C60} + {0E9D2957-34FA-40EE-B4B2-0D008D2FE317} = {3114F0D4-BEBA-4574-A349-D03477C64C60} + EndGlobalSection GlobalSection(ExtensibilityGlobals) = postSolution SolutionGuid = {E950FA16-07C1-4613-8328-906BC10C7C02} EndGlobalSection diff --git a/bddisasm/Makefile b/bddisasm/Makefile index da67f43..88db5e1 100644 --- a/bddisasm/Makefile +++ b/bddisasm/Makefile @@ -1,6 +1,6 @@ .PHONY: clean -SRC_FILES := crt.c bddisasm.c bdformat.c bdhelpers.c +SRC_FILES := bddisasm_crt.c bdx86_decoder.c bdx86_formatter.c bdx86_helpers.c OBJECTS := $(SRC_FILES:.c=.o) diff --git a/bddisasm/bddisasm.vcxproj b/bddisasm/bddisasm.vcxproj index 062d6fb..ec7b93a 100644 --- a/bddisasm/bddisasm.vcxproj +++ b/bddisasm/bddisasm.vcxproj @@ -115,7 +115,8 @@ WindowsKernelModeDriver10.0 Unicode true - + + Desktop false 1 @@ -143,7 +144,8 @@ StaticLibrary WindowsKernelModeDriver10.0 Unicode - + + Desktop false 1 @@ -643,10 +645,10 @@ - - - - + + + + NotUsing NotUsing NotUsing @@ -665,22 +667,23 @@ - - + + + - - - - - - - - - - - - - + + + + + + + + + + + + + diff --git a/bddisasm/bddisasm.vcxproj.filters b/bddisasm/bddisasm.vcxproj.filters index b8052d0..26dcf34 100644 --- a/bddisasm/bddisasm.vcxproj.filters +++ b/bddisasm/bddisasm.vcxproj.filters @@ -19,69 +19,87 @@ {5e26c505-e8f5-4e6c-9d54-f20e36b637b8} + + {39065bbd-3fd0-42b0-ba8e-d7395674b7ce} + + + {032f0e51-6265-4031-b702-5eb620d95964} + + + {5eb8f135-5960-4e0e-a5a8-5214a7a9edcb} + + + {db15a655-cc99-4e12-a8c3-55a485ee713c} + + + {b9961460-d06f-4288-9708-44ca965c4a0d} + - + Source Files - - Source Files + + Source Files\x86 - - Source Files + + Source Files\x86 - - Source Files + + Source Files\x86 - - Header Files + + Header Files\public - - Header Files + + Header Files\public\x86 - - Header Files + + Header Files\public\x86 - - Header Files + + Header Files\public - - Header Files + + Header Files\public\x86 - - Header Files - - - Header Files - - - Header Files - - + Header Files\public Header Files\public - - Header Files\public + + Header Files\public\x86 - - Header Files\public + + Header Files\private\x86 - - Header Files\public + + Header Files\private\x86 - - Header Files\public + + Header Files\private\x86 - - Header Files\public + + Header Files\private\x86 - - Header Files + + Header Files\private + + + Header Files\private\x86\tables + + + Header Files\private\x86\tables + + + Header Files\private\x86\tables + + + Header Files\private\x86\tables \ No newline at end of file diff --git a/bddisasm/crt.c b/bddisasm/bddisasm_crt.c similarity index 97% rename from bddisasm/crt.c rename to bddisasm/bddisasm_crt.c index 2a07d7b..556939c 100644 --- a/bddisasm/crt.c +++ b/bddisasm/bddisasm_crt.c @@ -2,7 +2,7 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#include "include/nd_crt.h" +#include "include/bddisasm_crt.h" // // nd_strcat_s diff --git a/bddisasm/bddisasm.c b/bddisasm/bdx86_decoder.c similarity index 67% rename from bddisasm/bddisasm.c rename to bddisasm/bdx86_decoder.c index 0866257..abdae82 100644 --- a/bddisasm/bddisasm.c +++ b/bddisasm/bdx86_decoder.c @@ -2,137 +2,17 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#include "include/nd_crt.h" +#include "include/bddisasm_crt.h" #include "../inc/bddisasm.h" // The table definitions. -#include "include/tabledefs.h" +#include "include/bdx86_tabledefs.h" #ifndef UNREFERENCED_PARAMETER #define UNREFERENCED_PARAMETER(P) ((void)(P)) #endif -static const ND_UINT16 gOperandMap[] = -{ - ND_OPE_D, // ND_OPT_A - ND_OPE_V, // ND_OPT_B - ND_OPE_R, // ND_OPT_C - ND_OPE_R, // ND_OPT_D - ND_OPE_M, // ND_OPT_E - ND_OPE_S, // ND_OPT_F - ND_OPE_R, // ND_OPT_G - ND_OPE_V, // ND_OPT_H - ND_OPE_I, // ND_OPT_I - ND_OPE_D, // ND_OPT_J - ND_OPE_S, // ND_OPT_K - ND_OPE_L, // ND_OPT_L - ND_OPE_M, // ND_OPT_M - ND_OPE_M, // ND_OPT_N - ND_OPE_D, // ND_OPT_O - ND_OPE_R, // ND_OPT_P - ND_OPE_M, // ND_OPT_Q - ND_OPE_M, // ND_OPT_R - ND_OPE_R, // ND_OPT_S - ND_OPE_R, // ND_OPT_T - ND_OPE_M, // ND_OPT_U - ND_OPE_R, // ND_OPT_V - ND_OPE_M, // ND_OPT_W - ND_OPE_S, // ND_OPT_X - ND_OPE_S, // ND_OPT_Y - ND_OPE_O, // ND_OPT_Z - ND_OPE_R, // ND_OPT_rB - ND_OPE_M, // ND_OPT_mB - ND_OPE_R, // ND_OPT_rK - ND_OPE_V, // ND_OPT_vK - ND_OPE_M, // ND_OPT_mK - ND_OPE_A, // ND_OPT_aK - ND_OPE_R, // ND_OPT_mR - ND_OPE_M, // ND_OPT_mM - ND_OPE_R, // ND_OPT_rT - ND_OPE_M, // ND_OPT_mT - ND_OPE_V, // ND_OPT_vT - ND_OPE_1, // ND_OPT_1 - - ND_OPE_S, // ND_OPT_RIP - ND_OPE_S, // ND_OPT_MXCSR - ND_OPE_S, // ND_OPT_PKRU - ND_OPE_S, // ND_OPT_SSP - ND_OPE_S, // ND_OPT_UIF - - ND_OPE_S, // ND_OPT_GPR_AH - ND_OPE_S, // ND_OPT_GPR_rAX - ND_OPE_S, // ND_OPT_GPR_rCX - ND_OPE_S, // ND_OPT_GPR_rDX - ND_OPE_S, // ND_OPT_GPR_rBX - ND_OPE_S, // ND_OPT_GPR_rSP - ND_OPE_S, // ND_OPT_GPR_rBP - ND_OPE_S, // ND_OPT_GPR_rSI - ND_OPE_S, // ND_OPT_GPR_rDI - ND_OPE_S, // ND_OPT_GPR_rR8 - ND_OPE_S, // ND_OPT_GPR_rR9 - ND_OPE_S, // ND_OPT_GPR_rR11 - - ND_OPE_S, // ND_OPT_SEG_CS - ND_OPE_S, // ND_OPT_SEG_SS - ND_OPE_S, // ND_OPT_SEG_DS - ND_OPE_S, // ND_OPT_SEG_ES - ND_OPE_S, // ND_OPT_SEG_FS - ND_OPE_S, // ND_OPT_SEG_GS - - ND_OPE_S, // ND_OPT_FPU_ST0 - ND_OPE_M, // ND_OPT_FPU_STX - - ND_OPE_S, // ND_OPT_SSE_XMM0 - ND_OPE_S, // ND_OPT_SSE_XMM1 - ND_OPE_S, // ND_OPT_SSE_XMM2 - ND_OPE_S, // ND_OPT_SSE_XMM3 - ND_OPE_S, // ND_OPT_SSE_XMM4 - ND_OPE_S, // ND_OPT_SSE_XMM5 - ND_OPE_S, // ND_OPT_SSE_XMM6 - ND_OPE_S, // ND_OPT_SSE_XMM7 - - ND_OPE_S, // ND_OPT_MEM_rAX (as used by MONITOR, MONITORX and RMPADJUST) - ND_OPE_S, // ND_OPT_MEM_rCX (as used by RMPUPDATE) - ND_OPE_S, // ND_OPT_MEM_rBX_AL (as used by XLAT) - ND_OPE_S, // ND_OPT_MEM_rDI (as used by masked moves) - ND_OPE_S, // ND_OPT_MEM_SHS - ND_OPE_S, // ND_OPT_MEM_SHSP - ND_OPE_S, // ND_OPT_MEM_SHS0 - ND_OPE_S, // ND_OPT_MEM_SMSRT - ND_OPE_S, // ND_OPT_MEM_DMSRT - - ND_OPE_L, // ND_OPT_Im2z - - ND_OPE_S, // ND_OPT_CR_0 - ND_OPE_S, // ND_OPT_IDTR - ND_OPE_S, // ND_OPT_GDTR - ND_OPE_S, // ND_OPT_LDTR - ND_OPE_S, // ND_OPT_TR - - ND_OPE_S, // ND_OPT_X87_CONTROL - ND_OPE_S, // ND_OPT_X87_TAG - ND_OPE_S, // ND_OPT_X87_STATUS - - ND_OPE_E, // ND_OPT_MSR - ND_OPE_E, // ND_OPT_XCR - ND_OPE_S, // ND_OPT_MSR_TSC - ND_OPE_S, // ND_OPT_MSR_TSCAUX - ND_OPE_S, // ND_OPT_MSR_SEIP - ND_OPE_S, // ND_OPT_MSR_SESP - ND_OPE_S, // ND_OPT_MSR_SCS - ND_OPE_S, // ND_OPT_MSR_STAR - ND_OPE_S, // ND_OPT_MSR_LSTAR - ND_OPE_S, // ND_OPT_MSR_FMASK - ND_OPE_S, // ND_OPT_MSR_FSBASE - ND_OPE_S, // ND_OPT_MSR_GSBASE - ND_OPE_S, // ND_OPT_MSR_KGSBASE - ND_OPE_S, // ND_OPT_XCR_0 - ND_OPE_S, // ND_OPT_REG_BANK - ND_OPE_S, // Unused. -}; - - static const ND_UINT8 gDispsizemap16[4][8] = { { 0, 0, 0, 0, 0, 0, 2, 0 }, @@ -158,8 +38,8 @@ NdGetVersion( ND_UINT32 *Major, ND_UINT32 *Minor, ND_UINT32 *Revision, - char **BuildDate, - char **BuildTime + const char **BuildDate, + const char **BuildTime ) { if (ND_NULL != Major) @@ -209,7 +89,6 @@ NdGetVersion( } - // // NdFetchData // @@ -248,7 +127,11 @@ NdFetchXop( RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); // Make sure we don't have any other prefix. - if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + if (Instrux->HasOpSize || + Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || + Instrux->HasRex || + Instrux->HasRex2) { return ND_STATUS_XOP_WITH_PREFIX; } @@ -318,8 +201,12 @@ NdFetchVex2( if ((ND_CODE_64 == Instrux->DefCode) || ((Code[Offset + 1] & 0xC0) == 0xC0)) { // Make sure we don't have any other prefix. - if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || - Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + if (Instrux->HasOpSize || + Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || + Instrux->HasRex || + Instrux->HasRex2 || + Instrux->HasLock) { return ND_STATUS_VEX_WITH_PREFIX; } @@ -370,8 +257,12 @@ NdFetchVex3( RET_GT((ND_SIZET)Offset + 3, Size, ND_STATUS_BUFFER_TOO_SMALL); // Make sure we don't have any other prefix. - if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || - Instrux->HasRepRepzXrelease || Instrux->HasRex || Instrux->HasLock) + if (Instrux->HasOpSize || + Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || + Instrux->HasRex || + Instrux->HasRex2 || + Instrux->HasLock) { return ND_STATUS_VEX_WITH_PREFIX; } @@ -449,32 +340,57 @@ NdFetchEvex( Instrux->Evex.Evex[3] = Code[Offset + 3]; // Legacy prefixes are not accepted with EVEX. - if (Instrux->HasOpSize || Instrux->HasRepnzXacquireBnd || Instrux->HasRepRepzXrelease || Instrux->HasRex) + if (Instrux->HasOpSize || + Instrux->HasRepnzXacquireBnd || + Instrux->HasRepRepzXrelease || + Instrux->HasRex || + Instrux->HasRex2 || + Instrux->HasLock) { return ND_STATUS_EVEX_WITH_PREFIX; } // Do the opcode independent checks. Opcode dependent checks are done when decoding each instruction. - if (Instrux->Evex.zero != 0 || Instrux->Evex.one != 1 || Instrux->Evex.m == 0) + if (Instrux->Evex.m == 0) { return ND_STATUS_INVALID_ENCODING; } - // Fill in the generic extension bits + // APX not enabled, legacy EVEX prefix. + if (!(Instrux->FeatMode & ND_FEAT_APX)) + { + // Map > 3 is for APX instructions. B4 must be 0, and X4 must be 1 if APX is not enabled. + if (Instrux->Evex.m > 3 || Instrux->Evex.b4 != 0 || Instrux->Evex.x4 != 1) + { + return ND_STATUS_INVALID_ENCODING; + } + } + + // Fill in the generic extension bits. We initially optimistically fill in all possible values. + // Once we determine the opcode and, subsequently, the EVEX extension mode, we will do further + // validations, and reset unused fields to 0. Instrux->Exs.r = ~Instrux->Evex.r; Instrux->Exs.x = ~Instrux->Evex.x; Instrux->Exs.b = ~Instrux->Evex.b; Instrux->Exs.rp = ~Instrux->Evex.rp; + Instrux->Exs.b4 = Instrux->Evex.b4; + Instrux->Exs.x4 = ~Instrux->Evex.x4; Instrux->Exs.m = Instrux->Evex.m; Instrux->Exs.w = Instrux->Evex.w; Instrux->Exs.v = ~Instrux->Evex.v; Instrux->Exs.vp = ~Instrux->Evex.vp; Instrux->Exs.p = Instrux->Evex.p; + Instrux->Exs.z = Instrux->Evex.z; Instrux->Exs.l = Instrux->Evex.l; Instrux->Exs.bm = Instrux->Evex.bm; Instrux->Exs.k = Instrux->Evex.a; + // EVEX extensions. + Instrux->Exs.nf = (Instrux->Evex.Evex[3] >> 2) & 1; + Instrux->Exs.nd = (Instrux->Evex.Evex[3] >> 4) & 1; + Instrux->Exs.sc = (Instrux->Evex.Evex[3] & 0xF); + // Do EVEX validations outside 64 bits mode. if (ND_CODE_64 != Instrux->DefCode) { @@ -489,6 +405,9 @@ NdFetchEvex( // Evex.R' is ignored, so we force it to 0. Instrux->Exs.rp = 0; + // Evex.B4 & Evex.X4 are ignored, so we force them to 0. + Instrux->Exs.b4 = Instrux->Exs.x4 = 0; + // High bit inside Evex.VVVV is ignored, so we force it to 0. Instrux->Exs.v &= 0x7; @@ -510,6 +429,64 @@ NdFetchEvex( } +// +// NdFetchRex2 +// +static NDSTATUS +NdFetchRex2( + INSTRUX *Instrux, + const ND_UINT8 *Code, + ND_UINT8 Offset, + ND_SIZET Size + ) +{ + if (ND_CODE_64 != Instrux->DefCode) + { + // AAD instruction outside 64-bit mode. + return ND_STATUS_SUCCESS; + } + + if (!(Instrux->FeatMode & ND_FEAT_APX)) + { + // APX not enabled, #UD. + return ND_STATUS_SUCCESS; + } + + // One more byte has to follow. + RET_GT((ND_SIZET)Offset + 2, Size, ND_STATUS_BUFFER_TOO_SMALL); + + // This is REX2. + Instrux->HasRex2 = ND_TRUE; + Instrux->EncMode = ND_ENCM_LEGACY; + Instrux->Rex2.Rex2[0] = Code[Offset + 0]; + Instrux->Rex2.Rex2[1] = Code[Offset + 1]; + + // REX illegal with REX2. + if (Instrux->HasRex) + { + return ND_STATUS_INVALID_PREFIX_SEQUENCE; + } + + // Fill in the generic extension bits + Instrux->Exs.r = Instrux->Rex2.r3; + Instrux->Exs.rp = Instrux->Rex2.r4; + Instrux->Exs.x = Instrux->Rex2.x3; + Instrux->Exs.x4 = Instrux->Rex2.x4; + Instrux->Exs.b = Instrux->Rex2.b3; + Instrux->Exs.b4 = Instrux->Rex2.b4; + Instrux->Exs.w = Instrux->Rex2.w; + + // Update Instrux length & offset, and make sure we don't exceed 15 bytes. + Instrux->Length += 2; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + // // NdFetchPrefixes // @@ -687,15 +664,19 @@ NdFetchPrefixes( return status; } } + else if (Code[Offset] == ND_PREFIX_REX2) + { + status = NdFetchRex2(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + } else { return ND_STATUS_INVALID_INSTRUX; } } - else - { - Instrux->EncMode = ND_ENCM_LEGACY; - } done_prefixes: // The total length of the instruction is the total length of the prefixes right now. @@ -719,6 +700,13 @@ NdFetchOpcode( // At least one byte must be available, for the fetched opcode. RET_GT((ND_SIZET)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL); + // With REX2, only legacy map & 0x0F map are valid. A single opcode byte can be present, and no + // opcode extensions are accepted (for example, 0x0F 0x38 is invalid). + if (Instrux->HasRex2 && Instrux->OpLength != 0) + { + return ND_STATUS_INVALID_ENCODING; + } + Instrux->OpCodeBytes[Instrux->OpLength++] = Code[Offset]; Instrux->Length++; @@ -846,8 +834,6 @@ NdFetchDisplacement( if (0 != displSize) { - static const ND_UINT32 signMask[4] = { 0x80, 0x8000, 0, 0x80000000 }; - // Make sure enough buffer space is available. RET_GT((ND_SIZET)Offset + displSize, Size, ND_STATUS_BUFFER_TOO_SMALL); @@ -855,7 +841,6 @@ NdFetchDisplacement( Instrux->HasDisp = ND_TRUE; Instrux->Displacement = (ND_UINT32)NdFetchData(Code + Offset, displSize); - Instrux->SignDisp = (Instrux->Displacement & signMask[displSize - 1]) ? ND_TRUE : ND_FALSE; // Fill in displacement info. Instrux->DispLength = displSize; @@ -872,10 +857,33 @@ NdFetchDisplacement( // -// NdFetchAddress +// NdFetchModrmSibDisplacement // static NDSTATUS -NdFetchAddress( +NdFetchModrmSibDisplacement( + INSTRUX *Instrux, + const ND_UINT8 *Code, + ND_UINT8 Offset, + ND_SIZET Size + ) +{ + NDSTATUS status; + + status = NdFetchModrmAndSib(Instrux, Code, Offset, Size); + if (!ND_SUCCESS(status)) + { + return status; + } + + return NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); +} + + +// +// NdFetchAddressFar +// +static NDSTATUS +NdFetchAddressFar( INSTRUX *Instrux, const ND_UINT8 *Code, ND_UINT8 Offset, @@ -883,7 +891,6 @@ NdFetchAddress( ND_UINT8 AddressSize ) { - //. Make sure the RET_GT((ND_SIZET)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL); Instrux->HasAddr = ND_TRUE; @@ -903,6 +910,36 @@ NdFetchAddress( } +// +// NdFetchAddressNear +// +static NDSTATUS +NdFetchAddressNear( + INSTRUX *Instrux, + const ND_UINT8 *Code, + ND_UINT8 Offset, + ND_SIZET Size, + ND_UINT8 AddressSize + ) +{ + RET_GT((ND_SIZET)Offset + AddressSize, Size, ND_STATUS_BUFFER_TOO_SMALL); + + Instrux->HasAddrNear = ND_TRUE; + Instrux->AddrLength = AddressSize; + Instrux->AddrOffset = Offset; + + Instrux->AddressNear = (ND_UINT64)NdFetchData(Code + Offset, Instrux->AddrLength); + + Instrux->Length += Instrux->AddrLength; + if (Instrux->Length > ND_MAX_INSTRUCTION_LENGTH) + { + return ND_STATUS_INSTRUCTION_TOO_LONG; + } + + return ND_STATUS_SUCCESS; +} + + // // NdFetchImmediate // @@ -923,10 +960,7 @@ NdFetchImmediate( if (Instrux->HasImm2) { - Instrux->HasImm3 = ND_TRUE; - Instrux->Imm3Length = ImmediateSize; - Instrux->Imm3Offset = Offset; - Instrux->Immediate3 = (ND_UINT8)imm; + return ND_STATUS_INVALID_INSTRUX; } else if (Instrux->HasImm1) { @@ -1051,6 +1085,12 @@ NdGetSegOverride( ND_UINT8 DefaultSeg ) { + // Return default seg, if no override present. + if (Instrux->Seg == 0) + { + return DefaultSeg; + } + // In 64 bit mode, the segment override is ignored, except for FS and GS. if ((Instrux->DefCode == ND_CODE_64) && (Instrux->Seg != ND_PREFIX_G2_SEG_FS) && @@ -1149,6 +1189,233 @@ NdGetCompDispSize( } +// +// NdParseMemoryOperand16 +// +static NDSTATUS +NdParseMemoryOperand16( + INSTRUX *Instrux, + ND_OPERAND *Operand + ) +{ + if (Instrux->Attributes & ND_FLAG_NOA16) + { + return ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED; + } + + switch (Instrux->ModRm.rm) + { + case 0: + // [bx + si] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.Scale = 1; + Operand->Info.Memory.Base = NDR_BX; + Operand->Info.Memory.Index = NDR_SI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_DS; + break; + case 1: + // [bx + di] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.Scale = 1; + Operand->Info.Memory.Base = NDR_BX; + Operand->Info.Memory.Index = NDR_DI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_DS; + break; + case 2: + // [bp + si] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.Scale = 1; + Operand->Info.Memory.Base = NDR_BP; + Operand->Info.Memory.Index = NDR_SI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_SS; + break; + case 3: + // [bp + di] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.Scale = 1; + Operand->Info.Memory.Base = NDR_BP; + Operand->Info.Memory.Index = NDR_DI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.IndexSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_SS; + break; + case 4: + // [si] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.Base = NDR_SI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_DS; + break; + case 5: + // [di] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.Base = NDR_DI; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_DS; + break; + case 6: + // [bp] + if (Instrux->ModRm.mod != 0) + { + // If mod is not zero, than we have "[bp + displacement]". + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.Base = NDR_BP; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_SS; + } + else + { + // If mod is zero, than we only have a displacement that is used to directly address mem. + Operand->Info.Memory.Seg = NDR_DS; + } + break; + case 7: + // [bx] + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.Base = NDR_BX; + Operand->Info.Memory.BaseSize = ND_SIZE_16BIT; + Operand->Info.Memory.Seg = NDR_DS; + break; + } + + // Store the displacement. + Operand->Info.Memory.HasDisp = !!Instrux->HasDisp; + Operand->Info.Memory.DispSize = Instrux->DispLength; + Operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + + return ND_STATUS_SUCCESS; +} + + +// +// NdParseMemoryOperand3264 +// +static NDSTATUS +NdParseMemoryOperand3264( + INSTRUX *Instrux, + ND_OPERAND *Operand, + ND_REG_SIZE VsibRegSize + ) +{ + ND_UINT8 defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT); + + // Implicit segment is DS. + Operand->Info.Memory.Seg = NDR_DS; + + if (Instrux->HasSib) + { + // Check for base. + if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == NDR_RBP)) + { + // Mod is mem without displacement and base reg is RBP -> no base reg used. + // Note that this addressing mode is not RIP relative. + } + else + { + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.BaseSize = defsize; + Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->Sib.base; + + // If APX is present, extend the base. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + + if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP)) + { + Operand->Info.Memory.Seg = NDR_SS; + } + } + + // Check for index. + if (ND_HAS_VSIB(Instrux)) + { + // With VSIB, the index reg can be 4 (RSP equivalent). Bit 4 of the 32-bit index register is given by the + // EVEX.V' field. + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.IndexSize = defsize; + Operand->Info.Memory.Index = (ND_UINT8)((Instrux->Exs.vp << 4) | (Instrux->Exs.x << 3) | Instrux->Sib.index); + Operand->Info.Memory.IndexSize = (ND_UINT8)VsibRegSize; + Operand->Info.Memory.Scale = 1 << Instrux->Sib.scale; + } + else + { + // Regular SIB, index RSP is ignored. Bit 4 of the 32-bit index register is given by the X4 field. + Operand->Info.Memory.Index = (ND_UINT8)(Instrux->Exs.x << 3) | Instrux->Sib.index; + + // If APX is present, extend the index. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4; + } + + if (Operand->Info.Memory.Index != NDR_RSP) + { + // Index * Scale is present. + Operand->Info.Memory.HasIndex = ND_TRUE; + Operand->Info.Memory.IndexSize = defsize; + Operand->Info.Memory.Scale = 1 << Instrux->Sib.scale; + } + } + } + else + { + if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == NDR_RBP)) + { + // + // RIP relative addressing addresses a memory region relative to the current RIP; However, + // the current RIP, when executing the current instruction, is already updated and points + // to the next instruction, therefore, we must add the instruction length also to the final + // address. Note that RIP relative addressing is used even if the instruction uses 32 bit + // addressing, as long as we're in long mode. + // + Operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64); + + // Some instructions (example: MPX) don't support RIP relative addressing. + if (Operand->Info.Memory.IsRipRel && !!(Instrux->Attributes & ND_FLAG_NO_RIP_REL)) + { + return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED; + } + } + else + { + Operand->Info.Memory.HasBase = ND_TRUE; + Operand->Info.Memory.BaseSize = defsize; + Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; + + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + + if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP)) + { + Operand->Info.Memory.Seg = NDR_SS; + } + } + } + + Operand->Info.Memory.HasDisp = Instrux->HasDisp; + Operand->Info.Memory.DispSize = Instrux->DispLength; + Operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); + + return ND_STATUS_SUCCESS; +} + + + // // NdParseOperand // @@ -1196,6 +1463,9 @@ NdParseOperand( // Store operand access modes. operand->Access.Access = opa; + // Implicit operand access, by default. + operand->Encoding = ND_OPE_S; + // // Fill in operand size. @@ -1600,38 +1870,48 @@ NdParseOperand( } // Store operand info. - operand->Size = operand->RawSize = bcstSize = size; + operand->Size = bcstSize = size; // // Fill in the operand type. // switch (opt) { - case ND_OPT_CONST_1: + case ND_OPT_1: // operand is an implicit constant (used by shift/rotate instruction). operand->Type = ND_OP_CONST; + operand->Encoding = ND_OPE_1; operand->Info.Constant.Const = 1; break; - case ND_OPT_RIP: + case ND_OPT_rIP: // The operand is the instruction pointer. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_RIP; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = 0; Instrux->RipAccess |= operand->Access.Access; + // Fill in branch information. + Instrux->BranchInfo.IsBranch = 1; + Instrux->BranchInfo.IsConditional = Instrux->Category == ND_CAT_COND_BR; + // Indirect branches are those which get their target address from a register or memory, including RET familly. + Instrux->BranchInfo.IsIndirect = ((!Instrux->Operands[0].Flags.IsDefault) && + ((Instrux->Operands[0].Type == ND_OP_REG) || (Instrux->Operands[0].Type == ND_OP_MEM))) || + (Instrux->Category == ND_CAT_RET); + // CS operand is ALWAYS before rIP. + Instrux->BranchInfo.IsFar = !!(Instrux->CsAccess & ND_ACCESS_ANY_WRITE); break; - case ND_OPT_GPR_rAX: - // Operator is the accumulator. + case ND_OPT_rAX: + // Operand is the accumulator. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = NDR_RAX; break; - case ND_OPT_GPR_AH: - // Operator is the accumulator. + case ND_OPT_AH: + // Operand is the accumulator. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = ND_SIZE_8BIT; @@ -1639,31 +1919,31 @@ NdParseOperand( operand->Info.Register.IsHigh8 = ND_TRUE; break; - case ND_OPT_GPR_rCX: - // Operator is the counter register. + case ND_OPT_rCX: + // Operand is the counter register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = NDR_RCX; break; - case ND_OPT_GPR_rDX: - // Operator is rDX. + case ND_OPT_rDX: + // Operand is rDX. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = NDR_RDX; break; - case ND_OPT_GPR_rBX: - // Operator is BX. + case ND_OPT_rBX: + // Operand is BX. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = NDR_RBX; break; - case ND_OPT_GPR_rBP: + case ND_OPT_rBP: // Operand is rBP. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1671,7 +1951,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_RBP; break; - case ND_OPT_GPR_rSP: + case ND_OPT_rSP: // Operand is rSP. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1679,7 +1959,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_RSP; break; - case ND_OPT_GPR_rSI: + case ND_OPT_rSI: // Operand is rSI. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1687,7 +1967,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_RSI; break; - case ND_OPT_GPR_rDI: + case ND_OPT_rDI: // Operand is rDI. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1695,7 +1975,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_RDI; break; - case ND_OPT_GPR_rR8: + case ND_OPT_rR8: // Operand is R8. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1703,7 +1983,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_R8; break; - case ND_OPT_GPR_rR9: + case ND_OPT_rR9: // Operand is R9. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1711,7 +1991,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_R9; break; - case ND_OPT_GPR_rR11: + case ND_OPT_rR11: // Operand is R11. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_GPR; @@ -1719,7 +1999,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_R11; break; - case ND_OPT_SEG_CS: + case ND_OPT_CS: // Operand is the CS register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1728,7 +2008,7 @@ NdParseOperand( Instrux->CsAccess |= operand->Access.Access; break; - case ND_OPT_SEG_SS: + case ND_OPT_SS: // Operand is the SS register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1736,7 +2016,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_SS; break; - case ND_OPT_SEG_DS: + case ND_OPT_DS: // Operand is the DS register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1744,7 +2024,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_DS; break; - case ND_OPT_SEG_ES: + case ND_OPT_ES: // Operand is the ES register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1752,7 +2032,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_ES; break; - case ND_OPT_SEG_FS: + case ND_OPT_FS: // Operand is the FS register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1760,7 +2040,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_FS; break; - case ND_OPT_SEG_GS: + case ND_OPT_GS: // Operand is the GS register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SEG; @@ -1768,7 +2048,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_GS; break; - case ND_OPT_FPU_ST0: + case ND_OPT_ST0: // Operand is the ST(0) register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_FPU; @@ -1776,31 +2056,32 @@ NdParseOperand( operand->Info.Register.Reg = 0; break; - case ND_OPT_FPU_STX: + case ND_OPT_STi: // Operand is the ST(i) register. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; operand->Info.Register.Type = ND_REG_FPU; operand->Info.Register.Size = ND_SIZE_80BIT; operand->Info.Register.Reg = Instrux->ModRm.rm; break; - case ND_OPT_SSE_XMM0: - case ND_OPT_SSE_XMM1: - case ND_OPT_SSE_XMM2: - case ND_OPT_SSE_XMM3: - case ND_OPT_SSE_XMM4: - case ND_OPT_SSE_XMM5: - case ND_OPT_SSE_XMM6: - case ND_OPT_SSE_XMM7: + case ND_OPT_XMM0: + case ND_OPT_XMM1: + case ND_OPT_XMM2: + case ND_OPT_XMM3: + case ND_OPT_XMM4: + case ND_OPT_XMM5: + case ND_OPT_XMM6: + case ND_OPT_XMM7: // Operand is a hard-coded XMM register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SSE; operand->Info.Register.Size = ND_SIZE_128BIT; - operand->Info.Register.Reg = opt - ND_OPT_SSE_XMM0; + operand->Info.Register.Reg = opt - ND_OPT_XMM0; break; // Special operands. These are always implicit, and can't be encoded inside the instruction. - case ND_OPT_CR_0: + case ND_OPT_CR0: // The operand is implicit and is control register 0. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_CR; @@ -1808,7 +2089,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_CR0; break; - case ND_OPT_SYS_GDTR: + case ND_OPT_GDTR: // The operand is implicit and is the global descriptor table register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1816,7 +2097,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_GDTR; break; - case ND_OPT_SYS_IDTR: + case ND_OPT_IDTR: // The operand is implicit and is the interrupt descriptor table register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1824,7 +2105,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IDTR; break; - case ND_OPT_SYS_LDTR: + case ND_OPT_LDTR: // The operand is implicit and is the local descriptor table register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1832,7 +2113,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_LDTR; break; - case ND_OPT_SYS_TR: + case ND_OPT_TR: // The operand is implicit and is the task register. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1840,7 +2121,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_TR; break; - case ND_OPT_X87_CONTROL: + case ND_OPT_X87CONTROL: // The operand is implicit and is the x87 control word. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1848,7 +2129,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_X87_CONTROL; break; - case ND_OPT_X87_TAG: + case ND_OPT_X87TAG: // The operand is implicit and is the x87 tag word. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1856,7 +2137,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_X87_TAG; break; - case ND_OPT_X87_STATUS: + case ND_OPT_X87STATUS: // The operand is implicit and is the x87 status word. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_SYS; @@ -1899,12 +2180,13 @@ NdParseOperand( case ND_OPT_MSR: // The operand is implicit and is a MSR (usually selected by the ECX register). operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_E; operand->Info.Register.Type = ND_REG_MSR; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = 0xFFFFFFFF; break; - case ND_OPT_MSR_TSC: + case ND_OPT_TSC: // The operand is implicit and is the IA32_TSC. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1912,7 +2194,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_TSC; break; - case ND_OPT_MSR_TSCAUX: + case ND_OPT_TSCAUX: // The operand is implicit and is the IA32_TSCAUX. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1920,7 +2202,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_TSC_AUX; break; - case ND_OPT_MSR_SCS: + case ND_OPT_SCS: // The operand is implicit and is the IA32_SYSENTER_CS. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1928,7 +2210,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_SYSENTER_CS; break; - case ND_OPT_MSR_SESP: + case ND_OPT_SESP: // The operand is implicit and is the IA32_SYSENTER_ESP. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1936,7 +2218,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_SYSENTER_ESP; break; - case ND_OPT_MSR_SEIP: + case ND_OPT_SEIP: // The operand is implicit and is the IA32_SYSENTER_EIP. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1944,7 +2226,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_SYSENTER_EIP; break; - case ND_OPT_MSR_STAR: + case ND_OPT_STAR: // The operand is implicit and is the IA32_STAR. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1952,7 +2234,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_STAR; break; - case ND_OPT_MSR_LSTAR: + case ND_OPT_LSTAR: // The operand is implicit and is the IA32_STAR. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1960,7 +2242,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_LSTAR; break; - case ND_OPT_MSR_FMASK: + case ND_OPT_FMASK: // The operand is implicit and is the IA32_FMASK. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1968,7 +2250,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_FMASK; break; - case ND_OPT_MSR_FSBASE: + case ND_OPT_FSBASE: // The operand is implicit and is the IA32_FS_BASE MSR. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1976,7 +2258,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_FS_BASE; break; - case ND_OPT_MSR_GSBASE: + case ND_OPT_GSBASE: // The operand is implicit and is the IA32_GS_BASE MSR. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1984,7 +2266,7 @@ NdParseOperand( operand->Info.Register.Reg = NDR_IA32_GS_BASE; break; - case ND_OPT_MSR_KGSBASE: + case ND_OPT_KGSBASE: // The operand is implicit and is the IA32_KERNEL_GS_BASE MSR. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_MSR; @@ -1995,12 +2277,13 @@ NdParseOperand( case ND_OPT_XCR: // The operand is implicit and is an extended control register (usually selected by ECX register). operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_E; operand->Info.Register.Type = ND_REG_XCR; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = 0xFF; break; - case ND_OPT_XCR_0: + case ND_OPT_XCR0: // The operand is implicit and is XCR0. operand->Type = ND_OP_REG; operand->Info.Register.Type = ND_REG_XCR; @@ -2008,12 +2291,12 @@ NdParseOperand( operand->Info.Register.Reg = 0; break; - case ND_OPT_REG_BANK: + case ND_OPT_BANK: // Multiple registers are accessed. if ((Instrux->Instruction == ND_INS_PUSHA) || (Instrux->Instruction == ND_INS_POPA)) { operand->Type = ND_OP_REG; - operand->Size = operand->RawSize = Instrux->WordLength; + operand->Size = Instrux->WordLength; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = Instrux->WordLength; operand->Info.Register.Reg = NDR_EAX; @@ -2028,39 +2311,74 @@ NdParseOperand( case ND_OPT_A: // Fetch the address. NOTE: The size can't be larger than 8 bytes. - status = NdFetchAddress(Instrux, Code, Offset, Size, (ND_UINT8)size); - if (!ND_SUCCESS(status)) + if (ops == ND_OPS_p) { - return status; - } + status = NdFetchAddressFar(Instrux, Code, Offset, Size, (ND_UINT8)size); + if (!ND_SUCCESS(status)) + { + return status; + } - // Fill in operand info. - operand->Type = ND_OP_ADDR; - operand->Info.Address.BaseSeg = Instrux->Address.Cs; - operand->Info.Address.Offset = Instrux->Address.Ip; + // Fill in operand info. + operand->Type = ND_OP_ADDR_FAR; + operand->Encoding = ND_OPE_D; + operand->Info.Address.BaseSeg = Instrux->Address.Cs; + operand->Info.Address.Offset = Instrux->Address.Ip; + } + else + { + status = NdFetchAddressNear(Instrux, Code, Offset, Size, (ND_UINT8)size); + if (!ND_SUCCESS(status)) + { + return status; + } + + // Fill in operand info. + operand->Type = ND_OP_ADDR_NEAR; + operand->Encoding = ND_OPE_D; + operand->Info.AddressNear.Target = Instrux->AddressNear; + } break; case ND_OPT_B: // General purpose register encoded in VEX.vvvv field. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_V; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v; // EVEX.V' must be 0, if a GPR is encoded using EVEX encoding. if (Instrux->Exs.vp != 0) { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + // If APX is present, V' can be used to extend the GPR to R16-R31. + // Otherwise, #UD is triggered. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.vp << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } - operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v; break; case ND_OPT_C: // Control register, encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_CR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg; + + // If APX is present, use R4 as well. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.rp << 4; + } + // On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing // higher 8 control registers. if ((ND_CODE_64 != Instrux->DefCode) && (Instrux->HasLock)) @@ -2083,9 +2401,16 @@ NdParseOperand( case ND_OPT_D: // Debug register, encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_DR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg; + + // If APX is present, use R4 as well. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.rp << 4; + } // Only DR0-DR7 valid. if (operand->Info.Register.Reg >= 8) @@ -2098,6 +2423,7 @@ NdParseOperand( case ND_OPT_T: // Test register, encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_TR; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); @@ -2113,8 +2439,11 @@ NdParseOperand( case ND_OPT_S: // Segment register, encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_SEG; operand->Info.Register.Size = (ND_REG_SIZE)size; + + // When addressing segment registers, any extension field (REX.R, REX2.R3, REX2.R4) is ignored. operand->Info.Register.Reg = Instrux->ModRm.reg; // Only ES, CS, SS, DS, FS, GS valid. @@ -2133,21 +2462,27 @@ NdParseOperand( case ND_OPT_E: // General purpose register or memory, encoded in modrm.rm. - if (Instrux->ModRm.mod == 3) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_GPR; - operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && - (operand->Info.Register.Reg >= 4) && - (ND_ENCM_LEGACY == Instrux->EncMode) && - !Instrux->HasRex; - } - else + if (Instrux->ModRm.mod != 3) { goto memory; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; + + // If APX is present, use B4 as well. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex && !Instrux->HasRex2; break; case ND_OPT_F: @@ -2156,7 +2491,7 @@ NdParseOperand( operand->Info.Register.Type = ND_REG_FLG; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = 0; - Instrux->FlagsAccess.RegAccess |= operand->Access.Access; + Instrux->RflAccess |= operand->Access.Access; break; case ND_OPT_K: @@ -2180,39 +2515,54 @@ NdParseOperand( case ND_OPT_G: // General purpose register encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg; - // EVEX.R' must be 0 if a GPR is encoded. if (Instrux->Exs.rp != 0) { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + // If APX is present, use R' (R4) to extent the register to 5 bits. + // Otherwise, generate #UD. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.rp << 4; + } + else + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } } - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && - (operand->Info.Register.Reg >= 4) && + (operand->Info.Register.Reg >= 4) && (ND_ENCM_LEGACY == Instrux->EncMode) && - !Instrux->HasRex; + !Instrux->HasRex && !Instrux->HasRex2; break; case ND_OPT_R: // General purpose register encoded in modrm.rm. - if ((Instrux->ModRm.mod == 3) || (0 != (Instrux->Attributes & ND_FLAG_MFR))) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_GPR; - operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && - (operand->Info.Register.Reg >= 4) && - (ND_ENCM_LEGACY == Instrux->EncMode) && - !Instrux->HasRex; - } - else + if ((Instrux->ModRm.mod != 3) && (0 == (Instrux->Attributes & ND_FLAG_MFR))) { return ND_STATUS_INVALID_ENCODING; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_GPR; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm; + + // If APX is present, use B4 as well. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && + (operand->Info.Register.Reg >= 4) && + (ND_ENCM_LEGACY == Instrux->EncMode) && + !Instrux->HasRex && !Instrux->HasRex2; break; case ND_OPT_I: @@ -2228,11 +2578,7 @@ NdParseOperand( } // Get the last immediate. - if (Instrux->HasImm3) - { - imm = Instrux->Immediate3; - } - else if (Instrux->HasImm2) + if (Instrux->HasImm2) { imm = Instrux->Immediate2; } @@ -2242,6 +2588,8 @@ NdParseOperand( } operand->Type = ND_OP_IMM; + operand->Encoding = ND_OPE_I; + operand->Info.Immediate.RawSize = (ND_UINT8)size; if (operand->Flags.SignExtendedDws) { @@ -2266,11 +2614,11 @@ NdParseOperand( } break; - case ND_OPT_Im2z: - { - operand->Type = ND_OP_IMM; - operand->Info.Immediate.Imm = Instrux->SseImmediate & 3; - } + case ND_OPT_m2zI: + operand->Type = ND_OP_IMM; + operand->Encoding = ND_OPE_L; + operand->Info.Immediate.Imm = Instrux->SseImmediate & 3; + operand->Info.Immediate.RawSize = (ND_UINT8)size; break; case ND_OPT_J: @@ -2285,10 +2633,12 @@ NdParseOperand( Instrux->IsRipRelative = ND_TRUE; operand->Type = ND_OP_OFFS; + operand->Encoding = ND_OPE_D; // The relative offset is forced to the default word length. Care must be taken with the 32 bit // branches that have 0x66 prefix (in 32 bit mode)! operand->Size = Instrux->WordLength; operand->Info.RelativeOffset.Rel = ND_SIGN_EX(size, Instrux->RelativeOffset); + operand->Info.RelativeOffset.RawSize = (ND_UINT8)size; break; @@ -2300,6 +2650,7 @@ NdParseOperand( } operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; operand->Info.Register.Type = ND_REG_MMX; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = Instrux->ModRm.rm; @@ -2308,6 +2659,7 @@ NdParseOperand( case ND_OPT_P: // The reg field of the ModR/M byte selects a packed quadword MMX technology register. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_MMX; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = Instrux->ModRm.reg; @@ -2315,39 +2667,37 @@ NdParseOperand( case ND_OPT_Q: // The rm field inside Mod R/M encodes a MMX register or memory. - if (Instrux->ModRm.mod == 3) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_MMX; - operand->Info.Register.Size = ND_SIZE_64BIT; - operand->Info.Register.Reg = Instrux->ModRm.rm; - } - else + if (Instrux->ModRm.mod != 3) { goto memory; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_MMX; + operand->Info.Register.Size = ND_SIZE_64BIT; + operand->Info.Register.Reg = Instrux->ModRm.rm; break; case ND_OPT_O: // Absolute address, encoded in instruction bytes. + // NOTE: The moffset len can't exceed 8 bytes. + status = NdFetchMoffset(Instrux, Code, Offset, Size, 2 << Instrux->AddrMode); + if (!ND_SUCCESS(status)) { - // NOTE: The moffset len can't exceed 8 bytes. - status = NdFetchMoffset(Instrux, Code, Offset, Size, 2 << Instrux->AddrMode); - if (!ND_SUCCESS(status)) - { - return status; - } - - // operand info. - Instrux->MemoryAccess |= operand->Access.Access; - operand->Type = ND_OP_MEM; - operand->Info.Memory.HasDisp = ND_TRUE; - operand->Info.Memory.IsDirect = ND_TRUE; - operand->Info.Memory.DispSize = Instrux->MoffsetLength; - operand->Info.Memory.Disp = Instrux->Moffset; - operand->Info.Memory.HasSeg = ND_TRUE; - operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); + return status; } + + // operand info. + Instrux->MemoryAccess |= operand->Access.Access; + operand->Type = ND_OP_MEM; + operand->Encoding = ND_OPE_D; + operand->Info.Memory.HasDisp = ND_TRUE; + operand->Info.Memory.IsDirect = ND_TRUE; + operand->Info.Memory.DispSize = Instrux->MoffsetLength; + operand->Info.Memory.Disp = Instrux->Moffset; + operand->Info.Memory.HasSeg = ND_TRUE; + operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; case ND_OPT_M: @@ -2360,185 +2710,25 @@ NdParseOperand( memory: Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; + operand->Encoding = ND_OPE_M; operand->Info.Memory.HasSeg = ND_TRUE; - if (ND_ADDR_16 == Instrux->AddrMode) + // Parse mode specific memory information. + if (ND_ADDR_16 != Instrux->AddrMode) { - // 16 bit addressing, make sure the instruction supports this. - if (!!(Instrux->Attributes & ND_FLAG_NOA16)) + status = NdParseMemoryOperand3264(Instrux, operand, vsibRegSize); + if (!ND_SUCCESS(status)) { - return ND_STATUS_16_BIT_ADDRESSING_NOT_SUPPORTED; + return status; } - - switch (Instrux->ModRm.rm) - { - case 0: - // [bx + si] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.HasIndex = ND_TRUE; - operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = NDR_BX; - operand->Info.Memory.Index = NDR_SI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_DS; - break; - case 1: - // [bx + di] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.HasIndex = ND_TRUE; - operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = NDR_BX; - operand->Info.Memory.Index = NDR_DI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_DS; - break; - case 2: - // [bp + si] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.HasIndex = ND_TRUE; - operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = NDR_BP; - operand->Info.Memory.Index = NDR_SI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_SS; - break; - case 3: - // [bp + di] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.HasIndex = ND_TRUE; - operand->Info.Memory.Scale = 1; - operand->Info.Memory.Base = NDR_BP; - operand->Info.Memory.Index = NDR_DI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.IndexSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_SS; - break; - case 4: - // [si] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.Base = NDR_SI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_DS; - break; - case 5: - // [di] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.Base = NDR_DI; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_DS; - break; - case 6: - // [bp] - if (Instrux->ModRm.mod != 0) - { - // If mod is not zero, than we have "[bp + displacement]". - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.Base = NDR_BP; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_SS; - } - else - { - // If mod is zero, than we only have a displacement that is used to directly address mem. - operand->Info.Memory.Seg = NDR_DS; - } - break; - case 7: - // [bx] - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.Base = NDR_BX; - operand->Info.Memory.BaseSize = ND_SIZE_16BIT; - operand->Info.Memory.Seg = NDR_DS; - break; - } - - // Store the displacement. - operand->Info.Memory.HasDisp = !!Instrux->HasDisp; - operand->Info.Memory.DispSize = Instrux->DispLength; - operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); } else { - ND_UINT8 defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT); - - // Implicit segment is DS. - operand->Info.Memory.Seg = NDR_DS; - - if (Instrux->HasSib) + status = NdParseMemoryOperand16(Instrux, operand); + if (!ND_SUCCESS(status)) { - // Check for base. - if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == NDR_RBP)) - { - // Mod is mem without displacement and base reg is RBP -> no base reg used. - // Note that this addressing mode is not RIP relative. - } - else - { - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.BaseSize = defsize; - operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->Sib.base); - - if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP)) - { - operand->Info.Memory.Seg = NDR_SS; - } - } - - // Check for index. - if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != NDR_RSP) || ND_HAS_VSIB(Instrux)) - { - // Index * Scale is present. - operand->Info.Memory.HasIndex = ND_TRUE; - operand->Info.Memory.IndexSize = defsize; - operand->Info.Memory.Index = (ND_UINT8)((Instrux->Exs.x << 3) | Instrux->Sib.index); - - if (ND_HAS_VSIB(Instrux)) - { - operand->Info.Memory.IndexSize = vsibRegSize; - operand->Info.Memory.Index |= Instrux->Exs.vp << 4; - } - - operand->Info.Memory.Scale = 1 << Instrux->Sib.scale; - } + return status; } - else - { - if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == NDR_RBP)) - { - // - // RIP relative addressing addresses a memory region relative to the current RIP; However, - // the current RIP, when executing the current instruction, is already updated and points - // to the next instruction, therefore, we must add the instruction length also to the final - // address. Note that RIP relative addressing is used even if the instruction uses 32 bit - // addressing, as long as we're in long mode. - // - operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64); - - // Some instructions (example: MPX) don't support RIP relative addressing. - if (operand->Info.Memory.IsRipRel && !!(Instrux->Attributes & ND_FLAG_NO_RIP_REL)) - { - return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED; - } - } - else - { - operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.BaseSize = defsize; - operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - - if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP)) - { - operand->Info.Memory.Seg = NDR_SS; - } - } - } - - operand->Info.Memory.HasDisp = Instrux->HasDisp; - operand->Info.Memory.DispSize = Instrux->DispLength; - operand->Info.Memory.Disp = ND_SIGN_EX(Instrux->DispLength, Instrux->Displacement); } // Get the segment. Note that in long mode, segment prefixes are ignored, except for FS and GS. @@ -2601,7 +2791,10 @@ memory: } // Override operand size. - operand->Size = operand->RawSize = size; + operand->Size = size; + + operand->Info.Memory.Broadcast.Size = (ND_UINT8)operand->Size; + operand->Info.Memory.Broadcast.Count = (ND_UINT8)(bcstSize / operand->Size); } // Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement @@ -2640,17 +2833,12 @@ memory: case ND_OPT_H: // Vector register, encoded in VEX/EVEX.vvvv. - if (ND_ENCM_LEGACY == Instrux->EncMode) - { - return ND_STATUS_HINT_OPERAND_NOT_USED; - } - else - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_SSE; - operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.vp << 4) | Instrux->Exs.v); - } + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_V; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + // V' will be 0 for any non-EVEX encoded instruction. + operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.vp << 4) | Instrux->Exs.v); break; case ND_OPT_L: @@ -2662,6 +2850,7 @@ memory: } operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_L; operand->Info.Register.Type = ND_REG_SSE; operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); operand->Info.Register.Reg = (Instrux->SseImmediate >> 4) & 0xF; @@ -2681,49 +2870,57 @@ memory: } operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; operand->Info.Register.Type = ND_REG_SSE; operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - if (Instrux->HasEvex || Instrux->HasMvex) + + if (Instrux->HasEvex) { operand->Info.Register.Reg |= Instrux->Exs.x << 4; } + break; case ND_OPT_V: // Vector register encoded in modrm.reg. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_SSE; operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); - if (Instrux->HasEvex || Instrux->HasMvex) + + if (Instrux->HasEvex) { operand->Info.Register.Reg |= Instrux->Exs.rp << 4; } + break; case ND_OPT_W: // Vector register or memory encoded in modrm.rm. - if (Instrux->ModRm.mod == 3) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_SSE; - operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - if (Instrux->HasEvex || Instrux->HasMvex) - { - operand->Info.Register.Reg |= Instrux->Exs.x << 4; - } - } - else + if (Instrux->ModRm.mod != 3) { goto memory; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_SSE; + operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size); + operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + + // For vector registers, the X extension bit is used to extend the register to 5 bits. + if (Instrux->HasEvex) + { + operand->Info.Register.Reg |= Instrux->Exs.x << 4; + } + break; case ND_OPT_X: case ND_OPT_Y: - case ND_OPT_MEM_rDI: + case ND_OPT_pDI: // RSI/RDI based addressing, as used by string instructions. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2743,7 +2940,7 @@ memory: } break; - case ND_OPT_MEM_rBX_AL: + case ND_OPT_pBXAL: // [rBX + AL], used by XLAT. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2758,7 +2955,7 @@ memory: operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; - case ND_OPT_MEM_rAX: + case ND_OPT_pAX: // [rAX], used implicitly by MONITOR, MONITORX and RMPADJUST instructions. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2769,7 +2966,7 @@ memory: operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; - case ND_OPT_MEM_rCX: + case ND_OPT_pCX: // [rCX], used implicitly by RMPUPDATE. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2780,7 +2977,7 @@ memory: operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); break; - case ND_OPT_MEM_SHS: + case ND_OPT_SHS: // Shadow stack access using the current SSP. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2788,7 +2985,7 @@ memory: operand->Info.Memory.ShStkType = ND_SHSTK_SSP_LD_ST; break; - case ND_OPT_MEM_SHS0: + case ND_OPT_SHS0: // Shadow stack access using the IA32_PL0_SSP. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2796,7 +2993,7 @@ memory: operand->Info.Memory.ShStkType = ND_SHSTK_PL0_SSP; break; - case ND_OPT_MEM_SMSRT: + case ND_OPT_SMT: // Table of MSR addresses, encoded in [RSI]. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2806,7 +3003,7 @@ memory: operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode. break; - case ND_OPT_MEM_DMSRT: + case ND_OPT_DMT: // Table of MSR addresses, encoded in [RDI]. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2816,7 +3013,7 @@ memory: operand->Info.Memory.HasSeg = ND_FALSE; // Linear Address directly, only useable in 64 bit mode. break; - case ND_OPT_MEM_SHSP: + case ND_OPT_SHSP: // Shadow stack push/pop access. Instrux->MemoryAccess |= operand->Access.Access; operand->Type = ND_OP_MEM; @@ -2827,49 +3024,62 @@ memory: case ND_OPT_Z: // A GPR Register is selected by the low 3 bits inside the opcode. REX.B can be used to extend it. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_O; operand->Info.Register.Type = ND_REG_GPR; operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7)); + operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7); + + // If APX is present, extend the register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Register.Reg |= Instrux->Exs.b4 << 4; + } + operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) && - (operand->Info.Register.Reg >= 4) && + (operand->Info.Register.Reg >= 4) && (ND_ENCM_LEGACY == Instrux->EncMode) && - !Instrux->HasRex; + !Instrux->HasRex && !Instrux->HasRex2; break; case ND_OPT_rB: // reg inside modrm selects a BND register. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_BND; operand->Info.Register.Size = (ND_REG_SIZE)size; operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + if (operand->Info.Register.Reg >= 4) { return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } + break; case ND_OPT_mB: // rm inside modrm selects either a BND register, either memory. - if (Instrux->ModRm.mod == 3) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_BND; - operand->Info.Register.Size = (ND_REG_SIZE)size; - operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); - if (operand->Info.Register.Reg >= 4) - { - return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; - } - } - else + if (Instrux->ModRm.mod != 3) { goto memory; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_BND; + operand->Info.Register.Size = (ND_REG_SIZE)size; + operand->Info.Register.Reg = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + + if (operand->Info.Register.Reg >= 4) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + break; case ND_OPT_rK: // reg inside modrm selects a mask register. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_MSK; // Opcode dependent #UD, R and R' must be zero (1 actually, but they're inverted). @@ -2880,40 +3090,42 @@ memory: operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = (ND_UINT8)(Instrux->ModRm.reg); - break; case ND_OPT_vK: // vex.vvvv selects a mask register. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_V; operand->Info.Register.Type = ND_REG_MSK; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = (ND_UINT8)Instrux->Exs.v; + if (operand->Info.Register.Reg >= 8) { return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } + break; case ND_OPT_mK: // rm inside modrm selects either a mask register, either memory. - if (Instrux->ModRm.mod == 3) - { - operand->Type = ND_OP_REG; - operand->Info.Register.Type = ND_REG_MSK; - operand->Info.Register.Size = ND_SIZE_64BIT; - // X and B are ignored when Msk registers are being addressed. - operand->Info.Register.Reg = Instrux->ModRm.rm; - } - else + if (Instrux->ModRm.mod != 3) { goto memory; } + + operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; + operand->Info.Register.Type = ND_REG_MSK; + operand->Info.Register.Size = ND_SIZE_64BIT; + // X and B are ignored when Msk registers are being addressed. + operand->Info.Register.Reg = Instrux->ModRm.rm; break; case ND_OPT_aK: // aaa inside evex selects either a mask register, which is used for masking a destination operand. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_A; operand->Info.Register.Type = ND_REG_MSK; operand->Info.Register.Size = ND_SIZE_64BIT; operand->Info.Register.Reg = Instrux->Exs.k; @@ -2926,8 +3138,16 @@ memory: // - The ES segment register cannot be overridden // - The size of the base register is selected by the address size, not the operand size. operand->Type = ND_OP_MEM; + operand->Encoding = ND_OPE_R; operand->Info.Memory.HasBase = ND_TRUE; operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg); + + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Memory.Base |= Instrux->Exs.rp << 4; + } + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.HasSeg = ND_TRUE; operand->Info.Memory.Seg = NDR_ES; @@ -2936,8 +3156,16 @@ memory: case ND_OPT_mM: // Sigh. rm field inside mod r/m encodes memory, even if mod is 3. operand->Type = ND_OP_MEM; + operand->Encoding = ND_OPE_M; operand->Info.Memory.HasBase = ND_TRUE; - operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.m << 3) | Instrux->ModRm.rm); + operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm); + + // If APX is present, extend the base register. + if (Instrux->FeatMode & ND_FEAT_APX) + { + operand->Info.Memory.Base |= Instrux->Exs.b4 << 4; + } + operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode; operand->Info.Memory.HasSeg = ND_TRUE; operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS); @@ -2946,6 +3174,7 @@ memory: case ND_OPT_rT: // Tile register encoded in ModR/M.reg field. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_R; operand->Info.Register.Type = ND_REG_TILE; operand->Info.Register.Size = size; operand->Info.Register.Reg = Instrux->ModRm.reg; @@ -2956,11 +3185,21 @@ memory: return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } + // #UD of R4 is not 0. + if (Instrux->FeatMode & ND_FEAT_APX) + { + if (Instrux->Exs.rp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + break; case ND_OPT_mT: // Tile register encoded in ModR/M.rm field. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_M; operand->Info.Register.Type = ND_REG_TILE; operand->Info.Register.Size = size; operand->Info.Register.Reg = Instrux->ModRm.rm; @@ -2971,11 +3210,21 @@ memory: return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } + // #UD of B4 is not 0. + if (Instrux->FeatMode & ND_FEAT_APX) + { + if (Instrux->Exs.b4 != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + break; case ND_OPT_vT: // Tile register encoded in vex.vvvv field. operand->Type = ND_OP_REG; + operand->Encoding = ND_OPE_V; operand->Info.Register.Type = ND_REG_TILE; operand->Info.Register.Size = size; operand->Info.Register.Reg = Instrux->Exs.v; @@ -2986,18 +3235,38 @@ memory: return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; } + // #UD of V4 is not 0. + if (Instrux->FeatMode & ND_FEAT_APX) + { + if (Instrux->Exs.vp != 0) + { + return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION; + } + } + + break; + + case ND_OPT_dfv: + // Default flags value encoded in vex.vvvv field. + operand->Type = ND_OP_DFV; + operand->Encoding = ND_OPE_V; + operand->Info.DefaultFlags.CF = (Instrux->Exs.v >> 0) & 1; + operand->Info.DefaultFlags.ZF = (Instrux->Exs.v >> 1) & 1; + operand->Info.DefaultFlags.SF = (Instrux->Exs.v >> 2) & 1; + operand->Info.DefaultFlags.OF = (Instrux->Exs.v >> 3) & 1; + operand->Size = 0; break; default: return ND_STATUS_INVALID_INSTRUX; } - // Handle block addressing - used by AVX512_4FMAPS and AVX512_4VNNIW instructions. Also used by VP2INTERSECTD/Q - // instructions. Also note that in block addressing, the base of the block is masked using the size of the block; - // for example, for a block size of 1, the first register must be even; For a block size of 4, the first register - // must be divisible by 4. if (operand->Type == ND_OP_REG) { + // Handle block addressing - used by AVX512_4FMAPS and AVX512_4VNNIW instructions. Also used by VP2INTERSECTD/Q + // instructions. Also note that in block addressing, the base of the block is masked using the size of the block; + // for example, for a block size of 1, the first register must be even; For a block size of 4, the first register + // must be divisible by 4. if (opb != 0) { operand->Info.Register.Count = opb; @@ -3008,14 +3277,15 @@ memory: { operand->Info.Register.Count = 1; } + + // Handle zero-upper semantic for destination operands. Applies to destination registers only. + if ((Instrux->HasNd || Instrux->HasZu) && operand->Access.Write && !operand->Flags.IsDefault) + { + operand->Info.Register.IsZeroUpper = 1; + } } - // Store the operand encoding inside the bitmap. - Instrux->OperandsEncodingMap |= (1 << gOperandMap[opt]); - - operand->Encoding = (ND_OPERAND_ENCODING)gOperandMap[opt]; - - // Handle decorators. + // Handle decorators. Note that only Mask, Zero and Broadcast are stored per-operand. if (0 != opd) { // Check for mask register. Mask if present only if the operand supports masking and if the @@ -3023,12 +3293,12 @@ memory: if ((opd & ND_OPD_MASK) && (Instrux->HasMask)) { operand->Decorator.HasMask = ND_TRUE; - operand->Decorator.Mask.Msk = (ND_UINT8)Instrux->Exs.k; + operand->Decorator.Msk = (ND_UINT8)Instrux->Exs.k; } // Check for zeroing. The operand must support zeroing and the z bit inside evex3 must be set. Note that // zeroing is allowed only for register destinations, and NOT for memory. - if ((opd & ND_OPD_Z) && (Instrux->HasZero)) + if ((opd & ND_OPD_ZERO) && (Instrux->HasZero)) { if (operand->Type == ND_OP_MEM) { @@ -3042,18 +3312,6 @@ memory: if ((opd & ND_OPD_BCAST) && (Instrux->HasBroadcast)) { operand->Decorator.HasBroadcast = ND_TRUE; - operand->Decorator.Broadcast.Size = (ND_UINT8)operand->Size; - operand->Decorator.Broadcast.Count = (ND_UINT8)(bcstSize / operand->Size); - } - - if (opd & ND_OPD_SAE) - { - operand->Decorator.HasSae = Instrux->HasSae; - } - - if (opd & ND_OPD_ER) - { - operand->Decorator.HasEr = Instrux->HasEr; } } @@ -3068,22 +3326,19 @@ static NDSTATUS NdFindInstruction( INSTRUX *Instrux, const ND_UINT8 *Code, - ND_UINT8 Offset, ND_SIZET Size, - ND_INSTRUCTION **InsDef + ND_IDBE **InsDef ) { NDSTATUS status; const ND_TABLE *pTable; - ND_INSTRUCTION *pIns; + ND_IDBE *pIns; ND_BOOL stop, redf2, redf3; - ND_UINT32 nextOpcode, nextIndex; - - UNREFERENCED_PARAMETER(Offset); + ND_UINT32 nextOpcode; // pre-init status = ND_STATUS_SUCCESS; - pIns = (ND_INSTRUCTION *)ND_NULL; + pIns = (ND_IDBE *)ND_NULL; stop = ND_FALSE; nextOpcode = 0; redf2 = redf3 = ND_FALSE; @@ -3091,16 +3346,25 @@ NdFindInstruction( switch (Instrux->EncMode) { case ND_ENCM_LEGACY: - pTable = (const ND_TABLE *)gRootTable; + if (Instrux->Rex2.m0 == 1) + { + // Legacy map ID 1. + pTable = (const ND_TABLE*)gLegacyMap_opcode.Table[0x0F]; + } + else + { + // Legacy map ID 0. + pTable = (const ND_TABLE*)&gLegacyMap_opcode; + } break; case ND_ENCM_XOP: - pTable = (const ND_TABLE *)gXopTable; + pTable = (const ND_TABLE *)gXopMap_mmmmm.Table[Instrux->Exs.m]; break; case ND_ENCM_VEX: - pTable = (const ND_TABLE *)gVexTable; + pTable = (const ND_TABLE *)gVexMap_mmmmm.Table[Instrux->Exs.m]; break; case ND_ENCM_EVEX: - pTable = (const ND_TABLE *)gEvexTable; + pTable = (const ND_TABLE *)gEvexMap_mmmmm.Table[Instrux->Exs.m]; break; default: pTable = (const ND_TABLE *)ND_NULL; @@ -3113,7 +3377,7 @@ NdFindInstruction( { case ND_ILUT_INSTRUCTION: // We've found the leaf entry, which is an instruction - we can leave. - pIns = (ND_INSTRUCTION *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction); + pIns = (ND_IDBE *)(((ND_TABLE_INSTRUCTION *)pTable)->Instruction); stop = ND_TRUE; break; @@ -3125,23 +3389,16 @@ NdFindInstruction( stop = ND_TRUE; break; } + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpCodeBytes[nextOpcode++]]; break; - case ND_ILUT_OPCODE_3DNOW: + case ND_ILUT_OPCODE_LAST: // We need an opcode to select the next table, but the opcode is AFTER the modrm/sib/displacement. if (!Instrux->HasModRm) { - // Fetch modrm - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - stop = ND_TRUE; - break; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + // Fetch modrm, SIB & displacement + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); if (!ND_SUCCESS(status)) { stop = ND_TRUE; @@ -3164,16 +3421,8 @@ NdFindInstruction( // We need modrm.mod to select the next table. if (!Instrux->HasModRm) { - // Fetch modrm - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - stop = ND_TRUE; - break; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + // Fetch modrm, SIB & displacement + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); if (!ND_SUCCESS(status)) { stop = ND_TRUE; @@ -3189,16 +3438,8 @@ NdFindInstruction( // We need modrm.reg to select the next table. if (!Instrux->HasModRm) { - // Fetch modrm - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - stop = ND_TRUE; - break; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + // Fetch modrm, SIB & displacement + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); if (!ND_SUCCESS(status)) { stop = ND_TRUE; @@ -3214,16 +3455,8 @@ NdFindInstruction( // We need modrm.rm to select the next table. if (!Instrux->HasModRm) { - // Fetch modrm - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - stop = ND_TRUE; - break; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + // Fetch modrm, SIB & displacement + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); if (!ND_SUCCESS(status)) { stop = ND_TRUE; @@ -3242,124 +3475,120 @@ NdFindInstruction( // We can only redirect once through one mandatory prefix, otherwise we may // enter an infinite loop (see CRC32 Gw Eb -> 0x66 0xF2 0x0F ...) redf2 = ND_TRUE; - nextIndex = ND_ILUT_INDEX_MAN_PREF_F2; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_F2]; Instrux->HasMandatoryF2 = ND_TRUE; } else if ((Instrux->Rep == 0xF3) && !redf3) { redf3 = ND_TRUE; - nextIndex = ND_ILUT_INDEX_MAN_PREF_F3; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_F3]; Instrux->HasMandatoryF3 = ND_TRUE; } else if (Instrux->HasOpSize) { - nextIndex = ND_ILUT_INDEX_MAN_PREF_66; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_66]; Instrux->HasMandatory66 = ND_TRUE; } else { - nextIndex = ND_ILUT_INDEX_MAN_PREF_NONE; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MAN_PREF_NP]; } - pTable = (const ND_TABLE *)pTable->Table[nextIndex]; break; case ND_ILUT_MODE: + if (ND_NULL != pTable->Table[Instrux->DefCode + 1]) { - static const ND_UINT8 indexes[3] = - { - ND_ILUT_INDEX_MODE_16, ND_ILUT_INDEX_MODE_32, ND_ILUT_INDEX_MODE_64 - }; - - nextIndex = ND_ILUT_INDEX_MODE_NONE; - - if (ND_NULL != pTable->Table[indexes[Instrux->DefCode]]) - { - nextIndex = indexes[Instrux->DefCode]; - } - - pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode + 1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_MODE_NONE]; } break; case ND_ILUT_DSIZE: + // Handle default/forced redirections in 64 bit mode. + if (ND_CODE_64 == Instrux->DefCode) { - static const ND_UINT8 indexes[3] = + // 64-bit mode, we may have forced/default operand sizes. + if ((ND_NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w)) { - ND_ILUT_INDEX_DSIZE_16, ND_ILUT_INDEX_DSIZE_32, ND_ILUT_INDEX_DSIZE_64 - }; - - nextIndex = ND_ILUT_INDEX_DSIZE_NONE; - - if (ND_NULL != pTable->Table[indexes[Instrux->OpMode]]) - { - nextIndex = indexes[Instrux->OpMode]; + pTable = (const ND_TABLE *)pTable->Table[4]; } - - // Handle default/forced redirections in 64 bit mode. - if (ND_CODE_64 == Instrux->DefCode) + else if (ND_NULL != pTable->Table[5]) { - if ((ND_NULL != pTable->Table[4]) && (!Instrux->HasOpSize || Instrux->Exs.w)) - { - nextIndex = 4; - } - else if (ND_NULL != pTable->Table[5]) - { - nextIndex = 5; - } + pTable = (const ND_TABLE *)pTable->Table[5]; } - - pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + else if (ND_NULL != pTable->Table[Instrux->OpMode + 1]) + { + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpMode + 1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_DSIZE_NONE]; + } + } + else if (ND_NULL != pTable->Table[Instrux->OpMode + 1]) + { + pTable = (const ND_TABLE *)pTable->Table[Instrux->OpMode + 1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_DSIZE_NONE]; } break; case ND_ILUT_ASIZE: + if (ND_NULL != pTable->Table[Instrux->AddrMode + 1]) { - static const ND_UINT8 indexes[3] = {ND_ILUT_INDEX_ASIZE_16, ND_ILUT_INDEX_ASIZE_32, ND_ILUT_INDEX_ASIZE_64}; - - nextIndex = ND_ILUT_INDEX_ASIZE_NONE; - - if (ND_NULL != pTable->Table[indexes[Instrux->AddrMode]]) - { - nextIndex = indexes[Instrux->AddrMode]; - } - - pTable = (const ND_TABLE *)pTable->Table[nextIndex]; + pTable = (const ND_TABLE *)pTable->Table[Instrux->AddrMode + 1]; + } + else + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_ASIZE_NONE]; } break; case ND_ILUT_AUXILIARY: // Auxiliary redirection. Default to table[0] if nothing matches. - if (Instrux->HasRex && Instrux->Rex.b && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB])) + if ((Instrux->Exs.b || Instrux->Exs.b4) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB])) { - nextIndex = ND_ILUT_INDEX_AUX_REXB; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REXB]; } - else if (Instrux->HasRex && Instrux->Rex.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW])) + else if (Instrux->Exs.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW])) { - nextIndex = ND_ILUT_INDEX_AUX_REXW; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REXW]; } - else if ((Instrux->DefCode == ND_CODE_64) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_O64])) + else if ((Instrux->DefCode == ND_CODE_64) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_MO64])) { - nextIndex = ND_ILUT_INDEX_AUX_O64; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_MO64]; } - else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_F3])) + else if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REPZ])) { - nextIndex = ND_ILUT_INDEX_AUX_F3; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REPZ]; } else if ((Instrux->Rep != 0) && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REP])) { - nextIndex = ND_ILUT_INDEX_AUX_REP; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REP]; } else if (Instrux->DefCode == ND_CODE_64 && Instrux->HasModRm && Instrux->ModRm.mod == 0 && Instrux->ModRm.rm == NDR_RBP && ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_RIPREL]) { - nextIndex = ND_ILUT_INDEX_AUX_RIPREL; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_RIPREL]; + } + else if (Instrux->HasRex2 && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX2])) + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REX2]; + } + else if (Instrux->HasRex2 && Instrux->Rex2.w && (ND_NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX2W])) + { + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_REX2W]; } else { - nextIndex = ND_ILUT_INDEX_AUX_NONE; + pTable = (const ND_TABLE *)pTable->Table[ND_ILUT_INDEX_AUX_NONE]; } - pTable = (const ND_TABLE *)pTable->Table[nextIndex]; break; case ND_ILUT_VENDOR: @@ -3398,33 +3627,27 @@ NdFindInstruction( } break; - case ND_ILUT_VEX_MMMMM: + case ND_ILUT_EX_M: pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.m]; break; - case ND_ILUT_VEX_PP: + case ND_ILUT_EX_PP: pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.p]; break; - case ND_ILUT_VEX_L: - if (Instrux->HasEvex && Instrux->Exs.bm) + case ND_ILUT_EX_L: + if (Instrux->HasEvex && Instrux->Exs.m != 4 && Instrux->Exs.bm) { // We have evex; we need to fetch the modrm now, because we have to make sure we don't have SAE or ER; // if we do have SAE or ER, we have to check the modrm byte and see if it is a reg-reg form (mod = 3), // in which case L'L is forced to the maximum vector length of the instruction. We know for sure that // all EVEX instructions have modrm. + // Skip these checks for EVEX map 4, which are legacy instructions promoted to EVEX, and which do not + // support SAE, ER or broadcast. if (!Instrux->HasModRm) { - // Fetch modrm - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - stop = ND_TRUE; - break; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); + // Fetch modrm, SIB & displacement + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); if (!ND_SUCCESS(status)) { stop = ND_TRUE; @@ -3461,14 +3684,29 @@ NdFindInstruction( } break; - case ND_ILUT_VEX_W: + case ND_ILUT_EX_W: pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w]; break; - case ND_ILUT_VEX_WI: + case ND_ILUT_EX_WI: pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode == ND_CODE_64 ? Instrux->Exs.w : 0]; break; + case ND_ILUT_EX_ND: + // New data modified field encoded in EVEX payload byte 3. + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.nd]; + break; + + case ND_ILUT_EX_NF: + // No flags modifier field encoded in EVEX payload byte 3. + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.nf]; + break; + + case ND_ILUT_EX_SC: + // Standard condition field encoded in EVEX payload byte 3. + pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.sc]; + break; + default: status = ND_STATUS_INTERNAL_ERROR; stop = ND_TRUE; @@ -3476,66 +3714,48 @@ NdFindInstruction( } } + // Error - leave now. if (!ND_SUCCESS(status)) { goto cleanup_and_exit; } - if (ND_NULL != pIns) - { - // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now. - if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm)) - { - if (0 == (pIns->Attributes & ND_FLAG_MFR)) - { - // Fetch Mod R/M and SIB. - status = NdFetchModrmAndSib(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - goto cleanup_and_exit; - } - - // Fetch displacement. - status = NdFetchDisplacement(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - goto cleanup_and_exit; - } - } - else - { - // Handle special MOV with control and debug registers - the mod is always forced to register. SIB - // and displacement is ignored. - status = NdFetchModrm(Instrux, Code, Instrux->Length, Size); - if (!ND_SUCCESS(status)) - { - goto cleanup_and_exit; - } - } - } - - // Store primary opcode. - Instrux->PrimaryOpCode = Instrux->OpCodeBytes[Instrux->OpLength - 1]; - - Instrux->MainOpOffset = ND_IS_3DNOW(Instrux) ? - Instrux->Length - 1 : Instrux->OpOffset + Instrux->OpLength - 1; - - // Make sure the instruction is valid in the given mode. - if ((ND_CODE_64 == Instrux->DefCode) && (pIns->Attributes & ND_FLAG_I64)) - { - status = ND_STATUS_INVALID_ENCODING_IN_MODE; - } - - if ((ND_CODE_64 != Instrux->DefCode) && (pIns->Attributes & ND_FLAG_O64)) - { - status = ND_STATUS_INVALID_ENCODING_IN_MODE; - } - } - else + // No encoding found - leave now. + if (ND_NULL == pIns) { status = ND_STATUS_INVALID_ENCODING; + goto cleanup_and_exit; } + // Bingo! Valid instruction found for the encoding. If Modrm is needed and we didn't fetch it - do it now. + if ((pIns->Attributes & ND_FLAG_MODRM) && (!Instrux->HasModRm)) + { + if (0 == (pIns->Attributes & ND_FLAG_MFR)) + { + // Fetch Mod R/M, SIB & displacement. + status = NdFetchModrmSibDisplacement(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + else + { + // Handle special MOV with control and debug registers - the mod is always forced to register. SIB + // and displacement is ignored. + status = NdFetchModrm(Instrux, Code, Instrux->Length, Size); + if (!ND_SUCCESS(status)) + { + goto cleanup_and_exit; + } + } + } + + // Store primary opcode. + Instrux->PrimaryOpCode = Instrux->OpCodeBytes[Instrux->OpLength - 1]; + + Instrux->MainOpOffset = ND_IS_3DNOW(Instrux) ? Instrux->Length - 1 : Instrux->OpOffset + Instrux->OpLength - 1; + cleanup_and_exit: *InsDef = pIns; @@ -3543,11 +3763,117 @@ cleanup_and_exit: } +// +// NdGetAddrAndOpMode +// +static NDSTATUS +NdGetAddrAndOpMode( + INSTRUX *Instrux + ) +{ + // Fill in addressing mode & default op size. + switch (Instrux->DefCode) + { + case ND_CODE_16: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_16; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_16 : ND_ADDR_32; + Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_64; + Instrux->OpMode = Instrux->Exs.w ? ND_OPSZ_64 : (Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32); + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetEffectiveAddrAndOpMode +// +static NDSTATUS +NdGetEffectiveAddrAndOpMode( + INSTRUX *Instrux + ) +{ + static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; + ND_BOOL w64, f64, d64, has66; + + if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64)) + { + // Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0. + Instrux->Exs.w = 0; + } + + // Extract the flags. + w64 = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG); + + // In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored. + f64 = 0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD != Instrux->VendMode); + + // In 64 bit mode, the operand defaults to 64 bit. No 32 bit form of the instruction exists. Note that on AMD, + // only default 64 bit operands exist, even for branches - no operand is forced to 64 bit. + d64 = (0 != (Instrux->Attributes & ND_FLAG_D64)) || + (0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD == Instrux->VendMode)); + + // Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix, + // then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32 + // have mandatory 0xF2, and 0x66 is in fact a size changing prefix. + // For legacy instructions promoted to EVEX, in some cases, the compressed prefix pp has the same meaning + // as the legacy 0x66 prefix. + has66 = (Instrux->HasOpSize && (!Instrux->HasMandatory66 || (Instrux->Attributes & ND_FLAG_S66))) || + ((Instrux->Exs.p == 1) && (Instrux->Attributes & ND_FLAG_SCALABLE)); + + // Fill in the effective operand size. Also validate instruction validity in given mode. + switch (Instrux->DefCode) + { + case ND_CODE_16: + if (Instrux->Attributes & ND_FLAG_O64) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + Instrux->EfOpMode = has66 ? ND_OPSZ_32 : ND_OPSZ_16; + break; + case ND_CODE_32: + if (Instrux->Attributes & ND_FLAG_O64) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + Instrux->EfOpMode = has66 ? ND_OPSZ_16 : ND_OPSZ_32; + break; + case ND_CODE_64: + // Make sure instruction valid in mode. + if (Instrux->Attributes & ND_FLAG_I64) + { + return ND_STATUS_INVALID_ENCODING_IN_MODE; + } + + Instrux->EfOpMode = (w64 || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32); + Instrux->AddrMode = !!(Instrux->Attributes & ND_FLAG_I67) ? ND_ADDR_64 : Instrux->AddrMode; + break; + default: + return ND_STATUS_INVALID_INSTRUX; + } + + // Fill in the default word length. It can't be more than 8 bytes. + Instrux->WordLength = szLut[Instrux->EfOpMode]; + + return ND_STATUS_SUCCESS; +} + // // NdGetVectorLength // -static inline NDSTATUS +static NDSTATUS NdGetVectorLength( INSTRUX *Instrux ) @@ -3600,186 +3926,264 @@ NdGetVectorLength( // -// NdGetAddrAndOpMode -// -static inline NDSTATUS -NdGetAddrAndOpMode( - INSTRUX *Instrux - ) -{ - // Fill in addressing mode & default op size. - switch (Instrux->DefCode) - { - case ND_CODE_16: - Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_16; - Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_32 : ND_OPSZ_16; - break; - case ND_CODE_32: - Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_16 : ND_ADDR_32; - Instrux->OpMode = Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32; - break; - case ND_CODE_64: - Instrux->AddrMode = Instrux->HasAddrSize ? ND_ADDR_32 : ND_ADDR_64; - Instrux->OpMode = Instrux->Exs.w ? ND_OPSZ_64 : (Instrux->HasOpSize ? ND_OPSZ_16 : ND_OPSZ_32); - break; - default: - return ND_STATUS_INVALID_INSTRUX; - } - - return ND_STATUS_SUCCESS; -} - - -// -// NdGetEffectiveOpMode -// -static inline NDSTATUS -NdGetEffectiveOpMode( - INSTRUX *Instrux - ) -{ - static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT }; - ND_BOOL width, f64, d64, has66; - - if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64)) - { - // Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0. - Instrux->Exs.w = 0; - } - - // Extract the flags. - width = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG); - // In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored. - f64 = 0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD != Instrux->VendMode); - // In 64 bit mode, the operand defaults to 64 bit. No 32 bit form of the instruction exists. Note that on AMD, - // only default 64 bit operands exist, even for branches - no operand is forced to 64 bit. - d64 = (0 != (Instrux->Attributes & ND_FLAG_D64)) || - (0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD == Instrux->VendMode)); - // Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix, - // then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32 - // have mandatory 0xF2, and 0x66 is in fact a size changing prefix. - has66 = Instrux->HasOpSize && (!Instrux->HasMandatory66 || (Instrux->Attributes & ND_FLAG_S66)); - - // Fill in the effective operand size. - switch (Instrux->DefCode) - { - case ND_CODE_16: - Instrux->EfOpMode = has66 ? ND_OPSZ_32 : ND_OPSZ_16; - break; - case ND_CODE_32: - Instrux->EfOpMode = has66 ? ND_OPSZ_16 : ND_OPSZ_32; - break; - case ND_CODE_64: - Instrux->EfOpMode = (width || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32); - Instrux->AddrMode = !!(Instrux->Attributes & ND_FLAG_I67) ? ND_ADDR_64 : Instrux->AddrMode; - break; - default: - return ND_STATUS_INVALID_INSTRUX; - } - - // Fill in the default word length. It can't be more than 8 bytes. - Instrux->WordLength = szLut[Instrux->EfOpMode]; - - return ND_STATUS_SUCCESS; -} - - -// -// NdPostProcessEvex +// NdLegacyPrefixChecks // static NDSTATUS -NdPostProcessEvex( +NdLegacyPrefixChecks( INSTRUX *Instrux ) { - // Handle embedded broadcast/rounding-control. - if (Instrux->Exs.bm == 1) + // These checks only apply to legacy encoded instructions. + + // Check for LOCK. LOCK can be present only in two cases: + // 1. For certain RMW instructions, as long as the destination operand is memory + // 2. For MOV to/from CR0 in 32-bit mode on AMD CPUs, which allows access to CR8 + // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix). + if (Instrux->HasLock) { - if (Instrux->ModRm.mod == 3) + if (0 != (Instrux->Attributes & ND_FLAG_LOCK_SPECIAL) && (ND_CODE_32 == Instrux->DefCode)) { - // reg form for the instruction, check for ER or SAE support. - if (Instrux->ValidDecorators.Er) - { - Instrux->HasEr = 1; - Instrux->HasSae = 1; - Instrux->RoundingMode = (ND_UINT8)Instrux->Exs.l; - } - else if (Instrux->ValidDecorators.Sae) - { - Instrux->HasSae = 1; - } - else if (!!(Instrux->Attributes & ND_FLAG_IER)) - { - // The encoding behaves as if embedded rounding is enabled, but it is in fact ignored. - Instrux->HasIgnEr = 1; - } - else - { - return ND_STATUS_ER_SAE_NOT_SUPPORTED; - } + // Special case of LOCK being used by MOV cr to access CR8. + } + else if (Instrux->ValidPrefixes.Lock && (Instrux->Operands[0].Type == ND_OP_MEM)) + { + Instrux->IsLockEnabled = 1; } else { - // mem form for the instruction, check for broadcast. - if (Instrux->ValidDecorators.Broadcast) + return ND_STATUS_BAD_LOCK_PREFIX; + } + } + + // Chec for REP prefixes. There are multiple uses: + // 1. REP/REPNZ/REPZ, for string/IO instructions + // 2. XACQUIRE/XRELEASE, for HLE-enabled instructions + // 3. BND prefix, for branches + // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix). + if (Instrux->Rep != 0) + { + if (Instrux->Attributes & ND_FLAG_NOREP) + { + return ND_STATUS_INVALID_ENCODING; + } + + Instrux->IsRepEnabled = Instrux->ValidPrefixes.Rep != 0; + + Instrux->IsRepcEnabled = Instrux->ValidPrefixes.RepCond != 0; + + // Bound enablement. + Instrux->IsBndEnabled = (Instrux->ValidPrefixes.Bnd != 0) && (Instrux->Rep == ND_PREFIX_G1_BND); + + // Check if the instruction is REPed. + Instrux->IsRepeated = Instrux->IsRepEnabled || Instrux->IsRepcEnabled; + + // Check if the instruction is XACQUIRE or XRELEASE enabled. + if ((Instrux->IsLockEnabled || Instrux->ValidPrefixes.HleNoLock) && + (Instrux->Operands[0].Type == ND_OP_MEM)) + { + if ((Instrux->ValidPrefixes.Xacquire || Instrux->ValidPrefixes.Hle) && + (Instrux->Rep == ND_PREFIX_G1_XACQUIRE)) { - Instrux->HasBroadcast = 1; + Instrux->IsXacquireEnabled = ND_TRUE; } - else + else if ((Instrux->ValidPrefixes.Xrelease || Instrux->ValidPrefixes.Hle) && + (Instrux->Rep == ND_PREFIX_G1_XRELEASE)) { - return ND_STATUS_BROADCAST_NOT_SUPPORTED; + Instrux->IsXreleaseEnabled = ND_TRUE; } } } - // Handle masking. - if (Instrux->Exs.k != 0) + // Check for segment prefixes. Besides offering segment override when accessing memory: + // 1. Allow for branch hints to conditional branches + // 2. Allow for Do Not Track prefix for indirect branches, to inhibit CET-IBT tracking + // Segment prefixes are allowed with XOP/VEX/EVEX instructions, but they have the legacy meaning (no BHINT or DNT). + if (Instrux->Seg != 0) { - if (Instrux->ValidDecorators.Mask) + // Branch hint enablement. + Instrux->IsBhintEnabled = Instrux->ValidPrefixes.Bhint && ( + (Instrux->Seg == ND_PREFIX_G2_BR_TAKEN) || + (Instrux->Seg == ND_PREFIX_G2_BR_NOT_TAKEN) || + (Instrux->Seg == ND_PREFIX_G2_BR_ALT)); + + // Do-not-track hint enablement. + Instrux->IsDntEnabled = Instrux->ValidPrefixes.Dnt && (Instrux->Seg == ND_PREFIX_G2_NO_TRACK); + } + + // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix). + if (Instrux->HasOpSize && (Instrux->Attributes & ND_FLAG_NO66)) + { + return ND_STATUS_INVALID_ENCODING; + } + + // Address size override is allowed with all XOP/VEX/EVEX prefixes. + if (Instrux->HasAddrSize && (Instrux->Attributes & ND_FLAG_NO67)) + { + return ND_STATUS_INVALID_ENCODING; + } + + // For XOP/VEX/EVEX instructions, a #UD is generated (which is checked when fetching the XOP/VEX/EVEX prefix). + if (Instrux->HasRex2 && (Instrux->Attributes & ND_FLAG_NOREX2)) + { + return ND_STATUS_INVALID_ENCODING; + } + + // Check if the instruction is CET tracked. The do not track prefix (0x3E) works only for indirect near JMP and CALL + // instructions. It is always enabled for far JMP and CALL instructions. + Instrux->IsCetTracked = ND_HAS_CETT(Instrux) && !Instrux->IsDntEnabled; + + return ND_STATUS_SUCCESS; +} + + +// +// NdGetEvexFields +// +static NDSTATUS +NdGetEvexFields( + INSTRUX *Instrux + ) +{ + // Validate the EVEX prefix, depending on the EVEX extension mode. + if (Instrux->EvexMode == ND_EVEXM_EVEX) + { + // Handle embedded broadcast/rounding-control. + if (Instrux->Exs.bm == 1) { - Instrux->HasMask = 1; + if (Instrux->ModRm.mod == 3) + { + // reg form for the instruction, check for ER or SAE support. + if (Instrux->ValidDecorators.Er) + { + Instrux->HasEr = 1; + Instrux->HasSae = 1; + Instrux->RoundingMode = (ND_UINT8)Instrux->Exs.l; + } + else if (Instrux->ValidDecorators.Sae) + { + Instrux->HasSae = 1; + } + else if (!!(Instrux->Attributes & ND_FLAG_IER)) + { + // The encoding behaves as if embedded rounding is enabled, but it is in fact ignored. + Instrux->HasIgnEr = 1; + } + else + { + return ND_STATUS_ER_SAE_NOT_SUPPORTED; + } + } + else + { + // mem form for the instruction, check for broadcast. + if (Instrux->ValidDecorators.Broadcast) + { + Instrux->HasBroadcast = 1; + } + else + { + return ND_STATUS_BROADCAST_NOT_SUPPORTED; + } + } + } + + // Handle masking. + if (Instrux->Exs.k != 0) + { + if (Instrux->ValidDecorators.Mask) + { + Instrux->HasMask = 1; + } + else + { + return ND_STATUS_MASK_NOT_SUPPORTED; + } } else { - return ND_STATUS_MASK_NOT_SUPPORTED; + if (!!(Instrux->Attributes & ND_FLAG_MMASK)) + { + return ND_STATUS_MASK_REQUIRED; + } } + + // Handle zeroing. + if (Instrux->Exs.z != 0) + { + if (Instrux->ValidDecorators.Zero) + { + // Zeroing restrictions: + // - valid with register only; + // - valid only if masking is also used; + if (Instrux->HasMask) + { + Instrux->HasZero = 1; + } + else + { + return ND_STATUS_ZEROING_NO_MASK; + } + } + else + { + return ND_STATUS_ZEROING_NOT_SUPPORTED; + } + } + + // EVEX instructions with 8 bit displacement use compressed displacement addressing, where the displacement + // is scaled according to the data type accessed by the instruction. + if (Instrux->HasDisp && Instrux->DispLength == 1) + { + Instrux->HasCompDisp = ND_TRUE; + } + + // Legacy EVEX. + Instrux->Exs.nd = 0; + Instrux->Exs.nf = 0; + Instrux->Exs.sc = 0; } else { - if (!!(Instrux->Attributes & ND_FLAG_MMASK)) - { - return ND_STATUS_MASK_REQUIRED; - } - } + // EVEX extension for VEX/Legacy/Conditional instructions. + const ND_UINT8 b3mask[4] = + { // Bit 7 6 5 4 3 2 1 0 + 0x00, // Regular form: | z | L | L | b | V4 | a | a | a | + 0xD3, // VEX form: | 0 | 0 | L | 0 | V4 | NF | 0 | 0 | + 0xE3, // Legacy form: | 0 | 0 | 0 | ND | V4 | NF | 0 | 0 | + 0xE0, // Cond form: | 0 | 0 | 0 | ND | SC3 | SC2 | SC1 | SC0 | + }; - // Handle zeroing. - if (Instrux->Exs.z != 0) - { - if (Instrux->ValidDecorators.Zero) + // EVEX flavors are only valid in APX mode. Outside APX, only legacy EVEX is valid. + if (0 == (Instrux->FeatMode & ND_FEAT_APX)) { - // Zeroing restrictions: - // - valid with register only; - // - valid only if masking is also used; - if (Instrux->HasMask) - { - Instrux->HasZero = 1; - } - else - { - return ND_STATUS_ZEROING_NO_MASK; - } + return ND_STATUS_INVALID_ENCODING; } - else - { - return ND_STATUS_ZEROING_NOT_SUPPORTED; - } - } - // EVEX instructions with 8 bit displacement use compressed displacement addressing, where the displacement - // is scaled according to the data type accessed by the instruction. - if (Instrux->HasDisp && Instrux->DispLength == 1) - { - Instrux->HasCompDisp = ND_TRUE; + // Apply EVEX payload byte 3 mask. + if (0 != (Instrux->Evex.Evex[3] & b3mask[Instrux->EvexMode])) + { + return ND_STATUS_INVALID_EVEX_BYTE3; + } + + if (Instrux->ValidDecorators.Nd) + { + Instrux->HasNd = (ND_BOOL)Instrux->Exs.nd; + } + + if (Instrux->ValidDecorators.Nf) + { + Instrux->HasNf = (ND_BOOL)Instrux->Exs.nf; + } + + if (Instrux->ValidDecorators.Zu) + { + Instrux->HasZu = (ND_BOOL)Instrux->Exs.nd; + } + + Instrux->Exs.z = 0; + Instrux->Exs.l = 0; + Instrux->Exs.bm = 0; + Instrux->Exs.k = 0; } return ND_STATUS_SUCCESS; @@ -3787,122 +4191,136 @@ NdPostProcessEvex( // -// NdValidateInstruction +// NdVexExceptionChecks // -static inline NDSTATUS -NdValidateInstruction( +static NDSTATUS +NdVexExceptionChecks( INSTRUX *Instrux ) { - // If LOCK is present, make sure that the instruction 1. supports LOCKing and 2. the destination is memory. - // A special case are MOV to/from CRs, on AMD, in 16/32 bit mode. - if (Instrux->HasLock && (0 == (Instrux->Attributes & ND_FLAG_LOCK_SPECIAL) || (ND_CODE_64 == Instrux->DefCode)) && - (!ND_LOCK_SUPPORT(Instrux) || (Instrux->Operands[0].Type != ND_OP_MEM))) + // These checks only apply to XOP/VEX/EVEX encoded instructions. + + // Instructions that don't use VEX/XOP/EVEX vvvv field must set it to 1111b/0 logic, otherwise a #UD will + // be generated. + if ((Instrux->Attributes & ND_FLAG_NOV) && (0 != Instrux->Exs.v)) { - return ND_STATUS_BAD_LOCK_PREFIX; + return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; } - // Some instructions (example: PTWRITE) do not accept the 0x66 prefix. - if (Instrux->HasOpSize && (0 != (Instrux->Attributes & ND_FLAG_NO66))) + // Instruction that don't use EVEX.V' field must set to to 1b/0 logic, otherwise a #UD will be generated. + if ((Instrux->Attributes & ND_FLAG_NOVP) && (0 != Instrux->Exs.vp)) { - return ND_STATUS_66_NOT_ACCEPTED; + return ND_STATUS_BAD_EVEX_V_PRIME; } - // 16 bit addressing is checked when decoding the memory operand (if present). - // RIP-relative addressing is checked when decoding the memory operand (if present). - // Register validity is checked when decoding the said register. - // Memory/register encoding for instructions which don't support it is checked when decoding the operand. - - // VEX/EVEX validations. - if (ND_ENCM_LEGACY != Instrux->EncMode) + // VSIB instructions have a restriction: the same vector register can't be used by more than one operand. + // The exception is SCATTER*, which can use the VSIB reg as two sources. + if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER) { - // Instructions that don't use VEX/XOP/EVEX vvvv field must set it to 1111b/0, otherwise a #UD will be generated. - if ((0 == (Instrux->OperandsEncodingMap & (1 << ND_OPE_V))) && (0 != Instrux->Exs.v)) - { - return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; - } + ND_UINT8 usedVects[32] = { 0 }; + ND_UINT32 i; - // Instruction that don't use EVEX.V' field must set to to 1b/0, otherwise a #UD will be generated. - if ((0 == (Instrux->OperandsEncodingMap & (1 << ND_OPE_V))) && !ND_HAS_VSIB(Instrux) && (0 != Instrux->Exs.vp)) + for (i = 0; i < Instrux->OperandsCount; i++) { - return ND_STATUS_BAD_EVEX_V_PRIME; - } - - // VSIB instructions have a restriction: the same vector register can't be used by more than one operand. - // The exception is SCATTER*, which can use the VSIB reg as two sources. - if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER) - { - ND_UINT8 usedVects[32] = { 0 }; - ND_UINT32 i; - - for (i = 0; i < Instrux->OperandsCount; i++) + if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands[i].Info.Register.Type == ND_REG_SSE) { - if (Instrux->Operands[i].Type == ND_OP_REG && Instrux->Operands[i].Info.Register.Type == ND_REG_SSE) + if (++usedVects[Instrux->Operands[i].Info.Register.Reg] > 1) { - if (++usedVects[Instrux->Operands[i].Info.Register.Reg] > 1) - { - return ND_STATUS_INVALID_VSIB_REGS; - } - } - else if (Instrux->Operands[i].Type == ND_OP_MEM) - { - if (++usedVects[Instrux->Operands[i].Info.Memory.Index] > 1) - { - return ND_STATUS_INVALID_VSIB_REGS; - } + return ND_STATUS_INVALID_VSIB_REGS; } } - } - - // Handle AMX exception class. - if (Instrux->ExceptionClass == ND_EXC_AMX) - { - if (Instrux->ExceptionType == ND_EXT_AMX_E4) + else if (Instrux->Operands[i].Type == ND_OP_MEM) { - // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs. - if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg || - Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg || - Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) + if (++usedVects[Instrux->Operands[i].Info.Memory.Index] > 1) { - return ND_STATUS_INVALID_TILE_REGS; - } - } - else - { - // #UD if vex.vvvv is not 0 (0b1111 negated) for all other exception classes, as they do not use it. - if (Instrux->Exs.v != 0) - { - return ND_STATUS_VEX_VVVV_MUST_BE_ZERO; - } - } - } - - // Handle EVEX exception class. - if (Instrux->ExceptionClass == ND_EXC_EVEX) - { - // If E4* or E10* exception class is used (check out AVX512-FP16 instructions), an additional #UD case - // exists: if the destination register is equal to either of the source registers. - if (Instrux->ExceptionType == ND_EXT_E4S || Instrux->ExceptionType == ND_EXT_E10S) - { - // Note that operand 0 is the destination, operand 1 is the mask, operand 2 is first source, operand - // 3 is the second source. - - if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[2].Type == ND_OP_REG && - Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) - { - return ND_STATUS_INVALID_DEST_REGS; - } - - - if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[3].Type == ND_OP_REG && - Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[3].Info.Register.Reg) - { - return ND_STATUS_INVALID_DEST_REGS; + return ND_STATUS_INVALID_VSIB_REGS; } } } } + // Handle AMX exception class. + if (Instrux->ExceptionType == ND_EXT_AMX_E4) + { + // #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs. + if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg || + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg || + Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) + { + return ND_STATUS_INVALID_TILE_REGS; + } + } + + // If E4* or E10* exception class is used (check out AVX512-FP16 instructions), an additional #UD case + // exists: if the destination register is equal to either of the source registers. + else if (Instrux->ExceptionType == ND_EXT_E4S || Instrux->ExceptionType == ND_EXT_E10S) + { + // Note that operand 0 is the destination, operand 1 is the mask, operand 2 is first source, operand + // 3 is the second source. + if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[2].Type == ND_OP_REG && + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg) + { + return ND_STATUS_INVALID_DEST_REGS; + } + + if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[3].Type == ND_OP_REG && + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[3].Info.Register.Reg) + { + return ND_STATUS_INVALID_DEST_REGS; + } + } + + // Handle PUSH2/POP2 exceptions, which have restrictions on the destination registers. + else if (Instrux->ExceptionType == ND_EXT_APX_EVEX_PP2) + { + // The registers cannot be RSP for either PUSH2 or POP2. + if (Instrux->Operands[0].Info.Register.Reg == NDR_RSP || + Instrux->Operands[1].Info.Register.Reg == NDR_RSP) + { + return ND_STATUS_INVALID_DEST_REGS; + } + + // The destination registers cannot be the same for POP2. + if (Instrux->Operands[0].Access.Write && + Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg) + { + return ND_STATUS_INVALID_DEST_REGS; + } + } + + return ND_STATUS_SUCCESS; +} + + +// +// NdCopyInstructionInfo +// +static NDSTATUS +NdCopyInstructionInfo( + INSTRUX *Instrux, + ND_IDBE *Idbe + ) +{ + Instrux->Mnemonic = gMnemonics[Idbe->Mnemonic]; + Instrux->Attributes = Idbe->Attributes; + Instrux->Instruction = (ND_INS_CLASS)Idbe->Instruction; + Instrux->Category = (ND_INS_CATEGORY)Idbe->Category; + Instrux->IsaSet = (ND_INS_SET)Idbe->IsaSet; + Instrux->FlagsAccess.Undefined.Raw = Idbe->SetFlags & Idbe->ClearedFlags; + Instrux->FlagsAccess.Tested.Raw = Idbe->TestedFlags; + Instrux->FlagsAccess.Modified.Raw = Idbe->ModifiedFlags; + Instrux->FlagsAccess.Set.Raw = Idbe->SetFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->FlagsAccess.Cleared.Raw = Idbe->ClearedFlags ^ Instrux->FlagsAccess.Undefined.Raw; + Instrux->CpuidFlag.Flag = Idbe->CpuidFlag; + Instrux->ValidModes.Raw = Idbe->ValidModes; + Instrux->ValidPrefixes.Raw = Idbe->ValidPrefixes; + Instrux->ValidDecorators.Raw = Idbe->ValidDecorators; + *((ND_UINT8*)&Instrux->FpuFlagsAccess) = Idbe->FpuFlags; + // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used. + Instrux->ExceptionType = Idbe->ExcType; + Instrux->TupleType = Idbe->TupleType; + Instrux->EvexMode = Idbe->EvexMode; + return ND_STATUS_SUCCESS; } @@ -3944,13 +4362,12 @@ NdDecodeWithContext( ) { NDSTATUS status; - PND_INSTRUCTION pIns; + PND_IDBE pIns; ND_UINT32 opIndex; - ND_SIZET i; // pre-init status = ND_STATUS_SUCCESS; - pIns = (PND_INSTRUCTION)ND_NULL; + pIns = (PND_IDBE)ND_NULL; opIndex = 0; // validate @@ -3984,7 +4401,7 @@ NdDecodeWithContext( return ND_STATUS_INVALID_PARAMETER; } - if (ND_VEND_CYRIX < Context->VendMode) + if (ND_VEND_MAX < Context->VendMode) { return ND_STATUS_INVALID_PARAMETER; } @@ -3997,16 +4414,19 @@ NdDecodeWithContext( Instrux->DefStack = (ND_UINT8)Context->DefStack; Instrux->VendMode = (ND_UINT8)Context->VendMode; Instrux->FeatMode = (ND_UINT8)Context->FeatMode; + Instrux->EncMode = ND_ENCM_LEGACY; // Assume legacy encoding by default. - // Copy the instruction bytes. - for (opIndex = 0; opIndex < ((Size < ND_MAX_INSTRUCTION_LENGTH) ? Size : ND_MAX_INSTRUCTION_LENGTH); opIndex++) + // Fetch the instruction bytes. + for (opIndex = 0; + opIndex < ((Size < ND_MAX_INSTRUCTION_LENGTH) ? Size : ND_MAX_INSTRUCTION_LENGTH); + opIndex++) { Instrux->InstructionBytes[opIndex] = Code[opIndex]; } - // Fetch prefixes. We peek at the first byte, if that's not a prefix, there's no need to call the main decoder. - if (ND_PREF_CODE_NONE != gPrefixesMap[Instrux->InstructionBytes[0]]) + if (gPrefixesMap[Instrux->InstructionBytes[0]] != ND_PREF_CODE_NONE) { + // Fetch prefixes. We peek at the first byte, to see if it's worth calling the prefix decoder. status = NdFetchPrefixes(Instrux, Instrux->InstructionBytes, 0, Size); if (!ND_SUCCESS(status)) { @@ -4022,45 +4442,21 @@ NdDecodeWithContext( } // Start iterating the tables, in order to extract the instruction entry. - status = NdFindInstruction(Instrux, Instrux->InstructionBytes, Instrux->Length, Size, &pIns); + status = NdFindInstruction(Instrux, Instrux->InstructionBytes, Size, &pIns); if (!ND_SUCCESS(status)) { return status; } - // Instruction found, copy information inside the Instrux. - Instrux->Attributes = pIns->Attributes; - Instrux->Instruction = Instrux->Iclass = (ND_INS_CLASS)pIns->Instruction; - Instrux->Category = (ND_INS_CATEGORY)pIns->Category; - Instrux->IsaSet = (ND_INS_SET)pIns->IsaSet; - Instrux->FlagsAccess.Undefined.Raw = pIns->SetFlags & pIns->ClearedFlags; - Instrux->FlagsAccess.Tested.Raw = pIns->TestedFlags; - Instrux->FlagsAccess.Modified.Raw = pIns->ModifiedFlags; - Instrux->FlagsAccess.Set.Raw = pIns->SetFlags ^ Instrux->FlagsAccess.Undefined.Raw; - Instrux->FlagsAccess.Cleared.Raw = pIns->ClearedFlags ^ Instrux->FlagsAccess.Undefined.Raw; - Instrux->CpuidFlag.Flag = pIns->CpuidFlag; - Instrux->ValidModes.Raw = pIns->ValidModes; - Instrux->ValidPrefixes.Raw = pIns->ValidPrefixes; - Instrux->ValidDecorators.Raw = pIns->ValidDecorators; - *((ND_UINT8*)&Instrux->FpuFlagsAccess) = pIns->FpuFlags; - // Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used. - Instrux->ExceptionClass = pIns->ExcClass; - Instrux->ExceptionType = pIns->ExcType; - // Used only by EVEX instructions. - Instrux->TupleType = pIns->TupleType; - - // Copy the mnemonic, up until the ND_NULL terminator. - for (i = 0; i < sizeof(Instrux->Mnemonic); i++) + // Copy information inside the Instrux. + status = NdCopyInstructionInfo(Instrux, pIns); + if (!ND_SUCCESS(status)) { - Instrux->Mnemonic[i] = gMnemonics[pIns->Mnemonic][i]; - if (Instrux->Mnemonic[i] == 0) - { - break; - } + return status; } // Get effective operand mode. - status = NdGetEffectiveOpMode(Instrux); + status = NdGetEffectiveAddrAndOpMode(Instrux); if (!ND_SUCCESS(status)) { return status; @@ -4070,8 +4466,9 @@ NdDecodeWithContext( { // Post-process EVEX encoded instructions. This does two thing: // - check and fill in decorator info; - // - generate error for invalid broadcast/rounding, mask or zeroing bits. - status = NdPostProcessEvex(Instrux); + // - generate error for invalid broadcast/rounding, mask or zeroing bits; + // - generate error if any reserved bits are set. + status = NdGetEvexFields(Instrux); if (!ND_SUCCESS(status)) { return status; @@ -4088,20 +4485,13 @@ NdDecodeWithContext( } } - // Handle condition byte, if present. - if (ND_HAS_SSE_CONDITION(Instrux)) - { - Instrux->SseCondition = Instrux->Immediate1 & 0x1F; - } - - // Handle predicate, if present. - if (ND_HAS_CONDITION(Instrux)) - { - Instrux->Condition = Instrux->Predicate = Instrux->PrimaryOpCode & 0xF; - } - Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount); - Instrux->OperandsCount = Instrux->ExpOperandsCount + ND_IMP_OPS_CNT(pIns->OpsCount); + Instrux->OperandsCount = Instrux->ExpOperandsCount; + + if (!(Context->Options & ND_OPTION_ONLY_EXPLICIT_OPERANDS)) + { + Instrux->OperandsCount += ND_IMP_OPS_CNT(pIns->OpsCount); + } // And now decode each operand. for (opIndex = 0; opIndex < Instrux->OperandsCount; ++opIndex) @@ -4114,46 +4504,28 @@ NdDecodeWithContext( } } - // Check if the instruction is XACQUIRE or XRELEASE enabled. - if ((Instrux->Rep != 0) && (Instrux->HasLock || (!!Instrux->ValidPrefixes.HleNoLock)) && - (Instrux->Operands[0].Type == ND_OP_MEM)) + if (ND_ENCM_LEGACY == Instrux->EncMode) { - if ((ND_XACQUIRE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XACQUIRE)) + // Do legacy prefix checks. Only available for legacy instructions. For XOP/VEX/EVEX instructions: + // 1. LOCK, REP, 0x66, REX, REX2 cause #UD (checkd during XOP/VEX/EVEX fetch) + // 2. Segment prefixes do not have BHINT or DNT semantic + // 3. 0x67 can be used to override address mode + // This has to be done after operand parsing, since some #UD conditions depend on them. + status = NdLegacyPrefixChecks(Instrux); + if (!ND_SUCCESS(status)) { - Instrux->IsXacquireEnabled = ND_TRUE; - } - else if ((ND_XRELEASE_SUPPORT(Instrux) || ND_HLE_SUPPORT(Instrux)) && (Instrux->Rep == ND_PREFIX_G1_XRELEASE)) - { - Instrux->IsXreleaseEnabled = ND_TRUE; + return status; } } - - // Check if the instruction is REPed. - Instrux->IsRepeated = ((Instrux->Rep != 0) && (ND_REP_SUPPORT(Instrux) || ND_REPC_SUPPORT(Instrux))); - - // Check if the instruction is CET tracked. The do not track prefix (0x3E) works only for indirect near JMP and CALL - // instructions. It is always enabled for far JMP and CALL instructions. - Instrux->IsCetTracked = ND_HAS_CETT(Instrux) && ((!ND_DNT_SUPPORT(Instrux)) || - (Instrux->Seg != ND_PREFIX_G2_NO_TRACK)); - - // Fill in branch information. - if (!!(Instrux->RipAccess & ND_ACCESS_ANY_WRITE)) + else { - Instrux->BranchInfo.IsBranch = 1; - Instrux->BranchInfo.IsConditional = Instrux->Category == ND_CAT_COND_BR; - // Indirect branches are those which get their target address from a register or memory, including RET familly. - Instrux->BranchInfo.IsIndirect = ((!Instrux->Operands[0].Flags.IsDefault) && - ((Instrux->Operands[0].Type == ND_OP_REG) || (Instrux->Operands[0].Type == ND_OP_MEM))) || - (Instrux->Category == ND_CAT_RET); - Instrux->BranchInfo.IsFar = !!(Instrux->CsAccess & ND_ACCESS_ANY_WRITE); - } - - // Do instruction validations. These checks are made in order to filter out encodings that would normally - // be invalid and would generate #UD. - status = NdValidateInstruction(Instrux); - if (!ND_SUCCESS(status)) - { - return status; + // Do XOP/VEX/EVEX encoding checks. Additional #UD conditions, some dependent on encoded registers. + // This has to be done after operand parsing, since some #UD conditions depend on them. + status = NdVexExceptionChecks(Instrux); + if (!ND_SUCCESS(status)) + { + return status; + } } // All done! Instruction successfully decoded! diff --git a/bddisasm/bdformat.c b/bddisasm/bdx86_formatter.c similarity index 83% rename from bddisasm/bdformat.c rename to bddisasm/bdx86_formatter.c index 1de15f9..834274a 100644 --- a/bddisasm/bdformat.c +++ b/bddisasm/bdx86_formatter.c @@ -2,7 +2,7 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#include "include/nd_crt.h" +#include "include/bddisasm_crt.h" #include "../inc/bddisasm.h" @@ -18,24 +18,32 @@ static const char *gReg8Bit64[] = { "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", + "r16b", "r17b", "r18b", "r19b", "r20b", "r21b", "r22b", "r23b", + "r24b", "r25b", "r26b", "r27b", "r28b", "r29b", "r30b", "r31b", }; static const char *gReg16Bit[] = { "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w", + "r16w", "r17w", "r18w", "r19w", "r20w", "r21w", "r22w", "r23w", + "r24w", "r25w", "r26w", "r27w", "r28w", "r29w", "r30w", "r31w", }; static const char *gReg32Bit[] = { "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", + "r16d", "r17d", "r18d", "r19d", "r20d", "r21d", "r22d", "r23d", + "r24d", "r25d", "r26d", "r27d", "r28d", "r29d", "r30d", "r31d", }; static const char *gReg64Bit[] = { "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; static const char *gRegFpu[] = @@ -52,12 +60,16 @@ static const char *gRegControl[] = { "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", + "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23", + "cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31", }; static const char *gRegDebug[] = { "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", "dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15", + "dr16", "dr17", "dr18", "dr19", "dr20", "dr21", "dr22", "dr23", + "dr24", "dr25", "dr26", "dr27", "dr28", "dr29", "dr30", "dr31", }; static const char *gRegTest[] = @@ -110,21 +122,12 @@ static const char *gRegTile[] = "tmm0", "tmm1", "tmm2", "tmm3", "tmm4", "tmm5", "tmm6", "tmm7", }; -static const char *gConditionCodes[] = -{ - "EQ", "LT", "LE", "UNORD", "NEQ", "NLT", "NLE", "ORD", - "EQ_UQ", "NGE", "NGT", "ND_FALSE", "NEQ_OQ", "GE", "GT", "TRUE", - "EQ_OS", "LT_OQ", "LE_OQ", "UNORD_S", "NEQ_US", "NLT_UQ", "NLE_UQ", "ORD_S", - "EQ_US", "NGE_UQ", "NGT_UQ", "FALSE_OS", "NEQ_OS", "GE_OQ", "GT_OQ", "TRUE_US", -}; - static const char *gEmbeddedRounding[] = { "rn", "rd", "ru", "rz", }; - // // NdSprintf // @@ -217,69 +220,61 @@ NdToText( nd_memzero(temp, sizeof(temp)); // First, store the prefixes. - if (Instrux->Rep != 0) + + // Check for REPZ/REPNZ support, and store prefixes. + if (Instrux->IsRepcEnabled) { - // Check for REPZ/REPNZ support, and store prefixes. - if (ND_REPC_SUPPORT(Instrux)) + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) { - if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) - { - res = nd_strcat_s(Buffer, BufferSize, "REPZ "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) - { - res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - } - - // Check for REP support and store prefixes. - if (ND_REP_SUPPORT(Instrux)) - { - if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) - { - res = nd_strcat_s(Buffer, BufferSize, "REP "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) - { - res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - } - - if (Instrux->IsXreleaseEnabled) - { - res = nd_strcat_s(Buffer, BufferSize, "XRELEASE "); + res = nd_strcat_s(Buffer, BufferSize, "REPZ "); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } - else if (Instrux->IsXacquireEnabled) + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) { - res = nd_strcat_s(Buffer, BufferSize, "XACQUIRE "); + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } } - if (Instrux->HasLock) + // Check for REP support and store prefixes. + if (Instrux->IsRepEnabled) { - if (ND_LOCK_SUPPORT(Instrux)) + if (Instrux->Rep == ND_PREFIX_G1_REPE_REPZ) { - res = nd_strcat_s(Buffer, BufferSize, "LOCK "); + res = nd_strcat_s(Buffer, BufferSize, "REP "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->Rep == ND_PREFIX_G1_REPNE_REPNZ) + { + res = nd_strcat_s(Buffer, BufferSize, "REPNZ "); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } } - if (Instrux->Rep == ND_PREFIX_G1_BND) + if (Instrux->IsXreleaseEnabled) { - if (ND_BND_SUPPORT(Instrux)) - { - res = nd_strcat_s(Buffer, BufferSize, "BND "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } + res = nd_strcat_s(Buffer, BufferSize, "XRELEASE "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else if (Instrux->IsXacquireEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "XACQUIRE "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } - if (Instrux->HasSeg && ND_BHINT_SUPPORT(Instrux)) + if (Instrux->IsLockEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "LOCK "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + if (Instrux->IsBndEnabled) + { + res = nd_strcat_s(Buffer, BufferSize, "BND "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + if (Instrux->IsBhintEnabled) { switch (Instrux->Seg) { @@ -303,23 +298,27 @@ NdToText( } } - if (Instrux->HasSeg && ND_DNT_SUPPORT(Instrux)) + if (Instrux->IsDntEnabled) { - if (!Instrux->IsCetTracked) - { - res = nd_strcat_s(Buffer, BufferSize, "DNT "); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } + res = nd_strcat_s(Buffer, BufferSize, "DNT "); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } // Store the mnemonic. res = nd_strcat_s(Buffer, BufferSize, Instrux->Mnemonic); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - // Store condition code, if any. - if (ND_HAS_SSE_CONDITION(Instrux)) + // Store NF specifier, if NoFlags presetn. + if (Instrux->HasNf) { - res = nd_strcat_s(Buffer, BufferSize, gConditionCodes[Instrux->SseCondition]); + res = nd_strcat_s(Buffer, BufferSize, "{NF}"); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + + // Store ZU specifier, if ZeroUpper present. + if (Instrux->HasZu) + { + res = nd_strcat_s(Buffer, BufferSize, "{ZU}"); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } @@ -406,7 +405,7 @@ NdToText( { case ND_SIZE_8BIT: // 8 bit register. - if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex) + if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex || Instrux->HasRex2) { res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Register.Reg]); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); @@ -444,11 +443,6 @@ NdToText( case ND_REG_SEG: { - if (pOp->Info.Register.Reg >= ND_MAX_SEG_REGS) - { - return ND_STATUS_INVALID_INSTRUX; - } - res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Register.Reg]); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } @@ -671,7 +665,7 @@ NdToText( } break; - case ND_OP_ADDR: + case ND_OP_ADDR_FAR: { switch (Instrux->AddrLength) { @@ -701,6 +695,36 @@ NdToText( } break; + case ND_OP_ADDR_NEAR: + { + status = NdSprintf(temp, sizeof(temp), "0x%016llx", pOp->Info.AddressNear.Target); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + + case ND_OP_DFV: + { + status = NdSprintf(temp, sizeof(temp), "%c%c%c%c", + pOp->Info.DefaultFlags.OF ? '1' : '0', + pOp->Info.DefaultFlags.SF ? '1' : '0', + pOp->Info.DefaultFlags.ZF ? '1' : '0', + pOp->Info.DefaultFlags.CF ? '1' : '0'); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + break; + case ND_OP_MEM: { // Prepend the size. For VSIB addressing, store the VSIB element size, not the total accessed size. @@ -755,11 +779,6 @@ NdToText( // Perpend the segment, only if it is overridden via a prefix. if (pOp->Info.Memory.HasSeg && Instrux->HasSeg) { - if (pOp->Info.Memory.Seg >= ND_MAX_SEG_REGS) - { - return ND_STATUS_INVALID_INSTRUX; - } - if ((ND_CODE_64 != Instrux->DefCode) || (NDR_FS == pOp->Info.Memory.Seg) || (NDR_GS == pOp->Info.Memory.Seg)) { @@ -778,16 +797,20 @@ NdToText( // Base, if any. if (pOp->Info.Memory.HasBase) { - if (pOp->Info.Memory.Base >= ND_MAX_GPR_REGS) - { - return ND_STATUS_INVALID_INSTRUX; - } - switch (pOp->Info.Memory.BaseSize) { case ND_SIZE_8BIT: - res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Base]); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex || Instrux->HasRex2) + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Memory.Base]); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + + } + else + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Base]); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } break; case ND_SIZE_16BIT: res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Base]); @@ -823,8 +846,16 @@ NdToText( switch (pOp->Info.Memory.IndexSize) { case ND_SIZE_8BIT: - res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Index]); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + if ((Instrux->EncMode != ND_ENCM_LEGACY) || Instrux->HasRex || Instrux->HasRex2) + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit64[pOp->Info.Memory.Index]); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } + else + { + res = nd_strcat_s(Buffer, BufferSize, gReg8Bit[pOp->Info.Memory.Index]); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } break; case ND_SIZE_16BIT: res = nd_strcat_s(Buffer, BufferSize, gReg16Bit[pOp->Info.Memory.Index]); @@ -913,7 +944,18 @@ NdToText( // Now displacement. if (pOp->Info.Memory.HasBase || pOp->Info.Memory.HasIndex) { - res = nd_strcat_s(Buffer, BufferSize, Instrux->SignDisp ? "-" : "+"); + ND_BOOL sign; + + if (ND_GET_SIGN(8, pOp->Info.Memory.Disp)) + { + sign = ND_TRUE; + } + else + { + sign = ND_FALSE; + } + + res = nd_strcat_s(Buffer, BufferSize, sign ? "-" : "+"); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } @@ -951,6 +993,19 @@ NdToText( // And the ending "]" res = nd_strcat_s(Buffer, BufferSize, "]"); RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + + // Handle memory broadcast. + if (pOp->Info.Memory.HasBroadcast) + { + status = NdSprintf(temp, sizeof(temp), "{1to%d}", pOp->Info.Memory.Broadcast.Count); + if (!ND_SUCCESS(status)) + { + return status; + } + + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } } break; @@ -958,28 +1013,10 @@ NdToText( return ND_STATUS_INVALID_INSTRUX; } - // Handle memory broadcast. - if (pOp->Decorator.HasBroadcast) - { - status = NdSprintf(temp, sizeof(temp), "{1to%d}", pOp->Decorator.Broadcast.Count); - if (!ND_SUCCESS(status)) - { - return status; - } - - res = nd_strcat_s(Buffer, BufferSize, temp); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - // Handle masking. if (pOp->Decorator.HasMask) { - if (pOp->Decorator.Mask.Msk >= ND_MAX_MSK_REGS) - { - return ND_STATUS_INVALID_INSTRUX; - } - - status = NdSprintf(temp, sizeof(temp), "{%s}", gRegMask[pOp->Decorator.Mask.Msk]); + status = NdSprintf(temp, sizeof(temp), "{%s}", gRegMask[pOp->Decorator.Msk]); if (!ND_SUCCESS(status)) { return status; @@ -996,30 +1033,30 @@ NdToText( RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } - // Append Suppress All Exceptions decorator. - if (pOp->Decorator.HasSae && !pOp->Decorator.HasEr) + // If this is the last reg/mem operand, display {sae} and {er} decorators. + if ((pOp->Type == ND_OP_MEM || pOp->Type == ND_OP_REG) && + (opIndex + 1 >= Instrux->ExpOperandsCount || Instrux->Operands[opIndex + 1].Type == ND_OP_IMM)) { - // ER implies SAE, so if we have ER, we will list that. - res = nd_strcat_s(Buffer, BufferSize, ", {sae}"); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); - } - - // Append Embedded Rounding decorator. - if (pOp->Decorator.HasEr) - { - if (Instrux->RoundingMode >= 4) + // Append Suppress All Exceptions decorator. + if (Instrux->HasSae && !Instrux->HasEr) { - return ND_STATUS_INVALID_INSTRUX; + // ER implies SAE, so if we have ER, we will list that. + res = nd_strcat_s(Buffer, BufferSize, ", {sae}"); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); } - status = NdSprintf(temp, sizeof(temp), ", {%s-sae}", gEmbeddedRounding[Instrux->RoundingMode]); - if (!ND_SUCCESS(status)) + // Append Embedded Rounding decorator. + if (Instrux->HasEr) { - return status; - } + status = NdSprintf(temp, sizeof(temp), ", {%s-sae}", gEmbeddedRounding[Instrux->RoundingMode]); + if (!ND_SUCCESS(status)) + { + return status; + } - res = nd_strcat_s(Buffer, BufferSize, temp); - RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + res = nd_strcat_s(Buffer, BufferSize, temp); + RET_EQ(res, ND_NULL, ND_STATUS_BUFFER_OVERFLOW); + } } } diff --git a/bddisasm/bdhelpers.c b/bddisasm/bdx86_helpers.c similarity index 99% rename from bddisasm/bdhelpers.c rename to bddisasm/bdx86_helpers.c index 69627c1..f220649 100644 --- a/bddisasm/bdhelpers.c +++ b/bddisasm/bdx86_helpers.c @@ -2,7 +2,7 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#include "include/nd_crt.h" +#include "include/bddisasm_crt.h" #include "../inc/bddisasm.h" diff --git a/bddisasm/include/nd_crt.h b/bddisasm/include/bddisasm_crt.h similarity index 97% rename from bddisasm/include/nd_crt.h rename to bddisasm/include/bddisasm_crt.h index 0a97d6e..c92ca5b 100644 --- a/bddisasm/include/nd_crt.h +++ b/bddisasm/include/bddisasm_crt.h @@ -5,7 +5,7 @@ #ifndef ND_CRT_H #define ND_CRT_H -#include "../../inc/disasmtypes.h" +#include "../../inc/bddisasm_types.h" #ifndef UNREFERENCED_PARAMETER #define UNREFERENCED_PARAMETER(P) ((void)(P)) diff --git a/bddisasm/include/bdx86_instructions.h b/bddisasm/include/bdx86_instructions.h new file mode 100644 index 0000000..4c21138 --- /dev/null +++ b/bddisasm/include/bdx86_instructions.h @@ -0,0 +1,114205 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + +#ifndef BDX86_INSTRUCTIONS_H +#define BDX86_INSTRUCTIONS_H + +const ND_IDBE gInstructions[4075] = +{ + // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" + { + .Instruction = ND_INS_AAA, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 0, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_AF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" + { + .Instruction = ND_INS_AAD, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 1, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2 Instruction:"AADD My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AADD, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 2, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_RAOINT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AADD, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_RAOINT, + .Mnemonic = 2, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RAOINT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" + { + .Instruction = ND_INS_AAM, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 3, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:5 Instruction:"AAND My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AAND, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 4, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_RAOINT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:6 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AAND, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_RAOINT, + .Mnemonic = 4, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RAOINT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:7 Instruction:"AAS" Encoding:"0x3F"/"" + { + .Instruction = ND_INS_AAS, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 5, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_AF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:8 Instruction:"ADC Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x10 /r"/"MR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:9 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x11 /r"/"MR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:10 Instruction:"ADC Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x11 /r"/"MR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:11 Instruction:"ADC Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x12 /r"/"RM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:12 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x13 /r"/"RM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:13 Instruction:"ADC Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x13 /r"/"RM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:14 Instruction:"ADC Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /2 ib"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:15 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /2 iz"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:16 Instruction:"ADC Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /2 iz"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:17 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /2 ib"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:18 Instruction:"ADC Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /2 ib"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:19 Instruction:"ADC Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x10 /r"/"VMR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:20 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x11 /r"/"VMR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:21 Instruction:"ADC Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x11 /r"/"VMR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:22 Instruction:"ADC Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x12 /r"/"VRM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:23 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x13 /r"/"VRM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:24 Instruction:"ADC Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x13 /r"/"VRM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:25 Instruction:"ADC Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /2 ib"/"VMI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:26 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /2 iz"/"VMI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:27 Instruction:"ADC Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /2 iz"/"VMI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:28 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /2 ib"/"VMI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:29 Instruction:"ADC Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /2 ib"/"VMI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:30 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:31 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:32 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:33 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:34 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:35 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:36 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:37 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:38 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:39 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" + { + .Instruction = ND_INS_ADC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 6, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:40 Instruction:"ADCX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x66 /r"/"RM" + { + .Instruction = ND_INS_ADCX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 7, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:41 Instruction:"ADCX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x66 /r"/"VRM" + { + .Instruction = ND_INS_ADCX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 7, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:42 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" + { + .Instruction = ND_INS_ADCX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_ADX, + .Mnemonic = 7, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_ADX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:43 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x00 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:44 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x01 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:45 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x01 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:46 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x02 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:47 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x03 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:48 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x03 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:49 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:50 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:51 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:52 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:53 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:54 Instruction:"ADD Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x00 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:55 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x01 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:56 Instruction:"ADD Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x01 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:57 Instruction:"ADD Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x02 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:58 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x03 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:59 Instruction:"ADD Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x03 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:60 Instruction:"ADD Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:61 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:62 Instruction:"ADD Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:63 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:64 Instruction:"ADD Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:65 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x00 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:66 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x01 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:67 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x01 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:68 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x02 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:69 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x03 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:70 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x03 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:71 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:72 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /0 iz"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:73 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /0 iz"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:74 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:75 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:76 Instruction:"ADD Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x00 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:77 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x01 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:78 Instruction:"ADD Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x01 /r"/"VMR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:79 Instruction:"ADD Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x02 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:80 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x03 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:81 Instruction:"ADD Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x03 /r"/"VRM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:82 Instruction:"ADD Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:83 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /0 iz"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:84 Instruction:"ADD Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /0 iz"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:85 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:86 Instruction:"ADD Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /0 ib"/"VMI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:87 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:88 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:89 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:90 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:91 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:92 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:93 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:94 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:95 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:96 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" + { + .Instruction = ND_INS_ADD, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 8, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:97 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" + { + .Instruction = ND_INS_ADDPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 9, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:98 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" + { + .Instruction = ND_INS_ADDPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 10, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:99 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" + { + .Instruction = ND_INS_ADDSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 11, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:100 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" + { + .Instruction = ND_INS_ADDSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 12, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:101 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" + { + .Instruction = ND_INS_ADDSUBPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 13, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:102 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" + { + .Instruction = ND_INS_ADDSUBPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 14, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:103 Instruction:"ADOX Gy,Ey" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0x66 /r"/"RM" + { + .Instruction = ND_INS_ADOX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 15, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:104 Instruction:"ADOX By,Gy,Ey" Encoding:"evex m:4 l:0 nd:1 nf:0 p:2 0x66 /r"/"VRM" + { + .Instruction = ND_INS_ADOX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 15, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:105 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" + { + .Instruction = ND_INS_ADOX, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_ADX, + .Mnemonic = 15, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_ADX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:106 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" + { + .Instruction = ND_INS_AESDEC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 16, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:107 Instruction:"AESDEC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem"/"RM" + { + .Instruction = ND_INS_AESDEC128KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 17, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:108 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" + { + .Instruction = ND_INS_AESDEC128KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 17, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:109 Instruction:"AESDEC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem"/"RM" + { + .Instruction = ND_INS_AESDEC256KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 18, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:110 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" + { + .Instruction = ND_INS_AESDEC256KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 18, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:111 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" + { + .Instruction = ND_INS_AESDECLAST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 19, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:112 Instruction:"AESDECWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem"/"M" + { + .Instruction = ND_INS_AESDECWIDE128KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 20, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:113 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" + { + .Instruction = ND_INS_AESDECWIDE128KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_KL, + .Mnemonic = 20, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:114 Instruction:"AESDECWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem"/"M" + { + .Instruction = ND_INS_AESDECWIDE256KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 21, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:115 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" + { + .Instruction = ND_INS_AESDECWIDE256KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_KL, + .Mnemonic = 21, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:116 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" + { + .Instruction = ND_INS_AESENC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 22, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:117 Instruction:"AESENC128KL Vdq,M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem"/"RM" + { + .Instruction = ND_INS_AESENC128KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 23, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:118 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" + { + .Instruction = ND_INS_AESENC128KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 23, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:119 Instruction:"AESENC256KL Vdq,M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem"/"RM" + { + .Instruction = ND_INS_AESENC256KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 24, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:120 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" + { + .Instruction = ND_INS_AESENC256KL, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 24, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:121 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" + { + .Instruction = ND_INS_AESENCLAST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 25, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:122 Instruction:"AESENCWIDE128KL M384" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem"/"M" + { + .Instruction = ND_INS_AESENCWIDE128KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 26, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:123 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" + { + .Instruction = ND_INS_AESENCWIDE128KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_KL, + .Mnemonic = 26, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:124 Instruction:"AESENCWIDE256KL M512" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem"/"M" + { + .Instruction = ND_INS_AESENCWIDE256KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 27, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:125 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" + { + .Instruction = ND_INS_AESENCWIDE256KL, + .Category = ND_CAT_WIDE_KL, + .IsaSet = ND_SET_KL, + .Mnemonic = 27, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 8), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:126 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" + { + .Instruction = ND_INS_AESIMC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 28, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:127 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" + { + .Instruction = ND_INS_AESKEYGENASSIST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 29, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:128 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:129 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:130 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:131 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:132 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:133 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:134 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:135 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:136 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:137 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:138 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:139 Instruction:"AND Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:140 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:141 Instruction:"AND Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:142 Instruction:"AND Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:143 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:144 Instruction:"AND Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:145 Instruction:"AND Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:146 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:147 Instruction:"AND Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:148 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:149 Instruction:"AND Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:150 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:151 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:152 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:153 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:154 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:155 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:156 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:157 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:158 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:159 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:160 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:161 Instruction:"AND Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:162 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:163 Instruction:"AND Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r"/"VMR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:164 Instruction:"AND Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:165 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:166 Instruction:"AND Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r"/"VRM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:167 Instruction:"AND Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:168 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:169 Instruction:"AND Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:170 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:171 Instruction:"AND Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib"/"VMI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:172 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:173 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:174 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:175 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:176 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:177 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:178 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:179 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:180 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:181 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" + { + .Instruction = ND_INS_AND, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 30, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:182 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF2 /r"/"RVM" + { + .Instruction = ND_INS_ANDN, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 31, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:183 Instruction:"ANDN Gy,By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF2 /r"/"RVM" + { + .Instruction = ND_INS_ANDN, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 31, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:184 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" + { + .Instruction = ND_INS_ANDN, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 31, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:185 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" + { + .Instruction = ND_INS_ANDNPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 32, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:186 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" + { + .Instruction = ND_INS_ANDNPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE, + .Mnemonic = 33, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:187 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" + { + .Instruction = ND_INS_ANDPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 34, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:188 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" + { + .Instruction = ND_INS_ANDPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE, + .Mnemonic = 35, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:189 Instruction:"AOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AOR, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 36, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_RAOINT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:190 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AOR, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_RAOINT, + .Mnemonic = 36, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RAOINT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:191 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" + { + .Instruction = ND_INS_ARPL, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 37, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:192 Instruction:"AXOR My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AXOR, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 38, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_RAOINT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:193 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AXOR, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_RAOINT, + .Mnemonic = 38, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RAOINT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:194 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_BEXTR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 39, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:195 Instruction:"BEXTR Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_BEXTR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 39, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:196 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_BEXTR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 39, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:197 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" + { + .Instruction = ND_INS_BEXTR, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 39, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:198 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" + { + .Instruction = ND_INS_BLCFILL, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 40, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:199 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" + { + .Instruction = ND_INS_BLCI, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 41, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:200 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" + { + .Instruction = ND_INS_BLCIC, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 42, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:201 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" + { + .Instruction = ND_INS_BLCMSK, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 43, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:202 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" + { + .Instruction = ND_INS_BLCS, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 44, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:203 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" + { + .Instruction = ND_INS_BLENDPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 45, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:204 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" + { + .Instruction = ND_INS_BLENDPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 46, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:205 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" + { + .Instruction = ND_INS_BLENDVPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 47, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:206 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" + { + .Instruction = ND_INS_BLENDVPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 48, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:207 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" + { + .Instruction = ND_INS_BLSFILL, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 49, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:208 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /3"/"VM" + { + .Instruction = ND_INS_BLSI, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 50, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:209 Instruction:"BLSI By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /3"/"VM" + { + .Instruction = ND_INS_BLSI, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 50, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:210 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" + { + .Instruction = ND_INS_BLSI, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 50, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:211 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" + { + .Instruction = ND_INS_BLSIC, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 51, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:212 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /2"/"VM" + { + .Instruction = ND_INS_BLSMSK, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 52, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:213 Instruction:"BLSMSK By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /2"/"VM" + { + .Instruction = ND_INS_BLSMSK, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 52, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:214 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" + { + .Instruction = ND_INS_BLSMSK, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 52, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:215 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:0 0xF3 /1"/"VM" + { + .Instruction = ND_INS_BLSR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 53, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:216 Instruction:"BLSR By,Ey" Encoding:"evex m:2 p:0 l:0 nf:1 0xF3 /1"/"VM" + { + .Instruction = ND_INS_BLSR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 53, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:217 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" + { + .Instruction = ND_INS_BLSR, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 53, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:218 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" + { + .Instruction = ND_INS_BNDCL, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 54, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:219 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" + { + .Instruction = ND_INS_BNDCN, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 55, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:220 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" + { + .Instruction = ND_INS_BNDCU, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 56, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:221 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx NP 0x0F 0x1A /r:mem mib"/"RM" + { + .Instruction = ND_INS_BNDLDX, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 57, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:222 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" + { + .Instruction = ND_INS_BNDMK, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 58, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:223 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" + { + .Instruction = ND_INS_BNDMOV, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 59, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:224 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" + { + .Instruction = ND_INS_BNDMOV, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 59, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:225 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx NP 0x0F 0x1B /r:mem mib"/"MR" + { + .Instruction = ND_INS_BNDSTX, + .Category = ND_CAT_MPX, + .IsaSet = ND_SET_MPX, + .Mnemonic = 60, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NORIPREL|ND_FLAG_I67|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_MIB, + .CpuidFlag = ND_CFF_MPX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:226 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" + { + .Instruction = ND_INS_BOUND, + .Category = ND_CAT_INTERRUPT, + .IsaSet = ND_SET_I186, + .Mnemonic = 61, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_a, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:227 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" + { + .Instruction = ND_INS_BSF, + .Category = ND_CAT_I386, + .IsaSet = ND_SET_I386, + .Mnemonic = 62, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:228 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" + { + .Instruction = ND_INS_BSR, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 63, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:229 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:230 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:231 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:232 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:233 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:234 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:235 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:236 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" + { + .Instruction = ND_INS_BSWAP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 64, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:237 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" + { + .Instruction = ND_INS_BT, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 65, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:238 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" + { + .Instruction = ND_INS_BT, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 65, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:239 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" + { + .Instruction = ND_INS_BTC, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 66, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:240 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" + { + .Instruction = ND_INS_BTC, + .Category = ND_CAT_I386, + .IsaSet = ND_SET_I386, + .Mnemonic = 66, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:241 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" + { + .Instruction = ND_INS_BTR, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 67, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:242 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" + { + .Instruction = ND_INS_BTR, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 67, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:243 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" + { + .Instruction = ND_INS_BTS, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 68, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_BITBASE, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:244 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" + { + .Instruction = ND_INS_BTS, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 68, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:245 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:0 0xF5 /r"/"RMV" + { + .Instruction = ND_INS_BZHI, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 69, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:246 Instruction:"BZHI Gy,Ey,By" Encoding:"evex m:2 p:0 l:0 nf:1 0xF5 /r"/"RMV" + { + .Instruction = ND_INS_BZHI, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 69, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:247 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" + { + .Instruction = ND_INS_BZHI, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 69, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:248 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" + { + .Instruction = ND_INS_CALLNR, + .Category = ND_CAT_CALL, + .IsaSet = ND_SET_I86, + .Mnemonic = 70, + .ValidPrefixes = ND_PREF_BND, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:249 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" + { + .Instruction = ND_INS_CALLNI, + .Category = ND_CAT_CALL, + .IsaSet = ND_SET_I86, + .Mnemonic = 70, + .ValidPrefixes = ND_PREF_BND|ND_PREF_DNT, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:250 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" + { + .Instruction = ND_INS_CALLFD, + .Category = ND_CAT_CALL, + .IsaSet = ND_SET_I86, + .Mnemonic = 71, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:251 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" + { + .Instruction = ND_INS_CALLFI, + .Category = ND_CAT_CALL, + .IsaSet = ND_SET_I86, + .Mnemonic = 71, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_CETT|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:252 Instruction:"CBW" Encoding:"ds16 0x98"/"" + { + .Instruction = ND_INS_CBW, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 72, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:253 Instruction:"CCMPBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:254 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:255 Instruction:"CCMPBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:256 Instruction:"CCMPBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:257 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:258 Instruction:"CCMPBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:259 Instruction:"CCMPBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:260 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:261 Instruction:"CCMPBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:262 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:263 Instruction:"CCMPBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 73, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:264 Instruction:"CCMPC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:265 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:266 Instruction:"CCMPC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:267 Instruction:"CCMPC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:268 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:269 Instruction:"CCMPC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:270 Instruction:"CCMPC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:271 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:272 Instruction:"CCMPC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:273 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:274 Instruction:"CCMPC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 74, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:275 Instruction:"CCMPF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:276 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:277 Instruction:"CCMPF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:278 Instruction:"CCMPF Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:279 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:280 Instruction:"CCMPF Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:281 Instruction:"CCMPF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:282 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:283 Instruction:"CCMPF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:284 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:285 Instruction:"CCMPF Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 75, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:286 Instruction:"CCMPL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:287 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:288 Instruction:"CCMPL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:289 Instruction:"CCMPL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:290 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:291 Instruction:"CCMPL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:292 Instruction:"CCMPL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:293 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:294 Instruction:"CCMPL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:295 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:296 Instruction:"CCMPL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 76, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:297 Instruction:"CCMPLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:298 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:299 Instruction:"CCMPLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:300 Instruction:"CCMPLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:301 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:302 Instruction:"CCMPLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:303 Instruction:"CCMPLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:304 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:305 Instruction:"CCMPLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:306 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:307 Instruction:"CCMPLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 77, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:308 Instruction:"CCMPNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:309 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:310 Instruction:"CCMPNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:311 Instruction:"CCMPNBE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:312 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:313 Instruction:"CCMPNBE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:314 Instruction:"CCMPNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:315 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:316 Instruction:"CCMPNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:317 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:318 Instruction:"CCMPNBE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 78, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:319 Instruction:"CCMPNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:320 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:321 Instruction:"CCMPNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:322 Instruction:"CCMPNC Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:323 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:324 Instruction:"CCMPNC Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:325 Instruction:"CCMPNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:326 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:327 Instruction:"CCMPNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:328 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:329 Instruction:"CCMPNC Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 79, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:330 Instruction:"CCMPNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:331 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:332 Instruction:"CCMPNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:333 Instruction:"CCMPNL Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:334 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:335 Instruction:"CCMPNL Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:336 Instruction:"CCMPNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:337 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:338 Instruction:"CCMPNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:339 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:340 Instruction:"CCMPNL Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 80, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:341 Instruction:"CCMPNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:342 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:343 Instruction:"CCMPNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:344 Instruction:"CCMPNLE Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:345 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:346 Instruction:"CCMPNLE Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:347 Instruction:"CCMPNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:348 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:349 Instruction:"CCMPNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:350 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:351 Instruction:"CCMPNLE Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 81, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:352 Instruction:"CCMPNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:353 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:354 Instruction:"CCMPNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:355 Instruction:"CCMPNO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:356 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:357 Instruction:"CCMPNO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:358 Instruction:"CCMPNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:359 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:360 Instruction:"CCMPNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:361 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:362 Instruction:"CCMPNO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 82, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:363 Instruction:"CCMPNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:364 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:365 Instruction:"CCMPNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:366 Instruction:"CCMPNS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:367 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:368 Instruction:"CCMPNS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:369 Instruction:"CCMPNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:370 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:371 Instruction:"CCMPNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:372 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:373 Instruction:"CCMPNS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 83, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:374 Instruction:"CCMPNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:375 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:376 Instruction:"CCMPNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:377 Instruction:"CCMPNZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:378 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:379 Instruction:"CCMPNZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:380 Instruction:"CCMPNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:381 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:382 Instruction:"CCMPNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:383 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:384 Instruction:"CCMPNZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 84, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:385 Instruction:"CCMPO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:386 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:387 Instruction:"CCMPO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:388 Instruction:"CCMPO Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:389 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:390 Instruction:"CCMPO Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:391 Instruction:"CCMPO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:392 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:393 Instruction:"CCMPO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:394 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:395 Instruction:"CCMPO Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 85, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:396 Instruction:"CCMPS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:397 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:398 Instruction:"CCMPS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:399 Instruction:"CCMPS Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:400 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:401 Instruction:"CCMPS Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:402 Instruction:"CCMPS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:403 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:404 Instruction:"CCMPS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:405 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:406 Instruction:"CCMPS Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 86, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:407 Instruction:"CCMPT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:408 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:409 Instruction:"CCMPT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:410 Instruction:"CCMPT Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:411 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:412 Instruction:"CCMPT Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:413 Instruction:"CCMPT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:414 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:415 Instruction:"CCMPT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:416 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:417 Instruction:"CCMPT Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 87, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:418 Instruction:"CCMPZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:419 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:420 Instruction:"CCMPZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r"/"MRV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:421 Instruction:"CCMPZ Gb,Eb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:422 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:423 Instruction:"CCMPZ Gv,Ev,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r"/"RMV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:424 Instruction:"CCMPZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:425 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:426 Instruction:"CCMPZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:427 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:428 Instruction:"CCMPZ Ev,Ib,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib"/"MIV" + { + .Instruction = ND_INS_CCMP, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 88, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:429 Instruction:"CDQ" Encoding:"ds32 0x99"/"" + { + .Instruction = ND_INS_CDQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 89, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:430 Instruction:"CDQE" Encoding:"ds64 0x98"/"" + { + .Instruction = ND_INS_CDQE, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 90, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:431 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:432 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:433 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:434 Instruction:"CFCMOVBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:435 Instruction:"CFCMOVBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:436 Instruction:"CFCMOVBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:437 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:438 Instruction:"CFCMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 91, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:439 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:440 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:441 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:442 Instruction:"CFCMOVC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:443 Instruction:"CFCMOVC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:444 Instruction:"CFCMOVC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:445 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:446 Instruction:"CFCMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 92, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:447 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:448 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:449 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:450 Instruction:"CFCMOVL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:451 Instruction:"CFCMOVL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:452 Instruction:"CFCMOVL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:453 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:454 Instruction:"CFCMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 93, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:455 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:456 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:457 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:458 Instruction:"CFCMOVLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:459 Instruction:"CFCMOVLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:460 Instruction:"CFCMOVLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:461 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:462 Instruction:"CFCMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 94, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:463 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:464 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:465 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:466 Instruction:"CFCMOVNBE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:467 Instruction:"CFCMOVNBE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:468 Instruction:"CFCMOVNBE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:469 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:470 Instruction:"CFCMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 95, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:471 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:472 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:473 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:474 Instruction:"CFCMOVNC Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:475 Instruction:"CFCMOVNC Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:476 Instruction:"CFCMOVNC Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:477 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:478 Instruction:"CFCMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 96, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:479 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:480 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:481 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:482 Instruction:"CFCMOVNL Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:483 Instruction:"CFCMOVNL Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:484 Instruction:"CFCMOVNL Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:485 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:486 Instruction:"CFCMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 97, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:487 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:488 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:489 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:490 Instruction:"CFCMOVNLE Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:491 Instruction:"CFCMOVNLE Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:492 Instruction:"CFCMOVNLE Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:493 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:494 Instruction:"CFCMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 98, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:495 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:496 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:497 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:498 Instruction:"CFCMOVNO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:499 Instruction:"CFCMOVNO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:500 Instruction:"CFCMOVNO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:501 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:502 Instruction:"CFCMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 99, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:503 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:504 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:505 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:506 Instruction:"CFCMOVNP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:507 Instruction:"CFCMOVNP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:508 Instruction:"CFCMOVNP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:509 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:510 Instruction:"CFCMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:511 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:512 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:513 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:514 Instruction:"CFCMOVNS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:515 Instruction:"CFCMOVNS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:516 Instruction:"CFCMOVNS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:517 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:518 Instruction:"CFCMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:519 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:520 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:521 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:522 Instruction:"CFCMOVNZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:523 Instruction:"CFCMOVNZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:524 Instruction:"CFCMOVNZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:525 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:526 Instruction:"CFCMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:527 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:528 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:529 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:530 Instruction:"CFCMOVO Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:531 Instruction:"CFCMOVO Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:532 Instruction:"CFCMOVO Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:533 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:534 Instruction:"CFCMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:535 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:536 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:537 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:538 Instruction:"CFCMOVP Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:539 Instruction:"CFCMOVP Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:540 Instruction:"CFCMOVP Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:541 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:542 Instruction:"CFCMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:543 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:544 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:545 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:546 Instruction:"CFCMOVS Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:547 Instruction:"CFCMOVS Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:548 Instruction:"CFCMOVS Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:549 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:550 Instruction:"CFCMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:551 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:552 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:553 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:554 Instruction:"CFCMOVZ Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r"/"RM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:555 Instruction:"CFCMOVZ Rv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:556 Instruction:"CFCMOVZ Mv,Gv" Encoding:"evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem"/"MR" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:557 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:558 Instruction:"CFCMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r"/"VRM" + { + .Instruction = ND_INS_CFCMOV, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CFCMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:559 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" + { + .Instruction = ND_INS_CLAC, + .Category = ND_CAT_SMAP, + .IsaSet = ND_SET_SMAP, + .Mnemonic = 107, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_AC, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SMAP, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:560 Instruction:"CLC" Encoding:"0xF8"/"" + { + .Instruction = ND_INS_CLC, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 108, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:561 Instruction:"CLD" Encoding:"0xFC"/"" + { + .Instruction = ND_INS_CLD, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 109, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_DF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:562 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" + { + .Instruction = ND_INS_CLDEMOTE, + .Category = ND_CAT_CLDEMOTE, + .IsaSet = ND_SET_CLDEMOTE, + .Mnemonic = 110, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CLDEMOTE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:563 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" + { + .Instruction = ND_INS_CLEVICT0, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 111, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:564 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" + { + .Instruction = ND_INS_CLEVICT1, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 112, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:565 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" + { + .Instruction = ND_INS_CLFLUSH, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_CLFSH, + .Mnemonic = 113, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CLFSH, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:566 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" + { + .Instruction = ND_INS_CLFLUSHOPT, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_CLFSHOPT, + .Mnemonic = 114, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CLFSHOPT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:567 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" + { + .Instruction = ND_INS_CLGI, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 115, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:568 Instruction:"CLI" Encoding:"0xFA"/"" + { + .Instruction = ND_INS_CLI, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 116, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_IF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:569 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" + { + .Instruction = ND_INS_CLRSSBSY, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 117, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:570 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" + { + .Instruction = ND_INS_CLTS, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 118, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:571 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" + { + .Instruction = ND_INS_CLUI, + .Category = ND_CAT_UINTR, + .IsaSet = ND_SET_UINTR, + .Mnemonic = 119, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_UINTR, + .Operands = + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:572 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" + { + .Instruction = ND_INS_CLWB, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_CLWB, + .Mnemonic = 120, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CLWB, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:573 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" + { + .Instruction = ND_INS_CLZERO, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_CLZERO, + .Mnemonic = 121, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:574 Instruction:"CMC" Encoding:"0xF5"/"" + { + .Instruction = ND_INS_CMC, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 122, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:575 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 123, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:576 Instruction:"CMOVBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 123, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:577 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 123, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:578 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 124, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:579 Instruction:"CMOVC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 124, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:580 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 124, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:581 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 125, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:582 Instruction:"CMOVL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 125, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:583 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 125, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:584 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 126, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:585 Instruction:"CMOVLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 126, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:586 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 126, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:587 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 127, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:588 Instruction:"CMOVNBE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 127, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:589 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 127, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:590 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 128, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:591 Instruction:"CMOVNC Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 128, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:592 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 128, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:593 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 129, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:594 Instruction:"CMOVNL Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 129, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:595 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 129, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:596 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 130, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:597 Instruction:"CMOVNLE Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 130, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:598 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 130, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:599 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 131, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:600 Instruction:"CMOVNO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 131, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:601 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 131, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:602 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 132, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:603 Instruction:"CMOVNP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 132, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:604 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 132, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:605 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 133, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:606 Instruction:"CMOVNS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 133, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:607 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 133, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:608 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 134, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:609 Instruction:"CMOVNZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 134, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:610 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 134, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:611 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 135, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:612 Instruction:"CMOVO Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 135, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:613 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 135, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:614 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 136, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:615 Instruction:"CMOVP Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 136, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:616 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 136, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:617 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 137, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:618 Instruction:"CMOVS Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 137, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:619 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 137, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:620 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 138, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:621 Instruction:"CMOVZ Bv,Gv,Ev" Encoding:"evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r"/"VRM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 138, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:622 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" + { + .Instruction = ND_INS_CMOVcc, + .Category = ND_CAT_CMOV, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 138, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMOV, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:623 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:624 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:625 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:626 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:627 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:628 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:629 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:630 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:631 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:632 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" + { + .Instruction = ND_INS_CMP, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:633 Instruction:"CMPBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE6 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPBEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 140, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:634 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPBEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 140, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:635 Instruction:"CMPCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE2 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPCXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 141, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:636 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPCXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 141, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:637 Instruction:"CMPLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEE /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPLEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 142, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:638 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPLEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 142, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:639 Instruction:"CMPLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEC /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPLXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 143, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:640 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPLXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 143, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:641 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE7 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNBEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 144, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:642 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNBEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 144, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:643 Instruction:"CMPNCXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE3 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNCXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 145, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:644 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNCXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 145, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:645 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEF /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNLEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 146, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:646 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNLEXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 146, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:647 Instruction:"CMPNLXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xED /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNLXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 147, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:648 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNLXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 147, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:649 Instruction:"CMPNOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE1 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNOXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 148, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:650 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNOXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 148, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:651 Instruction:"CMPNPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEB /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNPXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 149, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:652 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNPXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 149, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:653 Instruction:"CMPNSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE9 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNSXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 150, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:654 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNSXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 150, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:655 Instruction:"CMPNZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE5 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNZXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 151, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:656 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPNZXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 151, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:657 Instruction:"CMPOXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE0 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPOXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 152, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:658 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPOXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 152, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:659 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_CMPPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 153, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:660 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_CMPPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 154, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:661 Instruction:"CMPPXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xEA /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPPXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 155, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:662 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPPXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 155, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:663 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 156, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:664 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 156, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:665 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 157, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:666 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 157, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:667 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_CMPSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 157, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:668 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 158, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:669 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 158, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:670 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_CMPSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 159, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:671 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 160, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:672 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" + { + .Instruction = ND_INS_CMPS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 160, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:673 Instruction:"CMPSXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE8 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPSXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 161, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:674 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPSXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 161, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:675 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" + { + .Instruction = ND_INS_CMPXCHG, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 162, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:676 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" + { + .Instruction = ND_INS_CMPXCHG, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 162, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:677 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" + { + .Instruction = ND_INS_CMPXCHG16B, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_CMPXCHG16B, + .Mnemonic = 163, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CX8, + .Operands = + { + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:678 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" + { + .Instruction = ND_INS_CMPXCHG8B, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_PENTIUMREAL, + .Mnemonic = 164, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CX8, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:679 Instruction:"CMPZXADD My,Gy,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xE4 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPZXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 165, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CMPCCXADD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:680 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" + { + .Instruction = ND_INS_CMPZXADD, + .Category = ND_CAT_CMPCCXADD, + .IsaSet = ND_SET_CMPCCXADD, + .Mnemonic = 165, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_14, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CMPCCXADD, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:681 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" + { + .Instruction = ND_INS_COMISD, + .Category = ND_CAT_SSE2, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 166, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:682 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" + { + .Instruction = ND_INS_COMISS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 167, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:683 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" + { + .Instruction = ND_INS_CPUID, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 168, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:684 Instruction:"CQO" Encoding:"ds64 0x99"/"" + { + .Instruction = ND_INS_CQO, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 169, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:685 Instruction:"CRC32 Gy,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r"/"RM" + { + .Instruction = ND_INS_CRC32, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:686 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r"/"RM" + { + .Instruction = ND_INS_CRC32, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:687 Instruction:"CRC32 Gy,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r"/"RM" + { + .Instruction = ND_INS_CRC32, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:688 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" + { + .Instruction = ND_INS_CRC32, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:689 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" + { + .Instruction = ND_INS_CRC32, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:690 Instruction:"CTESTBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:691 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:692 Instruction:"CTESTBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:693 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:694 Instruction:"CTESTBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:695 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:696 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:697 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:698 Instruction:"CTESTBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:699 Instruction:"CTESTC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:700 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:701 Instruction:"CTESTC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:702 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:703 Instruction:"CTESTC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:704 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:705 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:706 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:707 Instruction:"CTESTC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:708 Instruction:"CTESTF Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:709 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:710 Instruction:"CTESTF Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:711 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:712 Instruction:"CTESTF Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:713 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:714 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:715 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:716 Instruction:"CTESTF Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:717 Instruction:"CTESTL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:718 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:719 Instruction:"CTESTL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:720 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:721 Instruction:"CTESTL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:722 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:723 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:724 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:725 Instruction:"CTESTL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:726 Instruction:"CTESTLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:727 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:728 Instruction:"CTESTLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:729 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:730 Instruction:"CTESTLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:731 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:732 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:733 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:734 Instruction:"CTESTLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:735 Instruction:"CTESTNBE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:736 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:737 Instruction:"CTESTNBE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:738 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:739 Instruction:"CTESTNBE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:740 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:741 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:742 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:743 Instruction:"CTESTNBE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:744 Instruction:"CTESTNC Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:745 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:746 Instruction:"CTESTNC Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:747 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:748 Instruction:"CTESTNC Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:749 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:750 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:751 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:752 Instruction:"CTESTNC Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:753 Instruction:"CTESTNL Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:754 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:755 Instruction:"CTESTNL Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:756 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:757 Instruction:"CTESTNL Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:758 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:759 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:760 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:761 Instruction:"CTESTNL Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:762 Instruction:"CTESTNLE Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:763 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:764 Instruction:"CTESTNLE Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:765 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:766 Instruction:"CTESTNLE Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:767 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:768 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:769 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:770 Instruction:"CTESTNLE Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:771 Instruction:"CTESTNO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:772 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:773 Instruction:"CTESTNO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:774 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:775 Instruction:"CTESTNO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:776 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:777 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:778 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:779 Instruction:"CTESTNO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:780 Instruction:"CTESTNS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:781 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:782 Instruction:"CTESTNS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:783 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:784 Instruction:"CTESTNS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:785 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:786 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:787 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:788 Instruction:"CTESTNS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:789 Instruction:"CTESTNZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:790 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:791 Instruction:"CTESTNZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:792 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:793 Instruction:"CTESTNZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:794 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:795 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:796 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:797 Instruction:"CTESTNZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:798 Instruction:"CTESTO Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:799 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:800 Instruction:"CTESTO Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:801 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:802 Instruction:"CTESTO Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:803 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:804 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:805 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:806 Instruction:"CTESTO Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:807 Instruction:"CTESTS Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:808 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:809 Instruction:"CTESTS Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:810 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:811 Instruction:"CTESTS Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:812 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:813 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:814 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:815 Instruction:"CTESTS Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:816 Instruction:"CTESTT Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:817 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:818 Instruction:"CTESTT Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:819 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:820 Instruction:"CTESTT Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:821 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:822 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:823 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:824 Instruction:"CTESTT Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:825 Instruction:"CTESTZ Eb,Gb,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:826 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:827 Instruction:"CTESTZ Ev,Gv,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r"/"MRV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:828 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:829 Instruction:"CTESTZ Eb,Ib,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:830 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:831 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:832 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:833 Instruction:"CTESTZ Ev,Iz,dfv" Encoding:"evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz"/"MIV" + { + .Instruction = ND_INS_CTEST, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_CCMP, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_COND, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_dfv, ND_OPS_0, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:834 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" + { + .Instruction = ND_INS_CVTDQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 187, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:835 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" + { + .Instruction = ND_INS_CVTDQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 188, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:836 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" + { + .Instruction = ND_INS_CVTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 189, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:837 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" + { + .Instruction = ND_INS_CVTPD2PI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 190, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:838 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" + { + .Instruction = ND_INS_CVTPD2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 191, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:839 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" + { + .Instruction = ND_INS_CVTPI2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 192, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:840 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" + { + .Instruction = ND_INS_CVTPI2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 193, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:841 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" + { + .Instruction = ND_INS_CVTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 194, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:842 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" + { + .Instruction = ND_INS_CVTPS2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 195, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:843 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" + { + .Instruction = ND_INS_CVTPS2PI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 196, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:844 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" + { + .Instruction = ND_INS_CVTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 197, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:845 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" + { + .Instruction = ND_INS_CVTSD2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 198, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:846 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" + { + .Instruction = ND_INS_CVTSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 199, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:847 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" + { + .Instruction = ND_INS_CVTSI2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 200, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:848 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" + { + .Instruction = ND_INS_CVTSS2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 201, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:849 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" + { + .Instruction = ND_INS_CVTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 202, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:850 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" + { + .Instruction = ND_INS_CVTTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 203, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:851 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" + { + .Instruction = ND_INS_CVTTPD2PI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 204, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:852 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" + { + .Instruction = ND_INS_CVTTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 205, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:853 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" + { + .Instruction = ND_INS_CVTTPS2PI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 206, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:854 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" + { + .Instruction = ND_INS_CVTTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 207, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:855 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" + { + .Instruction = ND_INS_CVTTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_SSE, + .Mnemonic = 208, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:856 Instruction:"CWD" Encoding:"ds16 0x99"/"" + { + .Instruction = ND_INS_CWD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 209, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:857 Instruction:"CWDE" Encoding:"ds32 0x98"/"" + { + .Instruction = ND_INS_CWDE, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_I386, + .Mnemonic = 210, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:858 Instruction:"DAA" Encoding:"0x27"/"" + { + .Instruction = ND_INS_DAA, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 211, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:859 Instruction:"DAS" Encoding:"0x2F"/"" + { + .Instruction = ND_INS_DAS, + .Category = ND_CAT_DECIMAL, + .IsaSet = ND_SET_I86, + .Mnemonic = 212, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:860 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:861 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:862 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:863 Instruction:"DEC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:864 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:865 Instruction:"DEC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:866 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:867 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:868 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:869 Instruction:"DEC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:870 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:871 Instruction:"DEC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1"/"VM" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:872 Instruction:"DEC Zv" Encoding:"0x48"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:873 Instruction:"DEC Zv" Encoding:"0x49"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:874 Instruction:"DEC Zv" Encoding:"0x4A"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:875 Instruction:"DEC Zv" Encoding:"0x4B"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:876 Instruction:"DEC Zv" Encoding:"0x4C"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:877 Instruction:"DEC Zv" Encoding:"0x4D"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:878 Instruction:"DEC Zv" Encoding:"0x4E"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:879 Instruction:"DEC Zv" Encoding:"0x4F"/"O" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:880 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:881 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" + { + .Instruction = ND_INS_DEC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 213, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:882 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" + { + .Instruction = ND_INS_DELAY, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 214, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:883 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:884 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:885 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:886 Instruction:"DIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:887 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:888 Instruction:"DIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:889 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:890 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" + { + .Instruction = ND_INS_DIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:891 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" + { + .Instruction = ND_INS_DIVPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 216, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:892 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" + { + .Instruction = ND_INS_DIVPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 217, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:893 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" + { + .Instruction = ND_INS_DIVSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 218, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:894 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" + { + .Instruction = ND_INS_DIVSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 219, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:895 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" + { + .Instruction = ND_INS_DPPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 220, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:896 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" + { + .Instruction = ND_INS_DPPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 221, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:897 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" + { + .Instruction = ND_INS_EMMS, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 222, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + 0 + }, + }, + + // Pos:898 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" + { + .Instruction = ND_INS_ENCLS, + .Category = ND_CAT_SGX, + .IsaSet = ND_SET_SGX, + .Mnemonic = 223, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SGX, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + }, + }, + + // Pos:899 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" + { + .Instruction = ND_INS_ENCLU, + .Category = ND_CAT_SGX, + .IsaSet = ND_SET_SGX, + .Mnemonic = 224, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SGX, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + }, + }, + + // Pos:900 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" + { + .Instruction = ND_INS_ENCLV, + .Category = ND_CAT_SGX, + .IsaSet = ND_SET_SGX, + .Mnemonic = 225, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SGX, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CRW, 0, 0), + }, + }, + + // Pos:901 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg"/"RM" + { + .Instruction = ND_INS_ENCODEKEY128, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), + OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:902 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" + { + .Instruction = ND_INS_ENCODEKEY128, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), + OP(ND_OPT_XMM4, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 3), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:903 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg"/"RM" + { + .Instruction = ND_INS_ENCODEKEY256, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 227, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KEYLOCKER, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2), + OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:904 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" + { + .Instruction = ND_INS_ENCODEKEY256, + .Category = ND_CAT_AESKL, + .IsaSet = ND_SET_KL, + .Mnemonic = 227, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_RW, 0, 2), + OP(ND_OPT_XMM2, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 5), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:905 Instruction:"ENDBR32" Encoding:"cet repz 0x0F 0x1E /0xFB"/"" + { + .Instruction = ND_INS_ENDBR, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_IBT, + .Mnemonic = 228, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_IBT, + .Operands = + { + 0 + }, + }, + + // Pos:906 Instruction:"ENDBR64" Encoding:"cet repz 0x0F 0x1E /0xFA"/"" + { + .Instruction = ND_INS_ENDBR, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_IBT, + .Mnemonic = 229, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_IBT, + .Operands = + { + 0 + }, + }, + + // Pos:907 Instruction:"ENQCMD rM?,Moq" Encoding:"evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_ENQCMD, + .Category = ND_CAT_ENQCMD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 230, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_ENQCMD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:908 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_ENQCMD, + .Category = ND_CAT_ENQCMD, + .IsaSet = ND_SET_ENQCMD, + .Mnemonic = 230, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_ENQCMD, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:909 Instruction:"ENQCMDS rM?,Moq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_ENQCMDS, + .Category = ND_CAT_ENQCMD, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 231, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_ENQCMD, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:910 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_ENQCMDS, + .Category = ND_CAT_ENQCMD, + .IsaSet = ND_SET_ENQCMD, + .Mnemonic = 231, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_ENQCMD, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:911 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" + { + .Instruction = ND_INS_ENTER, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_I186, + .Mnemonic = 232, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:912 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" + { + .Instruction = ND_INS_ERETS, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_FRED, + .Mnemonic = 233, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_FRED, + .Operands = + { + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + }, + }, + + // Pos:913 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" + { + .Instruction = ND_INS_ERETU, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_FRED, + .Mnemonic = 234, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 9), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_FRED, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v5, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:914 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" + { + .Instruction = ND_INS_EXTRACTPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 235, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:915 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 ib ib"/"MII" + { + .Instruction = ND_INS_EXTRQ, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 236, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:916 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" + { + .Instruction = ND_INS_EXTRQ, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 236, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:917 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" + { + .Instruction = ND_INS_F2XM1, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 237, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:918 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" + { + .Instruction = ND_INS_FABS, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 238, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:919 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" + { + .Instruction = ND_INS_FADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 239, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:920 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" + { + .Instruction = ND_INS_FADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 239, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:921 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" + { + .Instruction = ND_INS_FADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 239, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:922 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" + { + .Instruction = ND_INS_FADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 239, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:923 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" + { + .Instruction = ND_INS_FADDP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 240, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:924 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" + { + .Instruction = ND_INS_FBLD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 241, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:925 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" + { + .Instruction = ND_INS_FBSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 242, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:926 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" + { + .Instruction = ND_INS_FCHS, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 243, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:927 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" + { + .Instruction = ND_INS_FCMOVB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 244, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:928 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" + { + .Instruction = ND_INS_FCMOVBE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 245, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:929 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" + { + .Instruction = ND_INS_FCMOVE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 246, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:930 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" + { + .Instruction = ND_INS_FCMOVNB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 247, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:931 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" + { + .Instruction = ND_INS_FCMOVNBE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 248, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:932 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" + { + .Instruction = ND_INS_FCMOVNE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 249, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:933 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" + { + .Instruction = ND_INS_FCMOVNU, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 250, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:934 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" + { + .Instruction = ND_INS_FCMOVU, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 251, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:935 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" + { + .Instruction = ND_INS_FCOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:936 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" + { + .Instruction = ND_INS_FCOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:937 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" + { + .Instruction = ND_INS_FCOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:938 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" + { + .Instruction = ND_INS_FCOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:939 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" + { + .Instruction = ND_INS_FCOMI, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 253, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:940 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" + { + .Instruction = ND_INS_FCOMIP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:941 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" + { + .Instruction = ND_INS_FCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:942 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" + { + .Instruction = ND_INS_FCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:943 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" + { + .Instruction = ND_INS_FCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:944 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" + { + .Instruction = ND_INS_FCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:945 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" + { + .Instruction = ND_INS_FCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:946 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" + { + .Instruction = ND_INS_FCOMPP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 256, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:947 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" + { + .Instruction = ND_INS_FCOS, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 257, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xeb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:948 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" + { + .Instruction = ND_INS_FDECSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 258, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:949 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" + { + .Instruction = ND_INS_FDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:950 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" + { + .Instruction = ND_INS_FDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:951 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" + { + .Instruction = ND_INS_FDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:952 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" + { + .Instruction = ND_INS_FDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:953 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" + { + .Instruction = ND_INS_FDIVP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 260, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:954 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" + { + .Instruction = ND_INS_FDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:955 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" + { + .Instruction = ND_INS_FDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:956 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" + { + .Instruction = ND_INS_FDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:957 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" + { + .Instruction = ND_INS_FDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:958 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" + { + .Instruction = ND_INS_FDIVRP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 262, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:959 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" + { + .Instruction = ND_INS_FEMMS, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 263, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + 0 + }, + }, + + // Pos:960 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" + { + .Instruction = ND_INS_FFREE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:961 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" + { + .Instruction = ND_INS_FFREEP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 265, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:962 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" + { + .Instruction = ND_INS_FIADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 266, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:963 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" + { + .Instruction = ND_INS_FIADD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 266, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:964 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" + { + .Instruction = ND_INS_FICOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:965 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" + { + .Instruction = ND_INS_FICOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:966 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" + { + .Instruction = ND_INS_FICOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:967 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" + { + .Instruction = ND_INS_FICOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:968 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" + { + .Instruction = ND_INS_FIDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 269, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:969 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" + { + .Instruction = ND_INS_FIDIV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 269, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:970 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" + { + .Instruction = ND_INS_FIDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 270, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:971 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" + { + .Instruction = ND_INS_FIDIVR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 270, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:972 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" + { + .Instruction = ND_INS_FILD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 271, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:973 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" + { + .Instruction = ND_INS_FILD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 271, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:974 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" + { + .Instruction = ND_INS_FILD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 271, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:975 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" + { + .Instruction = ND_INS_FIMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 272, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:976 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" + { + .Instruction = ND_INS_FIMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 272, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:977 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" + { + .Instruction = ND_INS_FINCSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 273, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:978 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" + { + .Instruction = ND_INS_FIST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 274, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:979 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" + { + .Instruction = ND_INS_FIST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 274, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:980 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" + { + .Instruction = ND_INS_FISTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:981 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" + { + .Instruction = ND_INS_FISTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:982 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" + { + .Instruction = ND_INS_FISTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:983 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" + { + .Instruction = ND_INS_FISTTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:984 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" + { + .Instruction = ND_INS_FISTTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:985 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" + { + .Instruction = ND_INS_FISTTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:986 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" + { + .Instruction = ND_INS_FISUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:987 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" + { + .Instruction = ND_INS_FISUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:988 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" + { + .Instruction = ND_INS_FISUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 278, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:989 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" + { + .Instruction = ND_INS_FISUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 278, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:990 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" + { + .Instruction = ND_INS_FLD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:991 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" + { + .Instruction = ND_INS_FLD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:992 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" + { + .Instruction = ND_INS_FLD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:993 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" + { + .Instruction = ND_INS_FLD, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:994 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" + { + .Instruction = ND_INS_FLD1, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:995 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" + { + .Instruction = ND_INS_FLDCW, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 281, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:996 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" + { + .Instruction = ND_INS_FLDENV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 282, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:997 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" + { + .Instruction = ND_INS_FLDL2E, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 283, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:998 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" + { + .Instruction = ND_INS_FLDL2T, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 284, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:999 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" + { + .Instruction = ND_INS_FLDLG2, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 285, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1000 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" + { + .Instruction = ND_INS_FLDLN2, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 286, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1001 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" + { + .Instruction = ND_INS_FLDPI, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 287, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1002 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" + { + .Instruction = ND_INS_FLDZ, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 288, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1003 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" + { + .Instruction = ND_INS_FMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 289, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1004 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" + { + .Instruction = ND_INS_FMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 289, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1005 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" + { + .Instruction = ND_INS_FMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 289, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1006 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" + { + .Instruction = ND_INS_FMUL, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 289, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1007 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" + { + .Instruction = ND_INS_FMULP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 290, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1008 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" + { + .Instruction = ND_INS_FNCLEX, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 291, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1009 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" + { + .Instruction = ND_INS_FNDISI, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 292, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1010 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" + { + .Instruction = ND_INS_FNINIT, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 293, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0x00, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1011 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" + { + .Instruction = ND_INS_FNOP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1012 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" + { + .Instruction = ND_INS_FNOP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1013 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" + { + .Instruction = ND_INS_FNOP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1014 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" + { + .Instruction = ND_INS_FNSAVE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 295, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0x00, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1015 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" + { + .Instruction = ND_INS_FNSTCW, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 296, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1016 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" + { + .Instruction = ND_INS_FNSTENV, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 297, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1017 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" + { + .Instruction = ND_INS_FNSTSW, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 298, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1018 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" + { + .Instruction = ND_INS_FNSTSW, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 298, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1019 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" + { + .Instruction = ND_INS_FPATAN, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 299, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1020 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" + { + .Instruction = ND_INS_FPREM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 300, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1021 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" + { + .Instruction = ND_INS_FPREM1, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 301, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1022 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" + { + .Instruction = ND_INS_FPTAN, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 302, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xeb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1023 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" + { + .Instruction = ND_INS_FRINEAR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 303, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1024 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" + { + .Instruction = ND_INS_FRNDINT, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 304, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1025 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" + { + .Instruction = ND_INS_FRSTOR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 305, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87CONTROL, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1026 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" + { + .Instruction = ND_INS_FSCALE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 306, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1027 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" + { + .Instruction = ND_INS_FSIN, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 307, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xeb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1028 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" + { + .Instruction = ND_INS_FSINCOS, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 308, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xeb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1029 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" + { + .Instruction = ND_INS_FSQRT, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 309, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1030 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" + { + .Instruction = ND_INS_FST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1031 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" + { + .Instruction = ND_INS_FST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1032 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" + { + .Instruction = ND_INS_FST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1033 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" + { + .Instruction = ND_INS_FSTDW, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 311, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1034 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1035 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1036 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1037 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1038 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1039 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" + { + .Instruction = ND_INS_FSTP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1040 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" + { + .Instruction = ND_INS_FSTPNCE, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 313, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1041 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" + { + .Instruction = ND_INS_FSTSG, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 314, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1042 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" + { + .Instruction = ND_INS_FSUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1043 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" + { + .Instruction = ND_INS_FSUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1044 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" + { + .Instruction = ND_INS_FSUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1045 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" + { + .Instruction = ND_INS_FSUB, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1046 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" + { + .Instruction = ND_INS_FSUBP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 316, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1047 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" + { + .Instruction = ND_INS_FSUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1048 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" + { + .Instruction = ND_INS_FSUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1049 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" + { + .Instruction = ND_INS_FSUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1050 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" + { + .Instruction = ND_INS_FSUBR, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1051 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" + { + .Instruction = ND_INS_FSUBRP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 318, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1052 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" + { + .Instruction = ND_INS_FTST, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 319, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1053 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" + { + .Instruction = ND_INS_FUCOM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 320, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1054 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" + { + .Instruction = ND_INS_FUCOMI, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 321, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1055 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" + { + .Instruction = ND_INS_FUCOMIP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 322, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xa2, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1056 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" + { + .Instruction = ND_INS_FUCOMP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 323, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1057 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" + { + .Instruction = ND_INS_FUCOMPP, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 324, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1058 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" + { + .Instruction = ND_INS_FXAM, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 325, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xaa, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1059 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" + { + .Instruction = ND_INS_FXCH, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 326, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1060 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" + { + .Instruction = ND_INS_FXCH, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 326, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1061 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" + { + .Instruction = ND_INS_FXCH, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 326, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xf3, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_STi, ND_OPS_ft, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_X87TAG, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1062 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" + { + .Instruction = ND_INS_FXRSTOR, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_FXSAVE, + .Mnemonic = 327, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_FXSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1063 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" + { + .Instruction = ND_INS_FXRSTOR64, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_FXSAVE, + .Mnemonic = 328, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_FXSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1064 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" + { + .Instruction = ND_INS_FXSAVE, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_FXSAVE, + .Mnemonic = 329, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_FXSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1065 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" + { + .Instruction = ND_INS_FXSAVE64, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_FXSAVE, + .Mnemonic = 330, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_FXSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1066 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" + { + .Instruction = ND_INS_FXTRACT, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 331, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1067 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" + { + .Instruction = ND_INS_FYL2X, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 332, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1068 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" + { + .Instruction = ND_INS_FYL2XP1, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 333, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xfb, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_X87STATUS, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1069 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" + { + .Instruction = ND_INS_GETSEC, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SMX, + .Mnemonic = 334, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = ND_CFF_SMX, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1070 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" + { + .Instruction = ND_INS_GF2P8AFFINEINVQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 335, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1071 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" + { + .Instruction = ND_INS_GF2P8AFFINEQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 336, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1072 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" + { + .Instruction = ND_INS_GF2P8MULB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 337, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1073 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" + { + .Instruction = ND_INS_HADDPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 338, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1074 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" + { + .Instruction = ND_INS_HADDPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 339, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1075 Instruction:"HLT" Encoding:"0xF4"/"" + { + .Instruction = ND_INS_HLT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I86, + .Mnemonic = 340, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1076 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" + { + .Instruction = ND_INS_HRESET, + .Category = ND_CAT_HRESET, + .IsaSet = ND_SET_HRESET, + .Mnemonic = 341, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_HRESET, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1077 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" + { + .Instruction = ND_INS_HSUBPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 342, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1078 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" + { + .Instruction = ND_INS_HSUBPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 343, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1079 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1080 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1081 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1082 Instruction:"IDIV Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1083 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1084 Instruction:"IDIV Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1085 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1086 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" + { + .Instruction = ND_INS_IDIV, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1087 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1088 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1089 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1090 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1091 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1092 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1093 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1094 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1095 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1096 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1097 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1098 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1099 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF|ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1100 Instruction:"IMUL Gv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF|ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1101 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF|ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1102 Instruction:"IMUL Gv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF|ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1103 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r"/"RM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1104 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r"/"RM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1105 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1106 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1107 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1108 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r"/"RM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1109 Instruction:"IMUL Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r"/"RM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1110 Instruction:"IMUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1111 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1112 Instruction:"IMUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1113 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r"/"VRM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1114 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r"/"VRM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1115 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r"/"VRM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1116 Instruction:"IMUL Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r"/"VRM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1117 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1118 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1119 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1120 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1121 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" + { + .Instruction = ND_INS_IMUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1122 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" + { + .Instruction = ND_INS_IN, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 346, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1123 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" + { + .Instruction = ND_INS_IN, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 346, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1124 Instruction:"IN AL,DX" Encoding:"0xEC"/"" + { + .Instruction = ND_INS_IN, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 346, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1125 Instruction:"IN eAX,DX" Encoding:"0xED"/"" + { + .Instruction = ND_INS_IN, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 346, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1126 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1127 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1128 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1129 Instruction:"INC Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1130 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1131 Instruction:"INC Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1132 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1133 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1134 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1135 Instruction:"INC Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1136 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1137 Instruction:"INC Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0"/"VM" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1138 Instruction:"INC Zv" Encoding:"0x40"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1139 Instruction:"INC Zv" Encoding:"0x41"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1140 Instruction:"INC Zv" Encoding:"0x42"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1141 Instruction:"INC Zv" Encoding:"0x43"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1142 Instruction:"INC Zv" Encoding:"0x44"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1143 Instruction:"INC Zv" Encoding:"0x45"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1144 Instruction:"INC Zv" Encoding:"0x46"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1145 Instruction:"INC Zv" Encoding:"0x47"/"O" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1146 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1147 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" + { + .Instruction = ND_INS_INC, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 347, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1148 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" + { + .Instruction = ND_INS_INCSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 348, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1149 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" + { + .Instruction = ND_INS_INCSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 349, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_SHS, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1150 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 350, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1151 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 350, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1152 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 351, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1153 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 351, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1154 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" + { + .Instruction = ND_INS_INSERTPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 352, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1155 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_INSERTPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 352, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1156 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" + { + .Instruction = ND_INS_INSERTQ, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 353, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1157 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" + { + .Instruction = ND_INS_INSERTQ, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 353, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1158 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 354, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1159 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" + { + .Instruction = ND_INS_INS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 354, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1160 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" + { + .Instruction = ND_INS_INT, + .Category = ND_CAT_INTERRUPT, + .IsaSet = ND_SET_I86, + .Mnemonic = 355, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_VM, + .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_CETT, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1161 Instruction:"INT1" Encoding:"0xF1"/"" + { + .Instruction = ND_INS_INT1, + .Category = ND_CAT_INTERRUPT, + .IsaSet = ND_SET_I86, + .Mnemonic = 356, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_VM, + .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1162 Instruction:"INT3" Encoding:"0xCC"/"" + { + .Instruction = ND_INS_INT3, + .Category = ND_CAT_INTERRUPT, + .IsaSet = ND_SET_I86, + .Mnemonic = 357, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_VM, + .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_CETT, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1163 Instruction:"INTO" Encoding:"0xCE"/"" + { + .Instruction = ND_INS_INTO, + .Category = ND_CAT_INTERRUPT, + .IsaSet = ND_SET_I86, + .Mnemonic = 358, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_VM, + .ModifiedFlags = 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_CETT|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1164 Instruction:"INVD" Encoding:"0x0F 0x08"/"" + { + .Instruction = ND_INS_INVD, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 359, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1165 Instruction:"INVEPT Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem"/"RM" + { + .Instruction = ND_INS_INVEPT, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 360, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INVEPT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1166 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" + { + .Instruction = ND_INS_INVEPT, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 360, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1167 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" + { + .Instruction = ND_INS_INVLPG, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 361, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1168 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" + { + .Instruction = ND_INS_INVLPGA, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 362, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1169 Instruction:"INVLPGB" Encoding:"NP 0x0F 0x01 /0xFE"/"" + { + .Instruction = ND_INS_INVLPGB, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_INVLPGB, + .Mnemonic = 363, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_INVLPGB, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1170 Instruction:"INVPCID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem"/"RM" + { + .Instruction = ND_INS_INVPCID, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 364, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INVPCID, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1171 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" + { + .Instruction = ND_INS_INVPCID, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_INVPCID, + .Mnemonic = 364, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_INVPCID, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1172 Instruction:"INVVPID Gy,Mdq" Encoding:"evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem"/"RM" + { + .Instruction = ND_INS_INVVPID, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 365, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INVVPID, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1173 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" + { + .Instruction = ND_INS_INVVPID, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 365, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1174 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" + { + .Instruction = ND_INS_IRET, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 366, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1175 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" + { + .Instruction = ND_INS_IRET, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 367, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1176 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" + { + .Instruction = ND_INS_IRET, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 368, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1177 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 369, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1178 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 369, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1179 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 370, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1180 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 370, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1181 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" + { + .Instruction = ND_INS_JrCXZ, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 371, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + }, + }, + + // Pos:1182 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" + { + .Instruction = ND_INS_JrCXZ, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 372, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + }, + }, + + // Pos:1183 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 373, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1184 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 373, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1185 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 374, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1186 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 374, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1187 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" + { + .Instruction = ND_INS_JMPNR, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 375, + .ValidPrefixes = ND_PREF_BND, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1188 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" + { + .Instruction = ND_INS_JMPNR, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 375, + .ValidPrefixes = ND_PREF_BND, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1189 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" + { + .Instruction = ND_INS_JMPNI, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 375, + .ValidPrefixes = ND_PREF_BND|ND_PREF_DNT, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1190 Instruction:"JMPABS Aq" Encoding:"rex2 w:0 0xA1 cq"/"D" + { + .Instruction = ND_INS_JMPABS, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 376, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NO66|ND_FLAG_NO67|ND_FLAG_NOREP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_A, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1191 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" + { + .Instruction = ND_INS_JMPE, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I64, + .Mnemonic = 377, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1192 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" + { + .Instruction = ND_INS_JMPE, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I64, + .Mnemonic = 377, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1193 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" + { + .Instruction = ND_INS_JMPFD, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 378, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1194 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" + { + .Instruction = ND_INS_JMPFI, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 378, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_CETT|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1195 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 379, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1196 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 379, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1197 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 380, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1198 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 380, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1199 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 381, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1200 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 381, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1201 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 382, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1202 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 382, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1203 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 383, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1204 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 383, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1205 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 384, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1206 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 384, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1207 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 385, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1208 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 385, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1209 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 386, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1210 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 386, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1211 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 387, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1212 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 387, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1213 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 388, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1214 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 388, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1215 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" + { + .Instruction = ND_INS_JrCXZ, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 389, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + }, + }, + + // Pos:1216 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 390, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1217 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 390, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1218 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 391, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1219 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" + { + .Instruction = ND_INS_Jcc, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 391, + .ValidPrefixes = ND_PREF_BND|ND_PREF_BH, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_COND|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1220 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" + { + .Instruction = ND_INS_KADD, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 392, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1221 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" + { + .Instruction = ND_INS_KADD, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 393, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1222 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" + { + .Instruction = ND_INS_KADD, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 394, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1223 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" + { + .Instruction = ND_INS_KADD, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 395, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1224 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" + { + .Instruction = ND_INS_KAND, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 396, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1225 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" + { + .Instruction = ND_INS_KAND, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 397, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1226 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" + { + .Instruction = ND_INS_KANDN, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 398, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1227 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" + { + .Instruction = ND_INS_KANDN, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 399, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1228 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" + { + .Instruction = ND_INS_KANDN, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 400, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1229 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" + { + .Instruction = ND_INS_KANDN, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 401, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1230 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" + { + .Instruction = ND_INS_KAND, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 402, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1231 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" + { + .Instruction = ND_INS_KAND, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 403, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1232 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" + { + .Instruction = ND_INS_KMERGE2L1H, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 404, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1233 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" + { + .Instruction = ND_INS_KMERGE2L1L, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 405, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1234 Instruction:"KMOVB rKb,Mb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1235 Instruction:"KMOVB rKb,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1236 Instruction:"KMOVB Mb,rKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1237 Instruction:"KMOVB rKb,Ry" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1238 Instruction:"KMOVB Gy,mKb" Encoding:"evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1239 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1240 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1241 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1242 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1243 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1244 Instruction:"KMOVD rKd,Md" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1245 Instruction:"KMOVD rKd,mKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1246 Instruction:"KMOVD Md,rKd" Encoding:"evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1247 Instruction:"KMOVD rKd,Ry" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1248 Instruction:"KMOVD Gy,mKd" Encoding:"evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1249 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1250 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1251 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1252 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1253 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1254 Instruction:"KMOVQ rKq,Mq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1255 Instruction:"KMOVQ rKq,mKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1256 Instruction:"KMOVQ Mq,rKq" Encoding:"evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1257 Instruction:"KMOVQ rKq,Ry" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1258 Instruction:"KMOVQ Gy,mKq" Encoding:"evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1259 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1260 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1261 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1262 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1263 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1264 Instruction:"KMOVW rKw,Mw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1265 Instruction:"KMOVW rKw,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1266 Instruction:"KMOVW Mw,rKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1267 Instruction:"KMOVW rKw,Ry" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1268 Instruction:"KMOVW Gy,mKw" Encoding:"evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_KMOV, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1269 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1270 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1271 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K21, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1272 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1273 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" + { + .Instruction = ND_INS_KMOV, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1274 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" + { + .Instruction = ND_INS_KNOT, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 410, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1275 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" + { + .Instruction = ND_INS_KNOT, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 411, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1276 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" + { + .Instruction = ND_INS_KNOT, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 412, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1277 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" + { + .Instruction = ND_INS_KNOT, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 413, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1278 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" + { + .Instruction = ND_INS_KOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 414, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1279 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" + { + .Instruction = ND_INS_KOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 415, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1280 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" + { + .Instruction = ND_INS_KOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 416, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1281 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" + { + .Instruction = ND_INS_KORTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 417, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1282 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" + { + .Instruction = ND_INS_KORTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 418, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1283 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" + { + .Instruction = ND_INS_KORTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 419, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1284 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" + { + .Instruction = ND_INS_KORTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 420, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1285 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" + { + .Instruction = ND_INS_KOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 421, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1286 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTL, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 422, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1287 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTL, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 423, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1288 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTL, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 424, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1289 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTL, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 425, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1290 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 426, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1291 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1292 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 428, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1293 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_KSHIFTR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 429, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1294 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" + { + .Instruction = ND_INS_KTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 430, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1295 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" + { + .Instruction = ND_INS_KTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 431, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1296 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" + { + .Instruction = ND_INS_KTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 432, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1297 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" + { + .Instruction = ND_INS_KTEST, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 433, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1298 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" + { + .Instruction = ND_INS_KUNPCKBW, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 434, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1299 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" + { + .Instruction = ND_INS_KUNPCKDQ, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 435, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1300 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" + { + .Instruction = ND_INS_KUNPCKWD, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 436, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1301 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXNOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 437, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1302 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXNOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 438, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1303 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXNOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 439, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1304 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXNOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 440, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1305 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 441, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1306 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 442, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1307 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 443, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1308 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" + { + .Instruction = ND_INS_KXOR, + .Category = ND_CAT_KMASK, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 444, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_K20, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1309 Instruction:"LAHF" Encoding:"0x9F"/"" + { + .Instruction = ND_INS_LAHF, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 445, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1310 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" + { + .Instruction = ND_INS_LAR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 446, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1311 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" + { + .Instruction = ND_INS_LAR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 446, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1312 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" + { + .Instruction = ND_INS_LDDQU, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 447, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1313 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" + { + .Instruction = ND_INS_LDMXCSR, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 448, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1314 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" + { + .Instruction = ND_INS_LDS, + .Category = ND_CAT_SEGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 449, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_DS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1315 Instruction:"LDTILECFG Moq" Encoding:"evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem"/"M" + { + .Instruction = ND_INS_LDTILECFG, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 450, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E1, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1316 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" + { + .Instruction = ND_INS_LDTILECFG, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 450, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1317 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" + { + .Instruction = ND_INS_LEA, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_I86, + .Mnemonic = 451, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_AG|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_0, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1318 Instruction:"LEAVE" Encoding:"0xC9"/"" + { + .Instruction = ND_INS_LEAVE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_I186, + .Mnemonic = 452, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rBP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1319 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" + { + .Instruction = ND_INS_LES, + .Category = ND_CAT_SEGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 453, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_ES, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1320 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" + { + .Instruction = ND_INS_LFENCE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + 0 + }, + }, + + // Pos:1321 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" + { + .Instruction = ND_INS_LFS, + .Category = ND_CAT_SEGOP, + .IsaSet = ND_SET_I386, + .Mnemonic = 455, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_FS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1322 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" + { + .Instruction = ND_INS_LGDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 456, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1323 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" + { + .Instruction = ND_INS_LGS, + .Category = ND_CAT_SEGOP, + .IsaSet = ND_SET_I386, + .Mnemonic = 457, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_GS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1324 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" + { + .Instruction = ND_INS_LIDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 458, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1325 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" + { + .Instruction = ND_INS_LKGS, + .Category = ND_CAT_LKGS, + .IsaSet = ND_SET_LKGS, + .Mnemonic = 459, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_LKGS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1326 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" + { + .Instruction = ND_INS_LKGS, + .Category = ND_CAT_LKGS, + .IsaSet = ND_SET_LKGS, + .Mnemonic = 459, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_LKGS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1327 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" + { + .Instruction = ND_INS_LLDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 460, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1328 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" + { + .Instruction = ND_INS_LLWPCB, + .Category = ND_CAT_LWP, + .IsaSet = ND_SET_LWP, + .Mnemonic = 461, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_LWP, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1329 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" + { + .Instruction = ND_INS_LMSW, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 462, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1330 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" + { + .Instruction = ND_INS_LOADIWKEY, + .Category = ND_CAT_KL, + .IsaSet = ND_SET_KL, + .Mnemonic = 463, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_KL, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1331 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 464, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1332 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 464, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1333 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 465, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1334 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 465, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1335 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 466, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1336 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 466, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1337 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 467, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1338 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" + { + .Instruction = ND_INS_LODS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 467, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1339 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" + { + .Instruction = ND_INS_LOOP, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 468, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1340 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" + { + .Instruction = ND_INS_LOOPNZ, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 469, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1341 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" + { + .Instruction = ND_INS_LOOPZ, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_I86, + .Mnemonic = 470, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CRCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1342 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" + { + .Instruction = ND_INS_LSL, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 471, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1343 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" + { + .Instruction = ND_INS_LSL, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 471, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1344 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" + { + .Instruction = ND_INS_LSS, + .Category = ND_CAT_SEGOP, + .IsaSet = ND_SET_I386, + .Mnemonic = 472, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1345 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" + { + .Instruction = ND_INS_LTR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 473, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1346 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" + { + .Instruction = ND_INS_LWPINS, + .Category = ND_CAT_LWP, + .IsaSet = ND_SET_LWP, + .Mnemonic = 474, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_LWP, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1347 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" + { + .Instruction = ND_INS_LWPVAL, + .Category = ND_CAT_LWP, + .IsaSet = ND_SET_LWP, + .Mnemonic = 475, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_LWP, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1348 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r"/"RM" + { + .Instruction = ND_INS_LZCNT, + .Category = ND_CAT_LZCNT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1349 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r"/"RM" + { + .Instruction = ND_INS_LZCNT, + .Category = ND_CAT_LZCNT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1350 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r"/"RM" + { + .Instruction = ND_INS_LZCNT, + .Category = ND_CAT_LZCNT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1351 Instruction:"LZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r"/"RM" + { + .Instruction = ND_INS_LZCNT, + .Category = ND_CAT_LZCNT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1352 Instruction:"LZCNT Gv,Ev" Encoding:"repz 0x0F 0xBD /r"/"RM" + { + .Instruction = ND_INS_LZCNT, + .Category = ND_CAT_LZCNT, + .IsaSet = ND_SET_LZCNT, + .Mnemonic = 476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_LZCNT, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1353 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" + { + .Instruction = ND_INS_MASKMOVDQU, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 477, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1354 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" + { + .Instruction = ND_INS_MASKMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 478, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_pDI, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1355 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" + { + .Instruction = ND_INS_MAXPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 479, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1356 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" + { + .Instruction = ND_INS_MAXPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 480, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1357 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" + { + .Instruction = ND_INS_MAXSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 481, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1358 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" + { + .Instruction = ND_INS_MAXSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 482, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1359 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" + { + .Instruction = ND_INS_MCOMMIT, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_MCOMMIT, + .Mnemonic = 483, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MCOMMIT, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1360 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" + { + .Instruction = ND_INS_MFENCE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 484, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + 0 + }, + }, + + // Pos:1361 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" + { + .Instruction = ND_INS_MINPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 485, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1362 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" + { + .Instruction = ND_INS_MINPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 486, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1363 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" + { + .Instruction = ND_INS_MINSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 487, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1364 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" + { + .Instruction = ND_INS_MINSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 488, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1365 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" + { + .Instruction = ND_INS_MONITOR, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 489, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MONITOR, + .Operands = + { + OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1366 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" + { + .Instruction = ND_INS_MONITORX, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MWAITT, + .Mnemonic = 490, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1367 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1368 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1369 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1370 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1371 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1372 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1373 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1374 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1375 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1376 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1377 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1378 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1379 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1380 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1381 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1382 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1383 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1384 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1385 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1386 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1387 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1388 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1389 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1390 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1391 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1392 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1393 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1394 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1395 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1396 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" + { + .Instruction = ND_INS_MOV, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = ND_PREF_XRELEASE|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1397 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" + { + .Instruction = ND_INS_MOV_CR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1398 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" + { + .Instruction = ND_INS_MOV_DR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1399 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" + { + .Instruction = ND_INS_MOV_CR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LOCKSP|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1400 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" + { + .Instruction = ND_INS_MOV_DR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1401 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" + { + .Instruction = ND_INS_MOV_TR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1402 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" + { + .Instruction = ND_INS_MOV_TR, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1403 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" + { + .Instruction = ND_INS_MOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 492, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1404 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" + { + .Instruction = ND_INS_MOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 492, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1405 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" + { + .Instruction = ND_INS_MOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 493, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1406 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" + { + .Instruction = ND_INS_MOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 493, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1407 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r"/"RM" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1408 Instruction:"MOVBE Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r"/"RM" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1409 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r"/"MR" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1410 Instruction:"MOVBE Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r"/"MR" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1411 Instruction:"MOVBE Gv,Mv" Encoding:"NP 0x0F 0x38 0xF0 /r:mem"/"RM" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVBE, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVBE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1412 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVBE, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVBE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1413 Instruction:"MOVBE Mv,Gv" Encoding:"NP 0x0F 0x38 0xF1 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVBE, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVBE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1414 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVBE, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MOVBE, + .Mnemonic = 494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_S66|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVBE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1415 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" + { + .Instruction = ND_INS_MOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 495, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1416 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" + { + .Instruction = ND_INS_MOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 495, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1417 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" + { + .Instruction = ND_INS_MOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 495, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_P, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1418 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" + { + .Instruction = ND_INS_MOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 495, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1419 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" + { + .Instruction = ND_INS_MOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 496, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1420 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_MOVDIR64B, + .Category = ND_CAT_MOVDIR64B, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 497, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1421 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" + { + .Instruction = ND_INS_MOVDIR64B, + .Category = ND_CAT_MOVDIR64B, + .IsaSet = ND_SET_MOVDIR64B, + .Mnemonic = 497, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVDIR64B, + .Operands = + { + OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1422 Instruction:"MOVDIRI My,Gy" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVDIRI, + .Category = ND_CAT_MOVDIRI, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 498, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1423 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVDIRI, + .Category = ND_CAT_MOVDIRI, + .IsaSet = ND_SET_MOVDIRI, + .Mnemonic = 498, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MOVDIRI, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1424 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" + { + .Instruction = ND_INS_MOVDQ2Q, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 499, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1425 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" + { + .Instruction = ND_INS_MOVDQA, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 500, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1426 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" + { + .Instruction = ND_INS_MOVDQA, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 500, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1427 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" + { + .Instruction = ND_INS_MOVDQU, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 501, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1428 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" + { + .Instruction = ND_INS_MOVDQU, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 501, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1429 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" + { + .Instruction = ND_INS_MOVHLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 502, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1430 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" + { + .Instruction = ND_INS_MOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 503, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1431 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 503, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1432 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" + { + .Instruction = ND_INS_MOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 504, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1433 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 504, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1434 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" + { + .Instruction = ND_INS_MOVLHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 505, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1435 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" + { + .Instruction = ND_INS_MOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 506, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1436 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 506, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1437 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 507, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1438 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" + { + .Instruction = ND_INS_MOVMSKPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 508, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1439 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" + { + .Instruction = ND_INS_MOVMSKPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 509, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1440 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTDQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 510, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1441 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" + { + .Instruction = ND_INS_MOVNTDQA, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 511, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1442 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTI, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 512, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1443 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 513, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1444 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 514, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1445 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 515, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1446 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 516, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1447 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_MOVNTSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE4A, + .Mnemonic = 517, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4A, + .Operands = + { + OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1448 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1449 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1450 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1451 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1452 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1453 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1454 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_MMX, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1455 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" + { + .Instruction = ND_INS_MOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1456 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" + { + .Instruction = ND_INS_MOVQ2DQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 519, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1457 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 520, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1458 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 520, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1459 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 521, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1460 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 521, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1461 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" + { + .Instruction = ND_INS_MOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 521, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1462 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" + { + .Instruction = ND_INS_MOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 521, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1463 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" + { + .Instruction = ND_INS_MOVSHDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 522, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1464 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" + { + .Instruction = ND_INS_MOVSLDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 523, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1465 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 524, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1466 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 524, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1467 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" + { + .Instruction = ND_INS_MOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 525, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1468 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" + { + .Instruction = ND_INS_MOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 525, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1469 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 526, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1470 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" + { + .Instruction = ND_INS_MOVS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 526, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_X, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1471 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" + { + .Instruction = ND_INS_MOVSX, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I386, + .Mnemonic = 527, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1472 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" + { + .Instruction = ND_INS_MOVSX, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I386, + .Mnemonic = 527, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1473 Instruction:"MOVSXD Gv,Ez" Encoding:"mo64 0x63 /r"/"RM" + { + .Instruction = ND_INS_MOVSXD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_LONGMODE, + .Mnemonic = 528, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1474 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" + { + .Instruction = ND_INS_MOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 529, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1475 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" + { + .Instruction = ND_INS_MOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 529, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1476 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" + { + .Instruction = ND_INS_MOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 530, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1477 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" + { + .Instruction = ND_INS_MOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_SSE, + .Mnemonic = 530, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1478 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" + { + .Instruction = ND_INS_MOVZX, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I386, + .Mnemonic = 531, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1479 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" + { + .Instruction = ND_INS_MOVZX, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I386, + .Mnemonic = 531, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1480 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" + { + .Instruction = ND_INS_MPSADBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 532, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1481 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1482 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1483 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1484 Instruction:"MUL Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1485 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1486 Instruction:"MUL Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1487 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1488 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" + { + .Instruction = ND_INS_MUL, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1489 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" + { + .Instruction = ND_INS_MULPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 534, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1490 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" + { + .Instruction = ND_INS_MULPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 535, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1491 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" + { + .Instruction = ND_INS_MULSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 536, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1492 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" + { + .Instruction = ND_INS_MULSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 537, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1493 Instruction:"MULX Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_MULX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 538, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1494 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_MULX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 538, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1495 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" + { + .Instruction = ND_INS_MWAIT, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SSE3, + .Mnemonic = 539, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MONITOR, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1496 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" + { + .Instruction = ND_INS_MWAITX, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MWAITT, + .Mnemonic = 540, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1497 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1498 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1499 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1500 Instruction:"NEG Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1501 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1502 Instruction:"NEG Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1503 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1504 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1505 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1506 Instruction:"NEG Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1507 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1508 Instruction:"NEG Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3"/"VM" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1509 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 541, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1510 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" + { + .Instruction = ND_INS_NEG, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 541, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1511 Instruction:"NOP" Encoding:"0x90"/"" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1512 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1513 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1514 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1515 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1516 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1517 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1518 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1519 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_NOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1520 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1521 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1522 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1523 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1524 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1525 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1526 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1527 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1528 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1529 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1530 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1531 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1532 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1533 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1534 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1535 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1536 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1537 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1538 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1539 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1540 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1541 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1542 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1543 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1544 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1545 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1A /r:reg"/"RM" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1546 Instruction:"NOP Gv,Ev" Encoding:"mpx NP 0x0F 0x1B /r:reg"/"RM" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1547 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1548 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1549 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1550 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1551 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1552 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1553 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1554 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1555 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1556 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1557 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1558 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1559 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /0:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1560 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1561 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /1:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1562 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1563 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /2:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1564 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1565 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /3:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1566 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1567 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /4:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1568 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1569 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /5:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1570 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1571 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /6:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1572 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1573 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /7:mem"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1574 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1575 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1576 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1577 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1578 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1579 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1580 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1581 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" + { + .Instruction = ND_INS_NOP, + .Category = ND_CAT_WIDENOP, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1582 Instruction:"NOT Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2"/"M" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1583 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2"/"M" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1584 Instruction:"NOT Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2"/"M" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1585 Instruction:"NOT Bb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2"/"VM" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1586 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2"/"VM" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1587 Instruction:"NOT Bv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2"/"VM" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1588 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 543, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1589 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" + { + .Instruction = ND_INS_NOT, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 543, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1590 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1591 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1592 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1593 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1594 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1595 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1596 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1597 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1598 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1599 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1600 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1601 Instruction:"OR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1602 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1603 Instruction:"OR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1604 Instruction:"OR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1605 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1606 Instruction:"OR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1607 Instruction:"OR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1608 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1609 Instruction:"OR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1610 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1611 Instruction:"OR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1612 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1613 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1614 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1615 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1616 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1617 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1618 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1619 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1620 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1621 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1622 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1623 Instruction:"OR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1624 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1625 Instruction:"OR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r"/"VMR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1626 Instruction:"OR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1627 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1628 Instruction:"OR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r"/"VRM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1629 Instruction:"OR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1630 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1631 Instruction:"OR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1632 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1633 Instruction:"OR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib"/"VMI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1634 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1635 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1636 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1637 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1638 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1639 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1640 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1641 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1642 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1643 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" + { + .Instruction = ND_INS_OR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 544, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1644 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" + { + .Instruction = ND_INS_ORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 545, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1645 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" + { + .Instruction = ND_INS_ORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE, + .Mnemonic = 546, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1646 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" + { + .Instruction = ND_INS_OUT, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1647 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" + { + .Instruction = ND_INS_OUT, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1648 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" + { + .Instruction = ND_INS_OUT, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1649 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" + { + .Instruction = ND_INS_OUT, + .Category = ND_CAT_IO, + .IsaSet = ND_SET_I86, + .Mnemonic = 547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1650 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 548, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1651 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 548, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1652 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 549, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1653 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 549, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1654 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 550, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1655 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" + { + .Instruction = ND_INS_OUTS, + .Category = ND_CAT_IOSTRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 550, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_X, ND_OPS_z, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rSI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1656 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" + { + .Instruction = ND_INS_PABSB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 551, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1657 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" + { + .Instruction = ND_INS_PABSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 551, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1658 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" + { + .Instruction = ND_INS_PABSD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 552, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1659 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" + { + .Instruction = ND_INS_PABSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 552, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1660 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" + { + .Instruction = ND_INS_PABSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 553, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1661 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" + { + .Instruction = ND_INS_PABSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 553, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1662 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" + { + .Instruction = ND_INS_PACKSSDW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 554, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1663 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" + { + .Instruction = ND_INS_PACKSSDW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 554, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1664 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" + { + .Instruction = ND_INS_PACKSSWB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 555, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1665 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" + { + .Instruction = ND_INS_PACKSSWB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 555, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1666 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" + { + .Instruction = ND_INS_PACKUSDW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 556, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1667 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" + { + .Instruction = ND_INS_PACKUSWB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 557, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1668 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" + { + .Instruction = ND_INS_PACKUSWB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 557, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1669 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" + { + .Instruction = ND_INS_PADDB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1670 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" + { + .Instruction = ND_INS_PADDB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1671 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" + { + .Instruction = ND_INS_PADDD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1672 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" + { + .Instruction = ND_INS_PADDD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1673 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" + { + .Instruction = ND_INS_PADDQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 560, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1674 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" + { + .Instruction = ND_INS_PADDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 560, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1675 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" + { + .Instruction = ND_INS_PADDSB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1676 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" + { + .Instruction = ND_INS_PADDSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1677 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" + { + .Instruction = ND_INS_PADDSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 562, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1678 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" + { + .Instruction = ND_INS_PADDSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 562, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1679 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" + { + .Instruction = ND_INS_PADDUSB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 563, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1680 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" + { + .Instruction = ND_INS_PADDUSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 563, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1681 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" + { + .Instruction = ND_INS_PADDUSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 564, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1682 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" + { + .Instruction = ND_INS_PADDUSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 564, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1683 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" + { + .Instruction = ND_INS_PADDW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 565, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1684 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" + { + .Instruction = ND_INS_PADDW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 565, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1685 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" + { + .Instruction = ND_INS_PALIGNR, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 566, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1686 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" + { + .Instruction = ND_INS_PALIGNR, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 566, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1687 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" + { + .Instruction = ND_INS_PAND, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_MMX, + .Mnemonic = 567, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1688 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" + { + .Instruction = ND_INS_PAND, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 567, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1689 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" + { + .Instruction = ND_INS_PANDN, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_MMX, + .Mnemonic = 568, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1690 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" + { + .Instruction = ND_INS_PANDN, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 568, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1691 Instruction:"PAUSE" Encoding:"repz 0x90"/"" + { + .Instruction = ND_INS_PAUSE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_PAUSE, + .Mnemonic = 569, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:1692 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" + { + .Instruction = ND_INS_PAVGB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 570, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1693 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" + { + .Instruction = ND_INS_PAVGB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 570, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1694 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" + { + .Instruction = ND_INS_PAVGUSB, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1695 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" + { + .Instruction = ND_INS_PAVGW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 572, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1696 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" + { + .Instruction = ND_INS_PAVGW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 572, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1697 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" + { + .Instruction = ND_INS_PBLENDVB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 573, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1698 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" + { + .Instruction = ND_INS_PBLENDW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 574, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1699 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" + { + .Instruction = ND_INS_PBNDKB, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_TSE, + .Mnemonic = 575, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_TSE, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1700 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" + { + .Instruction = ND_INS_PCLMULQDQ, + .Category = ND_CAT_PCLMULQDQ, + .IsaSet = ND_SET_PCLMULQDQ, + .Mnemonic = 576, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_PCLMULQDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1701 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 577, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1702 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 577, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1703 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 578, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1704 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 578, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1705 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 579, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1706 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 580, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1707 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" + { + .Instruction = ND_INS_PCMPEQW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 580, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1708 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" + { + .Instruction = ND_INS_PCMPESTRI, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 581, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 4), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1709 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" + { + .Instruction = ND_INS_PCMPESTRM, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 582, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 4), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1710 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 583, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1711 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 583, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1712 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 584, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1713 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 584, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1714 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 585, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1715 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1716 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" + { + .Instruction = ND_INS_PCMPGTW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1717 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" + { + .Instruction = ND_INS_PCMPISTRI, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 2), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1718 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" + { + .Instruction = ND_INS_PCMPISTRM, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE42, + .Mnemonic = 588, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 2), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE42, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1719 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" + { + .Instruction = ND_INS_PCONFIG, + .Category = ND_CAT_PCONFIG, + .IsaSet = ND_SET_PCONFIG, + .Mnemonic = 589, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_PCONFIG, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rBX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1720 Instruction:"PDEP Gy,By,Ey" Encoding:"evex m:2 p:3 l:0 nf:0 0xF5 /r"/"RVM" + { + .Instruction = ND_INS_PDEP, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 590, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1721 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" + { + .Instruction = ND_INS_PDEP, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 590, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1722 Instruction:"PEXT Gy,By,Ey" Encoding:"evex m:2 p:2 l:0 nf:0 0xF5 /r"/"RVM" + { + .Instruction = ND_INS_PEXT, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 591, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1723 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" + { + .Instruction = ND_INS_PEXT, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 591, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1724 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_PEXTRB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 592, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1725 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_PEXTRB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 592, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1726 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_PEXTRD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 593, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1727 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_PEXTRD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 593, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1728 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_PEXTRQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 594, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1729 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_PEXTRQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 594, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1730 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_PEXTRW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1731 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_PEXTRW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1732 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_PEXTRW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1733 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_PEXTRW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1734 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" + { + .Instruction = ND_INS_PF2ID, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 596, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1735 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" + { + .Instruction = ND_INS_PF2IW, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 597, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1736 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" + { + .Instruction = ND_INS_PFACC, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 598, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1737 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" + { + .Instruction = ND_INS_PFADD, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 599, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1738 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" + { + .Instruction = ND_INS_PFCMPEQ, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 600, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1739 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" + { + .Instruction = ND_INS_PFCMPGE, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 601, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1740 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" + { + .Instruction = ND_INS_PFCMPGT, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 602, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1741 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" + { + .Instruction = ND_INS_PFMAX, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 603, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1742 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" + { + .Instruction = ND_INS_PFMIN, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 604, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1743 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" + { + .Instruction = ND_INS_PFMUL, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 605, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1744 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" + { + .Instruction = ND_INS_PFNACC, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 606, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1745 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" + { + .Instruction = ND_INS_PFPNACC, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1746 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" + { + .Instruction = ND_INS_PFRCP, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1747 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" + { + .Instruction = ND_INS_PFRCPIT1, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 609, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1748 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" + { + .Instruction = ND_INS_PFRCPIT2, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1749 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" + { + .Instruction = ND_INS_PFRCPV, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 611, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1750 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" + { + .Instruction = ND_INS_PFRSQIT1, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 612, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1751 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" + { + .Instruction = ND_INS_PFRSQRT, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 613, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1752 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" + { + .Instruction = ND_INS_PFRSQRTV, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1753 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" + { + .Instruction = ND_INS_PFSUB, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 615, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1754 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" + { + .Instruction = ND_INS_PFSUBR, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 616, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1755 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" + { + .Instruction = ND_INS_PHADDD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 617, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1756 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" + { + .Instruction = ND_INS_PHADDD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 617, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1757 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" + { + .Instruction = ND_INS_PHADDSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 618, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1758 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" + { + .Instruction = ND_INS_PHADDSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 618, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1759 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" + { + .Instruction = ND_INS_PHADDW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 619, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1760 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" + { + .Instruction = ND_INS_PHADDW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 619, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1761 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" + { + .Instruction = ND_INS_PHMINPOSUW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 620, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1762 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" + { + .Instruction = ND_INS_PHSUBD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1763 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" + { + .Instruction = ND_INS_PHSUBD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1764 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" + { + .Instruction = ND_INS_PHSUBSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 622, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1765 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" + { + .Instruction = ND_INS_PHSUBSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 622, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1766 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" + { + .Instruction = ND_INS_PHSUBW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 623, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1767 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" + { + .Instruction = ND_INS_PHSUBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 623, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1768 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" + { + .Instruction = ND_INS_PI2FD, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 624, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1769 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" + { + .Instruction = ND_INS_PI2FW, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 625, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1770 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" + { + .Instruction = ND_INS_PINSRB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 626, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1771 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_PINSRB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 626, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1772 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + .Instruction = ND_INS_PINSRD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 627, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1773 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" + { + .Instruction = ND_INS_PINSRQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 628, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1774 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_PINSRW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1775 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" + { + .Instruction = ND_INS_PINSRW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1776 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_PINSRW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1777 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" + { + .Instruction = ND_INS_PINSRW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1778 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" + { + .Instruction = ND_INS_PMADDUBSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1779 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" + { + .Instruction = ND_INS_PMADDUBSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1780 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" + { + .Instruction = ND_INS_PMADDWD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1781 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" + { + .Instruction = ND_INS_PMADDWD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1782 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" + { + .Instruction = ND_INS_PMAXSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 632, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1783 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" + { + .Instruction = ND_INS_PMAXSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 633, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1784 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" + { + .Instruction = ND_INS_PMAXSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1785 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" + { + .Instruction = ND_INS_PMAXSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1786 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" + { + .Instruction = ND_INS_PMAXUB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 635, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1787 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" + { + .Instruction = ND_INS_PMAXUB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 635, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1788 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" + { + .Instruction = ND_INS_PMAXUD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 636, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1789 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" + { + .Instruction = ND_INS_PMAXUW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 637, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1790 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" + { + .Instruction = ND_INS_PMINSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 638, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1791 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" + { + .Instruction = ND_INS_PMINSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 639, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1792 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" + { + .Instruction = ND_INS_PMINSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1793 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" + { + .Instruction = ND_INS_PMINSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1794 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" + { + .Instruction = ND_INS_PMINUB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1795 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" + { + .Instruction = ND_INS_PMINUB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1796 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" + { + .Instruction = ND_INS_PMINUD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 642, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1797 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" + { + .Instruction = ND_INS_PMINUW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1798 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" + { + .Instruction = ND_INS_PMOVMSKB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSE, + .Mnemonic = 644, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1799 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" + { + .Instruction = ND_INS_PMOVMSKB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 644, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1800 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXBD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 645, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1801 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXBQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 646, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1802 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 647, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1803 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 648, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1804 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXWD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 649, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1805 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" + { + .Instruction = ND_INS_PMOVSXWQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 650, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1806 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXBD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 651, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1807 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXBQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 652, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1808 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 653, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1809 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 654, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1810 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXWD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 655, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1811 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" + { + .Instruction = ND_INS_PMOVZXWQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 656, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1812 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" + { + .Instruction = ND_INS_PMULDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 657, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1813 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" + { + .Instruction = ND_INS_PMULHRSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 658, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1814 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" + { + .Instruction = ND_INS_PMULHRSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 658, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1815 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" + { + .Instruction = ND_INS_PMULHRW, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 659, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1816 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" + { + .Instruction = ND_INS_PMULHUW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 660, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1817 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" + { + .Instruction = ND_INS_PMULHUW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 660, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1818 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" + { + .Instruction = ND_INS_PMULHW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 661, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1819 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" + { + .Instruction = ND_INS_PMULHW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 661, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1820 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" + { + .Instruction = ND_INS_PMULLD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 662, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1821 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" + { + .Instruction = ND_INS_PMULLW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 663, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1822 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" + { + .Instruction = ND_INS_PMULLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 663, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1823 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" + { + .Instruction = ND_INS_PMULUDQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 664, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1824 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" + { + .Instruction = ND_INS_PMULUDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 664, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1825 Instruction:"POP ES" Encoding:"0x07"/"" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1826 Instruction:"POP SS" Encoding:"0x17"/"" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1827 Instruction:"POP DS" Encoding:"0x1F"/"" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1828 Instruction:"POP Zv" Encoding:"0x58"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1829 Instruction:"POP Zv" Encoding:"0x59"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1830 Instruction:"POP Zv" Encoding:"0x5A"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1831 Instruction:"POP Zv" Encoding:"0x5B"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1832 Instruction:"POP Zv" Encoding:"0x5C"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1833 Instruction:"POP Zv" Encoding:"0x5D"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1834 Instruction:"POP Zv" Encoding:"0x5E"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1835 Instruction:"POP Zv" Encoding:"0x5F"/"O" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1836 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1837 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1838 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" + { + .Instruction = ND_INS_POP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1839 Instruction:"POP2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg"/"VM" + { + .Instruction = ND_INS_POP2, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 666, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_PP2, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1840 Instruction:"POP2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg"/"VM" + { + .Instruction = ND_INS_POP2P, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 667, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_PP2, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1841 Instruction:"POPA" Encoding:"ds16 0x61"/"" + { + .Instruction = ND_INS_POPA, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I386, + .Mnemonic = 668, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1842 Instruction:"POPAD" Encoding:"ds32 0x61"/"" + { + .Instruction = ND_INS_POPAD, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I386, + .Mnemonic = 669, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1843 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r"/"RM" + { + .Instruction = ND_INS_POPCNT, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1844 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r"/"RM" + { + .Instruction = ND_INS_POPCNT, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1845 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r"/"RM" + { + .Instruction = ND_INS_POPCNT, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1846 Instruction:"POPCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r"/"RM" + { + .Instruction = ND_INS_POPCNT, + .Category = ND_CAT_APX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1847 Instruction:"POPCNT Gv,Ev" Encoding:"repz 0x0F 0xB8 /r"/"RM" + { + .Instruction = ND_INS_POPCNT, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_POPCNT, + .Mnemonic = 670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_POPCNT, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1848 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" + { + .Instruction = ND_INS_POPF, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 671, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1849 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" + { + .Instruction = ND_INS_POPF, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 672, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1850 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" + { + .Instruction = ND_INS_POPF, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_I86, + .Mnemonic = 673, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1851 Instruction:"POPP Zv" Encoding:"rex2w 0x58"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1852 Instruction:"POPP Zv" Encoding:"rex2w 0x59"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1853 Instruction:"POPP Zv" Encoding:"rex2w 0x5A"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1854 Instruction:"POPP Zv" Encoding:"rex2w 0x5B"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1855 Instruction:"POPP Zv" Encoding:"rex2w 0x5C"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1856 Instruction:"POPP Zv" Encoding:"rex2w 0x5D"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1857 Instruction:"POPP Zv" Encoding:"rex2w 0x5E"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1858 Instruction:"POPP Zv" Encoding:"rex2w 0x5F"/"O" + { + .Instruction = ND_INS_POPP, + .Category = ND_CAT_POP, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1859 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" + { + .Instruction = ND_INS_POR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_MMX, + .Mnemonic = 675, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1860 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" + { + .Instruction = ND_INS_POR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 675, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1861 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" + { + .Instruction = ND_INS_PREFETCH, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 676, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1862 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" + { + .Instruction = ND_INS_PREFETCH, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 676, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1863 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" + { + .Instruction = ND_INS_PREFETCH, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 676, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1864 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" + { + .Instruction = ND_INS_PREFETCH, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 676, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1865 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" + { + .Instruction = ND_INS_PREFETCHE, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 677, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1866 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" + { + .Instruction = ND_INS_PREFETCHIT0, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCHITI, + .Mnemonic = 678, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_PREFETCHITI, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1867 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" + { + .Instruction = ND_INS_PREFETCHIT1, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCHITI, + .Mnemonic = 679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_PREFETCHITI, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), + }, + }, + + // Pos:1868 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" + { + .Instruction = ND_INS_PREFETCHM, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1869 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" + { + .Instruction = ND_INS_PREFETCHNTA, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 681, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1870 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" + { + .Instruction = ND_INS_PREFETCHNTA, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 681, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1871 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT0, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1872 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT0, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1873 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT1, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1874 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT1, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1875 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT2, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 684, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1876 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" + { + .Instruction = ND_INS_PREFETCHT2, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_SSE, + .Mnemonic = 684, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1877 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" + { + .Instruction = ND_INS_PREFETCHW, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 685, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1878 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" + { + .Instruction = ND_INS_PREFETCHWT1, + .Category = ND_CAT_PREFETCH, + .IsaSet = ND_SET_PREFETCH_NOP, + .Mnemonic = 686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), + }, + }, + + // Pos:1879 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" + { + .Instruction = ND_INS_PSADBW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 687, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1880 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" + { + .Instruction = ND_INS_PSADBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 687, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1881 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" + { + .Instruction = ND_INS_PSHUFB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 688, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1882 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" + { + .Instruction = ND_INS_PSHUFB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 688, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1883 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_PSHUFD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 689, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1884 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_PSHUFHW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 690, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1885 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_PSHUFLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 691, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1886 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_PSHUFW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 692, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1887 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" + { + .Instruction = ND_INS_PSIGNB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 693, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1888 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" + { + .Instruction = ND_INS_PSIGNB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 693, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1889 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" + { + .Instruction = ND_INS_PSIGND, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 694, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1890 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" + { + .Instruction = ND_INS_PSIGND, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 694, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1891 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" + { + .Instruction = ND_INS_PSIGNW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 695, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1892 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" + { + .Instruction = ND_INS_PSIGNW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSSE3, + .Mnemonic = 695, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSSE3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1893 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 696, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1894 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 696, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1895 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" + { + .Instruction = ND_INS_PSLLD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 696, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1896 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" + { + .Instruction = ND_INS_PSLLD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 696, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1897 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 697, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1898 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 698, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1899 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 698, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1900 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" + { + .Instruction = ND_INS_PSLLQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 698, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1901 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" + { + .Instruction = ND_INS_PSLLQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 698, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1902 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 699, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1903 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" + { + .Instruction = ND_INS_PSLLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 699, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1904 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" + { + .Instruction = ND_INS_PSLLW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 699, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1905 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" + { + .Instruction = ND_INS_PSLLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 699, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1906 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" + { + .Instruction = ND_INS_PSMASH, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 700, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_SNP, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1907 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" + { + .Instruction = ND_INS_PSRAD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 701, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1908 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" + { + .Instruction = ND_INS_PSRAD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 701, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1909 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" + { + .Instruction = ND_INS_PSRAD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 701, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1910 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" + { + .Instruction = ND_INS_PSRAD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 701, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1911 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" + { + .Instruction = ND_INS_PSRAW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 702, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1912 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" + { + .Instruction = ND_INS_PSRAW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 702, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1913 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" + { + .Instruction = ND_INS_PSRAW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 702, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1914 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" + { + .Instruction = ND_INS_PSRAW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 702, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1915 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 703, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1916 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 703, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1917 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" + { + .Instruction = ND_INS_PSRLD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 703, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1918 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" + { + .Instruction = ND_INS_PSRLD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 703, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1919 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 704, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1920 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 705, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1921 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 705, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1922 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" + { + .Instruction = ND_INS_PSRLQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 705, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1923 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" + { + .Instruction = ND_INS_PSRLQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 705, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1924 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 706, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1925 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" + { + .Instruction = ND_INS_PSRLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 706, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1926 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" + { + .Instruction = ND_INS_PSRLW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 706, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1927 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" + { + .Instruction = ND_INS_PSRLW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 706, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1928 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" + { + .Instruction = ND_INS_PSUBB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 707, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1929 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" + { + .Instruction = ND_INS_PSUBB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 707, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1930 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" + { + .Instruction = ND_INS_PSUBD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 708, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1931 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" + { + .Instruction = ND_INS_PSUBD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 708, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1932 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" + { + .Instruction = ND_INS_PSUBQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 709, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1933 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" + { + .Instruction = ND_INS_PSUBQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 709, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1934 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" + { + .Instruction = ND_INS_PSUBSB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 710, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1935 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" + { + .Instruction = ND_INS_PSUBSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 710, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1936 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" + { + .Instruction = ND_INS_PSUBSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 711, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1937 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" + { + .Instruction = ND_INS_PSUBSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 711, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1938 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" + { + .Instruction = ND_INS_PSUBUSB, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 712, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1939 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" + { + .Instruction = ND_INS_PSUBUSB, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 712, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1940 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" + { + .Instruction = ND_INS_PSUBUSW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 713, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1941 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" + { + .Instruction = ND_INS_PSUBUSW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 713, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1942 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" + { + .Instruction = ND_INS_PSUBW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 714, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1943 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" + { + .Instruction = ND_INS_PSUBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 714, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1944 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" + { + .Instruction = ND_INS_PSWAPD, + .Category = ND_CAT_3DNOW, + .IsaSet = ND_SET_3DNOW, + .Mnemonic = 715, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_3DNOW|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_3DNOW, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1945 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" + { + .Instruction = ND_INS_PTEST, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 716, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1946 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" + { + .Instruction = ND_INS_PTWRITE, + .Category = ND_CAT_PTWRITE, + .IsaSet = ND_SET_PTWRITE, + .Mnemonic = 717, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NO66|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_PTWRITE, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1947 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHBW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 718, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1948 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 718, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1949 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHDQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 719, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1950 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 719, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1951 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHQDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 720, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1952 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHWD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 721, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1953 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKHWD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 721, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1954 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLBW, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 722, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1955 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLBW, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 722, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1956 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLDQ, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 723, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1957 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 723, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1958 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLQDQ, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 724, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1959 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLWD, + .Category = ND_CAT_MMX, + .IsaSet = ND_SET_MMX, + .Mnemonic = 725, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1960 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" + { + .Instruction = ND_INS_PUNPCKLWD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 725, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1961 Instruction:"PUSH ES" Encoding:"0x06"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_ES, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1962 Instruction:"PUSH CS" Encoding:"0x0E"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1963 Instruction:"PUSH SS" Encoding:"0x16"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_SS, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1964 Instruction:"PUSH DS" Encoding:"0x1E"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_DS, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1965 Instruction:"PUSH Zv" Encoding:"0x50"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1966 Instruction:"PUSH Zv" Encoding:"0x51"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1967 Instruction:"PUSH Zv" Encoding:"0x52"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1968 Instruction:"PUSH Zv" Encoding:"0x53"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1969 Instruction:"PUSH Zv" Encoding:"0x54"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1970 Instruction:"PUSH Zv" Encoding:"0x55"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1971 Instruction:"PUSH Zv" Encoding:"0x56"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1972 Instruction:"PUSH Zv" Encoding:"0x57"/"O" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1973 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1974 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXDW, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1975 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1976 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_FS, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1977 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" + { + .Instruction = ND_INS_PUSH, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_GS, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1978 Instruction:"PUSH2 Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg"/"VM" + { + .Instruction = ND_INS_PUSH2, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 727, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_PP2, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1979 Instruction:"PUSH2P Bv,Rv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg"/"VM" + { + .Instruction = ND_INS_PUSH2P, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 728, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_PP2, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1980 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" + { + .Instruction = ND_INS_PUSHA, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I386, + .Mnemonic = 729, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1981 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" + { + .Instruction = ND_INS_PUSHAD, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I386, + .Mnemonic = 730, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v8, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1982 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" + { + .Instruction = ND_INS_PUSHF, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 731, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1983 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" + { + .Instruction = ND_INS_PUSHF, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 732, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1984 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" + { + .Instruction = ND_INS_PUSHF, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_I86, + .Mnemonic = 733, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1985 Instruction:"PUSHP Zv" Encoding:"rex2w 0x50"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1986 Instruction:"PUSHP Zv" Encoding:"rex2w 0x51"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1987 Instruction:"PUSHP Zv" Encoding:"rex2w 0x52"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1988 Instruction:"PUSHP Zv" Encoding:"rex2w 0x53"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1989 Instruction:"PUSHP Zv" Encoding:"rex2w 0x54"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1990 Instruction:"PUSHP Zv" Encoding:"rex2w 0x55"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1991 Instruction:"PUSHP Zv" Encoding:"rex2w 0x56"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1992 Instruction:"PUSHP Zv" Encoding:"rex2w 0x57"/"O" + { + .Instruction = ND_INS_PUSHP, + .Category = ND_CAT_PUSH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1993 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" + { + .Instruction = ND_INS_PVALIDATE, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 735, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SNP, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:1994 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" + { + .Instruction = ND_INS_PXOR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_MMX, + .Mnemonic = 736, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_MMX, + .Operands = + { + OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1995 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" + { + .Instruction = ND_INS_PXOR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 736, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:1996 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1997 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1998 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:1999 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2000 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2001 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2002 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2003 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2004 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2005 Instruction:"RCL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2006 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2007 Instruction:"RCL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2008 Instruction:"RCL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2009 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2010 Instruction:"RCL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2011 Instruction:"RCL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2012 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2013 Instruction:"RCL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2014 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2015 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2016 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2017 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2018 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2019 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2020 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2021 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2022 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2023 Instruction:"RCL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2024 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2025 Instruction:"RCL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib"/"VMI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2026 Instruction:"RCL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2027 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2028 Instruction:"RCL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2"/"VM1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2029 Instruction:"RCL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2030 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2031 Instruction:"RCL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2"/"VMC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2032 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2033 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2034 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2035 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2036 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2037 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" + { + .Instruction = ND_INS_RCL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2038 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" + { + .Instruction = ND_INS_RCPPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 738, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2039 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" + { + .Instruction = ND_INS_RCPSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 739, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2040 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2041 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2042 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2043 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2044 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2045 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2046 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2047 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2048 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2049 Instruction:"RCR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2050 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2051 Instruction:"RCR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2052 Instruction:"RCR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2053 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2054 Instruction:"RCR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2055 Instruction:"RCR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2056 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2057 Instruction:"RCR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2058 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2059 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2060 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2061 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2062 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2063 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2064 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2065 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2066 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2067 Instruction:"RCR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2068 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2069 Instruction:"RCR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib"/"VMI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2070 Instruction:"RCR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2071 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2072 Instruction:"RCR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3"/"VM1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2073 Instruction:"RCR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2074 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2075 Instruction:"RCR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3"/"VMC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2076 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2077 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2078 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2079 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2080 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2081 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" + { + .Instruction = ND_INS_RCR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2082 Instruction:"RDFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /0:reg"/"M" + { + .Instruction = ND_INS_RDFSBASE, + .Category = ND_CAT_RDWRFSGS, + .IsaSet = ND_SET_RDWRFSGS, + .Mnemonic = 741, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RDWRFSGS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2083 Instruction:"RDGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /1:reg"/"M" + { + .Instruction = ND_INS_RDGSBASE, + .Category = ND_CAT_RDWRFSGS, + .IsaSet = ND_SET_RDWRFSGS, + .Mnemonic = 742, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RDWRFSGS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2084 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" + { + .Instruction = ND_INS_RDMSR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_PENTIUMREAL, + .Mnemonic = 743, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = ND_CFF_MSR, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2085 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" + { + .Instruction = ND_INS_RDMSRLIST, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSRLIST, + .Mnemonic = 744, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSRLIST, + .Operands = + { + OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2086 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" + { + .Instruction = ND_INS_RDPID, + .Category = ND_CAT_RDPID, + .IsaSet = ND_SET_RDPID, + .Mnemonic = 745, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDPID, + .Operands = + { + OP(ND_OPT_R, ND_OPS_yf, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2087 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" + { + .Instruction = ND_INS_RDPKRU, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_PKU, + .Mnemonic = 746, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_PKU, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2088 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" + { + .Instruction = ND_INS_RDPMC, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_RDPMC, + .Mnemonic = 747, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2089 Instruction:"RDPRU" Encoding:"NP 0x0F 0x01 /0xFD"/"" + { + .Instruction = ND_INS_RDPRU, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_RDPRU, + .Mnemonic = 748, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDPRU, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2090 Instruction:"RDRAND Rv" Encoding:"NP 0x0F 0xC7 /6:reg"/"M" + { + .Instruction = ND_INS_RDRAND, + .Category = ND_CAT_RDRAND, + .IsaSet = ND_SET_RDRAND, + .Mnemonic = 749, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDRAND, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2091 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" + { + .Instruction = ND_INS_RDRAND, + .Category = ND_CAT_RDRAND, + .IsaSet = ND_SET_RDRAND, + .Mnemonic = 749, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_S66|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDRAND, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2092 Instruction:"RDSEED Rv" Encoding:"NP 0x0F 0xC7 /7:reg"/"M" + { + .Instruction = ND_INS_RDSEED, + .Category = ND_CAT_RDSEED, + .IsaSet = ND_SET_RDSEED, + .Mnemonic = 750, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDSEED, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2093 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" + { + .Instruction = ND_INS_RDSEED, + .Category = ND_CAT_RDSEED, + .IsaSet = ND_SET_RDSEED, + .Mnemonic = 750, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_S66|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDSEED, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2094 Instruction:"RDSSPD Rd" Encoding:"cet repz 0x0F 0x1E /1:reg"/"M" + { + .Instruction = ND_INS_RSSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 751, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2095 Instruction:"RDSSPQ Rq" Encoding:"cet repz rexw 0x0F 0x1E /1:reg"/"M" + { + .Instruction = ND_INS_RSSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 752, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2096 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" + { + .Instruction = ND_INS_RDTSC, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_PENTIUMREAL, + .Mnemonic = 753, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2097 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" + { + .Instruction = ND_INS_RDTSCP, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_RDTSCP, + .Mnemonic = 754, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RDTSCP, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_TSC, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_TSCAUX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2098 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" + { + .Instruction = ND_INS_RETF, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 755, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2099 Instruction:"RETF" Encoding:"0xCB"/"" + { + .Instruction = ND_INS_RETF, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 755, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v2, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2100 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" + { + .Instruction = ND_INS_RETN, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 756, + .ValidPrefixes = ND_PREF_BND, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2101 Instruction:"RETN" Encoding:"0xC3"/"" + { + .Instruction = ND_INS_RETN, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_I86, + .Mnemonic = 756, + .ValidPrefixes = ND_PREF_BND, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2102 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" + { + .Instruction = ND_INS_RMPADJUST, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 757, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_SNP, + .Operands = + { + OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2103 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" + { + .Instruction = ND_INS_RMPQUERY, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 758, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RMPQUERY, + .Operands = + { + OP(ND_OPT_pAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2104 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" + { + .Instruction = ND_INS_RMPUPDATE, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SNP, + .Mnemonic = 759, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_SNP, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_pCX, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2105 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2106 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2107 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2108 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2109 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2110 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2111 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2112 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2113 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2114 Instruction:"ROL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2115 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2116 Instruction:"ROL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2117 Instruction:"ROL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2118 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2119 Instruction:"ROL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2120 Instruction:"ROL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2121 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2122 Instruction:"ROL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2123 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2124 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2125 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2126 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2127 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2128 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2129 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2130 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2131 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2132 Instruction:"ROL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2133 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2134 Instruction:"ROL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib"/"VMI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2135 Instruction:"ROL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2136 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2137 Instruction:"ROL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0"/"VM1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2138 Instruction:"ROL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2139 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2140 Instruction:"ROL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0"/"VMC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2141 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2142 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2143 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2144 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2145 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2146 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" + { + .Instruction = ND_INS_ROL, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2147 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2148 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2149 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2150 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2151 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2152 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2153 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2154 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2155 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2156 Instruction:"ROR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2157 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2158 Instruction:"ROR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2159 Instruction:"ROR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2160 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2161 Instruction:"ROR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2162 Instruction:"ROR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2163 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2164 Instruction:"ROR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2165 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2166 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2167 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2168 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2169 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2170 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2171 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2172 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2173 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2174 Instruction:"ROR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2175 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2176 Instruction:"ROR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib"/"VMI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2177 Instruction:"ROR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2178 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2179 Instruction:"ROR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1"/"VM1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2180 Instruction:"ROR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2181 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2182 Instruction:"ROR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1"/"VMC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2183 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2184 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2185 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2186 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2187 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2188 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" + { + .Instruction = ND_INS_ROR, + .Category = ND_CAT_ROTATE, + .IsaSet = ND_SET_I86, + .Mnemonic = 761, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2189 Instruction:"RORX Gy,Ey,Ib" Encoding:"evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib"/"RMI" + { + .Instruction = ND_INS_RORX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2190 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" + { + .Instruction = ND_INS_RORX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2191 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" + { + .Instruction = ND_INS_ROUNDPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2192 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" + { + .Instruction = ND_INS_ROUNDPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 764, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2193 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" + { + .Instruction = ND_INS_ROUNDSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 765, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2194 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" + { + .Instruction = ND_INS_ROUNDSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE4, + .Mnemonic = 766, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2195 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" + { + .Instruction = ND_INS_RSM, + .Category = ND_CAT_SYSRET, + .IsaSet = ND_SET_I486, + .Mnemonic = 767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2196 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" + { + .Instruction = ND_INS_RSQRTPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 768, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2197 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" + { + .Instruction = ND_INS_RSQRTSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 769, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2198 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" + { + .Instruction = ND_INS_RSTORSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 770, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2199 Instruction:"SAHF" Encoding:"0x9E"/"" + { + .Instruction = ND_INS_SAHF, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 771, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_AH, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2200 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2201 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2202 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2203 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2204 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2205 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2206 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2207 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2208 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2209 Instruction:"SAL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2210 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2211 Instruction:"SAL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2212 Instruction:"SAL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2213 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2214 Instruction:"SAL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2215 Instruction:"SAL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2216 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2217 Instruction:"SAL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2218 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2219 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2220 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2221 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2222 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2223 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2224 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2225 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2226 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2227 Instruction:"SAL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2228 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2229 Instruction:"SAL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib"/"VMI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2230 Instruction:"SAL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2231 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2232 Instruction:"SAL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6"/"VM1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2233 Instruction:"SAL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2234 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2235 Instruction:"SAL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6"/"VMC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2236 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2237 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2238 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2239 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2240 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2241 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" + { + .Instruction = ND_INS_SAL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2242 Instruction:"SALC" Encoding:"0xD6"/"" + { + .Instruction = ND_INS_SALC, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 773, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2243 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2244 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2245 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2246 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2247 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2248 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2249 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2250 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2251 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2252 Instruction:"SAR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2253 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2254 Instruction:"SAR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2255 Instruction:"SAR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2256 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2257 Instruction:"SAR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2258 Instruction:"SAR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2259 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2260 Instruction:"SAR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2261 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2262 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2263 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2264 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2265 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2266 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2267 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2268 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2269 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2270 Instruction:"SAR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2271 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2272 Instruction:"SAR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib"/"VMI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2273 Instruction:"SAR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2274 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2275 Instruction:"SAR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7"/"VM1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2276 Instruction:"SAR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2277 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2278 Instruction:"SAR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7"/"VMC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2279 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2280 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2281 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2282 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2283 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2284 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" + { + .Instruction = ND_INS_SAR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2285 Instruction:"SARX Gy,Ey,By" Encoding:"evex m:2 p:2 l:0 nf:0 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SARX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 775, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2286 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SARX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 775, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2287 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" + { + .Instruction = ND_INS_SAVEPREVSSP, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 776, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_SHS, ND_OPS_12, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2288 Instruction:"SBB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r"/"MR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2289 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r"/"MR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2290 Instruction:"SBB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r"/"MR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2291 Instruction:"SBB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r"/"RM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2292 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r"/"RM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2293 Instruction:"SBB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r"/"RM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2294 Instruction:"SBB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2295 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2296 Instruction:"SBB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2297 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2298 Instruction:"SBB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2299 Instruction:"SBB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r"/"VMR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2300 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r"/"VMR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2301 Instruction:"SBB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r"/"VMR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2302 Instruction:"SBB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r"/"VRM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2303 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r"/"VRM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2304 Instruction:"SBB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r"/"VRM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2305 Instruction:"SBB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib"/"VMI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2306 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz"/"VMI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2307 Instruction:"SBB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz"/"VMI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2308 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib"/"VMI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2309 Instruction:"SBB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib"/"VMI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2310 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2311 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2312 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2313 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2314 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2315 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2316 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2317 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2318 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2319 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" + { + .Instruction = ND_INS_SBB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 777, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2320 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 778, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2321 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 778, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2322 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 779, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2323 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 779, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2324 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 780, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2325 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 780, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2326 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 781, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2327 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" + { + .Instruction = ND_INS_SCAS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 781, + .ValidPrefixes = ND_PREF_REPC, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CR, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2328 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" + { + .Instruction = ND_INS_SEAMCALL, + .Category = ND_CAT_TDX, + .IsaSet = ND_SET_TDX, + .Mnemonic = 782, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2329 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" + { + .Instruction = ND_INS_SEAMOPS, + .Category = ND_CAT_TDX, + .IsaSet = ND_SET_TDX, + .Mnemonic = 783, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rR8, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rR9, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2330 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" + { + .Instruction = ND_INS_SEAMRET, + .Category = ND_CAT_TDX, + .IsaSet = ND_SET_TDX, + .Mnemonic = 784, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:2331 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" + { + .Instruction = ND_INS_SENDUIPI, + .Category = ND_CAT_UINTR, + .IsaSet = ND_SET_UINTR, + .Mnemonic = 785, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_UINTR, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2332 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" + { + .Instruction = ND_INS_SERIALIZE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SERIALIZE, + .Mnemonic = 786, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SERIALIZE, + .Operands = + { + 0 + }, + }, + + // Pos:2333 Instruction:"SETBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x46 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 787, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2334 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 787, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2335 Instruction:"SETC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x42 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 788, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2336 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 788, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2337 Instruction:"SETL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4C /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 789, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2338 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 789, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2339 Instruction:"SETLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4E /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 790, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2340 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 790, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2341 Instruction:"SETNBE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x47 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 791, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2342 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 791, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2343 Instruction:"SETNC Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x43 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 792, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2344 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 792, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_CF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2345 Instruction:"SETNL Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4D /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 793, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2346 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 793, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2347 Instruction:"SETNLE Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4F /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 794, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2348 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 794, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2349 Instruction:"SETNO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x41 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 795, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2350 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 795, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2351 Instruction:"SETNP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4B /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 796, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2352 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 796, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2353 Instruction:"SETNS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x49 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 797, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2354 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 797, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2355 Instruction:"SETNZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x45 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 798, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2356 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 798, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2357 Instruction:"SETO Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x40 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 799, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2358 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 799, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_OF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2359 Instruction:"SETP Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x4A /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 800, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2360 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 800, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_PF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2361 Instruction:"SETS Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x48 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 801, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2362 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 801, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_SF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2363 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" + { + .Instruction = ND_INS_SETSSBSY, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 802, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_SHS0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2364 Instruction:"SETZ Eb" Encoding:"evex m:4 l:0 nf:0 p:3 0x44 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 803, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ZU, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2365 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" + { + .Instruction = ND_INS_SETcc, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_I386, + .Mnemonic = 803, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_ZF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_COND|ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2366 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" + { + .Instruction = ND_INS_SFENCE, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 804, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + 0 + }, + }, + + // Pos:2367 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" + { + .Instruction = ND_INS_SGDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 805, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_GDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2368 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r"/"RM" + { + .Instruction = ND_INS_SHA1MSG1, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 806, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2369 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" + { + .Instruction = ND_INS_SHA1MSG1, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 806, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2370 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r"/"RM" + { + .Instruction = ND_INS_SHA1MSG2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 807, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2371 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" + { + .Instruction = ND_INS_SHA1MSG2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 807, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2372 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r"/"RM" + { + .Instruction = ND_INS_SHA1NEXTE, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 808, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2373 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" + { + .Instruction = ND_INS_SHA1NEXTE, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 808, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2374 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib"/"RMI" + { + .Instruction = ND_INS_SHA1RNDS4, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 809, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2375 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" + { + .Instruction = ND_INS_SHA1RNDS4, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 809, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2376 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r"/"RM" + { + .Instruction = ND_INS_SHA256MSG1, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 810, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2377 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" + { + .Instruction = ND_INS_SHA256MSG1, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 810, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2378 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r"/"RM" + { + .Instruction = ND_INS_SHA256MSG2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 811, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2379 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" + { + .Instruction = ND_INS_SHA256MSG2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 811, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2380 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r"/"RM" + { + .Instruction = ND_INS_SHA256RNDS2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 812, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_SHA, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2381 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" + { + .Instruction = ND_INS_SHA256RNDS2, + .Category = ND_CAT_SHA, + .IsaSet = ND_SET_SHA, + .Mnemonic = 812, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2382 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2383 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2384 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2385 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2386 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2387 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2388 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2389 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2390 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2391 Instruction:"SHL Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2392 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2393 Instruction:"SHL Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2394 Instruction:"SHL Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2395 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2396 Instruction:"SHL Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2397 Instruction:"SHL Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2398 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2399 Instruction:"SHL Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2400 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2401 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2402 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2403 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2404 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2405 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2406 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2407 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2408 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2409 Instruction:"SHL Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2410 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2411 Instruction:"SHL Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib"/"VMI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2412 Instruction:"SHL Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2413 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2414 Instruction:"SHL Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4"/"VM1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2415 Instruction:"SHL Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2416 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2417 Instruction:"SHL Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4"/"VMC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2418 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2419 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2420 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2421 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2422 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2423 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" + { + .Instruction = ND_INS_SHL, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 813, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2424 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib"/"MRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2425 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r"/"MRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2426 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib"/"MRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2427 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r"/"MRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2428 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib"/"MRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2429 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r"/"MRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2430 Instruction:"SHLD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib"/"MRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2431 Instruction:"SHLD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r"/"MRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2432 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib"/"VMRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2433 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r"/"VMRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2434 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib"/"VMRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2435 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r"/"VMRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2436 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib"/"VMRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2437 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r"/"VMRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2438 Instruction:"SHLD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib"/"VMRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2439 Instruction:"SHLD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r"/"VMRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2440 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I386, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2441 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" + { + .Instruction = ND_INS_SHLD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I386, + .Mnemonic = 814, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2442 Instruction:"SHLX Gy,Ey,By" Encoding:"evex m:2 p:1 l:0 nf:0 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SHLX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 815, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2443 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SHLX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 815, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2444 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2445 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2446 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2447 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2448 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2449 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2450 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2451 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2452 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2453 Instruction:"SHR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2454 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2455 Instruction:"SHR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2456 Instruction:"SHR Eb,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2457 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2458 Instruction:"SHR Ev,1" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2459 Instruction:"SHR Eb,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2460 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2461 Instruction:"SHR Ev,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2462 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2463 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2464 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2465 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2466 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2467 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2468 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2469 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2470 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2471 Instruction:"SHR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2472 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2473 Instruction:"SHR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib"/"VMI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2474 Instruction:"SHR Bb,Eb,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2475 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2476 Instruction:"SHR Bv,Ev,1" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5"/"VM1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2477 Instruction:"SHR Bb,Eb,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2478 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2479 Instruction:"SHR Bv,Ev,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5"/"VMC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2480 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2481 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2482 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2483 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2484 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2485 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" + { + .Instruction = ND_INS_SHR, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I86, + .Mnemonic = 816, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2486 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib"/"MRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2487 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r"/"MRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2488 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib"/"MRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2489 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r"/"MRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2490 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib"/"MRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2491 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r"/"MRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2492 Instruction:"SHRD Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib"/"MRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2493 Instruction:"SHRD Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r"/"MRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2494 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib"/"VMRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2495 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r"/"VMRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2496 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib"/"VMRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2497 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r"/"VMRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(4, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2498 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib"/"VMRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2499 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r"/"VMRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2500 Instruction:"SHRD Bv,Ev,Gv,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib"/"VMRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2501 Instruction:"SHRD Bv,Ev,Gv,CL" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r"/"VMRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2502 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I386, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2503 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" + { + .Instruction = ND_INS_SHRD, + .Category = ND_CAT_SHIFT, + .IsaSet = ND_SET_I386, + .Mnemonic = 817, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2504 Instruction:"SHRX Gy,Ey,By" Encoding:"evex m:2 p:3 l:0 nf:0 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SHRX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 818, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_BMI, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2505 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" + { + .Instruction = ND_INS_SHRX, + .Category = ND_CAT_BMI2, + .IsaSet = ND_SET_BMI2, + .Mnemonic = 818, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_13, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI2, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2506 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" + { + .Instruction = ND_INS_SHUFPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 819, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2507 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" + { + .Instruction = ND_INS_SHUFPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 820, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2508 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" + { + .Instruction = ND_INS_SIDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 821, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_IDTR, ND_OPS_s, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2509 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" + { + .Instruction = ND_INS_SKINIT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 822, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2510 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" + { + .Instruction = ND_INS_SLDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 823, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2511 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" + { + .Instruction = ND_INS_SLDT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 823, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_LDTR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2512 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" + { + .Instruction = ND_INS_SLWPCB, + .Category = ND_CAT_LWP, + .IsaSet = ND_SET_LWP, + .Mnemonic = 824, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_LWP, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2513 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" + { + .Instruction = ND_INS_SMSW, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 825, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2514 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" + { + .Instruction = ND_INS_SMSW, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286REAL, + .Mnemonic = 825, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_CR0, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2515 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" + { + .Instruction = ND_INS_SPFLT, + .Category = ND_CAT_UNKNOWN, + .IsaSet = ND_SET_UNKNOWN, + .Mnemonic = 826, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2516 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" + { + .Instruction = ND_INS_SQRTPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 827, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2517 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" + { + .Instruction = ND_INS_SQRTPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 828, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2518 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" + { + .Instruction = ND_INS_SQRTSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 829, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2519 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" + { + .Instruction = ND_INS_SQRTSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 830, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2520 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" + { + .Instruction = ND_INS_STAC, + .Category = ND_CAT_SMAP, + .IsaSet = ND_SET_SMAP, + .Mnemonic = 831, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_AC, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SMAP, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2521 Instruction:"STC" Encoding:"0xF9"/"" + { + .Instruction = ND_INS_STC, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 832, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_CF, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2522 Instruction:"STD" Encoding:"0xFD"/"" + { + .Instruction = ND_INS_STD, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 833, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_DF, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2523 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" + { + .Instruction = ND_INS_STGI, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 834, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:2524 Instruction:"STI" Encoding:"0xFB"/"" + { + .Instruction = ND_INS_STI, + .Category = ND_CAT_FLAGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 835, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0|NDR_RFLAG_IF, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2525 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" + { + .Instruction = ND_INS_STMXCSR, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 836, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2526 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 837, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2527 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 837, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2528 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 838, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2529 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 838, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2530 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 839, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2531 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 839, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2532 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 840, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2533 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" + { + .Instruction = ND_INS_STOS, + .Category = ND_CAT_STRINGOP, + .IsaSet = ND_SET_I86, + .Mnemonic = 840, + .ValidPrefixes = ND_PREF_REP, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0|NDR_RFLAG_DF, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Y, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rDI, ND_OPS_asz, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2534 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" + { + .Instruction = ND_INS_STR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 841, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2535 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" + { + .Instruction = ND_INS_STR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 841, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_TR, ND_OPS_w, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2536 Instruction:"STTILECFG Moq" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem"/"M" + { + .Instruction = ND_INS_STTILECFG, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 842, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E2, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2537 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" + { + .Instruction = ND_INS_STTILECFG, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 842, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2538 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" + { + .Instruction = ND_INS_STUI, + .Category = ND_CAT_UINTR, + .IsaSet = ND_SET_UINTR, + .Mnemonic = 843, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_UINTR, + .Operands = + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2539 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2540 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2541 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2542 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2543 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2544 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2545 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2546 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2547 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2548 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2549 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2550 Instruction:"SUB Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2551 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2552 Instruction:"SUB Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2553 Instruction:"SUB Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2554 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2555 Instruction:"SUB Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2556 Instruction:"SUB Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2557 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2558 Instruction:"SUB Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2559 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2560 Instruction:"SUB Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2561 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2562 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2563 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2564 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2565 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2566 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2567 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2568 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2569 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2570 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2571 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2572 Instruction:"SUB Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2573 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2574 Instruction:"SUB Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r"/"VMR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2575 Instruction:"SUB Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2576 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2577 Instruction:"SUB Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r"/"VRM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2578 Instruction:"SUB Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2579 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2580 Instruction:"SUB Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2581 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2582 Instruction:"SUB Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib"/"VMI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2583 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2584 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2585 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2586 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2587 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2588 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2589 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2590 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2591 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2592 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" + { + .Instruction = ND_INS_SUB, + .Category = ND_CAT_ARITH, + .IsaSet = ND_SET_I86, + .Mnemonic = 844, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2593 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" + { + .Instruction = ND_INS_SUBPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 845, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2594 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" + { + .Instruction = ND_INS_SUBPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 846, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2595 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" + { + .Instruction = ND_INS_SUBSD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 847, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2596 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" + { + .Instruction = ND_INS_SUBSS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 848, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2597 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" + { + .Instruction = ND_INS_SWAPGS, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_LONGMODE, + .Mnemonic = 849, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_KGSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2598 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" + { + .Instruction = ND_INS_SYSCALL, + .Category = ND_CAT_SYSCALL, + .IsaSet = ND_SET_AMD, + .Mnemonic = 850, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 10), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_CETT, + .CpuidFlag = ND_CFF_FSC, + .Operands = + { + OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_LSTAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_FMASK, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2599 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" + { + .Instruction = ND_INS_SYSENTER, + .Category = ND_CAT_SYSCALL, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 851, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 9), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_IF, + .Attributes = ND_FLAG_CETT|ND_FLAG_NOREX2, + .CpuidFlag = ND_CFF_SEP, + .Operands = + { + OP(ND_OPT_SCS, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SESP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SEIP, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:2600 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" + { + .Instruction = ND_INS_SYSEXIT, + .Category = ND_CAT_SYSRET, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 852, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 5), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_NOREX2, + .CpuidFlag = ND_CFF_SEP, + .Operands = + { + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2601 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" + { + .Instruction = ND_INS_SYSRET, + .Category = ND_CAT_SYSRET, + .IsaSet = ND_SET_AMD, + .Mnemonic = 853, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 8), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = ND_CFF_FSC, + .Operands = + { + OP(ND_OPT_STAR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rCX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rR11, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_CS, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2602 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" + { + .Instruction = ND_INS_T1MSKC, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 854, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2603 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TCMMIMFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXCOMPLEX, + .Mnemonic = 855, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXCOMPLEX, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2604 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" + { + .Instruction = ND_INS_TCMMRLFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXCOMPLEX, + .Mnemonic = 856, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXCOMPLEX, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2605 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" + { + .Instruction = ND_INS_TDCALL, + .Category = ND_CAT_TDX, + .IsaSet = ND_SET_TDX, + .Mnemonic = 857, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:2606 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" + { + .Instruction = ND_INS_TDPBF16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXBF16, + .Mnemonic = 858, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXBF16, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2607 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" + { + .Instruction = ND_INS_TDPBSSD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXINT8, + .Mnemonic = 859, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXINT8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2608 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" + { + .Instruction = ND_INS_TDPBSUD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXINT8, + .Mnemonic = 860, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXINT8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2609 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" + { + .Instruction = ND_INS_TDPBUSD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXINT8, + .Mnemonic = 861, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXINT8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2610 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" + { + .Instruction = ND_INS_TDPBUUD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXINT8, + .Mnemonic = 862, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXINT8, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2611 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" + { + .Instruction = ND_INS_TDPFP16PS, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXFP16, + .Mnemonic = 863, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXFP16, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2612 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2613 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2614 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2615 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_NOREX2, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2616 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2617 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2618 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2619 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" + { + .Instruction = ND_INS_TEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 864, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2620 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" + { + .Instruction = ND_INS_TESTUI, + .Category = ND_CAT_UINTR, + .IsaSet = ND_SET_UINTR, + .Mnemonic = 865, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_UINTR, + .Operands = + { + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2621 Instruction:"TILELOADD rTt,Mt" Encoding:"evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + { + .Instruction = ND_INS_TILELOADD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 866, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E3, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2622 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILELOADD, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 866, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2623 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDT1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 867, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E3, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2624 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILELOADDT1, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 867, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2625 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" + { + .Instruction = ND_INS_TILERELEASE, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 868, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + 0 + }, + }, + + // Pos:2626 Instruction:"TILESTORED Mt,rTt" Encoding:"evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem"/"M" + { + .Instruction = ND_INS_TILESTORED, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 869, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_EVEX_E3, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2627 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" + { + .Instruction = ND_INS_TILESTORED, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 869, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2628 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" + { + .Instruction = ND_INS_TILEZERO, + .Category = ND_CAT_AMX, + .IsaSet = ND_SET_AMXTILE, + .Mnemonic = 870, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 0), + .TupleType = 0, + .ExcType = ND_EXT_AMX_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_AMXTILE, + .Operands = + { + OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2629 Instruction:"TLBSYNC" Encoding:"NP 0x0F 0x01 /0xFF"/"" + { + .Instruction = ND_INS_TLBSYNC, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_INVLPGB, + .Mnemonic = 871, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_INVLPGB, + .Operands = + { + 0 + }, + }, + + // Pos:2630 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" + { + .Instruction = ND_INS_TPAUSE, + .Category = ND_CAT_WAITPKG, + .IsaSet = ND_SET_WAITPKG, + .Mnemonic = 872, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_WAITPKG, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2631 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r"/"RM" + { + .Instruction = ND_INS_TZCNT, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2632 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r"/"RM" + { + .Instruction = ND_INS_TZCNT, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2633 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r"/"RM" + { + .Instruction = ND_INS_TZCNT, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2634 Instruction:"TZCNT Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r"/"RM" + { + .Instruction = ND_INS_TZCNT, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2635 Instruction:"TZCNT Gv,Ev" Encoding:"repz 0x0F 0xBC /r"/"RM" + { + .Instruction = ND_INS_TZCNT, + .Category = ND_CAT_BMI1, + .IsaSet = ND_SET_BMI1, + .Mnemonic = 873, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_BMI1, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2636 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" + { + .Instruction = ND_INS_TZMSK, + .Category = ND_CAT_BITBYTE, + .IsaSet = ND_SET_TBM, + .Mnemonic = 874, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TBM, + .Operands = + { + OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2637 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" + { + .Instruction = ND_INS_UCOMISD, + .Category = ND_CAT_SSE2, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 875, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2638 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" + { + .Instruction = ND_INS_UCOMISS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 876, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2639 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" + { + .Instruction = ND_INS_UD0, + .Category = ND_CAT_UD, + .IsaSet = ND_SET_UD, + .Mnemonic = 877, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2640 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" + { + .Instruction = ND_INS_UD1, + .Category = ND_CAT_UD, + .IsaSet = ND_SET_UD, + .Mnemonic = 878, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2641 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" + { + .Instruction = ND_INS_UD2, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_PPRO, + .Mnemonic = 879, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:2642 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" + { + .Instruction = ND_INS_UIRET, + .Category = ND_CAT_RET, + .IsaSet = ND_SET_UINTR, + .Mnemonic = 880, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 6), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_UINTR, + .Operands = + { + OP(ND_OPT_rIP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rSP, ND_OPS_ssz, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_K, ND_OPS_v3, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_SHSP, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2643 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" + { + .Instruction = ND_INS_UMONITOR, + .Category = ND_CAT_WAITPKG, + .IsaSet = ND_SET_WAITPKG, + .Mnemonic = 881, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_WAITPKG, + .Operands = + { + OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2644 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" + { + .Instruction = ND_INS_UMWAIT, + .Category = ND_CAT_WAITPKG, + .IsaSet = ND_SET_WAITPKG, + .Mnemonic = 882, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_WAITPKG, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2645 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" + { + .Instruction = ND_INS_UNPCKHPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 883, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2646 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" + { + .Instruction = ND_INS_UNPCKHPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 884, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2647 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" + { + .Instruction = ND_INS_UNPCKLPD, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 885, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2648 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" + { + .Instruction = ND_INS_UNPCKLPS, + .Category = ND_CAT_SSE, + .IsaSet = ND_SET_SSE, + .Mnemonic = 886, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2649 Instruction:"URDMSR Eq,Gq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg"/"MR" + { + .Instruction = ND_INS_URDMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 887, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_USER_MSR, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2650 Instruction:"URDMSR Rq,Id" Encoding:"evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + { + .Instruction = ND_INS_URDMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 887, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2651 Instruction:"URDMSR Rq,Gq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:reg"/"MR" + { + .Instruction = ND_INS_URDMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_USER_MSR, + .Mnemonic = 887, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_USER_MSR, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2652 Instruction:"URDMSR Rq,Id" Encoding:"vex m:7 p:3 l:0 w:0 0xF8 /0:reg id"/"MI" + { + .Instruction = ND_INS_URDMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_USER_MSR, + .Mnemonic = 887, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_USER_MSR, + .Operands = + { + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2653 Instruction:"UWRMSR Gq,Eq" Encoding:"evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg"/"RM" + { + .Instruction = ND_INS_UWRMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 888, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_USER_MSR, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2654 Instruction:"UWRMSR Id,Rq" Encoding:"evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + { + .Instruction = ND_INS_UWRMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 888, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_VEX, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP|ND_FLAG_O64, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2655 Instruction:"UWRMSR Gq,Rq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:reg"/"RM" + { + .Instruction = ND_INS_UWRMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_USER_MSR, + .Mnemonic = 888, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_USER_MSR, + .Operands = + { + OP(ND_OPT_G, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2656 Instruction:"UWRMSR Id,Rq" Encoding:"vex m:7 p:2 l:0 w:0 0xF8 /0:reg id"/"IM" + { + .Instruction = ND_INS_UWRMSR, + .Category = ND_CAT_USER_MSR, + .IsaSet = ND_SET_USER_MSR, + .Mnemonic = 888, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_O64, + .CpuidFlag = ND_CFF_USER_MSR, + .Operands = + { + OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2657 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" + { + .Instruction = ND_INS_V4FMADDPS, + .Category = ND_CAT_VFMAPS, + .IsaSet = ND_SET_AVX5124FMAPS, + .Mnemonic = 889, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124FMAPS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2658 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" + { + .Instruction = ND_INS_V4FMADDSS, + .Category = ND_CAT_VFMAPS, + .IsaSet = ND_SET_AVX5124FMAPS, + .Mnemonic = 890, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124FMAPS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2659 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" + { + .Instruction = ND_INS_V4FNMADDPS, + .Category = ND_CAT_VFMAPS, + .IsaSet = ND_SET_AVX5124FMAPS, + .Mnemonic = 891, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124FMAPS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2660 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" + { + .Instruction = ND_INS_V4FNMADDSS, + .Category = ND_CAT_VFMAPS, + .IsaSet = ND_SET_AVX5124FMAPS, + .Mnemonic = 892, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124FMAPS, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2661 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 893, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2662 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" + { + .Instruction = ND_INS_VADDPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 893, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2663 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 894, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2664 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 895, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2665 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" + { + .Instruction = ND_INS_VADDPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 895, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2666 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 896, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2667 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" + { + .Instruction = ND_INS_VADDSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 896, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2668 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 897, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2669 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" + { + .Instruction = ND_INS_VADDSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 898, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2670 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" + { + .Instruction = ND_INS_VADDSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 898, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2671 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" + { + .Instruction = ND_INS_VADDSUBPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 899, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2672 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" + { + .Instruction = ND_INS_VADDSUBPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 900, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2673 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + .Instruction = ND_INS_VAESDEC, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 901, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2674 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" + { + .Instruction = ND_INS_VAESDEC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 901, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2675 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + .Instruction = ND_INS_VAESDECLAST, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 902, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2676 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" + { + .Instruction = ND_INS_VAESDECLAST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 902, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2677 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + .Instruction = ND_INS_VAESENC, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 903, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2678 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" + { + .Instruction = ND_INS_VAESENC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 903, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2679 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + .Instruction = ND_INS_VAESENCLAST, + .Category = ND_CAT_VAES, + .IsaSet = ND_SET_VAES, + .Mnemonic = 904, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VAES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2680 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" + { + .Instruction = ND_INS_VAESENCLAST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 904, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2681 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" + { + .Instruction = ND_INS_VAESIMC, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 905, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2682 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" + { + .Instruction = ND_INS_VAESKEYGENASSIST, + .Category = ND_CAT_AES, + .IsaSet = ND_SET_AES, + .Mnemonic = 906, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AES, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2683 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VALIGND, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 907, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2684 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VALIGNQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 908, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2685 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" + { + .Instruction = ND_INS_VANDNPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 909, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:2686 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" + { + .Instruction = ND_INS_VANDNPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 909, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2687 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" + { + .Instruction = ND_INS_VANDNPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 910, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2688 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" + { + .Instruction = ND_INS_VANDNPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 910, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2689 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" + { + .Instruction = ND_INS_VANDPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 911, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:2690 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" + { + .Instruction = ND_INS_VANDPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 911, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2691 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" + { + .Instruction = ND_INS_VANDPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 912, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2692 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" + { + .Instruction = ND_INS_VANDPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 912, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2693 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" + { + .Instruction = ND_INS_VBCSTNEBF162PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 913, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2694 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" + { + .Instruction = ND_INS_VBCSTNESH2PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 914, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2695 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" + { + .Instruction = ND_INS_VBLENDMPD, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 915, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:2696 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" + { + .Instruction = ND_INS_VBLENDMPS, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 916, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2697 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" + { + .Instruction = ND_INS_VBLENDPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 917, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2698 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" + { + .Instruction = ND_INS_VBLENDPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 918, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2699 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" + { + .Instruction = ND_INS_VBLENDVPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 919, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2700 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" + { + .Instruction = ND_INS_VBLENDVPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 920, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2701 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" + { + .Instruction = ND_INS_VBROADCASTF128, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX, + .Mnemonic = 921, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2702 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" + { + .Instruction = ND_INS_VBROADCASTF32X2, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 922, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2703 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTF32X4, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 923, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2704 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTF32X8, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 924, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2705 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTF64X2, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 925, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2706 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTF64X4, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 926, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2707 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" + { + .Instruction = ND_INS_VBROADCASTI128, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 927, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2708 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" + { + .Instruction = ND_INS_VBROADCASTI32X2, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 928, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2709 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTI32X4, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 929, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2710 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTI32X8, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 930, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2711 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTI64X2, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 931, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2712 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" + { + .Instruction = ND_INS_VBROADCASTI64X4, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 932, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2713 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" + { + .Instruction = ND_INS_VBROADCASTSD, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 933, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2714 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" + { + .Instruction = ND_INS_VBROADCASTSD, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX, + .Mnemonic = 933, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2715 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" + { + .Instruction = ND_INS_VBROADCASTSS, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 934, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2716 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" + { + .Instruction = ND_INS_VBROADCASTSS, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX, + .Mnemonic = 934, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2717 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 935, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2718 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" + { + .Instruction = ND_INS_VCMPPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 935, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2719 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 936, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2720 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 937, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2721 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" + { + .Instruction = ND_INS_VCMPPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 937, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2722 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 938, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2723 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" + { + .Instruction = ND_INS_VCMPSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 938, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2724 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 939, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2725 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VCMPSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 940, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2726 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" + { + .Instruction = ND_INS_VCMPSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 940, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2727 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMISD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 941, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2728 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMISD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 941, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2729 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMISH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 942, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2730 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMISS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 943, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2731 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" + { + .Instruction = ND_INS_VCOMISS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 943, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2732 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" + { + .Instruction = ND_INS_VCOMPRESSPD, + .Category = ND_CAT_COMPRESS, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 944, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2733 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" + { + .Instruction = ND_INS_VCOMPRESSPS, + .Category = ND_CAT_COMPRESS, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 945, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2734 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" + { + .Instruction = ND_INS_VCVTDQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 946, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2735 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" + { + .Instruction = ND_INS_VCVTDQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 946, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2736 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" + { + .Instruction = ND_INS_VCVTDQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 946, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2737 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTDQ2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 947, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2738 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTDQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 948, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2739 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" + { + .Instruction = ND_INS_VCVTDQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 948, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2740 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTNE2PS2BF16, + .Category = ND_CAT_AVX512BF16, + .IsaSet = ND_SET_AVX512BF16, + .Mnemonic = 949, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BF16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2741 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" + { + .Instruction = ND_INS_VCVTNEEBF162PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 950, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2742 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" + { + .Instruction = ND_INS_VCVTNEEPH2PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 951, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2743 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" + { + .Instruction = ND_INS_VCVTNEOBF162PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 952, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2744 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" + { + .Instruction = ND_INS_VCVTNEOPH2PS, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 953, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2745 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" + { + .Instruction = ND_INS_VCVTNEPS2BF16, + .Category = ND_CAT_AVX512BF16, + .IsaSet = ND_SET_AVX512BF16, + .Mnemonic = 954, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BF16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2746 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" + { + .Instruction = ND_INS_VCVTNEPS2BF16, + .Category = ND_CAT_AVXNECONVERT, + .IsaSet = ND_SET_AVXNECONVERT, + .Mnemonic = 954, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVXNECONVERT, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2747 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 955, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2748 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" + { + .Instruction = ND_INS_VCVTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 955, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2749 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 956, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2750 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 957, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2751 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" + { + .Instruction = ND_INS_VCVTPD2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 957, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2752 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" + { + .Instruction = ND_INS_VCVTPD2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 957, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2753 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2QQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 958, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2754 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2UDQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 959, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2755 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPD2UQQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 960, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2756 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2DQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 961, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2757 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2PD, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 962, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2758 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 963, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2759 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" + { + .Instruction = ND_INS_VCVTPH2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_F16C, + .Mnemonic = 963, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_F16C, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2760 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" + { + .Instruction = ND_INS_VCVTPH2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_F16C, + .Mnemonic = 963, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_F16C, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2761 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2PSX, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 964, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2762 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2QQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 965, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2763 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2UDQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 966, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2764 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2UQQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 967, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2765 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2UW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 968, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2766 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" + { + .Instruction = ND_INS_VCVTPH2W, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 969, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2767 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 970, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2768 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" + { + .Instruction = ND_INS_VCVTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 970, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2769 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 971, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2770 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" + { + .Instruction = ND_INS_VCVTPS2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 971, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2771 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" + { + .Instruction = ND_INS_VCVTPS2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 971, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2772 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" + { + .Instruction = ND_INS_VCVTPS2PH, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 972, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2773 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" + { + .Instruction = ND_INS_VCVTPS2PH, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_F16C, + .Mnemonic = 972, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_F16C, + .Operands = + { + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2774 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" + { + .Instruction = ND_INS_VCVTPS2PH, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_F16C, + .Mnemonic = 972, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_11, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_F16C, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2775 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2PHX, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 973, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2776 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2QQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 974, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2777 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2UDQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 975, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2778 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VCVTPS2UQQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 976, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2779 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" + { + .Instruction = ND_INS_VCVTQQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 977, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2780 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTQQ2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 978, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2781 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTQQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 979, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2782 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSD2SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 980, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2783 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + .Instruction = ND_INS_VCVTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 981, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2784 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" + { + .Instruction = ND_INS_VCVTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 981, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2785 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSD2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 982, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2786 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSD2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 982, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2787 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" + { + .Instruction = ND_INS_VCVTSD2USI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 983, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2788 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSH2SD, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 984, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2789 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" + { + .Instruction = ND_INS_VCVTSH2SI, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 985, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2790 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSH2SS, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 986, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2791 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" + { + .Instruction = ND_INS_VCVTSH2USI, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 987, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2792 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 988, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2793 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 988, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2794 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 988, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2795 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 989, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2796 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 990, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2797 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSI2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 990, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2798 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSS2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 991, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2799 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" + { + .Instruction = ND_INS_VCVTSS2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 991, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2800 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" + { + .Instruction = ND_INS_VCVTSS2SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 992, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2801 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + .Instruction = ND_INS_VCVTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 993, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2802 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" + { + .Instruction = ND_INS_VCVTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 993, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2803 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" + { + .Instruction = ND_INS_VCVTSS2USI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 994, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2804 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 995, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2805 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" + { + .Instruction = ND_INS_VCVTTPD2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 995, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2806 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2QQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 996, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2807 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2UDQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 997, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2808 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPD2UQQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 998, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2809 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2DQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 999, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2810 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2QQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1000, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2811 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2UDQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1001, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2812 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2UQQ, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1002, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2813 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2UW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1003, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2814 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPH2W, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1004, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:2815 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1005, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2816 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" + { + .Instruction = ND_INS_VCVTTPS2DQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1005, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2817 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2QQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1006, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2818 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2UDQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1007, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2819 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VCVTTPS2UQQ, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1008, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2820 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1009, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2821 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSD2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1009, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2822 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" + { + .Instruction = ND_INS_VCVTTSD2USI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1010, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2823 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSH2SI, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1011, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2824 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" + { + .Instruction = ND_INS_VCVTTSH2USI, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1012, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2825 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1013, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2826 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" + { + .Instruction = ND_INS_VCVTTSS2SI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1013, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2827 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" + { + .Instruction = ND_INS_VCVTTSS2USI, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1014, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1F, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:2828 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUDQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1015, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HV, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2829 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUDQ2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1016, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2830 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUDQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1017, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2831 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUQQ2PD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1018, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2832 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUQQ2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1019, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2833 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" + { + .Instruction = ND_INS_VCVTUQQ2PS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1020, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2834 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" + { + .Instruction = ND_INS_VCVTUSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1021, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2835 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" + { + .Instruction = ND_INS_VCVTUSI2SD, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1021, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2836 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" + { + .Instruction = ND_INS_VCVTUSI2SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1022, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2837 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" + { + .Instruction = ND_INS_VCVTUSI2SS, + .Category = ND_CAT_CONVERT, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1023, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ER, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2838 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" + { + .Instruction = ND_INS_VCVTUW2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1024, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2839 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" + { + .Instruction = ND_INS_VCVTW2PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1025, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2840 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VDBPSADBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1026, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2841 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1027, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2842 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" + { + .Instruction = ND_INS_VDIVPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1027, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2843 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1028, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2844 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1029, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2845 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" + { + .Instruction = ND_INS_VDIVPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1029, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2846 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1030, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2847 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" + { + .Instruction = ND_INS_VDIVSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1030, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2848 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1031, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2849 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" + { + .Instruction = ND_INS_VDIVSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1032, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2850 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" + { + .Instruction = ND_INS_VDIVSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1032, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2851 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" + { + .Instruction = ND_INS_VDPBF16PS, + .Category = ND_CAT_AVX512BF16, + .IsaSet = ND_SET_AVX512BF16, + .Mnemonic = 1033, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BF16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:2852 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" + { + .Instruction = ND_INS_VDPPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1034, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2853 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" + { + .Instruction = ND_INS_VDPPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1035, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2854 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" + { + .Instruction = ND_INS_VERR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 1036, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2855 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" + { + .Instruction = ND_INS_VERW, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I286PROT, + .Mnemonic = 1037, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:2856 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" + { + .Instruction = ND_INS_VEXP2PD, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1038, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:2857 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" + { + .Instruction = ND_INS_VEXP2PS, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1039, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:2858 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" + { + .Instruction = ND_INS_VEXPANDPD, + .Category = ND_CAT_EXPAND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1040, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2859 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" + { + .Instruction = ND_INS_VEXPANDPS, + .Category = ND_CAT_EXPAND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1041, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2860 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTF128, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1042, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2861 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTF32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1043, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2862 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTF32X8, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1044, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2863 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTF64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1045, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2864 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTF64X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1046, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2865 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTI128, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1047, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2866 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTI32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1048, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2867 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTI32X8, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1049, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2868 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTI64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1050, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2869 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" + { + .Instruction = ND_INS_VEXTRACTI64X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1051, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2870 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1052, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2871 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1052, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2872 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1052, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2873 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VEXTRACTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1052, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2874 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" + { + .Instruction = ND_INS_VFCMADDCPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1053, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2875 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" + { + .Instruction = ND_INS_VFCMADDCSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1054, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2876 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" + { + .Instruction = ND_INS_VFCMULCPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1055, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2877 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" + { + .Instruction = ND_INS_VFCMULCSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1056, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2878 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VFIXUPIMMPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1057, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2879 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VFIXUPIMMPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1058, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2880 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VFIXUPIMMSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1059, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2881 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VFIXUPIMMSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1060, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2882 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1061, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2883 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1061, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2884 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1062, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2885 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1063, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2886 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1063, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2887 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1064, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2888 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1064, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2889 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1065, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2890 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1066, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2891 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1066, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2892 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1067, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2893 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1067, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2894 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1068, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2895 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1069, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2896 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1069, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2897 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1070, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2898 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1070, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2899 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1071, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2900 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1072, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2901 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1072, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2902 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1073, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2903 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1073, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2904 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1074, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2905 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1075, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2906 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1075, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2907 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1076, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2908 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1076, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2909 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1077, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2910 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADD231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1078, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2911 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" + { + .Instruction = ND_INS_VFMADD231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1078, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2912 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDCPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1079, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2913 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDCSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1080, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2914 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1081, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2915 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1081, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2916 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1082, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2917 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1082, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2918 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1083, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2919 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1083, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2920 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1084, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2921 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1084, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2922 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1085, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2923 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1085, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2924 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1086, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2925 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1087, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2926 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1087, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2927 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1088, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2928 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1088, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2929 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1089, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2930 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1090, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2931 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1090, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2932 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1091, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2933 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1091, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2934 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1092, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2935 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMADDSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1093, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2936 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" + { + .Instruction = ND_INS_VFMADDSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1093, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2937 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1094, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2938 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1094, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2939 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" + { + .Instruction = ND_INS_VFMADDSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1095, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2940 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMADDSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1095, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2941 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1096, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2942 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1096, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2943 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1097, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2944 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1098, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2945 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1098, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2946 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1099, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2947 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1099, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2948 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1100, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2949 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2950 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1101, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2951 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2952 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1102, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2953 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1103, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2954 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2955 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1104, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2956 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2957 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1105, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2958 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1106, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2959 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1107, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2960 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1107, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2961 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1108, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2962 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1108, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2963 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1109, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2964 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1110, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2965 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1110, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2966 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1111, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2967 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1111, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2968 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1112, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2969 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUB231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1113, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:2970 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" + { + .Instruction = ND_INS_VFMSUB231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1113, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2971 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1114, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2972 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1114, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2973 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1115, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2974 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1116, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2975 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1116, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2976 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1117, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2977 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1117, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2978 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1118, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2979 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1119, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2980 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1119, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2981 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1120, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:2982 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1120, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2983 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1121, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:2984 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMSUBADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1122, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2985 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" + { + .Instruction = ND_INS_VFMSUBADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1122, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2986 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1123, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2987 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1123, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2988 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1124, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2989 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1124, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2990 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1125, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2991 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1125, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2992 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1126, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2993 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1126, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2994 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1127, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2995 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1127, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2996 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" + { + .Instruction = ND_INS_VFMSUBSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1128, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2997 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" + { + .Instruction = ND_INS_VFMSUBSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1128, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:2998 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" + { + .Instruction = ND_INS_VFMULCPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1129, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:2999 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" + { + .Instruction = ND_INS_VFMULCSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1130, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10S, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3000 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1131, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3001 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1131, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3002 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1132, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3003 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1133, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3004 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1133, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3005 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1134, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3006 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1134, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3007 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1135, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3008 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1136, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3009 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1136, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3010 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1137, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3011 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1137, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3012 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1138, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3013 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3014 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1139, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3015 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1140, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3016 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1140, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3017 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1141, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3018 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1142, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3019 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1142, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3020 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1143, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3021 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1143, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3022 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1144, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3023 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1145, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3024 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1145, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3025 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1146, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3026 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1146, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3027 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1147, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3028 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" + { + .Instruction = ND_INS_VFNMADD231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1148, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3029 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" + { + .Instruction = ND_INS_VFNMADD231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1148, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3030 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1149, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3031 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMADDPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1149, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3032 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1150, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3033 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMADDPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1150, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3034 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMADDSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1151, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3035 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMADDSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1151, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3036 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMADDSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1152, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3037 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMADDSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1152, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3038 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1153, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3039 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB132PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1153, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3040 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1154, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3041 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1155, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3042 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB132PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1155, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3043 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1156, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3044 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB132SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1156, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3045 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1157, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3046 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1158, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3047 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB132SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1158, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3048 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1159, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3049 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB213PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1159, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3050 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1160, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3051 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1161, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3052 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB213PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1161, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3053 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1162, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3054 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB213SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1162, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3055 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1163, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3056 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1164, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3057 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB213SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1164, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3058 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1165, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3059 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB231PD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1165, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3060 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231PH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1166, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3061 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1167, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3062 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB231PS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1167, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3063 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1168, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3064 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB231SD, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1168, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3065 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231SH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1169, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3066 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" + { + .Instruction = ND_INS_VFNMSUB231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3067 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" + { + .Instruction = ND_INS_VFNMSUB231SS, + .Category = ND_CAT_VFMA, + .IsaSet = ND_SET_FMA, + .Mnemonic = 1170, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3068 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3069 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMSUBPD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1171, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3070 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3071 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMSUBPS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1172, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3072 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMSUBSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3073 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMSUBSD, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1173, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3074 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" + { + .Instruction = ND_INS_VFNMSUBSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3075 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" + { + .Instruction = ND_INS_VFNMSUBSS, + .Category = ND_CAT_FMA4, + .IsaSet = ND_SET_FMA4, + .Mnemonic = 1174, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_FMA4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3076 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1175, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3077 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1176, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3078 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1177, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3079 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1178, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3080 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1179, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3081 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" + { + .Instruction = ND_INS_VFPCLASSSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1180, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3082 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" + { + .Instruction = ND_INS_VFRCZPD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1181, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3083 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" + { + .Instruction = ND_INS_VFRCZPS, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1182, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3084 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" + { + .Instruction = ND_INS_VFRCZSD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1183, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3085 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" + { + .Instruction = ND_INS_VFRCZSS, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1184, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3086 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VGATHERDPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3087 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VGATHERDPD, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1185, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3088 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VGATHERDPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3089 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VGATHERDPS, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1186, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3090 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF0DPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1187, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3091 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF0DPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1188, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3092 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF0QPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1189, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3093 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF0QPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1190, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3094 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF1DPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1191, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3095 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF1DPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1192, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3096 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF1QPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1193, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3097 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" + { + .Instruction = ND_INS_VGATHERPF1QPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1194, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3098 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VGATHERQPD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1195, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3099 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VGATHERQPD, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1195, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3100 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VGATHERQPS, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1196, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3101 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VGATHERQPS, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1196, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3102 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" + { + .Instruction = ND_INS_VGETEXPPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1197, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:3103 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" + { + .Instruction = ND_INS_VGETEXPPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1198, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:3104 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" + { + .Instruction = ND_INS_VGETEXPPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1199, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:3105 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" + { + .Instruction = ND_INS_VGETEXPSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1200, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3106 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" + { + .Instruction = ND_INS_VGETEXPSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1201, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3107 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" + { + .Instruction = ND_INS_VGETEXPSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1202, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3108 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" + { + .Instruction = ND_INS_VGETMANTPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1203, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3109 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" + { + .Instruction = ND_INS_VGETMANTPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1204, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3110 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" + { + .Instruction = ND_INS_VGETMANTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1205, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3111 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VGETMANTSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1206, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3112 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VGETMANTSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1207, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3113 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VGETMANTSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1208, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3114 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" + { + .Instruction = ND_INS_VGF2P8AFFINEINVQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1209, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3115 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" + { + .Instruction = ND_INS_VGF2P8AFFINEINVQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1209, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3116 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" + { + .Instruction = ND_INS_VGF2P8AFFINEQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1210, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3117 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" + { + .Instruction = ND_INS_VGF2P8AFFINEQB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1210, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3118 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" + { + .Instruction = ND_INS_VGF2P8MULB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1211, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3119 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" + { + .Instruction = ND_INS_VGF2P8MULB, + .Category = ND_CAT_GFNI, + .IsaSet = ND_SET_GFNI, + .Mnemonic = 1211, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_GFNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3120 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" + { + .Instruction = ND_INS_VHADDPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1212, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3121 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" + { + .Instruction = ND_INS_VHADDPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1213, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3122 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" + { + .Instruction = ND_INS_VHSUBPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1214, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3123 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" + { + .Instruction = ND_INS_VHSUBPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1215, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3124 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTF128, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1216, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3125 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTF32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1217, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3126 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTF32X8, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1218, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3127 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTF64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1219, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3128 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTF64X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1220, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3129 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTI128, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1221, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3130 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTI32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1222, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3131 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTI32X8, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1223, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T8, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3132 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTI64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1224, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3133 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VINSERTI64X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1225, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T4, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3134 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3135 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3136 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3137 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VINSERTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1226, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3138 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" + { + .Instruction = ND_INS_VLDDQU, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1227, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3139 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" + { + .Instruction = ND_INS_VLDMXCSR, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1228, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3140 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" + { + .Instruction = ND_INS_VMASKMOVDQU, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1229, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_pDI, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3141 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" + { + .Instruction = ND_INS_VMASKMOVPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1230, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3142 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" + { + .Instruction = ND_INS_VMASKMOVPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1230, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3143 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" + { + .Instruction = ND_INS_VMASKMOVPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1231, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3144 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" + { + .Instruction = ND_INS_VMASKMOVPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1231, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3145 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1232, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:3146 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" + { + .Instruction = ND_INS_VMAXPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1232, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3147 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1233, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:3148 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1234, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:3149 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" + { + .Instruction = ND_INS_VMAXPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1234, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3150 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1235, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3151 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" + { + .Instruction = ND_INS_VMAXSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1235, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3152 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1236, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3153 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" + { + .Instruction = ND_INS_VMAXSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1237, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3154 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" + { + .Instruction = ND_INS_VMAXSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1237, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3155 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" + { + .Instruction = ND_INS_VMCALL, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1238, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + 0 + }, + }, + + // Pos:3156 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" + { + .Instruction = ND_INS_VMCLEAR, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1239, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3157 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" + { + .Instruction = ND_INS_VMFUNC, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1240, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + 0 + }, + }, + + // Pos:3158 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" + { + .Instruction = ND_INS_VMGEXIT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1241, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:3159 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" + { + .Instruction = ND_INS_VMGEXIT, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1241, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:3160 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1242, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:3161 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" + { + .Instruction = ND_INS_VMINPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1242, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3162 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1243, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:3163 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1244, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:3164 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" + { + .Instruction = ND_INS_VMINPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1244, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3165 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1245, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3166 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" + { + .Instruction = ND_INS_VMINSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1245, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3167 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1246, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3168 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" + { + .Instruction = ND_INS_VMINSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1247, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3169 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" + { + .Instruction = ND_INS_VMINSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1247, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3170 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" + { + .Instruction = ND_INS_VMLAUNCH, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1248, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3171 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" + { + .Instruction = ND_INS_VMLOAD, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1249, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3172 Instruction:"VMMCALL" Encoding:"NP 0x0F 0x01 /0xD9"/"" + { + .Instruction = ND_INS_VMMCALL, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1250, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:3173 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" + { + .Instruction = ND_INS_VMMCALL, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1250, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:3174 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" + { + .Instruction = ND_INS_VMOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1251, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3175 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" + { + .Instruction = ND_INS_VMOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1251, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3176 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" + { + .Instruction = ND_INS_VMOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1251, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3177 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" + { + .Instruction = ND_INS_VMOVAPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1251, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3178 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" + { + .Instruction = ND_INS_VMOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3179 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" + { + .Instruction = ND_INS_VMOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3180 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" + { + .Instruction = ND_INS_VMOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3181 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" + { + .Instruction = ND_INS_VMOVAPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1252, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3182 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1253, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3183 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1253, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3184 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1253, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3185 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" + { + .Instruction = ND_INS_VMOVD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1253, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3186 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" + { + .Instruction = ND_INS_VMOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_DUP, + .ExcType = ND_EXT_E5NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3187 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" + { + .Instruction = ND_INS_VMOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_DUP, + .ExcType = ND_EXT_E5NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3188 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" + { + .Instruction = ND_INS_VMOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_DUP, + .ExcType = ND_EXT_E5NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3189 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" + { + .Instruction = ND_INS_VMOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3190 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" + { + .Instruction = ND_INS_VMOVDDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1254, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3191 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" + { + .Instruction = ND_INS_VMOVDQA, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3192 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" + { + .Instruction = ND_INS_VMOVDQA, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1255, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3193 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQA32, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1256, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3194 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQA32, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1256, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3195 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQA64, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1257, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3196 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQA64, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1257, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3197 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" + { + .Instruction = ND_INS_VMOVDQU, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1258, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3198 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" + { + .Instruction = ND_INS_VMOVDQU, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1258, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3199 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQU16, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3200 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQU16, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1259, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3201 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQU32, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1260, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3202 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQU32, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1260, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3203 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQU64, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3204 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQU64, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1261, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3205 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" + { + .Instruction = ND_INS_VMOVDQU8, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1262, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3206 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" + { + .Instruction = ND_INS_VMOVDQU8, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1262, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3207 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVHLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1263, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3208 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVHLPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1263, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3209 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3210 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3211 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3212 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVHPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1264, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3213 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1265, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3214 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1265, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3215 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1265, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3216 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1265, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3217 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVLHPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1266, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3218 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVLHPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1266, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3219 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3220 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3221 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3222 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVLPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1267, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3223 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3224 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T2, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3225 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" + { + .Instruction = ND_INS_VMOVLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3226 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVLPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1268, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3227 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" + { + .Instruction = ND_INS_VMOVMSKPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1269, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3228 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" + { + .Instruction = ND_INS_VMOVMSKPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1270, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3229 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTDQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1271, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3230 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1271, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3231 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" + { + .Instruction = ND_INS_VMOVNTDQA, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1272, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3232 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" + { + .Instruction = ND_INS_VMOVNTDQA, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1272, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3233 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1273, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3234 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1273, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3235 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1274, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E1NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3236 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVNTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1274, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_1, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3237 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3238 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3239 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3240 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3241 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3242 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3243 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3244 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" + { + .Instruction = ND_INS_VMOVQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1275, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3245 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3246 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3247 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3248 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3249 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3250 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3251 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3252 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVSD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1276, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3253 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3254 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + { + .Instruction = ND_INS_VMOVSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3255 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" + { + .Instruction = ND_INS_VMOVSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3256 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + { + .Instruction = ND_INS_VMOVSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1277, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3257 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" + { + .Instruction = ND_INS_VMOVSHDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1278, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3258 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" + { + .Instruction = ND_INS_VMOVSHDUP, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1278, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3259 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" + { + .Instruction = ND_INS_VMOVSLDUP, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3260 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" + { + .Instruction = ND_INS_VMOVSLDUP, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1279, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3261 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3262 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3263 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3264 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3265 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3266 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3267 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3268 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVSS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1280, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3269 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" + { + .Instruction = ND_INS_VMOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1281, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3270 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" + { + .Instruction = ND_INS_VMOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1281, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3271 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" + { + .Instruction = ND_INS_VMOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1281, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3272 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" + { + .Instruction = ND_INS_VMOVUPD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1281, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3273 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" + { + .Instruction = ND_INS_VMOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1282, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3274 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" + { + .Instruction = ND_INS_VMOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1282, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3275 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" + { + .Instruction = ND_INS_VMOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1282, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3276 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" + { + .Instruction = ND_INS_VMOVUPS, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1282, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3277 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1283, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3278 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1283, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3279 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1283, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3280 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" + { + .Instruction = ND_INS_VMOVW, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1283, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3281 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" + { + .Instruction = ND_INS_VMPSADBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1284, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3282 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" + { + .Instruction = ND_INS_VMPTRLD, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1285, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3283 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" + { + .Instruction = ND_INS_VMPTRST, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1286, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3284 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" + { + .Instruction = ND_INS_VMREAD, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1287, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3285 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" + { + .Instruction = ND_INS_VMRESUME, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1288, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3286 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" + { + .Instruction = ND_INS_VMRUN, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1289, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3287 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" + { + .Instruction = ND_INS_VMSAVE, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_SVM, + .Mnemonic = 1290, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_SVM, + .Operands = + { + 0 + }, + }, + + // Pos:3288 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1291, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3289 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" + { + .Instruction = ND_INS_VMULPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1291, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3290 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1292, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3291 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1293, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3292 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" + { + .Instruction = ND_INS_VMULPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1293, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3293 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3294 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" + { + .Instruction = ND_INS_VMULSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1294, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3295 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1295, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3296 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" + { + .Instruction = ND_INS_VMULSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1296, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3297 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" + { + .Instruction = ND_INS_VMULSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1296, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3298 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" + { + .Instruction = ND_INS_VMWRITE, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1297, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_F64|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3299 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" + { + .Instruction = ND_INS_VMXOFF, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1298, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3300 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" + { + .Instruction = ND_INS_VMXON, + .Category = ND_CAT_VTX, + .IsaSet = ND_SET_VTX, + .Mnemonic = 1299, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_VTX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3301 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" + { + .Instruction = ND_INS_VORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1300, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3302 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" + { + .Instruction = ND_INS_VORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1300, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3303 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" + { + .Instruction = ND_INS_VORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1301, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3304 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" + { + .Instruction = ND_INS_VORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1301, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3305 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" + { + .Instruction = ND_INS_VP2INTERSECTD, + .Category = ND_CAT_AVX512VP2INTERSECT, + .IsaSet = ND_SET_AVX512VP2INTERSECT, + .Mnemonic = 1302, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VP2INTERSECT, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3306 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" + { + .Instruction = ND_INS_VP2INTERSECTQ, + .Category = ND_CAT_AVX512VP2INTERSECT, + .IsaSet = ND_SET_AVX512VP2INTERSECT, + .Mnemonic = 1303, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VP2INTERSECT, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3307 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" + { + .Instruction = ND_INS_VP4DPWSSD, + .Category = ND_CAT_VNNIW, + .IsaSet = ND_SET_AVX5124VNNIW, + .Mnemonic = 1304, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124VNNIW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3308 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" + { + .Instruction = ND_INS_VP4DPWSSDS, + .Category = ND_CAT_VNNIW, + .IsaSet = ND_SET_AVX5124VNNIW, + .Mnemonic = 1305, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1_4X, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX5124VNNIW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), + OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3309 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" + { + .Instruction = ND_INS_VPABSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1306, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3310 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" + { + .Instruction = ND_INS_VPABSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1306, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3311 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" + { + .Instruction = ND_INS_VPABSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1307, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3312 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" + { + .Instruction = ND_INS_VPABSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1307, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3313 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" + { + .Instruction = ND_INS_VPABSQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1308, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3314 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" + { + .Instruction = ND_INS_VPABSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1309, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3315 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" + { + .Instruction = ND_INS_VPABSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1309, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3316 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" + { + .Instruction = ND_INS_VPACKSSDW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3317 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" + { + .Instruction = ND_INS_VPACKSSDW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1310, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3318 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" + { + .Instruction = ND_INS_VPACKSSWB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1311, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3319 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" + { + .Instruction = ND_INS_VPACKSSWB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1311, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3320 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" + { + .Instruction = ND_INS_VPACKUSDW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3321 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" + { + .Instruction = ND_INS_VPACKUSDW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1312, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3322 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" + { + .Instruction = ND_INS_VPACKUSWB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1313, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3323 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" + { + .Instruction = ND_INS_VPACKUSWB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1313, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3324 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" + { + .Instruction = ND_INS_VPADDB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1314, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3325 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" + { + .Instruction = ND_INS_VPADDB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1314, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3326 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" + { + .Instruction = ND_INS_VPADDD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3327 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" + { + .Instruction = ND_INS_VPADDD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1315, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3328 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" + { + .Instruction = ND_INS_VPADDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1316, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3329 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" + { + .Instruction = ND_INS_VPADDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1316, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3330 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" + { + .Instruction = ND_INS_VPADDSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3331 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" + { + .Instruction = ND_INS_VPADDSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1317, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3332 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" + { + .Instruction = ND_INS_VPADDSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1318, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3333 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" + { + .Instruction = ND_INS_VPADDSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1318, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3334 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" + { + .Instruction = ND_INS_VPADDUSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1319, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3335 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" + { + .Instruction = ND_INS_VPADDUSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1319, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3336 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" + { + .Instruction = ND_INS_VPADDUSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1320, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3337 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" + { + .Instruction = ND_INS_VPADDUSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1320, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3338 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" + { + .Instruction = ND_INS_VPADDW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1321, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3339 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" + { + .Instruction = ND_INS_VPADDW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1321, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3340 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPALIGNR, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1322, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3341 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" + { + .Instruction = ND_INS_VPALIGNR, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1322, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3342 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" + { + .Instruction = ND_INS_VPAND, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1323, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3343 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" + { + .Instruction = ND_INS_VPANDD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1324, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3344 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" + { + .Instruction = ND_INS_VPANDN, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1325, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3345 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" + { + .Instruction = ND_INS_VPANDND, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1326, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3346 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" + { + .Instruction = ND_INS_VPANDNQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1327, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3347 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" + { + .Instruction = ND_INS_VPANDQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1328, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3348 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" + { + .Instruction = ND_INS_VPAVGB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1329, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3349 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" + { + .Instruction = ND_INS_VPAVGB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1329, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3350 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" + { + .Instruction = ND_INS_VPAVGW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1330, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3351 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" + { + .Instruction = ND_INS_VPAVGW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1330, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3352 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPBLENDD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1331, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3353 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" + { + .Instruction = ND_INS_VPBLENDMB, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1332, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3354 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" + { + .Instruction = ND_INS_VPBLENDMD, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1333, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3355 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" + { + .Instruction = ND_INS_VPBLENDMQ, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1334, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3356 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" + { + .Instruction = ND_INS_VPBLENDMW, + .Category = ND_CAT_BLEND, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1335, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3357 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" + { + .Instruction = ND_INS_VPBLENDVB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1336, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3358 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" + { + .Instruction = ND_INS_VPBLENDW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1337, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3359 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTB, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1338, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3360 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTB, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1338, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3361 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" + { + .Instruction = ND_INS_VPBROADCASTB, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1338, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3362 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTD, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1339, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3363 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTD, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1339, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3364 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" + { + .Instruction = ND_INS_VPBROADCASTD, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1339, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3365 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" + { + .Instruction = ND_INS_VPBROADCASTMB2Q, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1340, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3366 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" + { + .Instruction = ND_INS_VPBROADCASTMW2D, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1341, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E6NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3367 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTQ, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1342, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3368 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTQ, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1342, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3369 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" + { + .Instruction = ND_INS_VPBROADCASTQ, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1342, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3370 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTW, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1343, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3371 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" + { + .Instruction = ND_INS_VPBROADCASTW, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1343, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3372 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" + { + .Instruction = ND_INS_VPBROADCASTW, + .Category = ND_CAT_BROADCAST, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1343, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3373 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCLMULQDQ, + .Category = ND_CAT_VPCLMULQDQ, + .IsaSet = ND_SET_VPCLMULQDQ, + .Mnemonic = 1344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VPCLMULQDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3374 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCLMULQDQ, + .Category = ND_CAT_VPCLMULQDQ, + .IsaSet = ND_SET_VPCLMULQDQ, + .Mnemonic = 1344, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_VPCLMULQDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3375 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" + { + .Instruction = ND_INS_VPCMOV, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3376 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" + { + .Instruction = ND_INS_VPCMOV, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1345, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3377 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1346, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3378 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1347, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3379 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPEQB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1348, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3380 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPEQB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1348, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3381 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPEQD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1349, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3382 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPEQD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1349, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3383 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPEQQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1350, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3384 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPEQQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1350, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3385 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPEQW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1351, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3386 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPEQW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1351, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3387 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" + { + .Instruction = ND_INS_VPCMPESTRI, + .Category = ND_CAT_STTNI, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1352, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 4), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3388 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" + { + .Instruction = ND_INS_VPCMPESTRM, + .Category = ND_CAT_STTNI, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1353, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 4), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3389 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPGTB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1354, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3390 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPGTB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1354, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3391 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPGTD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1355, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3392 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPGTD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1355, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3393 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPGTQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1356, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3394 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPGTQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1356, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3395 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" + { + .Instruction = ND_INS_VPCMPGTW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1357, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3396 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" + { + .Instruction = ND_INS_VPCMPGTW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1357, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3397 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" + { + .Instruction = ND_INS_VPCMPISTRI, + .Category = ND_CAT_STTNI, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1358, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 2), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_y, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3398 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" + { + .Instruction = ND_INS_VPCMPISTRM, + .Category = ND_CAT_STTNI, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1359, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 2), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_XMM0, ND_OPS_dq, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3399 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1360, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3400 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPUB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1361, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3401 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPUD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1362, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3402 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPUQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1363, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3403 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1364, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3404 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPCMPW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1365, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3405 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1366, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3406 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1367, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3407 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" + { + .Instruction = ND_INS_VPCOMPRESSB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1368, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3408 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" + { + .Instruction = ND_INS_VPCOMPRESSD, + .Category = ND_CAT_COMPRESS, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1369, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3409 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" + { + .Instruction = ND_INS_VPCOMPRESSQ, + .Category = ND_CAT_COMPRESS, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1370, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3410 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" + { + .Instruction = ND_INS_VPCOMPRESSW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1371, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3411 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1372, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3412 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMUB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1373, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3413 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMUD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1374, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3414 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMUQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1375, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3415 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMUW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1376, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3416 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" + { + .Instruction = ND_INS_VPCOMW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1377, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3417 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" + { + .Instruction = ND_INS_VPCONFLICTD, + .Category = ND_CAT_CONFLICT, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1378, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3418 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" + { + .Instruction = ND_INS_VPCONFLICTQ, + .Category = ND_CAT_CONFLICT, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1379, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3419 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBSSD, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1380, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3420 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBSSDS, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1381, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3421 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBSUD, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1382, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3422 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBSUDS, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1383, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3423 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBUSD, + .Category = ND_CAT_VNNI, + .IsaSet = ND_SET_AVX512VNNI, + .Mnemonic = 1384, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3424 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBUSD, + .Category = ND_CAT_AVXVNNI, + .IsaSet = ND_SET_AVXVNNI, + .Mnemonic = 1384, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3425 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPBUSDS, + .Category = ND_CAT_VNNI, + .IsaSet = ND_SET_AVX512VNNI, + .Mnemonic = 1385, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3426 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBUSDS, + .Category = ND_CAT_AVXVNNI, + .IsaSet = ND_SET_AVXVNNI, + .Mnemonic = 1385, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3427 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBUUD, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1386, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3428 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VPDPBUUDS, + .Category = ND_CAT_AVXVNNIINT8, + .IsaSet = ND_SET_AVXVNNIINT8, + .Mnemonic = 1387, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT8, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3429 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWSSD, + .Category = ND_CAT_VNNI, + .IsaSet = ND_SET_AVX512VNNI, + .Mnemonic = 1388, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3430 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWSSD, + .Category = ND_CAT_AVXVNNI, + .IsaSet = ND_SET_AVXVNNI, + .Mnemonic = 1388, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3431 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" + { + .Instruction = ND_INS_VPDPWSSDS, + .Category = ND_CAT_VNNI, + .IsaSet = ND_SET_AVX512VNNI, + .Mnemonic = 1389, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3432 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWSSDS, + .Category = ND_CAT_AVXVNNI, + .IsaSet = ND_SET_AVXVNNI, + .Mnemonic = 1389, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3433 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWSUD, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1390, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3434 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWSUDS, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1391, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3435 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWUSD, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1392, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3436 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWUSDS, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1393, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3437 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWUUD, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1394, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3438 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" + { + .Instruction = ND_INS_VPDPWUUDS, + .Category = ND_CAT_AVXVNNIINT16, + .IsaSet = ND_SET_AVXVNNIINT16, + .Mnemonic = 1395, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXVNNIINT16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3439 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPERM2F128, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1396, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3440 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPERM2I128, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1397, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3441 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" + { + .Instruction = ND_INS_VPERMB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI, + .Mnemonic = 1398, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3442 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1399, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3443 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" + { + .Instruction = ND_INS_VPERMD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1399, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3444 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2B, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI, + .Mnemonic = 1400, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3445 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2D, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1401, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3446 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2PD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1402, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3447 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2PS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1403, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3448 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2Q, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1404, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3449 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMI2W, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1405, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3450 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVMLL" + { + .Instruction = ND_INS_VPERMIL2PD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3451 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLML" + { + .Instruction = ND_INS_VPERMIL2PD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1406, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3452 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVMLL" + { + .Instruction = ND_INS_VPERMIL2PS, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3453 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLML" + { + .Instruction = ND_INS_VPERMIL2PS, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1407, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_m2zI, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3454 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" + { + .Instruction = ND_INS_VPERMILPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3455 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPERMILPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3456 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" + { + .Instruction = ND_INS_VPERMILPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3457 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" + { + .Instruction = ND_INS_VPERMILPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1408, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3458 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" + { + .Instruction = ND_INS_VPERMILPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3459 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPERMILPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3460 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" + { + .Instruction = ND_INS_VPERMILPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3461 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" + { + .Instruction = ND_INS_VPERMILPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1409, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3462 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1410, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3463 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1410, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3464 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPERMPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1410, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3465 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" + { + .Instruction = ND_INS_VPERMPD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1410, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3466 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1411, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3467 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1411, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3468 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" + { + .Instruction = ND_INS_VPERMPS, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1411, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3469 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" + { + .Instruction = ND_INS_VPERMQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1412, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3470 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPERMQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1412, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3471 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" + { + .Instruction = ND_INS_VPERMQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1412, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3472 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2B, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI, + .Mnemonic = 1413, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3473 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2D, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1414, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3474 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2PD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1415, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3475 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2PS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1416, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3476 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2Q, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1417, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3477 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" + { + .Instruction = ND_INS_VPERMT2W, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1418, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3478 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" + { + .Instruction = ND_INS_VPERMW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1419, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3479 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" + { + .Instruction = ND_INS_VPEXPANDB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1420, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3480 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" + { + .Instruction = ND_INS_VPEXPANDD, + .Category = ND_CAT_EXPAND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1421, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3481 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" + { + .Instruction = ND_INS_VPEXPANDQ, + .Category = ND_CAT_EXPAND, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1422, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3482 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" + { + .Instruction = ND_INS_VPEXPANDW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1423, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3483 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1424, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3484 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1424, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3485 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1424, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3486 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1424, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3487 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1425, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3488 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1425, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3489 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1425, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3490 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1425, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3491 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1426, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3492 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1426, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3493 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1426, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3494 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1426, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3495 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3496 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3497 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3498 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3499 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3500 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" + { + .Instruction = ND_INS_VPEXTRW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1427, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3501 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VPGATHERDD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1428, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3502 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VPGATHERDD, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1428, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3503 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VPGATHERDQ, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1429, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3504 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VPGATHERDQ, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1429, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3505 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VPGATHERQD, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1430, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3506 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VPGATHERQD, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1430, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3507 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" + { + .Instruction = ND_INS_VPGATHERQQ, + .Category = ND_CAT_GATHER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1431, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3508 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" + { + .Instruction = ND_INS_VPGATHERQQ, + .Category = ND_CAT_AVX2GATHER, + .IsaSet = ND_SET_AVX2GATHER, + .Mnemonic = 1431, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3509 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" + { + .Instruction = ND_INS_VPHADDBD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1432, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3510 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" + { + .Instruction = ND_INS_VPHADDBQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1433, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3511 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" + { + .Instruction = ND_INS_VPHADDBW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1434, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3512 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" + { + .Instruction = ND_INS_VPHADDD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1435, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3513 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" + { + .Instruction = ND_INS_VPHADDDQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1436, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3514 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" + { + .Instruction = ND_INS_VPHADDSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1437, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3515 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" + { + .Instruction = ND_INS_VPHADDUBD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1438, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3516 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" + { + .Instruction = ND_INS_VPHADDUBQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1439, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3517 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" + { + .Instruction = ND_INS_VPHADDUBW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1440, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3518 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" + { + .Instruction = ND_INS_VPHADDUDQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1441, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3519 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" + { + .Instruction = ND_INS_VPHADDUWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1442, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3520 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" + { + .Instruction = ND_INS_VPHADDUWQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1443, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3521 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" + { + .Instruction = ND_INS_VPHADDW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1444, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3522 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" + { + .Instruction = ND_INS_VPHADDWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1445, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3523 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" + { + .Instruction = ND_INS_VPHADDWQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1446, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3524 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" + { + .Instruction = ND_INS_VPHMINPOSUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1447, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3525 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" + { + .Instruction = ND_INS_VPHSUBBW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1448, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3526 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" + { + .Instruction = ND_INS_VPHSUBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1449, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3527 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" + { + .Instruction = ND_INS_VPHSUBDQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1450, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3528 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" + { + .Instruction = ND_INS_VPHSUBSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1451, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3529 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" + { + .Instruction = ND_INS_VPHSUBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1452, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3530 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" + { + .Instruction = ND_INS_VPHSUBWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1453, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3531 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3532 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S8, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3533 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3534 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1454, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3535 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1455, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3536 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1455, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3537 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1456, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3538 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1456, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3539 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1457, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3540 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1457, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E9NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3541 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1457, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3542 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" + { + .Instruction = ND_INS_VPINSRW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1457, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3543 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" + { + .Instruction = ND_INS_VPLZCNTD, + .Category = ND_CAT_CONFLICT, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1458, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3544 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" + { + .Instruction = ND_INS_VPLZCNTQ, + .Category = ND_CAT_CONFLICT, + .IsaSet = ND_SET_AVX512CD, + .Mnemonic = 1459, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512CD, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3545 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSDD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1460, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3546 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSDQH, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1461, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3547 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSDQL, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1462, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3548 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSSDD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1463, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3549 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSSDQH, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1464, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3550 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSSDQL, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1465, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3551 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSSWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1466, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3552 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSSWW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1467, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3553 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1468, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3554 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMACSWW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1469, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3555 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMADCSSWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1470, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3556 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" + { + .Instruction = ND_INS_VPMADCSWD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1471, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3557 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" + { + .Instruction = ND_INS_VPMADD52HUQ, + .Category = ND_CAT_IFMA, + .IsaSet = ND_SET_AVX512IFMA, + .Mnemonic = 1472, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512IFMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3558 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" + { + .Instruction = ND_INS_VPMADD52HUQ, + .Category = ND_CAT_AVXIFMA, + .IsaSet = ND_SET_AVXIFMA, + .Mnemonic = 1472, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXIFMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3559 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" + { + .Instruction = ND_INS_VPMADD52LUQ, + .Category = ND_CAT_IFMA, + .IsaSet = ND_SET_AVX512IFMA, + .Mnemonic = 1473, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512IFMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3560 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" + { + .Instruction = ND_INS_VPMADD52LUQ, + .Category = ND_CAT_AVXIFMA, + .IsaSet = ND_SET_AVXIFMA, + .Mnemonic = 1473, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVXIFMA, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3561 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" + { + .Instruction = ND_INS_VPMADDUBSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1474, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3562 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" + { + .Instruction = ND_INS_VPMADDUBSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1474, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3563 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" + { + .Instruction = ND_INS_VPMADDWD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1475, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3564 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" + { + .Instruction = ND_INS_VPMADDWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1475, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3565 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" + { + .Instruction = ND_INS_VPMASKMOVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3566 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" + { + .Instruction = ND_INS_VPMASKMOVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1476, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3567 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" + { + .Instruction = ND_INS_VPMASKMOVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1477, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3568 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" + { + .Instruction = ND_INS_VPMASKMOVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1477, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3569 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1478, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3570 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" + { + .Instruction = ND_INS_VPMAXSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1478, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3571 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1479, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3572 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" + { + .Instruction = ND_INS_VPMAXSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1479, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3573 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1480, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3574 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1481, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3575 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" + { + .Instruction = ND_INS_VPMAXSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1481, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3576 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1482, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3577 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" + { + .Instruction = ND_INS_VPMAXUB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1482, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3578 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1483, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3579 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" + { + .Instruction = ND_INS_VPMAXUD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1483, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3580 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1484, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3581 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" + { + .Instruction = ND_INS_VPMAXUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1485, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3582 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" + { + .Instruction = ND_INS_VPMAXUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1485, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3583 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1486, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3584 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" + { + .Instruction = ND_INS_VPMINSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1486, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3585 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1487, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3586 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" + { + .Instruction = ND_INS_VPMINSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1487, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3587 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1488, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3588 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" + { + .Instruction = ND_INS_VPMINSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1489, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3589 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" + { + .Instruction = ND_INS_VPMINSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1489, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3590 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1490, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3591 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VPMINUB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1490, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3592 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3593 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" + { + .Instruction = ND_INS_VPMINUD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1491, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3594 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1492, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3595 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" + { + .Instruction = ND_INS_VPMINUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1493, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3596 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" + { + .Instruction = ND_INS_VPMINUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1493, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3597 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVB2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1494, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3598 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVD2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1495, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3599 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1496, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3600 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1497, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3601 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2B, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1498, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3602 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2D, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1499, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3603 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2Q, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1500, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3604 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVM2W, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1501, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3605 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVMSKB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1502, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3606 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVQ2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1503, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3607 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1504, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3608 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1505, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3609 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVQW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1506, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3610 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1507, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3611 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1508, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3612 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1509, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3613 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1510, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3614 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSQW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1511, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3615 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVSWB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1512, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3616 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1513, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3617 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1513, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3618 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1513, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3619 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1514, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3620 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1514, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3621 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1514, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3622 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1515, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3623 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1515, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3624 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXBW, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1515, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3625 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1516, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3626 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1516, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3627 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXDQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1516, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3628 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXWD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1517, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3629 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1517, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3630 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXWD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1517, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3631 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVSXWQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3632 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXWQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3633 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" + { + .Instruction = ND_INS_VPMOVSXWQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1518, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3634 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSDB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1519, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3635 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSDW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1520, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3636 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSQB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1521, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3637 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSQD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1522, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3638 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSQW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1523, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3639 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVUSWB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1524, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3640 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" + { + .Instruction = ND_INS_VPMOVW2M, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1525, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_E7NM, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3641 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" + { + .Instruction = ND_INS_VPMOVWB, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1526, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3642 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXBD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1527, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3643 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1527, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3644 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1527, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3645 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1528, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_OVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3646 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1528, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3647 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1528, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3648 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXBW, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1529, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3649 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1529, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3650 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXBW, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1529, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3651 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXDQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1530, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3652 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1530, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3653 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXDQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1530, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3654 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1531, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_HVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3655 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1531, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3656 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1531, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3657 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" + { + .Instruction = ND_INS_VPMOVZXWQ, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1532, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_QVM, + .ExcType = ND_EXT_E5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3658 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1532, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3659 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" + { + .Instruction = ND_INS_VPMOVZXWQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1532, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3660 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3661 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" + { + .Instruction = ND_INS_VPMULDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1533, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3662 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" + { + .Instruction = ND_INS_VPMULHRSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1534, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3663 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" + { + .Instruction = ND_INS_VPMULHRSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1534, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3664 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULHUW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1535, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3665 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" + { + .Instruction = ND_INS_VPMULHUW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1535, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3666 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULHW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1536, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3667 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" + { + .Instruction = ND_INS_VPMULHW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1536, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3668 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1537, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3669 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" + { + .Instruction = ND_INS_VPMULLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1537, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3670 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1538, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3671 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1539, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3672 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" + { + .Instruction = ND_INS_VPMULLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1539, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3673 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULTISHIFTQB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI, + .Mnemonic = 1540, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3674 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" + { + .Instruction = ND_INS_VPMULUDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3675 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" + { + .Instruction = ND_INS_VPMULUDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1541, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3676 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTB, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1542, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3677 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTD, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512VPOPCNTDQ, + .Mnemonic = 1543, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3678 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTQ, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512VPOPCNTDQ, + .Mnemonic = 1544, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512VPOPCNTDQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3679 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" + { + .Instruction = ND_INS_VPOPCNTW, + .Category = ND_CAT_VPOPCNT, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1545, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3680 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" + { + .Instruction = ND_INS_VPOR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1546, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3681 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" + { + .Instruction = ND_INS_VPORD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1547, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3682 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" + { + .Instruction = ND_INS_VPORQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1548, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3683 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" + { + .Instruction = ND_INS_VPPERM, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1549, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3684 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" + { + .Instruction = ND_INS_VPPERM, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1549, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3685 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" + { + .Instruction = ND_INS_VPROLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1550, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3686 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" + { + .Instruction = ND_INS_VPROLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1551, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3687 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VPROLVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1552, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3688 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VPROLVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1553, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3689 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" + { + .Instruction = ND_INS_VPRORD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1554, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3690 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" + { + .Instruction = ND_INS_VPRORQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1555, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3691 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VPRORVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1556, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3692 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VPRORVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1557, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3693 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3694 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3695 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" + { + .Instruction = ND_INS_VPROTB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1558, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3696 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3697 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3698 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" + { + .Instruction = ND_INS_VPROTD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1559, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3699 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1560, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3700 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1560, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3701 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" + { + .Instruction = ND_INS_VPROTQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1560, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3702 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3703 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3704 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" + { + .Instruction = ND_INS_VPROTW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1561, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3705 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_VPSADBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1562, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3706 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" + { + .Instruction = ND_INS_VPSADBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1562, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3707 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERDD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1563, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3708 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERDQ, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1564, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3709 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERQD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1565, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3710 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VPSCATTERQQ, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1566, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3711 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" + { + .Instruction = ND_INS_VPSHAB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1567, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3712 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" + { + .Instruction = ND_INS_VPSHAB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1567, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3713 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" + { + .Instruction = ND_INS_VPSHAD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1568, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3714 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" + { + .Instruction = ND_INS_VPSHAD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1568, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3715 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" + { + .Instruction = ND_INS_VPSHAQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1569, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3716 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" + { + .Instruction = ND_INS_VPSHAQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1569, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3717 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" + { + .Instruction = ND_INS_VPSHAW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1570, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3718 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" + { + .Instruction = ND_INS_VPSHAW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1570, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3719 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3720 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3721 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3722 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLB, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1571, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3723 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLD, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1572, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3724 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1573, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3725 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1574, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3726 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1575, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3727 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1576, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3728 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHLDVW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1577, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3729 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHLDW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1578, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3730 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1579, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3731 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" + { + .Instruction = ND_INS_VPSHLQ, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1579, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3732 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" + { + .Instruction = ND_INS_VPSHLW, + .Category = ND_CAT_XOP, + .IsaSet = ND_SET_XOP, + .Mnemonic = 1580, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_XOP, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3733 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1581, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3734 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1582, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3735 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVD, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1583, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3736 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVQ, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1584, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3737 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHRDVW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1585, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3738 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPSHRDW, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512VBMI2, + .Mnemonic = 1586, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512VBMI2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3739 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" + { + .Instruction = ND_INS_VPSHUFB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3740 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" + { + .Instruction = ND_INS_VPSHUFB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1587, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3741 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" + { + .Instruction = ND_INS_VPSHUFBITQMB, + .Category = ND_CAT_AVX512VBMI, + .IsaSet = ND_SET_AVX512BITALG, + .Mnemonic = 1588, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BITALG, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3742 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1589, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3743 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1589, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3744 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFHW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1590, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3745 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFHW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1590, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3746 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" + { + .Instruction = ND_INS_VPSHUFLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1591, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3747 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" + { + .Instruction = ND_INS_VPSHUFLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1591, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3748 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" + { + .Instruction = ND_INS_VPSIGNB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1592, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3749 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" + { + .Instruction = ND_INS_VPSIGND, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1593, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3750 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" + { + .Instruction = ND_INS_VPSIGNW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1594, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3751 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3752 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3753 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3754 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" + { + .Instruction = ND_INS_VPSLLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1595, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3755 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" + { + .Instruction = ND_INS_VPSLLDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1596, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3756 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSLLDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1596, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3757 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" + { + .Instruction = ND_INS_VPSLLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1597, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3758 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1597, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3759 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSLLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1597, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3760 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" + { + .Instruction = ND_INS_VPSLLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1597, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3761 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1598, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3762 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" + { + .Instruction = ND_INS_VPSLLVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1598, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3763 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1599, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3764 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" + { + .Instruction = ND_INS_VPSLLVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1599, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3765 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLVW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1600, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3766 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" + { + .Instruction = ND_INS_VPSLLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1601, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3767 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" + { + .Instruction = ND_INS_VPSLLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1601, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3768 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSLLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1601, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3769 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" + { + .Instruction = ND_INS_VPSLLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1601, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3770 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1602, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3771 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1602, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3772 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1602, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3773 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" + { + .Instruction = ND_INS_VPSRAD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1602, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3774 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRAQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1603, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3775 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1603, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3776 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1604, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3777 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" + { + .Instruction = ND_INS_VPSRAVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1604, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3778 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1605, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3779 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAVW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1606, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3780 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3781 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3782 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3783 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" + { + .Instruction = ND_INS_VPSRAW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1607, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3784 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3785 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3786 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3787 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1608, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3788 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" + { + .Instruction = ND_INS_VPSRLDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1609, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3789 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1609, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3790 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3791 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3792 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3793 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1610, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3794 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1611, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3795 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLVD, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1611, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3796 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1612, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3797 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLVQ, + .Category = ND_CAT_AVX2, + .IsaSet = ND_SET_AVX2, + .Mnemonic = 1612, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3798 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLVW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1613, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3799 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3800 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_M128, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3801 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_7, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3802 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" + { + .Instruction = ND_INS_VPSRLW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1614, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3803 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1615, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3804 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1615, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3805 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1616, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3806 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" + { + .Instruction = ND_INS_VPSUBD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1616, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3807 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1617, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3808 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" + { + .Instruction = ND_INS_VPSUBQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1617, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3809 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1618, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3810 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1618, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3811 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1619, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3812 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1619, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3813 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBUSB, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1620, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3814 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBUSB, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1620, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3815 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBUSW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3816 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBUSW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1621, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3817 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" + { + .Instruction = ND_INS_VPSUBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1622, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3818 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" + { + .Instruction = ND_INS_VPSUBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1622, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3819 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPTERNLOGD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1623, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3820 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VPTERNLOGQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1624, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3821 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" + { + .Instruction = ND_INS_VPTEST, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1625, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3822 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTMB, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1626, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3823 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTMD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1627, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3824 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTMQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1628, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3825 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTMW, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1629, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3826 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTNMB, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1630, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3827 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTNMD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1631, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3828 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTNMQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1632, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3829 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" + { + .Instruction = ND_INS_VPTESTNMW, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1633, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4nb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3830 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKHBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3831 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKHBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1634, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3832 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKHDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1635, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3833 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKHDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1635, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3834 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKHQDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1636, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3835 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKHQDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1636, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3836 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKHWD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1637, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3837 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKHWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1637, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3838 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKLBW, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1638, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3839 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKLBW, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1638, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3840 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKLDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1639, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3841 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKLDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1639, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3842 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKLQDQ, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3843 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKLQDQ, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1640, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3844 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" + { + .Instruction = ND_INS_VPUNPCKLWD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512BW, + .Mnemonic = 1641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FVM, + .ExcType = ND_EXT_E4NFnb, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512BW, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3845 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" + { + .Instruction = ND_INS_VPUNPCKLWD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1641, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3846 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" + { + .Instruction = ND_INS_VPXOR, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1642, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3847 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" + { + .Instruction = ND_INS_VPXORD, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1643, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3848 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" + { + .Instruction = ND_INS_VPXORQ, + .Category = ND_CAT_LOGICAL, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1644, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3849 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRANGEPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1645, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3850 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRANGEPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1646, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3851 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRANGESD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1647, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3852 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRANGESS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1648, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3853 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" + { + .Instruction = ND_INS_VRCP14PD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1649, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3854 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" + { + .Instruction = ND_INS_VRCP14PS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1650, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3855 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" + { + .Instruction = ND_INS_VRCP14SD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1651, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3856 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" + { + .Instruction = ND_INS_VRCP14SS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1652, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3857 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" + { + .Instruction = ND_INS_VRCP28PD, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1653, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:3858 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" + { + .Instruction = ND_INS_VRCP28PS, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1654, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:3859 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" + { + .Instruction = ND_INS_VRCP28SD, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1655, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3860 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" + { + .Instruction = ND_INS_VRCP28SS, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1656, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3861 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" + { + .Instruction = ND_INS_VRCPPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1657, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3862 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" + { + .Instruction = ND_INS_VRCPPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1658, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3863 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" + { + .Instruction = ND_INS_VRCPSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1659, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3864 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" + { + .Instruction = ND_INS_VRCPSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1660, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3865 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" + { + .Instruction = ND_INS_VREDUCEPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1661, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3866 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" + { + .Instruction = ND_INS_VREDUCEPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1662, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3867 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" + { + .Instruction = ND_INS_VREDUCEPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1663, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3868 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VREDUCESD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1664, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3869 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VREDUCESH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1665, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3870 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VREDUCESS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1666, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3871 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" + { + .Instruction = ND_INS_VRNDSCALEPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1667, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3872 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" + { + .Instruction = ND_INS_VRNDSCALEPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1668, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3873 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" + { + .Instruction = ND_INS_VRNDSCALEPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1669, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3874 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRNDSCALESD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1670, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3875 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRNDSCALESH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1671, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3876 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" + { + .Instruction = ND_INS_VRNDSCALESS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1672, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3877 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" + { + .Instruction = ND_INS_VROUNDPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1673, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3878 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" + { + .Instruction = ND_INS_VROUNDPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1674, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3879 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" + { + .Instruction = ND_INS_VROUNDSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1675, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3880 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" + { + .Instruction = ND_INS_VROUNDSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1676, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3881 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" + { + .Instruction = ND_INS_VRSQRT14PD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1677, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3882 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" + { + .Instruction = ND_INS_VRSQRT14PS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1678, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3883 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" + { + .Instruction = ND_INS_VRSQRT14SD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1679, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3884 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" + { + .Instruction = ND_INS_VRSQRT14SS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1680, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3885 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" + { + .Instruction = ND_INS_VRSQRT28PD, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1681, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), + }, + }, + + // Pos:3886 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" + { + .Instruction = ND_INS_VRSQRT28PS, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1682, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), + }, + }, + + // Pos:3887 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" + { + .Instruction = ND_INS_VRSQRT28SD, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1683, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3888 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" + { + .Instruction = ND_INS_VRSQRT28SS, + .Category = ND_CAT_KNL, + .IsaSet = ND_SET_AVX512ER, + .Mnemonic = 1684, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512ER, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3889 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" + { + .Instruction = ND_INS_VRSQRTPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1685, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), + }, + }, + + // Pos:3890 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" + { + .Instruction = ND_INS_VRSQRTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1686, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3891 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" + { + .Instruction = ND_INS_VRSQRTSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1687, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E10, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3892 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" + { + .Instruction = ND_INS_VRSQRTSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1688, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3893 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1689, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3894 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1690, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3895 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1691, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3896 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1692, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3897 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1693, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3898 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" + { + .Instruction = ND_INS_VSCALEFSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1694, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3899 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VSCATTERDPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1695, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3900 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VSCATTERDPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1696, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3901 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF0DPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1697, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3902 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF0DPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1698, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3903 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF0QPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1699, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3904 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF0QPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1700, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3905 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF1DPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1701, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3906 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF1DPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1702, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3907 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF1QPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1703, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3908 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" + { + .Instruction = ND_INS_VSCATTERPF1QPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512PF, + .Mnemonic = 1704, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12NP, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512PF, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3909 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VSCATTERQPD, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1705, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3910 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" + { + .Instruction = ND_INS_VSCATTERQPS, + .Category = ND_CAT_SCATTER, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1706, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E12, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3911 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" + { + .Instruction = ND_INS_VSHA512MSG1, + .Category = ND_CAT_SHA512, + .IsaSet = ND_SET_SHA512, + .Mnemonic = 1707, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_SHA512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3912 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" + { + .Instruction = ND_INS_VSHA512MSG2, + .Category = ND_CAT_SHA512, + .IsaSet = ND_SET_SHA512, + .Mnemonic = 1708, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_SHA512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3913 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" + { + .Instruction = ND_INS_VSHA512RNDS2, + .Category = ND_CAT_SHA512, + .IsaSet = ND_SET_SHA512, + .Mnemonic = 1709, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SHA512, + .Operands = + { + OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3914 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFF32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1710, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3915 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFF64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1711, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3916 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFI32X4, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1712, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3917 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFI64X2, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1713, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3918 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1714, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3919 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" + { + .Instruction = ND_INS_VSHUFPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1714, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3920 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" + { + .Instruction = ND_INS_VSHUFPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1715, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(5, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3921 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" + { + .Instruction = ND_INS_VSHUFPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1715, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3922 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM3MSG1, + .Category = ND_CAT_SM3, + .IsaSet = ND_SET_SM3, + .Mnemonic = 1716, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3923 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM3MSG2, + .Category = ND_CAT_SM3, + .IsaSet = ND_SET_SM3, + .Mnemonic = 1717, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3924 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" + { + .Instruction = ND_INS_VSM3RNDS2, + .Category = ND_CAT_SM3, + .IsaSet = ND_SET_SM3, + .Mnemonic = 1718, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM3, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3925 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM4KEY4, + .Category = ND_CAT_SM4, + .IsaSet = ND_SET_SM4, + .Mnemonic = 1719, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3926 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" + { + .Instruction = ND_INS_VSM4RNDS4, + .Category = ND_CAT_SM4, + .IsaSet = ND_SET_SM4, + .Mnemonic = 1720, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_6, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SM4, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3927 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" + { + .Instruction = ND_INS_VSQRTPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1721, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3928 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" + { + .Instruction = ND_INS_VSQRTPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1721, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3929 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" + { + .Instruction = ND_INS_VSQRTPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1722, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), + }, + }, + + // Pos:3930 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" + { + .Instruction = ND_INS_VSQRTPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1723, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3931 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" + { + .Instruction = ND_INS_VSQRTPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1723, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3932 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VSQRTSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1724, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3933 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VSQRTSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1724, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3934 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VSQRTSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1725, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3935 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" + { + .Instruction = ND_INS_VSQRTSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3936 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" + { + .Instruction = ND_INS_VSQRTSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1726, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3937 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" + { + .Instruction = ND_INS_VSTMXCSR, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1727, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = ND_EXT_5, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3938 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1728, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), + }, + }, + + // Pos:3939 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" + { + .Instruction = ND_INS_VSUBPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1728, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3940 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBPH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1729, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), + }, + }, + + // Pos:3941 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1730, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), + }, + }, + + // Pos:3942 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" + { + .Instruction = ND_INS_VSUBPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1730, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3943 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBSD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1731, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3944 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" + { + .Instruction = ND_INS_VSUBSD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1731, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3945 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBSH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1732, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + }, + }, + + // Pos:3946 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" + { + .Instruction = ND_INS_VSUBSS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1733, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), + }, + }, + + // Pos:3947 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" + { + .Instruction = ND_INS_VSUBSS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1733, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_2, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3948 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" + { + .Instruction = ND_INS_VTESTPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1734, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3949 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" + { + .Instruction = ND_INS_VTESTPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1735, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3950 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMISD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1736, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3951 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMISD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1736, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3952 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMISH, + .Category = ND_CAT_AVX512FP16, + .IsaSet = ND_SET_AVX512FP16, + .Mnemonic = 1737, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S16, + .ExcType = ND_EXT_E3NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512FP16, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3953 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMISS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1738, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_SAE, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = ND_TUPLE_T1S, + .ExcType = ND_EXT_E3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3954 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" + { + .Instruction = ND_INS_VUCOMISS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1738, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_3, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR|ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3955 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VUNPCKHPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1739, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3956 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" + { + .Instruction = ND_INS_VUNPCKHPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1739, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3957 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" + { + .Instruction = ND_INS_VUNPCKHPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3958 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" + { + .Instruction = ND_INS_VUNPCKHPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1740, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3959 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VUNPCKLPD, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1741, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3960 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" + { + .Instruction = ND_INS_VUNPCKLPD, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1741, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3961 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" + { + .Instruction = ND_INS_VUNPCKLPS, + .Category = ND_CAT_AVX512, + .IsaSet = ND_SET_AVX512F, + .Mnemonic = 1742, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4NF, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512F, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3962 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" + { + .Instruction = ND_INS_VUNPCKLPS, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1742, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3963 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" + { + .Instruction = ND_INS_VXORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1743, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), + }, + }, + + // Pos:3964 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" + { + .Instruction = ND_INS_VXORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1743, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3965 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" + { + .Instruction = ND_INS_VXORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX512DQ, + .Mnemonic = 1744, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, + .OpsCount = ND_OPS_CNT(4, 0), + .TupleType = ND_TUPLE_FV, + .ExcType = ND_EXT_E4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX512DQ, + .Operands = + { + OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_ZERO, 0), + OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), + }, + }, + + // Pos:3966 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" + { + .Instruction = ND_INS_VXORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1744, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3967 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" + { + .Instruction = ND_INS_VZEROALL, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1745, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = ND_EXT_8, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3968 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" + { + .Instruction = ND_INS_VZEROUPPER, + .Category = ND_CAT_AVX, + .IsaSet = ND_SET_AVX, + .Mnemonic = 1746, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = ND_EXT_8, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOV, + .CpuidFlag = ND_CFF_AVX, + .Operands = + { + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3969 Instruction:"WAIT" Encoding:"0x9B"/"" + { + .Instruction = ND_INS_WAIT, + .Category = ND_CAT_X87_ALU, + .IsaSet = ND_SET_X87, + .Mnemonic = 1747, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0xff, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:3970 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" + { + .Instruction = ND_INS_WBINVD, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 1748, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL, + .CpuidFlag = 0, + .Operands = + { + 0 + }, + }, + + // Pos:3971 Instruction:"WBNOINVD" Encoding:"repz 0x0F 0x09"/"" + { + .Instruction = ND_INS_WBNOINVD, + .Category = ND_CAT_WBNOINVD, + .IsaSet = ND_SET_WBNOINVD, + .Mnemonic = 1749, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = ND_CFF_WBNOINVD, + .Operands = + { + 0 + }, + }, + + // Pos:3972 Instruction:"WRFSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /2:reg"/"M" + { + .Instruction = ND_INS_WRFSBASE, + .Category = ND_CAT_RDWRFSGS, + .IsaSet = ND_SET_RDWRFSGS, + .Mnemonic = 1750, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RDWRFSGS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_FSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3973 Instruction:"WRGSBASE Ry" Encoding:"mo64 0xF3 0x0F 0xAE /3:reg"/"M" + { + .Instruction = ND_INS_WRGSBASE, + .Category = ND_CAT_RDWRFSGS, + .IsaSet = ND_SET_RDWRFSGS, + .Mnemonic = 1751, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_RDWRFSGS, + .Operands = + { + OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_GSBASE, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3974 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" + { + .Instruction = ND_INS_WRMSR, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_PENTIUMREAL, + .Mnemonic = 1752, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SERIAL|ND_FLAG_NOREX2, + .CpuidFlag = ND_CFF_MSR, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3975 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" + { + .Instruction = ND_INS_WRMSRLIST, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_MSRLIST, + .Mnemonic = 1753, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 3), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_O64, + .CpuidFlag = ND_CFF_MSRLIST, + .Operands = + { + OP(ND_OPT_SMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_DMT, ND_OPS_4096, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3976 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" + { + .Instruction = ND_INS_WRMSRNS, + .Category = ND_CAT_SYSTEM, + .IsaSet = ND_SET_WRMSRNS, + .Mnemonic = 1754, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_WRMSRNS, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3977 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" + { + .Instruction = ND_INS_WRPKRU, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_PKU, + .Mnemonic = 1755, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_PKU, + .Operands = + { + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3978 Instruction:"WRSSD My,Gy" Encoding:"evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem"/"MR" + { + .Instruction = ND_INS_WRSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1756, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_WRSS, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3979 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" + { + .Instruction = ND_INS_WRSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 1756, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3980 Instruction:"WRSSQ My,Gy" Encoding:"evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem"/"MR" + { + .Instruction = ND_INS_WRSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1757, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_WRSS, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3981 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" + { + .Instruction = ND_INS_WRSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 1757, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3982 Instruction:"WRUSSD My,Gy" Encoding:"evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem"/"MR" + { + .Instruction = ND_INS_WRUSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1758, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_WRUSS, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3983 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + { + .Instruction = ND_INS_WRUSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 1758, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3984 Instruction:"WRUSSQ My,Gy" Encoding:"evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem"/"MR" + { + .Instruction = ND_INS_WRUSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1759, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_WRUSS, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3985 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" + { + .Instruction = ND_INS_WRUSS, + .Category = ND_CAT_CET, + .IsaSet = ND_SET_CET_SS, + .Mnemonic = 1759, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SHS|ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_CET_SS, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:3986 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" + { + .Instruction = ND_INS_XABORT, + .Category = ND_CAT_UNCOND_BR, + .IsaSet = ND_SET_TSX, + .Mnemonic = 1760, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RTM, + .Operands = + { + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + }, + }, + + // Pos:3987 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" + { + .Instruction = ND_INS_XADD, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 1761, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3988 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" + { + .Instruction = ND_INS_XADD, + .Category = ND_CAT_SEMAPHORE, + .IsaSet = ND_SET_I486REAL, + .Mnemonic = 1761, + .ValidPrefixes = ND_PREF_LOCK|ND_PREF_HLE, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:3989 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" + { + .Instruction = ND_INS_XBEGIN, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_TSX, + .Mnemonic = 1762, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RTM, + .Operands = + { + OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_RCW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + }, + }, + + // Pos:3990 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3991 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLEWOL, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3992 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3993 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3994 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3995 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3996 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3997 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3998 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:3999 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" + { + .Instruction = ND_INS_XCHG, + .Category = ND_CAT_DATAXFER, + .IsaSet = ND_SET_I86, + .Mnemonic = 1763, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + }, + }, + + // Pos:4000 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" + { + .Instruction = ND_INS_XEND, + .Category = ND_CAT_COND_BR, + .IsaSet = ND_SET_TSX, + .Mnemonic = 1764, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RTM, + .Operands = + { + OP(ND_OPT_rIP, ND_OPS_yf, ND_OPF_OPDEF, ND_OPA_CW, 0, 0), + }, + }, + + // Pos:4001 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" + { + .Instruction = ND_INS_XGETBV, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1765, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4002 Instruction:"XLATB" Encoding:"0xD7"/"" + { + .Instruction = ND_INS_XLATB, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1766, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 2), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + OP(ND_OPT_pBXAL, ND_OPS_b, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4003 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4004 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4005 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4006 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4007 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4008 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4009 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4010 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4011 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4012 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4013 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4014 Instruction:"XOR Eb,Gb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4015 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4016 Instruction:"XOR Ev,Gv" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4017 Instruction:"XOR Gb,Eb" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4018 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4019 Instruction:"XOR Gv,Ev" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4020 Instruction:"XOR Eb,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4021 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4022 Instruction:"XOR Ev,Iz" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4023 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4024 Instruction:"XOR Ev,Ib" Encoding:"evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_NF, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM|ND_FLAG_NOV|ND_FLAG_NOVP, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4025 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4026 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4027 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4028 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4029 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4030 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4031 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4032 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4033 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4034 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4035 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND, + .OpsCount = ND_OPS_CNT(3, 1), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4036 Instruction:"XOR Bb,Eb,Gb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4037 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4038 Instruction:"XOR Bv,Ev,Gv" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r"/"VMR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4039 Instruction:"XOR Bb,Gb,Eb" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4040 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4041 Instruction:"XOR Bv,Gv,Ev" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r"/"VRM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4042 Instruction:"XOR Bb,Eb,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_b, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4043 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4044 Instruction:"XOR Bv,Ev,Iz" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_z, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4045 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4046 Instruction:"XOR Bv,Ev,Ib" Encoding:"evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib"/"VMI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_APX_F, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, + .ValidDecorators = ND_DECO_ND|ND_DECO_NF, + .OpsCount = ND_OPS_CNT(3, 0), + .TupleType = 0, + .ExcType = ND_EXT_APX_EVEX_INT, + .FpuFlags = 0, + .EvexMode = ND_EVEXM_LEGACY, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_SCALABLE|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_APX_F, + .Operands = + { + OP(ND_OPT_B, ND_OPS_v, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4047 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4048 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4049 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4050 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4051 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4052 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = 0, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4053 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4054 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_z, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4055 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM|ND_FLAG_I64, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4056 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" + { + .Instruction = ND_INS_XOR, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_I86, + .Mnemonic = 1767, + .ValidPrefixes = ND_PREF_HLE|ND_PREF_LOCK, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, + .SetFlags = 0|NDR_RFLAG_AF, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = 0, + .Operands = + { + OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_I, ND_OPS_b, ND_OPF_OPSIGNEXO1, ND_OPA_R, 0, 0), + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4057 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" + { + .Instruction = ND_INS_XORPD, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE2, + .Mnemonic = 1768, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE2, + .Operands = + { + OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4058 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" + { + .Instruction = ND_INS_XORPS, + .Category = ND_CAT_LOGICAL_FP, + .IsaSet = ND_SET_SSE, + .Mnemonic = 1769, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = ND_EXT_4, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM|ND_FLAG_VECTOR, + .CpuidFlag = ND_CFF_SSE, + .Operands = + { + OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4059 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" + { + .Instruction = ND_INS_XRESLDTRK, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_TSXLDTRK, + .Mnemonic = 1770, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TSXLDTRK, + .Operands = + { + 0 + }, + }, + + // Pos:4060 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" + { + .Instruction = ND_INS_XRSTOR, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1771, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4061 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" + { + .Instruction = ND_INS_XRSTOR, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1772, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4062 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" + { + .Instruction = ND_INS_XRSTORS, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVES, + .Mnemonic = 1773, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVES, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4063 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" + { + .Instruction = ND_INS_XRSTORS, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVES, + .Mnemonic = 1774, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVES, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4064 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" + { + .Instruction = ND_INS_XSAVE, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1775, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4065 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" + { + .Instruction = ND_INS_XSAVE, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1776, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4066 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" + { + .Instruction = ND_INS_XSAVEC, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVEC, + .Mnemonic = 1777, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVEC, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4067 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" + { + .Instruction = ND_INS_XSAVEC, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVEC, + .Mnemonic = 1778, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVEC, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4068 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" + { + .Instruction = ND_INS_XSAVEOPT, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1779, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4069 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" + { + .Instruction = ND_INS_XSAVEOPT, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1780, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4070 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" + { + .Instruction = ND_INS_XSAVES, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVES, + .Mnemonic = 1781, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVES, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4071 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" + { + .Instruction = ND_INS_XSAVES, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVES, + .Mnemonic = 1782, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(1, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVES, + .Operands = + { + OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR0, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_BANK, ND_OPS_unknown, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + }, + }, + + // Pos:4072 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" + { + .Instruction = ND_INS_XSETBV, + .Category = ND_CAT_XSAVE, + .IsaSet = ND_SET_XSAVE, + .Mnemonic = 1783, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 4), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_XSAVE, + .Operands = + { + OP(ND_OPT_rCX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rDX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_rAX, ND_OPS_d, ND_OPF_OPDEF, ND_OPA_R, 0, 0), + OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + // Pos:4073 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" + { + .Instruction = ND_INS_XSUSLDTRK, + .Category = ND_CAT_MISC, + .IsaSet = ND_SET_TSXLDTRK, + .Mnemonic = 1784, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_TSXLDTRK, + .Operands = + { + 0 + }, + }, + + // Pos:4074 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" + { + .Instruction = ND_INS_XTEST, + .Category = ND_CAT_LOGIC, + .IsaSet = ND_SET_TSX, + .Mnemonic = 1785, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(0, 1), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0|NDR_RFLAG_ZF, + .SetFlags = 0, + .ClearedFlags = 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, + .Attributes = ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RTM, + .Operands = + { + OP(ND_OPT_F, ND_OPS_v, ND_OPF_OPDEF, ND_OPA_W, 0, 0), + }, + }, + + +}; + +#endif diff --git a/bddisasm/include/mnemonics.h b/bddisasm/include/bdx86_mnemonics.h similarity index 70% rename from bddisasm/include/mnemonics.h rename to bddisasm/include/bdx86_mnemonics.h index 6e24ed3..64e1fd9 100644 --- a/bddisasm/include/mnemonics.h +++ b/bddisasm/include/bdx86_mnemonics.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Bitdefender + * Copyright (c) 2024 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ @@ -7,39 +7,46 @@ // This file was auto-generated by generate_tables.py. DO NOT MODIFY! // -#ifndef MNEMONICS_H -#define MNEMONICS_H +#ifndef BDX86_MNEMONICS_H +#define BDX86_MNEMONICS_H -const char *gMnemonics[1751] = +const char *gMnemonics[1786] = { "AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL", "AESDEC256KL", "AESDECLAST", "AESDECWIDE128KL", "AESDECWIDE256KL", "AESENC", "AESENC128KL", "AESENC256KL", "AESENCLAST", "AESENCWIDE128KL", "AESENCWIDE256KL", "AESIMC", "AESKEYGENASSIST", - "ALTINST", "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", - "AOR", "ARPL", "AXOR", "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", - "BLCS", "BLENDPD", "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", - "BLSI", "BLSIC", "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", - "BNDLDX", "BNDMK", "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", - "BSWAP", "BT", "BTC", "BTR", "BTS", "BZHI", "CALL", "CALLF", - "CBW", "CDQ", "CDQE", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", - "CLEVICT1", "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", - "CLTS", "CLUI", "CLWB", "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", - "CMOVLE", "CMOVNBE", "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", - "CMOVNP", "CMOVNS", "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", - "CMP", "CMPBEXADD", "CMPCXADD", "CMPLEXADD", "CMPLXADD", "CMPNBEXADD", + "AND", "ANDN", "ANDNPD", "ANDNPS", "ANDPD", "ANDPS", "AOR", "ARPL", + "AXOR", "BEXTR", "BLCFILL", "BLCI", "BLCIC", "BLCMSK", "BLCS", + "BLENDPD", "BLENDPS", "BLENDVPD", "BLENDVPS", "BLSFILL", "BLSI", + "BLSIC", "BLSMSK", "BLSR", "BNDCL", "BNDCN", "BNDCU", "BNDLDX", + "BNDMK", "BNDMOV", "BNDSTX", "BOUND", "BSF", "BSR", "BSWAP", + "BT", "BTC", "BTR", "BTS", "BZHI", "CALL", "CALLF", "CBW", "CCMPBE", + "CCMPC", "CCMPF", "CCMPL", "CCMPLE", "CCMPNBE", "CCMPNC", "CCMPNL", + "CCMPNLE", "CCMPNO", "CCMPNS", "CCMPNZ", "CCMPO", "CCMPS", "CCMPT", + "CCMPZ", "CDQ", "CDQE", "CFCMOVBE", "CFCMOVC", "CFCMOVL", "CFCMOVLE", + "CFCMOVNBE", "CFCMOVNC", "CFCMOVNL", "CFCMOVNLE", "CFCMOVNO", + "CFCMOVNP", "CFCMOVNS", "CFCMOVNZ", "CFCMOVO", "CFCMOVP", "CFCMOVS", + "CFCMOVZ", "CLAC", "CLC", "CLD", "CLDEMOTE", "CLEVICT0", "CLEVICT1", + "CLFLUSH", "CLFLUSHOPT", "CLGI", "CLI", "CLRSSBSY", "CLTS", "CLUI", + "CLWB", "CLZERO", "CMC", "CMOVBE", "CMOVC", "CMOVL", "CMOVLE", + "CMOVNBE", "CMOVNC", "CMOVNL", "CMOVNLE", "CMOVNO", "CMOVNP", + "CMOVNS", "CMOVNZ", "CMOVO", "CMOVP", "CMOVS", "CMOVZ", "CMP", + "CMPBEXADD", "CMPCXADD", "CMPLEXADD", "CMPLXADD", "CMPNBEXADD", "CMPNCXADD", "CMPNLEXADD", "CMPNLXADD", "CMPNOXADD", "CMPNPXADD", "CMPNSXADD", "CMPNZXADD", "CMPOXADD", "CMPPD", "CMPPS", "CMPPXADD", "CMPSB", "CMPSD", "CMPSQ", "CMPSS", "CMPSW", "CMPSXADD", "CMPXCHG", "CMPXCHG16B", "CMPXCHG8B", "CMPZXADD", "COMISD", "COMISS", "CPUID", - "CPU_READ", "CPU_WRITE", "CQO", "CRC32", "CVTDQ2PD", "CVTDQ2PS", - "CVTPD2DQ", "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", "CVTPS2DQ", - "CVTPS2PD", "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", "CVTSI2SS", - "CVTSS2SD", "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", "CVTTPS2DQ", - "CVTTPS2PI", "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", "DAA", - "DAS", "DEC", "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", "DIVSS", - "DMINT", "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", + "CQO", "CRC32", "CTESTBE", "CTESTC", "CTESTF", "CTESTL", "CTESTLE", + "CTESTNBE", "CTESTNC", "CTESTNL", "CTESTNLE", "CTESTNO", "CTESTNS", + "CTESTNZ", "CTESTO", "CTESTS", "CTESTT", "CTESTZ", "CVTDQ2PD", + "CVTDQ2PS", "CVTPD2DQ", "CVTPD2PI", "CVTPD2PS", "CVTPI2PD", "CVTPI2PS", + "CVTPS2DQ", "CVTPS2PD", "CVTPS2PI", "CVTSD2SI", "CVTSD2SS", "CVTSI2SD", + "CVTSI2SS", "CVTSS2SD", "CVTSS2SI", "CVTTPD2DQ", "CVTTPD2PI", + "CVTTPS2DQ", "CVTTPS2PI", "CVTTSD2SI", "CVTTSS2SI", "CWD", "CWDE", + "DAA", "DAS", "DEC", "DELAY", "DIV", "DIVPD", "DIVPS", "DIVSD", + "DIVSS", "DPPD", "DPPS", "EMMS", "ENCLS", "ENCLU", "ENCLV", "ENCODEKEY128", "ENCODEKEY256", "ENDBR32", "ENDBR64", "ENQCMD", "ENQCMDS", "ENTER", "ERETS", "ERETU", "EXTRACTPS", "EXTRQ", "F2XM1", "FABS", "FADD", "FADDP", "FBLD", "FBSTP", "FCHS", "FCMOVB", "FCMOVBE", "FCMOVE", @@ -61,24 +68,24 @@ const char *gMnemonics[1751] = "INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ", "INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ", - "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", - "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", - "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", - "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", - "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", - "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", - "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", "KORW", - "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", - "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", "KTESTW", - "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", - "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", "LAR", - "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", "LES", - "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LKGS", "LLDT", "LLWPCB", - "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", - "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", - "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", - "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", - "MONITORX", "MONTMUL", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", + "IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPABS", + "JMPE", "JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", + "JNZ", "JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", + "KADDW", "KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", + "KANDQ", "KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", + "KMOVQ", "KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", + "KORD", "KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", + "KORW", "KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", + "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", + "KTESTW", "KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", + "KXNORQ", "KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", + "LAR", "LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", + "LES", "LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LKGS", "LLDT", + "LLWPCB", "LMSW", "LOADIWKEY", "LODSB", "LODSD", "LODSQ", "LODSW", + "LOOP", "LOOPNZ", "LOOPZ", "LSL", "LSS", "LTR", "LWPINS", "LWPVAL", + "LZCNT", "MASKMOVDQU", "MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", + "MAXSS", "MCOMMIT", "MFENCE", "MINPD", "MINPS", "MINSD", "MINSS", + "MONITOR", "MONITORX", "MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B", "MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", @@ -104,52 +111,52 @@ const char *gMnemonics[1751] = "PMINUD", "PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", - "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", - "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", - "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1", "PREFETCHM", "PREFETCHNTA", - "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW", "PREFETCHWT1", - "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", - "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", - "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", - "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", - "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", - "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", - "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", - "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", - "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", - "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC", - "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPUPDATE", - "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", - "RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", - "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", - "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", - "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", - "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", - "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", - "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", - "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", - "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", - "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", - "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", - "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", - "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", - "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", - "TCMMRLFP16PS", "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", - "TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", - "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", - "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", - "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", - "UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", - "V4FNMADDSS", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", - "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST", - "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND", - "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", - "VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", - "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", - "VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", - "VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", - "VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", - "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", + "PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POP2", + "POP2P", "POPA", "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW", + "POPP", "POR", "PREFETCH", "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1", + "PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", + "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", + "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", + "PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", + "PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", + "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", + "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", + "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSH2", "PUSH2P", + "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PUSHP", "PVALIDATE", + "PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE", + "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND", + "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN", + "RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", + "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS", + "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", + "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", + "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL", + "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", + "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", + "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", + "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", + "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", + "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", + "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", + "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB", + "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL", "SYSENTER", + "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS", + "TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", + "TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", + "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", + "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", + "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", + "UWRMSR", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", + "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", + "VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", + "VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", + "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS", + "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", + "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", + "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", + "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", + "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD", + "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16", @@ -306,13 +313,11 @@ const char *gMnemonics[1751] = "VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", - "WRMSRNS", "WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", - "XABORT", "XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", - "XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", - "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", - "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", - "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", - "XSTORE", "XSUSLDTRK", "XTEST", + "WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", + "XADD", "XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD", + "XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", + "XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", + "XSAVES", "XSAVES64", "XSETBV", "XSUSLDTRK", "XTEST", }; diff --git a/bddisasm/include/prefixes.h b/bddisasm/include/bdx86_prefixes.h similarity index 89% rename from bddisasm/include/prefixes.h rename to bddisasm/include/bdx86_prefixes.h index c803535..c5e01c9 100644 --- a/bddisasm/include/prefixes.h +++ b/bddisasm/include/bdx86_prefixes.h @@ -2,8 +2,8 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#ifndef PREFIXES_H -#define PREFIXES_H +#ifndef BDX86_PREFIXES_H +#define BDX86_PREFIXES_H #define ND_PREF_CODE_NONE 0 #define ND_PREF_CODE_STANDARD 1 @@ -26,9 +26,9 @@ static const ND_UINT8 gPrefixesMap[256] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // A 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // B 0, 0, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // C - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // D + 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // D 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // E 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // F }; -#endif // PREFIXES_H +#endif // BDX86_PREFIXES_H diff --git a/bddisasm/include/bdx86_table_evex.h b/bddisasm/include/bdx86_table_evex.h new file mode 100644 index 0000000..cd5bc49 --- /dev/null +++ b/bddisasm/include/bdx86_table_evex.h @@ -0,0 +1,38359 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + +#ifndef BDX86_TABLE_EVEX_H +#define BDX86_TABLE_EVEX_H + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2650] // URDMSR Rq,Id +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2654] // UWRMSR Id,Rq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_07_opcode_f8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_02_modrmreg, + /* 03 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp_03_modrmreg, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_07_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)&gEvexMap_mmmmm_07_opcode_f8_pp, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2877] // VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2999] // VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d7_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2876] // VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2998] // VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_d6_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_d6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3065] // VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3060] // VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_be_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_be_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3027] // VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bd_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3022] // VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bc_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2968] // VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_bb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_bb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2963] // VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ba_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ba_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2909] // VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2904] // VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2983] // VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2934] // VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_b6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_b6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3055] // VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_af_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_af_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3050] // VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ae_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ae_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3017] // VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ad_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ad_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3012] // VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ac_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ac_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2958] // VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_ab_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_ab_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2953] // VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_aa_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_aa_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2899] // VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2894] // VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2978] // VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2929] // VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_a6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_a6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3045] // VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3040] // VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3007] // VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3002] // VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2948] // VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2943] // VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_9a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_9a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2889] // VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_99_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_99_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2884] // VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_98_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_98_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2973] // VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_97_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_97_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2924] // VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_96_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_96_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2875] // VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2913] // VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_57_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_57_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2874] // VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2912] // VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_56_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_56_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3891] // VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3889] // VRSQRTPH Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3863] // VRCPSH Vdq{K}{z},aKq,Hdq,Wsh +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3861] // VRCPPH Vfv{K}{z},aKq,Wfv|B16 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_4c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_4c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3106] // VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_43_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_43_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3103] // VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_42_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3897] // VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3894] // VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_2c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2761] // VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2790] // VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_06_opcode_13_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_06_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_06_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)&gEvexMap_mmmmm_06_opcode_13_pp, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)&gEvexMap_mmmmm_06_opcode_2c_pp, + /* 2d */ (const void *)&gEvexMap_mmmmm_06_opcode_2d_pp, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)&gEvexMap_mmmmm_06_opcode_42_pp, + /* 43 */ (const void *)&gEvexMap_mmmmm_06_opcode_43_pp, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)&gEvexMap_mmmmm_06_opcode_4c_pp, + /* 4d */ (const void *)&gEvexMap_mmmmm_06_opcode_4d_pp, + /* 4e */ (const void *)&gEvexMap_mmmmm_06_opcode_4e_pp, + /* 4f */ (const void *)&gEvexMap_mmmmm_06_opcode_4f_pp, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)&gEvexMap_mmmmm_06_opcode_56_pp, + /* 57 */ (const void *)&gEvexMap_mmmmm_06_opcode_57_pp, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)&gEvexMap_mmmmm_06_opcode_96_pp, + /* 97 */ (const void *)&gEvexMap_mmmmm_06_opcode_97_pp, + /* 98 */ (const void *)&gEvexMap_mmmmm_06_opcode_98_pp, + /* 99 */ (const void *)&gEvexMap_mmmmm_06_opcode_99_pp, + /* 9a */ (const void *)&gEvexMap_mmmmm_06_opcode_9a_pp, + /* 9b */ (const void *)&gEvexMap_mmmmm_06_opcode_9b_pp, + /* 9c */ (const void *)&gEvexMap_mmmmm_06_opcode_9c_pp, + /* 9d */ (const void *)&gEvexMap_mmmmm_06_opcode_9d_pp, + /* 9e */ (const void *)&gEvexMap_mmmmm_06_opcode_9e_pp, + /* 9f */ (const void *)&gEvexMap_mmmmm_06_opcode_9f_pp, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)&gEvexMap_mmmmm_06_opcode_a6_pp, + /* a7 */ (const void *)&gEvexMap_mmmmm_06_opcode_a7_pp, + /* a8 */ (const void *)&gEvexMap_mmmmm_06_opcode_a8_pp, + /* a9 */ (const void *)&gEvexMap_mmmmm_06_opcode_a9_pp, + /* aa */ (const void *)&gEvexMap_mmmmm_06_opcode_aa_pp, + /* ab */ (const void *)&gEvexMap_mmmmm_06_opcode_ab_pp, + /* ac */ (const void *)&gEvexMap_mmmmm_06_opcode_ac_pp, + /* ad */ (const void *)&gEvexMap_mmmmm_06_opcode_ad_pp, + /* ae */ (const void *)&gEvexMap_mmmmm_06_opcode_ae_pp, + /* af */ (const void *)&gEvexMap_mmmmm_06_opcode_af_pp, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)&gEvexMap_mmmmm_06_opcode_b6_pp, + /* b7 */ (const void *)&gEvexMap_mmmmm_06_opcode_b7_pp, + /* b8 */ (const void *)&gEvexMap_mmmmm_06_opcode_b8_pp, + /* b9 */ (const void *)&gEvexMap_mmmmm_06_opcode_b9_pp, + /* ba */ (const void *)&gEvexMap_mmmmm_06_opcode_ba_pp, + /* bb */ (const void *)&gEvexMap_mmmmm_06_opcode_bb_pp, + /* bc */ (const void *)&gEvexMap_mmmmm_06_opcode_bc_pp, + /* bd */ (const void *)&gEvexMap_mmmmm_06_opcode_bd_pp, + /* be */ (const void *)&gEvexMap_mmmmm_06_opcode_be_pp, + /* bf */ (const void *)&gEvexMap_mmmmm_06_opcode_bf_pp, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)&gEvexMap_mmmmm_06_opcode_d6_pp, + /* d7 */ (const void *)&gEvexMap_mmmmm_06_opcode_d7_pp, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3280] // VMOVW Rd,Vdq +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3279] // VMOVW Mw,Vdq +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2838] // VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2839] // VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2766] // VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2765] // VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7d_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2814] // VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2813] // VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2836] // VCVTUSI2SH Vdq,Hdq,Ey{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2762] // VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2832] // VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2829] // VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2810] // VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_7a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_7a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2791] // VCVTSH2USI Gy,Wsh{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2764] // VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2763] // VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_79_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_79_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2824] // VCVTTSH2USI Gy,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_02_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_02_wi_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2812] // VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2811] // VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_78_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_78_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp_02_wi, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3278] // VMOVW Vdq,Rd +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3277] // VMOVW Vdq,Mw +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_6e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3152] // VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3147] // VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5f_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2848] // VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2843] // VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3167] // VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3162] // VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5d_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3945] // VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3940] // VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2809] // VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2756] // VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2780] // VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2737] // VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5b_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2782] // VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2788] // VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2749] // VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2757] // VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_5a_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_5a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3295] // VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3290] // VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_59_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_59_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2668] // VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2663] // VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_58_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_58_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3934] // VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3929] // VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_51_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2729] // VCOMISH Vdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2f_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3952] // VUCOMISH Vdq,Wsh{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_2e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2789] // VCVTSH2SI Gy,Wsh{er} +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2d_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2823] // VCVTTSH2SI Gy,Wsh{sae} +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2c_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2795] // VCVTSI2SH Vdq,Hdq,Ey +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_2a_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2775] // VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2800] // VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_1d_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_1d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3256] // VMOVSH Wsh{K}{z},aKq,Hdq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3255] // VMOVSH Wsh{K},aKq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_11_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3254] // VMOVSH Vdq{K}{z},aKq,Hdq,Wsh +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3253] // VMOVSH Vdq{K}{z},aKq,Wsh +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_05_opcode_10_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_05_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gEvexMap_mmmmm_05_opcode_10_pp, + /* 11 */ (const void *)&gEvexMap_mmmmm_05_opcode_11_pp, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)&gEvexMap_mmmmm_05_opcode_1d_pp, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)&gEvexMap_mmmmm_05_opcode_2a_pp, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)&gEvexMap_mmmmm_05_opcode_2c_pp, + /* 2d */ (const void *)&gEvexMap_mmmmm_05_opcode_2d_pp, + /* 2e */ (const void *)&gEvexMap_mmmmm_05_opcode_2e_pp, + /* 2f */ (const void *)&gEvexMap_mmmmm_05_opcode_2f_pp, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)&gEvexMap_mmmmm_05_opcode_51_pp, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)&gEvexMap_mmmmm_05_opcode_58_pp, + /* 59 */ (const void *)&gEvexMap_mmmmm_05_opcode_59_pp, + /* 5a */ (const void *)&gEvexMap_mmmmm_05_opcode_5a_pp, + /* 5b */ (const void *)&gEvexMap_mmmmm_05_opcode_5b_pp, + /* 5c */ (const void *)&gEvexMap_mmmmm_05_opcode_5c_pp, + /* 5d */ (const void *)&gEvexMap_mmmmm_05_opcode_5d_pp, + /* 5e */ (const void *)&gEvexMap_mmmmm_05_opcode_5e_pp, + /* 5f */ (const void *)&gEvexMap_mmmmm_05_opcode_5f_pp, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)&gEvexMap_mmmmm_05_opcode_6e_pp, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)&gEvexMap_mmmmm_05_opcode_78_pp, + /* 79 */ (const void *)&gEvexMap_mmmmm_05_opcode_79_pp, + /* 7a */ (const void *)&gEvexMap_mmmmm_05_opcode_7a_pp, + /* 7b */ (const void *)&gEvexMap_mmmmm_05_opcode_7b_pp, + /* 7c */ (const void *)&gEvexMap_mmmmm_05_opcode_7c_pp, + /* 7d */ (const void *)&gEvexMap_mmmmm_05_opcode_7d_pp, + /* 7e */ (const void *)&gEvexMap_mmmmm_05_opcode_7e_pp, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 871] // DEC Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 868] // DEC Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 865] // DEC Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 862] // DEC Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1137] // INC Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1134] // INC Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1131] // INC Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1128] // INC Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1979] // PUSH2P Bv,Rv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd_01_nf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1978] // PUSH2 Bv,Rv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_00_nd, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w_01_nd, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 870] // DEC Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 867] // DEC Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 864] // DEC Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 861] // DEC Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1136] // INC Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1133] // INC Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1130] // INC Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1127] // INC Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ff_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 869] // DEC Bb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 866] // DEC Bb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 863] // DEC Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 860] // DEC Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1135] // INC Bb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1132] // INC Bb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1129] // INC Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1126] // INC Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fe_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 189] // AOR My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 192] // AXOR My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 5] // AAND My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2] // AADD My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_fc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1422] // MOVDIRI My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2649] // URDMSR Eq,Gq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w_00_nd, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 907] // ENQCMD rM?,Moq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2653] // UWRMSR Gq,Eq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w_00_nd, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 909] // ENQCMDS rM?,Moq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1420] // MOVDIR64B rMoq,Moq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1084] // IDIV Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1081] // IDIV Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 888] // DIV Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 885] // DIV Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1112] // IMUL Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1107] // IMUL Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1486] // MUL Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1483] // MUL Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1508] // NEG Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1505] // NEG Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1502] // NEG Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1499] // NEG Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1587] // NOT Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1584] // NOT Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 770] // CTESTNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 734] // CTESTLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 761] // CTESTNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 725] // CTESTL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 716] // CTESTF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 824] // CTESTT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 788] // CTESTNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 815] // CTESTS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 743] // CTESTNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 698] // CTESTBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 797] // CTESTNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 833] // CTESTZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 752] // CTESTNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 707] // CTESTC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 779] // CTESTNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 806] // CTESTO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 768] // CTESTNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 732] // CTESTLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 759] // CTESTNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 723] // CTESTL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 714] // CTESTF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 822] // CTESTT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 786] // CTESTNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 813] // CTESTS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 741] // CTESTNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 696] // CTESTBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 795] // CTESTNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 831] // CTESTZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 750] // CTESTNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 705] // CTESTC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 777] // CTESTNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 804] // CTESTO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1083] // IDIV Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1080] // IDIV Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 887] // DIV Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 884] // DIV Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1111] // IMUL Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1106] // IMUL Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1485] // MUL Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1482] // MUL Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1507] // NEG Bv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1504] // NEG Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1501] // NEG Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1498] // NEG Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1586] // NOT Bv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1583] // NOT Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 769] // CTESTNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 733] // CTESTLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 760] // CTESTNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 724] // CTESTL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 715] // CTESTF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 823] // CTESTT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 787] // CTESTNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 814] // CTESTS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 742] // CTESTNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 697] // CTESTBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 796] // CTESTNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 832] // CTESTZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 751] // CTESTNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 706] // CTESTC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 778] // CTESTNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 805] // CTESTO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 767] // CTESTNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 731] // CTESTLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 758] // CTESTNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 722] // CTESTL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 713] // CTESTF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 821] // CTESTT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 785] // CTESTNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 812] // CTESTS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 740] // CTESTNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 695] // CTESTBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 794] // CTESTNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 830] // CTESTZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 749] // CTESTNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 704] // CTESTC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 776] // CTESTNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 803] // CTESTO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1082] // IDIV Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1079] // IDIV Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 886] // DIV Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 883] // DIV Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1110] // IMUL Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1105] // IMUL Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1484] // MUL Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1481] // MUL Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1506] // NEG Bb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1503] // NEG Bb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1500] // NEG Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1497] // NEG Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1585] // NOT Bb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1582] // NOT Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 766] // CTESTNLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 730] // CTESTLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 757] // CTESTNL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 721] // CTESTL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 712] // CTESTF Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 820] // CTESTT Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 784] // CTESTNS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 811] // CTESTS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 739] // CTESTNBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 694] // CTESTBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 793] // CTESTNZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 829] // CTESTZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 748] // CTESTNC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 703] // CTESTC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 775] // CTESTNO Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 802] // CTESTO Eb,Ib,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 765] // CTESTNLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 729] // CTESTLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 756] // CTESTNL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 720] // CTESTL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 711] // CTESTF Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 819] // CTESTT Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 783] // CTESTNS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 810] // CTESTS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 738] // CTESTNBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 693] // CTESTBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 792] // CTESTNZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 828] // CTESTZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 747] // CTESTNC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 702] // CTESTC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 774] // CTESTNO Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 801] // CTESTO Eb,Ib,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1351] // LZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1349] // LZCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f5_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1350] // LZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1348] // LZCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f5_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2634] // TZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2632] // TZCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2633] // TZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2631] // TZCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f4_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1170] // INVPCID Gy,Mdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1172] // INVVPID Gy,Mdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 687] // CRC32 Gy,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 686] // CRC32 Gy,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f1_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1165] // INVEPT Gy,Mdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 685] // CRC32 Gy,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_f0_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_f0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 109] // AESDEC256KL Vdq,M512 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 119] // AESENC256KL Vdq,M512 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 107] // AESDEC128KL Vdq,M384 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2378] // SHA256MSG2 Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dd_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_dd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 117] // AESENC128KL Vdq,M384 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2376] // SHA256MSG1 Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_dc_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_dc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 903] // ENCODEKEY256 Gd,Rd +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2380] // SHA256RNDS2 Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_db_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_db_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 901] // ENCODEKEY128 Gd,Rd +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2370] // SHA1MSG2 Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_da_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_da_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2368] // SHA1MSG1 Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d9_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 114] // AESDECWIDE256KL M512 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 124] // AESENCWIDE256KL M512 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 112] // AESDECWIDE128KL M384 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 122] // AESENCWIDE128KL M384 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2372] // SHA1NEXTE Vdq,Wdq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d8_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp_02_modrmreg, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2374] // SHA1RNDS4 Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d4_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2278] // SAR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2269] // SAR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2260] // SAR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2251] // SAR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2235] // SAL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2226] // SAL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2217] // SAL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2208] // SAL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2479] // SHR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2470] // SHR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2461] // SHR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2452] // SHR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2417] // SHL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2408] // SHL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2399] // SHL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2390] // SHL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2075] // RCR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2066] // RCR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2057] // RCR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2048] // RCR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2031] // RCL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2022] // RCL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2013] // RCL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2004] // RCL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2182] // ROR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2173] // ROR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2164] // ROR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2155] // ROR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2140] // ROL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2131] // ROL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2122] // ROL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2113] // ROL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2277] // SAR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2268] // SAR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2259] // SAR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2250] // SAR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2234] // SAL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2225] // SAL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2216] // SAL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2207] // SAL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2478] // SHR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2469] // SHR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2460] // SHR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2451] // SHR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2416] // SHL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2407] // SHL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2398] // SHL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2389] // SHL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2074] // RCR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2065] // RCR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2056] // RCR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2047] // RCR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2030] // RCL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2021] // RCL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2012] // RCL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2003] // RCL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2181] // ROR Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2172] // ROR Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2163] // ROR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2154] // ROR Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2139] // ROL Bv,Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2130] // ROL Bv,Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2121] // ROL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2112] // ROL Ev,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2276] // SAR Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2267] // SAR Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2258] // SAR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2249] // SAR Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2233] // SAL Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2224] // SAL Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2215] // SAL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2206] // SAL Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2477] // SHR Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2468] // SHR Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2459] // SHR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2450] // SHR Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2415] // SHL Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2406] // SHL Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2397] // SHL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2388] // SHL Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2073] // RCR Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2064] // RCR Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2055] // RCR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2046] // RCR Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2029] // RCL Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2020] // RCL Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2011] // RCL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2002] // RCL Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2180] // ROR Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2171] // ROR Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2162] // ROR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2153] // ROR Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2138] // ROL Bb,Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2129] // ROL Bb,Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2120] // ROL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2111] // ROL Eb,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2275] // SAR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2266] // SAR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2257] // SAR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2248] // SAR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2232] // SAL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2223] // SAL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2214] // SAL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2205] // SAL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2476] // SHR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2467] // SHR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2458] // SHR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2449] // SHR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2414] // SHL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2405] // SHL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2396] // SHL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2387] // SHL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2072] // RCR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2063] // RCR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2054] // RCR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2045] // RCR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2028] // RCL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2019] // RCL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2010] // RCL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2001] // RCL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2179] // ROR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2170] // ROR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2161] // ROR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2152] // ROR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2137] // ROL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2128] // ROL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2119] // ROL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2110] // ROL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2274] // SAR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2265] // SAR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2256] // SAR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2247] // SAR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2231] // SAL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2222] // SAL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2213] // SAL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2204] // SAL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2475] // SHR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2466] // SHR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2457] // SHR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2448] // SHR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2413] // SHL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2404] // SHL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2395] // SHL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2386] // SHL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2071] // RCR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2062] // RCR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2053] // RCR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2044] // RCR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2027] // RCL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2018] // RCL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2009] // RCL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2000] // RCL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2178] // ROR Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2169] // ROR Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2160] // ROR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2151] // ROR Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2136] // ROL Bv,Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2127] // ROL Bv,Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2118] // ROL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2109] // ROL Ev,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2273] // SAR Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2264] // SAR Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2255] // SAR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2246] // SAR Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2230] // SAL Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2221] // SAL Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2212] // SAL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2203] // SAL Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2474] // SHR Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2465] // SHR Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2456] // SHR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2447] // SHR Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2412] // SHL Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2403] // SHL Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2394] // SHL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2385] // SHL Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2070] // RCR Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2061] // RCR Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2052] // RCR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2043] // RCR Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2026] // RCL Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2017] // RCL Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2008] // RCL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1999] // RCL Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2177] // ROR Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2168] // ROR Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2159] // ROR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2150] // ROR Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2135] // ROL Bb,Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2126] // ROL Bb,Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2117] // ROL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2108] // ROL Eb,1 +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_d0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2272] // SAR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2263] // SAR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2254] // SAR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2245] // SAR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2229] // SAL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2220] // SAL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2211] // SAL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2202] // SAL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2473] // SHR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2464] // SHR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2455] // SHR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2446] // SHR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2411] // SHL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2402] // SHL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2393] // SHL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2384] // SHL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2069] // RCR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2060] // RCR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2051] // RCR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2042] // RCR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2025] // RCL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2016] // RCL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2007] // RCL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1998] // RCL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2176] // ROR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2167] // ROR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2158] // ROR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2149] // ROR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2134] // ROL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2125] // ROL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2116] // ROL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2107] // ROL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2271] // SAR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2262] // SAR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2253] // SAR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2244] // SAR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2228] // SAL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2219] // SAL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2210] // SAL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2201] // SAL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2472] // SHR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2463] // SHR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2454] // SHR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2445] // SHR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2410] // SHL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2401] // SHL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2392] // SHL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2383] // SHL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2068] // RCR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2059] // RCR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2050] // RCR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2041] // RCR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2024] // RCL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2015] // RCL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2006] // RCL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1997] // RCL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2175] // ROR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2166] // ROR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2157] // ROR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2148] // ROR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2133] // ROL Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2124] // ROL Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2115] // ROL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2106] // ROL Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2270] // SAR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2261] // SAR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2252] // SAR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2243] // SAR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2227] // SAL Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2218] // SAL Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2209] // SAL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2200] // SAL Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2471] // SHR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2462] // SHR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2453] // SHR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2444] // SHR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2409] // SHL Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2400] // SHL Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2391] // SHL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2382] // SHL Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2067] // RCR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2058] // RCR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2049] // RCR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2040] // RCR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2023] // RCL Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2014] // RCL Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2005] // RCL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1996] // RCL Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2174] // ROR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2165] // ROR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2156] // ROR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2147] // ROR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2132] // ROL Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2123] // ROL Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2114] // ROL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2105] // ROL Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_c0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1116] // IMUL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1114] // IMUL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1109] // IMUL Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1104] // IMUL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_af_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1115] // IMUL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1113] // IMUL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1108] // IMUL Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1103] // IMUL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_af_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_af_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2501] // SHRD Bv,Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2497] // SHRD Bv,Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2493] // SHRD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2489] // SHRD Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2499] // SHRD Bv,Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2495] // SHRD Bv,Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2491] // SHRD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2487] // SHRD Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_ad_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_ad_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2439] // SHLD Bv,Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2435] // SHLD Bv,Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2431] // SHLD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2427] // SHLD Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2437] // SHLD Bv,Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2433] // SHLD Bv,Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2429] // SHLD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2425] // SHLD Ev,Gv,CL +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_a5_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_a5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1840] // POP2P Bv,Rv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd_01_nf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1839] // POP2 Bv,Rv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_00_nd, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w_01_nd, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_8f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1846] // POPCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1844] // POPCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1845] // POPCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1843] // POPCNT Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_88_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_88_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 764] // CTESTNLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 728] // CTESTLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 755] // CTESTNL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 719] // CTESTL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 710] // CTESTF Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 818] // CTESTT Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 782] // CTESTNS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 809] // CTESTS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 737] // CTESTNBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 692] // CTESTBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 791] // CTESTNZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 827] // CTESTZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 746] // CTESTNC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 701] // CTESTC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 773] // CTESTNO Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 800] // CTESTO Ev,Gv,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_85_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 763] // CTESTNLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 727] // CTESTLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 754] // CTESTNL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 718] // CTESTL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 709] // CTESTF Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 817] // CTESTT Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 781] // CTESTNS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 808] // CTESTS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 736] // CTESTNBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 691] // CTESTBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 790] // CTESTNZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 826] // CTESTZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 745] // CTESTNC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 700] // CTESTC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 772] // CTESTNO Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 799] // CTESTO Ev,Gv,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_85_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_85_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 762] // CTESTNLE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 726] // CTESTLE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 753] // CTESTNL Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 717] // CTESTL Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 708] // CTESTF Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 816] // CTESTT Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 780] // CTESTNS Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 807] // CTESTS Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 735] // CTESTNBE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 690] // CTESTBE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 789] // CTESTNZ Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 825] // CTESTZ Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 744] // CTESTNC Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 699] // CTESTC Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 771] // CTESTNO Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 798] // CTESTO Eb,Gb,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_84_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_84_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 351] // CCMPNLE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 307] // CCMPLE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 340] // CCMPNL Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 296] // CCMPL Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 285] // CCMPF Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 417] // CCMPT Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 373] // CCMPNS Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 406] // CCMPS Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 318] // CCMPNBE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 263] // CCMPBE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 384] // CCMPNZ Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 428] // CCMPZ Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 329] // CCMPNC Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 274] // CCMPC Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 362] // CCMPNO Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 395] // CCMPO Ev,Ib,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4046] // XOR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4035] // XOR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4024] // XOR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4013] // XOR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2582] // SUB Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2571] // SUB Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2560] // SUB Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2549] // SUB Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 171] // AND Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 160] // AND Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 149] // AND Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 138] // AND Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2309] // SBB Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2298] // SBB Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 29] // ADC Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 18] // ADC Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1633] // OR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1622] // OR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1611] // OR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1600] // OR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 86] // ADD Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 75] // ADD Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 64] // ADD Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 53] // ADD Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 350] // CCMPNLE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 306] // CCMPLE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 339] // CCMPNL Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 295] // CCMPL Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 284] // CCMPF Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 416] // CCMPT Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 372] // CCMPNS Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 405] // CCMPS Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 317] // CCMPNBE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 262] // CCMPBE Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 383] // CCMPNZ Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 427] // CCMPZ Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 328] // CCMPNC Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 273] // CCMPC Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 361] // CCMPNO Ev,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 394] // CCMPO Ev,Ib,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4045] // XOR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4034] // XOR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4023] // XOR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4012] // XOR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2581] // SUB Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2570] // SUB Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2559] // SUB Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2548] // SUB Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 170] // AND Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 159] // AND Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 148] // AND Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 137] // AND Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2308] // SBB Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2297] // SBB Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 28] // ADC Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 17] // ADC Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1632] // OR Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1621] // OR Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1610] // OR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1599] // OR Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 85] // ADD Bv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 74] // ADD Bv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 63] // ADD Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 52] // ADD Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_83_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 349] // CCMPNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 305] // CCMPLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 338] // CCMPNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 294] // CCMPL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 283] // CCMPF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 415] // CCMPT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 371] // CCMPNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 404] // CCMPS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 316] // CCMPNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 261] // CCMPBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 382] // CCMPNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 426] // CCMPZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 327] // CCMPNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 272] // CCMPC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 360] // CCMPNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 393] // CCMPO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4044] // XOR Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4033] // XOR Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4022] // XOR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4011] // XOR Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2580] // SUB Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2569] // SUB Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2558] // SUB Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2547] // SUB Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 169] // AND Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 158] // AND Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 147] // AND Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 136] // AND Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2307] // SBB Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2296] // SBB Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 27] // ADC Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 16] // ADC Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1631] // OR Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1620] // OR Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1609] // OR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1598] // OR Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 84] // ADD Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 73] // ADD Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 62] // ADD Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 51] // ADD Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg_07_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 348] // CCMPNLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 304] // CCMPLE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 337] // CCMPNL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 293] // CCMPL Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 282] // CCMPF Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 414] // CCMPT Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 370] // CCMPNS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 403] // CCMPS Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 315] // CCMPNBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 260] // CCMPBE Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 381] // CCMPNZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 425] // CCMPZ Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 326] // CCMPNC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 271] // CCMPC Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 359] // CCMPNO Ev,Iz,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 392] // CCMPO Ev,Iz,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4043] // XOR Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4032] // XOR Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4021] // XOR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4010] // XOR Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2579] // SUB Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2568] // SUB Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2557] // SUB Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2546] // SUB Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 168] // AND Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 157] // AND Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 146] // AND Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 135] // AND Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2306] // SBB Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2295] // SBB Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 26] // ADC Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 15] // ADC Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1630] // OR Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1619] // OR Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1608] // OR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1597] // OR Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 83] // ADD Bv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 72] // ADD Bv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 61] // ADD Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 50] // ADD Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_81_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 347] // CCMPNLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 303] // CCMPLE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 336] // CCMPNL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 292] // CCMPL Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 281] // CCMPF Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 413] // CCMPT Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 369] // CCMPNS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 402] // CCMPS Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 314] // CCMPNBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 259] // CCMPBE Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 380] // CCMPNZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 424] // CCMPZ Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 325] // CCMPNC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 270] // CCMPC Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 358] // CCMPNO Eb,Ib,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 391] // CCMPO Eb,Ib,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4042] // XOR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4031] // XOR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4020] // XOR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4009] // XOR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2578] // SUB Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2567] // SUB Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2556] // SUB Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2545] // SUB Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 167] // AND Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 156] // AND Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 145] // AND Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 134] // AND Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2305] // SBB Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2294] // SBB Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 25] // ADC Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 14] // ADC Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1629] // OR Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1618] // OR Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1607] // OR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1596] // OR Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 82] // ADD Bb,Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 71] // ADD Bb,Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 60] // ADD Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 49] // ADD Eb,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_03_l, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_04_l, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_05_l, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_06_l, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg_07_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_80_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1102] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1098] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1094] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1090] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_6b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1101] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1097] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1093] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1089] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_6b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1100] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1096] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1092] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1088] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_69_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1099] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1095] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1091] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1087] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_69_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_69_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 104] // ADOX By,Gy,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 103] // ADOX Gy,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 41] // ADCX By,Gy,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 40] // ADCX Gy,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3980] // WRSSQ My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3978] // WRSSD My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_00_nd, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w_01_nd, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_66_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp_02_l, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3984] // WRUSSQ My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3982] // WRUSSD My,Gy +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_00_nd, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w_01_nd, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_65_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1410] // MOVBE Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_61_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1409] // MOVBE Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_61_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_61_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1408] // MOVBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_60_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1407] // MOVBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_60_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_60_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2347] // SETNLE Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 494] // CFCMOVNLE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 597] // CMOVNLE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 491] // CFCMOVNLE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 492] // CFCMOVNLE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 490] // CFCMOVNLE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 493] // CFCMOVNLE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 596] // CMOVNLE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 488] // CFCMOVNLE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 489] // CFCMOVNLE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 487] // CFCMOVNLE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4f_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2339] // SETLE Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 462] // CFCMOVLE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 585] // CMOVLE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 459] // CFCMOVLE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 460] // CFCMOVLE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 458] // CFCMOVLE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 461] // CFCMOVLE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 584] // CMOVLE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 456] // CFCMOVLE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 457] // CFCMOVLE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 455] // CFCMOVLE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4e_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2345] // SETNL Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 486] // CFCMOVNL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 594] // CMOVNL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 483] // CFCMOVNL Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 484] // CFCMOVNL Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 482] // CFCMOVNL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 485] // CFCMOVNL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 593] // CMOVNL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 480] // CFCMOVNL Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 481] // CFCMOVNL Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 479] // CFCMOVNL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4d_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2337] // SETL Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 454] // CFCMOVL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 582] // CMOVL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 451] // CFCMOVL Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 452] // CFCMOVL Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 450] // CFCMOVL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 453] // CFCMOVL Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 581] // CMOVL Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 448] // CFCMOVL Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 449] // CFCMOVL Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 447] // CFCMOVL Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4c_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2351] // SETNP Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 510] // CFCMOVNP Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 603] // CMOVNP Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 507] // CFCMOVNP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 508] // CFCMOVNP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 506] // CFCMOVNP Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 509] // CFCMOVNP Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 602] // CMOVNP Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 504] // CFCMOVNP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 505] // CFCMOVNP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 503] // CFCMOVNP Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2359] // SETP Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 542] // CFCMOVP Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 615] // CMOVP Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 539] // CFCMOVP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 540] // CFCMOVP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 538] // CFCMOVP Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 541] // CFCMOVP Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 614] // CMOVP Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 536] // CFCMOVP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 537] // CFCMOVP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 535] // CFCMOVP Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_4a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2353] // SETNS Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 518] // CFCMOVNS Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 606] // CMOVNS Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 515] // CFCMOVNS Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 516] // CFCMOVNS Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 514] // CFCMOVNS Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 517] // CFCMOVNS Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 605] // CMOVNS Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 512] // CFCMOVNS Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 513] // CFCMOVNS Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 511] // CFCMOVNS Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_49_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_49_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2361] // SETS Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 550] // CFCMOVS Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 618] // CMOVS Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 547] // CFCMOVS Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 548] // CFCMOVS Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 546] // CFCMOVS Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 549] // CFCMOVS Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 617] // CMOVS Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 544] // CFCMOVS Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 545] // CFCMOVS Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 543] // CFCMOVS Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_48_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_48_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2341] // SETNBE Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 470] // CFCMOVNBE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 588] // CMOVNBE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 467] // CFCMOVNBE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 468] // CFCMOVNBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 466] // CFCMOVNBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 469] // CFCMOVNBE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 587] // CMOVNBE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 464] // CFCMOVNBE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 465] // CFCMOVNBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 463] // CFCMOVNBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_47_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_47_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2333] // SETBE Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 438] // CFCMOVBE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 576] // CMOVBE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 435] // CFCMOVBE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 436] // CFCMOVBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 434] // CFCMOVBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 437] // CFCMOVBE Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 575] // CMOVBE Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 432] // CFCMOVBE Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 433] // CFCMOVBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 431] // CFCMOVBE Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_46_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_46_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2355] // SETNZ Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 526] // CFCMOVNZ Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 609] // CMOVNZ Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 523] // CFCMOVNZ Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 524] // CFCMOVNZ Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 522] // CFCMOVNZ Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 525] // CFCMOVNZ Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 608] // CMOVNZ Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 520] // CFCMOVNZ Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 521] // CFCMOVNZ Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 519] // CFCMOVNZ Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_45_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_45_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2364] // SETZ Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 558] // CFCMOVZ Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 621] // CMOVZ Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 555] // CFCMOVZ Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 556] // CFCMOVZ Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 554] // CFCMOVZ Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 557] // CFCMOVZ Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 620] // CMOVZ Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 552] // CFCMOVZ Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 553] // CFCMOVZ Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 551] // CFCMOVZ Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_44_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_44_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2343] // SETNC Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 478] // CFCMOVNC Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 591] // CMOVNC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 475] // CFCMOVNC Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 476] // CFCMOVNC Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 474] // CFCMOVNC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 477] // CFCMOVNC Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 590] // CMOVNC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 472] // CFCMOVNC Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 473] // CFCMOVNC Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 471] // CFCMOVNC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_43_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_43_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2335] // SETC Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 446] // CFCMOVC Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 579] // CMOVC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 443] // CFCMOVC Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 444] // CFCMOVC Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 442] // CFCMOVC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 445] // CFCMOVC Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 578] // CMOVC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 440] // CFCMOVC Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 441] // CFCMOVC Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 439] // CFCMOVC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_42_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2349] // SETNO Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 502] // CFCMOVNO Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 600] // CMOVNO Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 499] // CFCMOVNO Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 500] // CFCMOVNO Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 498] // CFCMOVNO Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 501] // CFCMOVNO Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 599] // CMOVNO Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 496] // CFCMOVNO Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 497] // CFCMOVNO Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 495] // CFCMOVNO Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_41_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_41_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2357] // SETO Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 534] // CFCMOVO Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 612] // CMOVO Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 531] // CFCMOVO Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 532] // CFCMOVO Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 530] // CFCMOVO Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 533] // CFCMOVO Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 611] // CMOVO Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 528] // CFCMOVO Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 529] // CFCMOVO Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 527] // CFCMOVO Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf_01_modrmmod, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_40_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_40_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 346] // CCMPNLE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 302] // CCMPLE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 335] // CCMPNL Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 291] // CCMPL Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 280] // CCMPF Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 412] // CCMPT Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 368] // CCMPNS Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 401] // CCMPS Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 313] // CCMPNBE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 258] // CCMPBE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 379] // CCMPNZ Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 423] // CCMPZ Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 324] // CCMPNC Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 269] // CCMPC Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 357] // CCMPNO Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 390] // CCMPO Gv,Ev,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 345] // CCMPNLE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 301] // CCMPLE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 334] // CCMPNL Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 290] // CCMPL Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 279] // CCMPF Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 411] // CCMPT Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 367] // CCMPNS Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 400] // CCMPS Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 312] // CCMPNBE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 257] // CCMPBE Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 378] // CCMPNZ Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 422] // CCMPZ Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 323] // CCMPNC Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 268] // CCMPC Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 356] // CCMPNO Gv,Ev,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 389] // CCMPO Gv,Ev,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 344] // CCMPNLE Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 300] // CCMPLE Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 333] // CCMPNL Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 289] // CCMPL Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 278] // CCMPF Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 410] // CCMPT Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 366] // CCMPNS Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 399] // CCMPS Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 311] // CCMPNBE Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 256] // CCMPBE Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 377] // CCMPNZ Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 421] // CCMPZ Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 322] // CCMPNC Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 267] // CCMPC Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 355] // CCMPNO Gb,Eb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 388] // CCMPO Gb,Eb,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_3a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_3a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 343] // CCMPNLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 299] // CCMPLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 332] // CCMPNL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 288] // CCMPL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 277] // CCMPF Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 409] // CCMPT Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 365] // CCMPNS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 398] // CCMPS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 310] // CCMPNBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 255] // CCMPBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 376] // CCMPNZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 420] // CCMPZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 321] // CCMPNC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 266] // CCMPC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 354] // CCMPNO Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 387] // CCMPO Ev,Gv,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_39_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 342] // CCMPNLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 298] // CCMPLE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 331] // CCMPNL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 287] // CCMPL Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 276] // CCMPF Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 408] // CCMPT Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 364] // CCMPNS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 397] // CCMPS Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 309] // CCMPNBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 254] // CCMPBE Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 375] // CCMPNZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 419] // CCMPZ Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 320] // CCMPNC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 265] // CCMPC Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 353] // CCMPNO Ev,Gv,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 386] // CCMPO Ev,Gv,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_39_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_39_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 341] // CCMPNLE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 297] // CCMPLE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 330] // CCMPNL Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 286] // CCMPL Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 275] // CCMPF Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 407] // CCMPT Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 363] // CCMPNS Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 396] // CCMPS Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 308] // CCMPNBE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 253] // CCMPBE Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 374] // CCMPNZ Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 418] // CCMPZ Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 319] // CCMPNC Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 264] // CCMPC Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 352] // CCMPNO Eb,Gb,dfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 385] // CCMPO Eb,Gb,dfv +}; + +const ND_TABLE_EX_SC gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc = +{ + ND_ILUT_EX_SC, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_03_leaf, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_04_leaf, + /* 05 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_05_leaf, + /* 06 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_06_leaf, + /* 07 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_07_leaf, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_08_leaf, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_09_leaf, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0a_leaf, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0b_leaf, + /* 0c */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0c_leaf, + /* 0d */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0d_leaf, + /* 0e */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0e_leaf, + /* 0f */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc_0f_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd_00_sc, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_38_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_38_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4041] // XOR Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4030] // XOR Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4019] // XOR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4008] // XOR Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4040] // XOR Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4029] // XOR Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4018] // XOR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4007] // XOR Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_33_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_33_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4039] // XOR Bb,Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4028] // XOR Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4017] // XOR Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4006] // XOR Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_32_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_32_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4038] // XOR Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4027] // XOR Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4016] // XOR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4005] // XOR Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4037] // XOR Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4026] // XOR Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4015] // XOR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4004] // XOR Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_31_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_31_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4036] // XOR Bb,Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4025] // XOR Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4014] // XOR Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4003] // XOR Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_30_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_30_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2500] // SHRD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2496] // SHRD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2492] // SHRD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2488] // SHRD Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2498] // SHRD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2494] // SHRD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2490] // SHRD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2486] // SHRD Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2c_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2577] // SUB Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2566] // SUB Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2555] // SUB Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2544] // SUB Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2576] // SUB Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2565] // SUB Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2554] // SUB Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2543] // SUB Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2575] // SUB Bb,Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2564] // SUB Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2553] // SUB Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2542] // SUB Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_2a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2574] // SUB Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2563] // SUB Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2552] // SUB Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2541] // SUB Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2573] // SUB Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2562] // SUB Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2551] // SUB Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2540] // SUB Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_29_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_29_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2572] // SUB Bb,Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2561] // SUB Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2550] // SUB Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2539] // SUB Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_28_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_28_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2438] // SHLD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2434] // SHLD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2430] // SHLD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2426] // SHLD Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2436] // SHLD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2432] // SHLD Bv,Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2428] // SHLD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2424] // SHLD Ev,Gv,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_24_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_24_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 166] // AND Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 155] // AND Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 144] // AND Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 133] // AND Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_23_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 165] // AND Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 154] // AND Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 143] // AND Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 132] // AND Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_23_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_23_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 164] // AND Bb,Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 153] // AND Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 142] // AND Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 131] // AND Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_22_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_22_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 163] // AND Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 152] // AND Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 141] // AND Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 130] // AND Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_21_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 162] // AND Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 151] // AND Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 140] // AND Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 129] // AND Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_21_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_21_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 161] // AND Bb,Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 150] // AND Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 139] // AND Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 128] // AND Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_20_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_20_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2304] // SBB Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2293] // SBB Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2303] // SBB Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2292] // SBB Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2302] // SBB Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2291] // SBB Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_1a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_1a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2301] // SBB Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2290] // SBB Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2300] // SBB Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2289] // SBB Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_19_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_19_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2299] // SBB Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2288] // SBB Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_18_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 24] // ADC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 13] // ADC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_13_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 23] // ADC Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 12] // ADC Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_13_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 22] // ADC Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 11] // ADC Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_12_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_12_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 21] // ADC Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 10] // ADC Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_11_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 20] // ADC Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 9] // ADC Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_11_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_11_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 19] // ADC Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 8] // ADC Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_10_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_10_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1628] // OR Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1617] // OR Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1606] // OR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1595] // OR Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1627] // OR Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1616] // OR Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1605] // OR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1594] // OR Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0b_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1626] // OR Bb,Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1615] // OR Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1604] // OR Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1593] // OR Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_0a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_0a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1625] // OR Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1614] // OR Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1603] // OR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1592] // OR Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1624] // OR Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1613] // OR Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1602] // OR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1591] // OR Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_09_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_09_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1623] // OR Bb,Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1612] // OR Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1601] // OR Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1590] // OR Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_08_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_08_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 81] // ADD Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 70] // ADD Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 59] // ADD Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 48] // ADD Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_03_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 80] // ADD Bv,Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 69] // ADD Bv,Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 58] // ADD Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 47] // ADD Gv,Ev +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_03_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_03_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 79] // ADD Bb,Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 68] // ADD Bb,Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 57] // ADD Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 46] // ADD Gb,Eb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_02_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_02_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 78] // ADD Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 67] // ADD Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 56] // ADD Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 45] // ADD Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_01_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 77] // ADD Bv,Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 66] // ADD Bv,Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 55] // ADD Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 44] // ADD Ev,Gv +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_01_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_01_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 76] // ADD Bb,Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 65] // ADD Bb,Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 54] // ADD Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 43] // ADD Eb,Gb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_04_opcode_00_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_04_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_04_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_04_opcode_00_pp, + /* 01 */ (const void *)&gEvexMap_mmmmm_04_opcode_01_pp, + /* 02 */ (const void *)&gEvexMap_mmmmm_04_opcode_02_pp, + /* 03 */ (const void *)&gEvexMap_mmmmm_04_opcode_03_pp, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gEvexMap_mmmmm_04_opcode_08_pp, + /* 09 */ (const void *)&gEvexMap_mmmmm_04_opcode_09_pp, + /* 0a */ (const void *)&gEvexMap_mmmmm_04_opcode_0a_pp, + /* 0b */ (const void *)&gEvexMap_mmmmm_04_opcode_0b_pp, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gEvexMap_mmmmm_04_opcode_10_pp, + /* 11 */ (const void *)&gEvexMap_mmmmm_04_opcode_11_pp, + /* 12 */ (const void *)&gEvexMap_mmmmm_04_opcode_12_pp, + /* 13 */ (const void *)&gEvexMap_mmmmm_04_opcode_13_pp, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)&gEvexMap_mmmmm_04_opcode_18_pp, + /* 19 */ (const void *)&gEvexMap_mmmmm_04_opcode_19_pp, + /* 1a */ (const void *)&gEvexMap_mmmmm_04_opcode_1a_pp, + /* 1b */ (const void *)&gEvexMap_mmmmm_04_opcode_1b_pp, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gEvexMap_mmmmm_04_opcode_20_pp, + /* 21 */ (const void *)&gEvexMap_mmmmm_04_opcode_21_pp, + /* 22 */ (const void *)&gEvexMap_mmmmm_04_opcode_22_pp, + /* 23 */ (const void *)&gEvexMap_mmmmm_04_opcode_23_pp, + /* 24 */ (const void *)&gEvexMap_mmmmm_04_opcode_24_pp, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gEvexMap_mmmmm_04_opcode_28_pp, + /* 29 */ (const void *)&gEvexMap_mmmmm_04_opcode_29_pp, + /* 2a */ (const void *)&gEvexMap_mmmmm_04_opcode_2a_pp, + /* 2b */ (const void *)&gEvexMap_mmmmm_04_opcode_2b_pp, + /* 2c */ (const void *)&gEvexMap_mmmmm_04_opcode_2c_pp, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)&gEvexMap_mmmmm_04_opcode_30_pp, + /* 31 */ (const void *)&gEvexMap_mmmmm_04_opcode_31_pp, + /* 32 */ (const void *)&gEvexMap_mmmmm_04_opcode_32_pp, + /* 33 */ (const void *)&gEvexMap_mmmmm_04_opcode_33_pp, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)&gEvexMap_mmmmm_04_opcode_38_pp, + /* 39 */ (const void *)&gEvexMap_mmmmm_04_opcode_39_pp, + /* 3a */ (const void *)&gEvexMap_mmmmm_04_opcode_3a_pp, + /* 3b */ (const void *)&gEvexMap_mmmmm_04_opcode_3b_pp, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)&gEvexMap_mmmmm_04_opcode_40_pp, + /* 41 */ (const void *)&gEvexMap_mmmmm_04_opcode_41_pp, + /* 42 */ (const void *)&gEvexMap_mmmmm_04_opcode_42_pp, + /* 43 */ (const void *)&gEvexMap_mmmmm_04_opcode_43_pp, + /* 44 */ (const void *)&gEvexMap_mmmmm_04_opcode_44_pp, + /* 45 */ (const void *)&gEvexMap_mmmmm_04_opcode_45_pp, + /* 46 */ (const void *)&gEvexMap_mmmmm_04_opcode_46_pp, + /* 47 */ (const void *)&gEvexMap_mmmmm_04_opcode_47_pp, + /* 48 */ (const void *)&gEvexMap_mmmmm_04_opcode_48_pp, + /* 49 */ (const void *)&gEvexMap_mmmmm_04_opcode_49_pp, + /* 4a */ (const void *)&gEvexMap_mmmmm_04_opcode_4a_pp, + /* 4b */ (const void *)&gEvexMap_mmmmm_04_opcode_4b_pp, + /* 4c */ (const void *)&gEvexMap_mmmmm_04_opcode_4c_pp, + /* 4d */ (const void *)&gEvexMap_mmmmm_04_opcode_4d_pp, + /* 4e */ (const void *)&gEvexMap_mmmmm_04_opcode_4e_pp, + /* 4f */ (const void *)&gEvexMap_mmmmm_04_opcode_4f_pp, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)&gEvexMap_mmmmm_04_opcode_60_pp, + /* 61 */ (const void *)&gEvexMap_mmmmm_04_opcode_61_pp, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)&gEvexMap_mmmmm_04_opcode_65_pp, + /* 66 */ (const void *)&gEvexMap_mmmmm_04_opcode_66_pp, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)&gEvexMap_mmmmm_04_opcode_69_pp, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)&gEvexMap_mmmmm_04_opcode_6b_pp, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)&gEvexMap_mmmmm_04_opcode_80_pp, + /* 81 */ (const void *)&gEvexMap_mmmmm_04_opcode_81_pp, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)&gEvexMap_mmmmm_04_opcode_83_pp, + /* 84 */ (const void *)&gEvexMap_mmmmm_04_opcode_84_pp, + /* 85 */ (const void *)&gEvexMap_mmmmm_04_opcode_85_pp, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)&gEvexMap_mmmmm_04_opcode_88_pp, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)&gEvexMap_mmmmm_04_opcode_8f_pp, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)&gEvexMap_mmmmm_04_opcode_a5_pp, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)&gEvexMap_mmmmm_04_opcode_ad_pp, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)&gEvexMap_mmmmm_04_opcode_af_pp, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)&gEvexMap_mmmmm_04_opcode_c0_pp, + /* c1 */ (const void *)&gEvexMap_mmmmm_04_opcode_c1_pp, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)&gEvexMap_mmmmm_04_opcode_d0_pp, + /* d1 */ (const void *)&gEvexMap_mmmmm_04_opcode_d1_pp, + /* d2 */ (const void *)&gEvexMap_mmmmm_04_opcode_d2_pp, + /* d3 */ (const void *)&gEvexMap_mmmmm_04_opcode_d3_pp, + /* d4 */ (const void *)&gEvexMap_mmmmm_04_opcode_d4_pp, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)&gEvexMap_mmmmm_04_opcode_d8_pp, + /* d9 */ (const void *)&gEvexMap_mmmmm_04_opcode_d9_pp, + /* da */ (const void *)&gEvexMap_mmmmm_04_opcode_da_pp, + /* db */ (const void *)&gEvexMap_mmmmm_04_opcode_db_pp, + /* dc */ (const void *)&gEvexMap_mmmmm_04_opcode_dc_pp, + /* dd */ (const void *)&gEvexMap_mmmmm_04_opcode_dd_pp, + /* de */ (const void *)&gEvexMap_mmmmm_04_opcode_de_pp, + /* df */ (const void *)&gEvexMap_mmmmm_04_opcode_df_pp, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)&gEvexMap_mmmmm_04_opcode_f0_pp, + /* f1 */ (const void *)&gEvexMap_mmmmm_04_opcode_f1_pp, + /* f2 */ (const void *)&gEvexMap_mmmmm_04_opcode_f2_pp, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)&gEvexMap_mmmmm_04_opcode_f4_pp, + /* f5 */ (const void *)&gEvexMap_mmmmm_04_opcode_f5_pp, + /* f6 */ (const void *)&gEvexMap_mmmmm_04_opcode_f6_pp, + /* f7 */ (const void *)&gEvexMap_mmmmm_04_opcode_f7_pp, + /* f8 */ (const void *)&gEvexMap_mmmmm_04_opcode_f8_pp, + /* f9 */ (const void *)&gEvexMap_mmmmm_04_opcode_f9_pp, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)&gEvexMap_mmmmm_04_opcode_fc_pp, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)&gEvexMap_mmmmm_04_opcode_fe_pp, + /* ff */ (const void *)&gEvexMap_mmmmm_04_opcode_ff_pp, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2189] // RORX Gy,Ey,Ib +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_ND gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd = +{ + ND_ILUT_EX_ND, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_f0_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l_00_nd, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_f0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3114] // VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_cf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_cf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3116] // VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_ce_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_ce_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2724] // VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2719] // VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_c2_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_c2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3734] // VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3733] // VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_73_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_73_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3738] // VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_72_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_72_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3725] // VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3724] // VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_71_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_71_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3729] // VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_70_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_70_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3079] // VFPCLASSSD rKq{K},aKq,Wsd,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3081] // VFPCLASSSS rKq{K},aKq,Wss,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3080] // VFPCLASSSH rKq{K},aKq,Wsh,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_67_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_67_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3076] // VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3078] // VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3077] // VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_66_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_66_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3868] // VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3870] // VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3869] // VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_57_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_57_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3865] // VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3867] // VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3866] // VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_56_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_56_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2880] // VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2881] // VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_55_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_55_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2878] // VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2879] // VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_54_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_54_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3851] // VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3852] // VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_51_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3849] // VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3850] // VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_50_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_50_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_44_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3373] // VPCLMULQDQ Vfv,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_44_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_44_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3917] // VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3916] // VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_43_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_43_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2840] // VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_42_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3404] // VPCMPW rKq{K},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3377] // VPCMPB rKq{K},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3403] // VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3400] // VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2869] // VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2867] // VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_3b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3133] // VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3131] // VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_3a_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_3a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2868] // VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2866] // VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_39_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_39_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3132] // VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3130] // VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_38_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_38_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3111] // VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3113] // VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3112] // VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_27_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_27_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3108] // VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3110] // VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3109] // VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_26_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_26_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3820] // VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3819] // VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_25_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_25_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3915] // VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3914] // VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_23_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_23_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3537] // VPINSRQ Vdq,Hdq,Eq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3535] // VPINSRD Vdq,Hdq,Ed,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_22_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_22_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3135] // VINSERTPS Vdq,Hdq,Udq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3134] // VINSERTPS Vdq,Hdq,Md,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_21_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3532] // VPINSRB Vdq,Hdq,Rd,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3531] // VPINSRB Vdq,Hdq,Mb,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_20_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3399] // VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3378] // VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3402] // VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3401] // VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2772] // VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2864] // VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2862] // VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_1b_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3128] // VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3126] // VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_1a_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_1a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2863] // VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2861] // VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_19_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_19_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3127] // VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3125] // VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_18_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2871] // VEXTRACTPS Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2870] // VEXTRACTPS Md,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3492] // VPEXTRQ Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3488] // VPEXTRD Ry,Vdq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3491] // VPEXTRQ Mq,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3487] // VPEXTRD Md,Vdq,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3497] // VPEXTRW Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3496] // VPEXTRW Mw,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3484] // VPEXTRB Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3483] // VPEXTRB Mb,Vdq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3340] // VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0f_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3874] // VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3876] // VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3875] // VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_0a_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_0a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3871] // VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_09_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_09_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3873] // VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3872] // VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_08_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_08_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3455] // VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_05_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_05_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3459] // VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_04_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_04_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2684] // VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2683] // VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_03_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_03_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3464] // VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_01_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_01_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3470] // VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_03_opcode_00_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_03_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_03_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_03_opcode_00_pp, + /* 01 */ (const void *)&gEvexMap_mmmmm_03_opcode_01_pp, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode_03_pp, + /* 04 */ (const void *)&gEvexMap_mmmmm_03_opcode_04_pp, + /* 05 */ (const void *)&gEvexMap_mmmmm_03_opcode_05_pp, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gEvexMap_mmmmm_03_opcode_08_pp, + /* 09 */ (const void *)&gEvexMap_mmmmm_03_opcode_09_pp, + /* 0a */ (const void *)&gEvexMap_mmmmm_03_opcode_0a_pp, + /* 0b */ (const void *)&gEvexMap_mmmmm_03_opcode_0b_pp, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)&gEvexMap_mmmmm_03_opcode_0f_pp, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)&gEvexMap_mmmmm_03_opcode_14_pp, + /* 15 */ (const void *)&gEvexMap_mmmmm_03_opcode_15_pp, + /* 16 */ (const void *)&gEvexMap_mmmmm_03_opcode_16_pp, + /* 17 */ (const void *)&gEvexMap_mmmmm_03_opcode_17_pp, + /* 18 */ (const void *)&gEvexMap_mmmmm_03_opcode_18_pp, + /* 19 */ (const void *)&gEvexMap_mmmmm_03_opcode_19_pp, + /* 1a */ (const void *)&gEvexMap_mmmmm_03_opcode_1a_pp, + /* 1b */ (const void *)&gEvexMap_mmmmm_03_opcode_1b_pp, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)&gEvexMap_mmmmm_03_opcode_1d_pp, + /* 1e */ (const void *)&gEvexMap_mmmmm_03_opcode_1e_pp, + /* 1f */ (const void *)&gEvexMap_mmmmm_03_opcode_1f_pp, + /* 20 */ (const void *)&gEvexMap_mmmmm_03_opcode_20_pp, + /* 21 */ (const void *)&gEvexMap_mmmmm_03_opcode_21_pp, + /* 22 */ (const void *)&gEvexMap_mmmmm_03_opcode_22_pp, + /* 23 */ (const void *)&gEvexMap_mmmmm_03_opcode_23_pp, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)&gEvexMap_mmmmm_03_opcode_25_pp, + /* 26 */ (const void *)&gEvexMap_mmmmm_03_opcode_26_pp, + /* 27 */ (const void *)&gEvexMap_mmmmm_03_opcode_27_pp, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)&gEvexMap_mmmmm_03_opcode_38_pp, + /* 39 */ (const void *)&gEvexMap_mmmmm_03_opcode_39_pp, + /* 3a */ (const void *)&gEvexMap_mmmmm_03_opcode_3a_pp, + /* 3b */ (const void *)&gEvexMap_mmmmm_03_opcode_3b_pp, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)&gEvexMap_mmmmm_03_opcode_3e_pp, + /* 3f */ (const void *)&gEvexMap_mmmmm_03_opcode_3f_pp, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)&gEvexMap_mmmmm_03_opcode_42_pp, + /* 43 */ (const void *)&gEvexMap_mmmmm_03_opcode_43_pp, + /* 44 */ (const void *)&gEvexMap_mmmmm_03_opcode_44_pp, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)&gEvexMap_mmmmm_03_opcode_50_pp, + /* 51 */ (const void *)&gEvexMap_mmmmm_03_opcode_51_pp, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)&gEvexMap_mmmmm_03_opcode_54_pp, + /* 55 */ (const void *)&gEvexMap_mmmmm_03_opcode_55_pp, + /* 56 */ (const void *)&gEvexMap_mmmmm_03_opcode_56_pp, + /* 57 */ (const void *)&gEvexMap_mmmmm_03_opcode_57_pp, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)&gEvexMap_mmmmm_03_opcode_66_pp, + /* 67 */ (const void *)&gEvexMap_mmmmm_03_opcode_67_pp, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)&gEvexMap_mmmmm_03_opcode_70_pp, + /* 71 */ (const void *)&gEvexMap_mmmmm_03_opcode_71_pp, + /* 72 */ (const void *)&gEvexMap_mmmmm_03_opcode_72_pp, + /* 73 */ (const void *)&gEvexMap_mmmmm_03_opcode_73_pp, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)&gEvexMap_mmmmm_03_opcode_c2_pp, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)&gEvexMap_mmmmm_03_opcode_ce_pp, + /* cf */ (const void *)&gEvexMap_mmmmm_03_opcode_cf_pp, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)&gEvexMap_mmmmm_03_opcode_f0_pp, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2504] // SHRX Gy,Ey,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2285] // SARX Gy,Ey,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2442] // SHLX Gy,Ey,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 195] // BEXTR Gy,Ey,By +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 194] // BEXTR Gy,Ey,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f7_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1493] // MULX Gy,By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f6_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1720] // PDEP Gy,By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1722] // PEXT Gy,By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 246] // BZHI Gy,Ey,By +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 245] // BZHI Gy,Ey,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f5_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 209] // BLSI By,Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 208] // BLSI By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 213] // BLSMSK By,Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 212] // BLSMSK By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 216] // BLSR By,Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 215] // BLSR By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 183] // ANDN Gy,By,Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 182] // ANDN Gy,By,Ey +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_f2_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 645] // CMPNLEXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ef_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 637] // CMPLEXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ee_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 647] // CMPNLXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ed_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 639] // CMPLXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ec_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 651] // CMPNPXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_eb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 661] // CMPPXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ea_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 653] // CMPNSXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 673] // CMPSXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 641] // CMPNBEXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 633] // CMPBEXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 655] // CMPNZXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 679] // CMPZXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 643] // CMPNCXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 635] // CMPCXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 649] // CMPNOXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 657] // CMPOXADD My,Gy,By +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_nf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_e0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_df_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2675] // VAESDECLAST Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_df_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_de_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2673] // VAESDEC Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_de_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2679] // VAESENCLAST Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_dd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2677] // VAESENC Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_dc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_dc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3118] // VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3887] // VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3888] // VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cd_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3885] // VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3886] // VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_cc_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3859] // VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3860] // VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_cb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_cb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3857] // VRCP28PD Voq{K}{z},aKq,Woq|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3858] // VRCP28PS Voq{K}{z},aKq,Woq|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_ca_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ca_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2856] // VEXP2PD Voq{K}{z},aKq,Woq|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2857] // VEXP2PS Voq{K}{z},aKq,Woq|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c8_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3907] // VSCATTERPF1QPD Mvm64n{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3908] // VSCATTERPF1QPS Mvm64n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3903] // VSCATTERPF0QPD Mvm64n{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3904] // VSCATTERPF0QPS Mvm64n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3096] // VGATHERPF1QPD Mvm64n{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3097] // VGATHERPF1QPS Mvm64n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3092] // VGATHERPF0QPD Mvm64n{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3093] // VGATHERPF0QPS Mvm64n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3905] // VSCATTERPF1DPD Mvm32h{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3906] // VSCATTERPF1DPS Mvm32n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3901] // VSCATTERPF0DPD Mvm32h{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3902] // VSCATTERPF0DPS Mvm32n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3094] // VGATHERPF1DPD Mvm32h{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3095] // VGATHERPF1DPS Mvm32n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3090] // VGATHERPF0DPD Mvm32h{K},aKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3091] // VGATHERPF0DPS Mvm32n{K},aKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3418] // VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3417] // VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_c4_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_c4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3063] // VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3066] // VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3058] // VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3061] // VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_be_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_be_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3025] // VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3028] // VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bd_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3020] // VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3023] // VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bc_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2966] // VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2969] // VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_bb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_bb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2961] // VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2964] // VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ba_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ba_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2907] // VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2910] // VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2902] // VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2905] // VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2981] // VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2984] // VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2932] // VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2935] // VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3557] // VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b5_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3559] // VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_b4_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_b4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3053] // VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3056] // VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_af_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_af_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3048] // VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3051] // VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ae_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ae_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3015] // VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3018] // VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ad_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ad_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3010] // VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3013] // VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ac_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ac_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2660] // V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2956] // VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2959] // VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_ab_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_ab_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2659] // V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2951] // VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2954] // VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_aa_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_aa_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2897] // VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2900] // VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2892] // VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2895] // VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2976] // VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2979] // VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2927] // VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2930] // VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3909] // VSCATTERQPD Mvm64n{K},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3910] // VSCATTERQPS Mvm64n{K},aKq,Vhv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3899] // VSCATTERDPD Mvm32h{K},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3900] // VSCATTERDPS Mvm32n{K},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3710] // VPSCATTERQQ Mvm64n{K},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3709] // VPSCATTERQD Mvm64n{K},aKq,Vhv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3708] // VPSCATTERDQ Mvm32h{K},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3707] // VPSCATTERDD Mvm32n{K},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_a0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3043] // VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3046] // VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3038] // VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3041] // VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3005] // VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3008] // VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3000] // VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3003] // VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2658] // V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2946] // VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2949] // VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2657] // V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2941] // VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2944] // VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_9a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_9a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2887] // VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2890] // VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_99_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_99_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2882] // VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2885] // VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_98_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_98_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2971] // VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2974] // VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_97_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_97_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2922] // VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2925] // VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_96_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_96_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3098] // VGATHERQPD Vfv{K},aKq,Mvm64n +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3100] // VGATHERQPS Vhv{K},aKq,Mvm64n +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_93_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3086] // VGATHERDPD Vfv{K},aKq,Mvm32h +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3088] // VGATHERDPS Vfv{K},aKq,Mvm32n +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_92_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3507] // VPGATHERQQ Vfv{K},aKq,Mvm64n +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3505] // VPGATHERQD Vhv{K},aKq,Mvm64n +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_91_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3503] // VPGATHERDQ Vfv{K},aKq,Mvm32h +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3501] // VPGATHERDD Vfv{K},aKq,Mvm32n +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_90_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3741] // VPSHUFBITQMB rK{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3478] // VPERMW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3441] // VPERMB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3409] // VPCOMPRESSQ Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3408] // VPCOMPRESSD Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2732] // VCOMPRESSPD Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2733] // VCOMPRESSPS Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_8a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_8a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3481] // VPEXPANDQ Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3480] // VPEXPANDD Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_89_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_89_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2858] // VEXPANDPD Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2859] // VEXPANDPS Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_88_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_88_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3673] // VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_83_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_83_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3474] // VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3475] // VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3476] // VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3473] // VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3477] // VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3472] // VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3368] // VPBROADCASTQ Vfv{K}{z},aKq,Rq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3363] // VPBROADCASTD Vfv{K}{z},aKq,Rd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod_01_wi, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3371] // VPBROADCASTW Vfv{K}{z},aKq,Rw +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod_01_w, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3360] // VPBROADCASTB Vfv{K}{z},aKq,Rb +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod_01_w, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_7a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3370] // VPBROADCASTW Vfv{K}{z},aKq,Ww +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_79_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_79_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3359] // VPBROADCASTB Vfv{K}{z},aKq,Wb +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_78_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_78_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3446] // VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3447] // VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_77_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_77_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3448] // VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3445] // VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_76_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_76_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3449] // VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3444] // VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_75_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_75_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3736] // VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3735] // VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_73_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_73_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2740] // VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2745] // VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3737] // VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_72_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_72_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3727] // VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3726] // VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_71_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_71_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3728] // VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_70_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_70_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3306] // VP2INTERSECTQ rKq+1,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3305] // VP2INTERSECTD rKq+1,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_68_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_68_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3356] // VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3353] // VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_66_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_66_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2695] // VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2696] // VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_65_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_65_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3355] // VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3354] // VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_64_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_64_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3410] // VPCOMPRESSW Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3407] // VPCOMPRESSB Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_63_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_63_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3482] // VPEXPANDW Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3479] // VPEXPANDB Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_62_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_62_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2712] // VBROADCASTI64X4 Voq{K}{z},aKq,Mqq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2710] // VBROADCASTI32X8 Voq{K}{z},aKq,Mqq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2711] // VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2709] // VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_5a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3367] // VPBROADCASTQ Vfv{K}{z},aKq,Wq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2708] // VBROADCASTI32X2 Vfv{K}{z},aKq,Wq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_59_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_59_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3362] // VPBROADCASTD Vfv{K}{z},aKq,Wd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_58_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_58_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3678] // VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3677] // VPOPCNTD Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_55_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_55_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3679] // VPOPCNTW Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3676] // VPOPCNTB Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_54_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_54_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3308] // VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3431] // VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_53_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_53_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3307] // VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2851] // VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3429] // VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_52_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_52_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3425] // VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_51_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3423] // VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_50_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_50_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3883] // VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3884] // VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3881] // VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3882] // VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3855] // VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3856] // VRCP14SS Vdq{K}{z},aKq,Hdq,Wss +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3853] // VRCP14PD Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3854] // VRCP14PS Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2621] // TILELOADD rTt,Mt +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm_04_l, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_modrmrm, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2626] // TILESTORED Mt,rTt +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm_04_l, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_modrmrm, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2623] // TILELOADDT1 rTt,Mt +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_RM gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm_04_l, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_modrmrm, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_4b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2536] // STTILECFG Moq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1315] // LDTILECFG Moq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_49_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_00_modrmreg, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3763] // VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3761] // VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_47_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_47_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3778] // VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3776] // VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_46_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_46_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3796] // VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3794] // VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_45_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_45_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3544] // VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3543] // VPLZCNTD Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_44_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_44_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3105] // VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3107] // VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_43_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_43_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3102] // VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3104] // VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_42_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3670] // VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3668] // VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_40_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_40_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3580] // VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3578] // VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3581] // VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3573] // VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3571] // VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3569] // VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3594] // VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3592] // VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3366] // VPBROADCASTMW2D Vfv,mKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3595] // VPMINUW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_3a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3606] // VPMOVQ2M rKq,Ufv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3598] // VPMOVD2M rKq,Ufv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3587] // VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3585] // VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_39_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_39_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3603] // VPMOVM2Q Vfv,mKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3602] // VPMOVM2D Vfv,mKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_38_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3583] // VPMINSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_38_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3393] // VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_37_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_37_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3469] // VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3442] // VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_36_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_36_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3608] // VPMOVQD Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3651] // VPMOVZXDQ Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_35_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_35_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3609] // VPMOVQW Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_34_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_34_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3657] // VPMOVZXWQ Vfv{K}{z},aKq,Wqv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_34_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3600] // VPMOVDW Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_33_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_33_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3654] // VPMOVZXWD Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_33_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3607] // VPMOVQB Wev{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_32_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_32_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3645] // VPMOVZXBQ Vfv{K}{z},aKq,Wev +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_32_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3599] // VPMOVDB Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_31_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_31_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3642] // VPMOVZXBD Vfv{K}{z},aKq,Wqv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_31_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3641] // VPMOVWB Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_30_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_30_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3648] // VPMOVZXBW Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_30_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3896] // VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3898] // VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3893] // VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3895] // VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3320] // VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3365] // VPBROADCASTMB2Q Vfv,mKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3231] // VMOVNTDQA Vfv,Mfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3640] // VPMOVW2M rKq,Ufv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3597] // VPMOVB2M rKq,Ufv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3383] // VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_29_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_29_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3604] // VPMOVM2W Vfv,mKq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3601] // VPMOVM2B Vfv,mKq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3660] // VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_28_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_28_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3828] // VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3827] // VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3824] // VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3823] // VPTESTMD rKq{K},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_27_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_27_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3829] // VPTESTNMW rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3826] // VPTESTNMB rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3825] // VPTESTMW rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3822] // VPTESTMB rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_26_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_26_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3613] // VPMOVSQD Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3625] // VPMOVSXDQ Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_25_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_25_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3614] // VPMOVSQW Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_24_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_24_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3631] // VPMOVSXWQ Vfv{K}{z},aKq,Wqv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_24_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3611] // VPMOVSDW Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_23_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_23_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3628] // VPMOVSXWD Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_23_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3612] // VPMOVSQB Wev{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_22_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_22_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3619] // VPMOVSXBQ Vfv{K}{z},aKq,Wev +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_22_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3610] // VPMOVSDB Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_21_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_21_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3616] // VPMOVSXBD Vfv{K}{z},aKq,Wqv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_21_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3615] // VPMOVSWB Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_20_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_20_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3622] // VPMOVSXBW Vfv{K}{z},aKq,Whv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_20_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_01_leaf, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3313] // VPABSQ Vfv{K}{z},aKq,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3311] // VPABSD Vfv{K}{z},aKq,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3314] // VPABSW Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3309] // VPABSB Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2706] // VBROADCASTF64X4 Voq{K}{z},aKq,Mqq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2704] // VBROADCASTF32X8 Voq{K}{z},aKq,Mqq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2705] // VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2703] // VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_1a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2713] // VBROADCASTSD Vuv{K}{z},aKq,Wsd +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2702] // VBROADCASTF32X2 Vuv{K}{z},aKq,Wq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_19_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_19_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2715] // VBROADCASTSS Vfv{K}{z},aKq,Wss +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_18_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3463] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3467] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3462] // VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3466] // VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_02_opcode_16_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3637] // VPMOVUSQD Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3688] // VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3687] // VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_15_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3638] // VPMOVUSQW Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3692] // VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3691] // VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_14_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3635] // VPMOVUSDW Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2758] // VCVTPH2PS Vfv{K}{z},aKq,Whv{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_13_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3636] // VPMOVUSQB Wev{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3765] // VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_12_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_12_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3634] // VPMOVUSDB Wqv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3779] // VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_11_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_11_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3639] // VPMOVUSWB Whv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3798] // VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_10_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_10_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3454] // VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3458] // VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_02_opcode_0c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3662] // VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_0b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_04_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3561] // VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_04_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_04_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_02_opcode_00_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3739] // VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_02_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_02_opcode_00_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_02_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_02_opcode_00_pp, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_02_opcode_04_pp, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)&gEvexMap_mmmmm_02_opcode_0b_pp, + /* 0c */ (const void *)&gEvexMap_mmmmm_02_opcode_0c_pp, + /* 0d */ (const void *)&gEvexMap_mmmmm_02_opcode_0d_pp, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gEvexMap_mmmmm_02_opcode_10_pp, + /* 11 */ (const void *)&gEvexMap_mmmmm_02_opcode_11_pp, + /* 12 */ (const void *)&gEvexMap_mmmmm_02_opcode_12_pp, + /* 13 */ (const void *)&gEvexMap_mmmmm_02_opcode_13_pp, + /* 14 */ (const void *)&gEvexMap_mmmmm_02_opcode_14_pp, + /* 15 */ (const void *)&gEvexMap_mmmmm_02_opcode_15_pp, + /* 16 */ (const void *)&gEvexMap_mmmmm_02_opcode_16_pp, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)&gEvexMap_mmmmm_02_opcode_18_pp, + /* 19 */ (const void *)&gEvexMap_mmmmm_02_opcode_19_pp, + /* 1a */ (const void *)&gEvexMap_mmmmm_02_opcode_1a_pp, + /* 1b */ (const void *)&gEvexMap_mmmmm_02_opcode_1b_pp, + /* 1c */ (const void *)&gEvexMap_mmmmm_02_opcode_1c_pp, + /* 1d */ (const void *)&gEvexMap_mmmmm_02_opcode_1d_pp, + /* 1e */ (const void *)&gEvexMap_mmmmm_02_opcode_1e_pp, + /* 1f */ (const void *)&gEvexMap_mmmmm_02_opcode_1f_pp, + /* 20 */ (const void *)&gEvexMap_mmmmm_02_opcode_20_pp, + /* 21 */ (const void *)&gEvexMap_mmmmm_02_opcode_21_pp, + /* 22 */ (const void *)&gEvexMap_mmmmm_02_opcode_22_pp, + /* 23 */ (const void *)&gEvexMap_mmmmm_02_opcode_23_pp, + /* 24 */ (const void *)&gEvexMap_mmmmm_02_opcode_24_pp, + /* 25 */ (const void *)&gEvexMap_mmmmm_02_opcode_25_pp, + /* 26 */ (const void *)&gEvexMap_mmmmm_02_opcode_26_pp, + /* 27 */ (const void *)&gEvexMap_mmmmm_02_opcode_27_pp, + /* 28 */ (const void *)&gEvexMap_mmmmm_02_opcode_28_pp, + /* 29 */ (const void *)&gEvexMap_mmmmm_02_opcode_29_pp, + /* 2a */ (const void *)&gEvexMap_mmmmm_02_opcode_2a_pp, + /* 2b */ (const void *)&gEvexMap_mmmmm_02_opcode_2b_pp, + /* 2c */ (const void *)&gEvexMap_mmmmm_02_opcode_2c_pp, + /* 2d */ (const void *)&gEvexMap_mmmmm_02_opcode_2d_pp, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)&gEvexMap_mmmmm_02_opcode_30_pp, + /* 31 */ (const void *)&gEvexMap_mmmmm_02_opcode_31_pp, + /* 32 */ (const void *)&gEvexMap_mmmmm_02_opcode_32_pp, + /* 33 */ (const void *)&gEvexMap_mmmmm_02_opcode_33_pp, + /* 34 */ (const void *)&gEvexMap_mmmmm_02_opcode_34_pp, + /* 35 */ (const void *)&gEvexMap_mmmmm_02_opcode_35_pp, + /* 36 */ (const void *)&gEvexMap_mmmmm_02_opcode_36_pp, + /* 37 */ (const void *)&gEvexMap_mmmmm_02_opcode_37_pp, + /* 38 */ (const void *)&gEvexMap_mmmmm_02_opcode_38_pp, + /* 39 */ (const void *)&gEvexMap_mmmmm_02_opcode_39_pp, + /* 3a */ (const void *)&gEvexMap_mmmmm_02_opcode_3a_pp, + /* 3b */ (const void *)&gEvexMap_mmmmm_02_opcode_3b_pp, + /* 3c */ (const void *)&gEvexMap_mmmmm_02_opcode_3c_pp, + /* 3d */ (const void *)&gEvexMap_mmmmm_02_opcode_3d_pp, + /* 3e */ (const void *)&gEvexMap_mmmmm_02_opcode_3e_pp, + /* 3f */ (const void *)&gEvexMap_mmmmm_02_opcode_3f_pp, + /* 40 */ (const void *)&gEvexMap_mmmmm_02_opcode_40_pp, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)&gEvexMap_mmmmm_02_opcode_42_pp, + /* 43 */ (const void *)&gEvexMap_mmmmm_02_opcode_43_pp, + /* 44 */ (const void *)&gEvexMap_mmmmm_02_opcode_44_pp, + /* 45 */ (const void *)&gEvexMap_mmmmm_02_opcode_45_pp, + /* 46 */ (const void *)&gEvexMap_mmmmm_02_opcode_46_pp, + /* 47 */ (const void *)&gEvexMap_mmmmm_02_opcode_47_pp, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)&gEvexMap_mmmmm_02_opcode_49_pp, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)&gEvexMap_mmmmm_02_opcode_4b_pp, + /* 4c */ (const void *)&gEvexMap_mmmmm_02_opcode_4c_pp, + /* 4d */ (const void *)&gEvexMap_mmmmm_02_opcode_4d_pp, + /* 4e */ (const void *)&gEvexMap_mmmmm_02_opcode_4e_pp, + /* 4f */ (const void *)&gEvexMap_mmmmm_02_opcode_4f_pp, + /* 50 */ (const void *)&gEvexMap_mmmmm_02_opcode_50_pp, + /* 51 */ (const void *)&gEvexMap_mmmmm_02_opcode_51_pp, + /* 52 */ (const void *)&gEvexMap_mmmmm_02_opcode_52_pp, + /* 53 */ (const void *)&gEvexMap_mmmmm_02_opcode_53_pp, + /* 54 */ (const void *)&gEvexMap_mmmmm_02_opcode_54_pp, + /* 55 */ (const void *)&gEvexMap_mmmmm_02_opcode_55_pp, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)&gEvexMap_mmmmm_02_opcode_58_pp, + /* 59 */ (const void *)&gEvexMap_mmmmm_02_opcode_59_pp, + /* 5a */ (const void *)&gEvexMap_mmmmm_02_opcode_5a_pp, + /* 5b */ (const void *)&gEvexMap_mmmmm_02_opcode_5b_pp, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)&gEvexMap_mmmmm_02_opcode_62_pp, + /* 63 */ (const void *)&gEvexMap_mmmmm_02_opcode_63_pp, + /* 64 */ (const void *)&gEvexMap_mmmmm_02_opcode_64_pp, + /* 65 */ (const void *)&gEvexMap_mmmmm_02_opcode_65_pp, + /* 66 */ (const void *)&gEvexMap_mmmmm_02_opcode_66_pp, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)&gEvexMap_mmmmm_02_opcode_68_pp, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)&gEvexMap_mmmmm_02_opcode_70_pp, + /* 71 */ (const void *)&gEvexMap_mmmmm_02_opcode_71_pp, + /* 72 */ (const void *)&gEvexMap_mmmmm_02_opcode_72_pp, + /* 73 */ (const void *)&gEvexMap_mmmmm_02_opcode_73_pp, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)&gEvexMap_mmmmm_02_opcode_75_pp, + /* 76 */ (const void *)&gEvexMap_mmmmm_02_opcode_76_pp, + /* 77 */ (const void *)&gEvexMap_mmmmm_02_opcode_77_pp, + /* 78 */ (const void *)&gEvexMap_mmmmm_02_opcode_78_pp, + /* 79 */ (const void *)&gEvexMap_mmmmm_02_opcode_79_pp, + /* 7a */ (const void *)&gEvexMap_mmmmm_02_opcode_7a_pp, + /* 7b */ (const void *)&gEvexMap_mmmmm_02_opcode_7b_pp, + /* 7c */ (const void *)&gEvexMap_mmmmm_02_opcode_7c_pp, + /* 7d */ (const void *)&gEvexMap_mmmmm_02_opcode_7d_pp, + /* 7e */ (const void *)&gEvexMap_mmmmm_02_opcode_7e_pp, + /* 7f */ (const void *)&gEvexMap_mmmmm_02_opcode_7f_pp, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)&gEvexMap_mmmmm_02_opcode_83_pp, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)&gEvexMap_mmmmm_02_opcode_88_pp, + /* 89 */ (const void *)&gEvexMap_mmmmm_02_opcode_89_pp, + /* 8a */ (const void *)&gEvexMap_mmmmm_02_opcode_8a_pp, + /* 8b */ (const void *)&gEvexMap_mmmmm_02_opcode_8b_pp, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)&gEvexMap_mmmmm_02_opcode_8d_pp, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)&gEvexMap_mmmmm_02_opcode_8f_pp, + /* 90 */ (const void *)&gEvexMap_mmmmm_02_opcode_90_pp, + /* 91 */ (const void *)&gEvexMap_mmmmm_02_opcode_91_pp, + /* 92 */ (const void *)&gEvexMap_mmmmm_02_opcode_92_pp, + /* 93 */ (const void *)&gEvexMap_mmmmm_02_opcode_93_pp, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)&gEvexMap_mmmmm_02_opcode_96_pp, + /* 97 */ (const void *)&gEvexMap_mmmmm_02_opcode_97_pp, + /* 98 */ (const void *)&gEvexMap_mmmmm_02_opcode_98_pp, + /* 99 */ (const void *)&gEvexMap_mmmmm_02_opcode_99_pp, + /* 9a */ (const void *)&gEvexMap_mmmmm_02_opcode_9a_pp, + /* 9b */ (const void *)&gEvexMap_mmmmm_02_opcode_9b_pp, + /* 9c */ (const void *)&gEvexMap_mmmmm_02_opcode_9c_pp, + /* 9d */ (const void *)&gEvexMap_mmmmm_02_opcode_9d_pp, + /* 9e */ (const void *)&gEvexMap_mmmmm_02_opcode_9e_pp, + /* 9f */ (const void *)&gEvexMap_mmmmm_02_opcode_9f_pp, + /* a0 */ (const void *)&gEvexMap_mmmmm_02_opcode_a0_pp, + /* a1 */ (const void *)&gEvexMap_mmmmm_02_opcode_a1_pp, + /* a2 */ (const void *)&gEvexMap_mmmmm_02_opcode_a2_pp, + /* a3 */ (const void *)&gEvexMap_mmmmm_02_opcode_a3_pp, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)&gEvexMap_mmmmm_02_opcode_a6_pp, + /* a7 */ (const void *)&gEvexMap_mmmmm_02_opcode_a7_pp, + /* a8 */ (const void *)&gEvexMap_mmmmm_02_opcode_a8_pp, + /* a9 */ (const void *)&gEvexMap_mmmmm_02_opcode_a9_pp, + /* aa */ (const void *)&gEvexMap_mmmmm_02_opcode_aa_pp, + /* ab */ (const void *)&gEvexMap_mmmmm_02_opcode_ab_pp, + /* ac */ (const void *)&gEvexMap_mmmmm_02_opcode_ac_pp, + /* ad */ (const void *)&gEvexMap_mmmmm_02_opcode_ad_pp, + /* ae */ (const void *)&gEvexMap_mmmmm_02_opcode_ae_pp, + /* af */ (const void *)&gEvexMap_mmmmm_02_opcode_af_pp, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)&gEvexMap_mmmmm_02_opcode_b4_pp, + /* b5 */ (const void *)&gEvexMap_mmmmm_02_opcode_b5_pp, + /* b6 */ (const void *)&gEvexMap_mmmmm_02_opcode_b6_pp, + /* b7 */ (const void *)&gEvexMap_mmmmm_02_opcode_b7_pp, + /* b8 */ (const void *)&gEvexMap_mmmmm_02_opcode_b8_pp, + /* b9 */ (const void *)&gEvexMap_mmmmm_02_opcode_b9_pp, + /* ba */ (const void *)&gEvexMap_mmmmm_02_opcode_ba_pp, + /* bb */ (const void *)&gEvexMap_mmmmm_02_opcode_bb_pp, + /* bc */ (const void *)&gEvexMap_mmmmm_02_opcode_bc_pp, + /* bd */ (const void *)&gEvexMap_mmmmm_02_opcode_bd_pp, + /* be */ (const void *)&gEvexMap_mmmmm_02_opcode_be_pp, + /* bf */ (const void *)&gEvexMap_mmmmm_02_opcode_bf_pp, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)&gEvexMap_mmmmm_02_opcode_c4_pp, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)&gEvexMap_mmmmm_02_opcode_c6_pp, + /* c7 */ (const void *)&gEvexMap_mmmmm_02_opcode_c7_pp, + /* c8 */ (const void *)&gEvexMap_mmmmm_02_opcode_c8_pp, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)&gEvexMap_mmmmm_02_opcode_ca_pp, + /* cb */ (const void *)&gEvexMap_mmmmm_02_opcode_cb_pp, + /* cc */ (const void *)&gEvexMap_mmmmm_02_opcode_cc_pp, + /* cd */ (const void *)&gEvexMap_mmmmm_02_opcode_cd_pp, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)&gEvexMap_mmmmm_02_opcode_cf_pp, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)&gEvexMap_mmmmm_02_opcode_dc_pp, + /* dd */ (const void *)&gEvexMap_mmmmm_02_opcode_dd_pp, + /* de */ (const void *)&gEvexMap_mmmmm_02_opcode_de_pp, + /* df */ (const void *)&gEvexMap_mmmmm_02_opcode_df_pp, + /* e0 */ (const void *)&gEvexMap_mmmmm_02_opcode_e0_pp, + /* e1 */ (const void *)&gEvexMap_mmmmm_02_opcode_e1_pp, + /* e2 */ (const void *)&gEvexMap_mmmmm_02_opcode_e2_pp, + /* e3 */ (const void *)&gEvexMap_mmmmm_02_opcode_e3_pp, + /* e4 */ (const void *)&gEvexMap_mmmmm_02_opcode_e4_pp, + /* e5 */ (const void *)&gEvexMap_mmmmm_02_opcode_e5_pp, + /* e6 */ (const void *)&gEvexMap_mmmmm_02_opcode_e6_pp, + /* e7 */ (const void *)&gEvexMap_mmmmm_02_opcode_e7_pp, + /* e8 */ (const void *)&gEvexMap_mmmmm_02_opcode_e8_pp, + /* e9 */ (const void *)&gEvexMap_mmmmm_02_opcode_e9_pp, + /* ea */ (const void *)&gEvexMap_mmmmm_02_opcode_ea_pp, + /* eb */ (const void *)&gEvexMap_mmmmm_02_opcode_eb_pp, + /* ec */ (const void *)&gEvexMap_mmmmm_02_opcode_ec_pp, + /* ed */ (const void *)&gEvexMap_mmmmm_02_opcode_ed_pp, + /* ee */ (const void *)&gEvexMap_mmmmm_02_opcode_ee_pp, + /* ef */ (const void *)&gEvexMap_mmmmm_02_opcode_ef_pp, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)&gEvexMap_mmmmm_02_opcode_f2_pp, + /* f3 */ (const void *)&gEvexMap_mmmmm_02_opcode_f3_pp, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)&gEvexMap_mmmmm_02_opcode_f5_pp, + /* f6 */ (const void *)&gEvexMap_mmmmm_02_opcode_f6_pp, + /* f7 */ (const void *)&gEvexMap_mmmmm_02_opcode_f7_pp, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3326] // VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fe_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fe_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3338] // VPADDW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3324] // VPADDB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3807] // VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3805] // VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_fa_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_fa_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3817] // VPSUBW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3803] // VPSUBB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3705] // VPSADBW Vfv,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f6_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3563] // VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3674] // VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f4_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3758] // VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f3_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3752] // VPSLLD Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_f2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3767] // VPSLLW Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_f1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_f1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3848] // VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3847] // VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_ef_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ef_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3574] // VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ee_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ee_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3332] // VPADDSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ed_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ed_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3330] // VPADDSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ec_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ec_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3682] // VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3681] // VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_eb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_eb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3588] // VPMINSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_ea_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_ea_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3811] // VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3809] // VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3229] // VMOVNTDQ Mfv,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2747] // VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2779] // VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2734] // VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2804] // VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3666] // VPMULHW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3664] // VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e4_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3350] // VPAVGW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e3_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3775] // VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3771] // VPSRAD Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_e2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3781] // VPSRAW Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3348] // VPAVGB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_e0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_e0_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3346] // VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3345] // VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_df_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_de_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3576] // VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_de_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3336] // VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_dd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3334] // VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_dc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_dc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3347] // VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3343] // VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_db_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_db_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_da_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3590] // VPMINUB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_da_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_da_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3815] // VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3813] // VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3240] // VMOVQ Wq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_d6_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3671] // VPMULLW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3328] // VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d4_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3791] // VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d3_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3785] // VPSRLD Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_d2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3800] // VPSRLW Vfv{K}{z},aKq,Hfv,Wdq +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_d1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_d1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3918] // VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3920] // VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c6_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3495] // VPEXTRW Gy,Udq,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3540] // VPINSRW Vdq,Hdq,Rv,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3539] // VPINSRW Vdq,Hdq,Mw,Ib +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2722] // VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2725] // VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2717] // VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2720] // VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_c2_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_c2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1258] // KMOVQ Gy,mKq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1248] // KMOVD Gy,mKd +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1238] // KMOVB Gy,mKb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1268] // KMOVW Gy,mKw +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_93_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1257] // KMOVQ rKq,Ry +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1247] // KMOVD rKd,Ry +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1237] // KMOVB rKb,Ry +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1267] // KMOVW rKw,Ry +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_92_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1246] // KMOVD Md,rKd +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1236] // KMOVB Mb,rKb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1256] // KMOVQ Mq,rKq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1266] // KMOVW Mw,rKw +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_91_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1245] // KMOVD rKd,mKd +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1235] // KMOVB rKb,mKb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1244] // KMOVD rKd,Md +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1234] // KMOVB rKb,Mb +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1255] // KMOVQ rKq,mKq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1265] // KMOVW rKw,mKw +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1254] // KMOVQ rKq,Mq +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1264] // KMOVW rKw,Mw +}; + +const ND_TABLE_EX_NF gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf = +{ + ND_ILUT_EX_NF, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_nf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_nf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_90_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3200] // VMOVDQU16 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3206] // VMOVDQU8 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3204] // VMOVDQU64 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3202] // VMOVDQU32 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3196] // VMOVDQA64 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3194] // VMOVDQA32 Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3239] // VMOVQ Vdq,Wq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3238] // VMOVQ Ey,Vdq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3183] // VMOVD Ey,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_7e_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_01_l, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp_02_l, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2835] // VCVTUSI2SD Vdq,Hdq{er},Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2834] // VCVTUSI2SD Vdq,Hdq,Ey +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_03_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2837] // VCVTUSI2SS Vss,Hss{er},Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2753] // VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2776] // VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp_03_wi, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2833] // VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2830] // VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2831] // VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2828] // VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2806] // VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2817] // VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_7a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_7a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2787] // VCVTSD2USI Gy,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2803] // VCVTSS2USI Gy,Wss{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2755] // VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2778] // VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2754] // VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2777] // VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_79_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_79_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2822] // VCVTTSD2USI Gy,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2827] // VCVTTSS2USI Gy,Wss{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2808] // VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2819] // VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2807] // VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2818] // VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_78_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_78_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_76_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3381] // VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_76_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_76_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_75_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3385] // VPCMPEQW rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_75_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_75_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_74_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3379] // VPCMPEQB rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_74_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3755] // VPSLLDQ Hfv,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3757] // VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3788] // VPSRLDQ Hfv,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3790] // VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_w, + /* 07 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_73_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3751] // VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3774] // VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3770] // VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3784] // VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3686] // VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3685] // VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3690] // VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3689] // VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_w, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_w, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_w, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_72_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3766] // VPSLLW Hfv{K}{z},aKq,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3780] // VPSRAW Hfv{K}{z},aKq,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3799] // VPSRLW Hfv{K}{z},aKq,Wfv,Ib +}; + +const ND_TABLE_MODRM_REG gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_71_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3746] // VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3744] // VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3742] // VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_70_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_70_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3199] // VMOVDQU16 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3205] // VMOVDQU8 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3203] // VMOVDQU64 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3201] // VMOVDQU32 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3195] // VMOVDQA64 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3193] // VMOVDQA32 Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3237] // VMOVQ Vdq,Eq +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3182] // VMOVD Vdq,Ed +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_6e_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3834] // VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3842] // VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3316] // VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3832] // VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_6a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_6a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_69_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3836] // VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_69_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_69_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_68_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3830] // VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_68_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_68_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_67_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3322] // VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_67_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_67_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3391] // VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_66_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_66_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_65_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3395] // VPCMPGTW rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_65_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_65_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_64_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3389] // VPCMPGTB rKq{K},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_64_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_64_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_63_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3318] // VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_63_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_63_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3840] // VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_62_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_62_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_61_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3844] // VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_61_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_61_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_60_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3838] // VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_60_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_60_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3150] // VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3153] // VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3145] // VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3148] // VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5f_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2846] // VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2849] // VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2841] // VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2844] // VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3165] // VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3168] // VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3160] // VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3163] // VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5d_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3943] // VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3946] // VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3938] // VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3941] // VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5c_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2815] // VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2767] // VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2781] // VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2738] // VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5b_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2785] // VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2798] // VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2750] // VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2769] // VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_5a_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_5a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3293] // VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3296] // VMULSS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3288] // VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3291] // VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_59_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_59_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2666] // VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2669] // VADDSS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2661] // VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2664] // VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_58_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_58_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3963] // VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3965] // VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_57_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_57_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3301] // VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3303] // VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_56_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_56_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2685] // VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2687] // VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_55_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_55_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2689] // VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2691] // VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_54_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_54_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3932] // VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_03_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3935] // VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3927] // VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3930] // VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_51_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2727] // VCOMISD Vdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2730] // VCOMISS Vdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2f_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3950] // VUCOMISD Vdq,Wsd{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3953] // VUCOMISS Vdq,Wss{sae} +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2e_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2783] // VCVTSD2SI Gy,Wsd{er} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2801] // VCVTSS2SI Gy,Wss{er} +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2820] // VCVTTSD2SI Gy,Wsd{sae} +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2825] // VCVTTSS2SI Gy,Wss{sae} +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3233] // VMOVNTPD Mfv,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3235] // VMOVNTPS Mfv,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2793] // VCVTSI2SD Vdq,Hdq{er},Ey +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2792] // VCVTSI2SD Vdq,Hdq,Ey +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_2a_pp_03_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_00_leaf, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2796] // VCVTSI2SS Vdq,Hdq{er},Ey +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_02_leaf, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp_03_wi, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3175] // VMOVAPD Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3179] // VMOVAPS Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_29_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_29_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3174] // VMOVAPD Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3178] // VMOVAPS Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_28_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_28_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3210] // VMOVHPD Mq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3214] // VMOVHPS Mq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3257] // VMOVSHDUP Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3209] // VMOVHPD Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3217] // VMOVLHPS Vdq,Hdq,Udq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3213] // VMOVHPS Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3955] // VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3957] // VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_15_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3959] // VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3961] // VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32 +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_14_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3220] // VMOVLPD Mq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3224] // VMOVLPS Mq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3188] // VMOVDDUP Voq{K}{z},aKq,Woq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3187] // VMOVDDUP Vqq{K}{z},aKq,Wqq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3186] // VMOVDDUP Vdq{K}{z},aKq,Wq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3259] // VMOVSLDUP Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3219] // VMOVLPD Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3207] // VMOVHLPS Vdq,Hdq,Udq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3223] // VMOVLPS Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_12_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_00_modrmmod, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_01_modrmmod, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_02_w, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3248] // VMOVSD Udq{K}{z},aKq,Hdq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3247] // VMOVSD Msd{K},aKq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3264] // VMOVSS Udq{K}{z},aKq,Hdq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3263] // VMOVSS Mss{K},aKq,Vdq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3270] // VMOVUPD Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3274] // VMOVUPS Wfv{K}{z},aKq,Vfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_11_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_11_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3246] // VMOVSD Vdq{K}{z},aKq,Hdq,Udq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3245] // VMOVSD Vdq{K}{z},aKq,Msd +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3262] // VMOVSS Vdq{K}{z},aKq,Hdq,Udq +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3261] // VMOVSS Vdq{K}{z},aKq,Mss +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_w, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3269] // VMOVUPD Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3273] // VMOVUPS Vfv{K}{z},aKq,Wfv +}; + +const ND_TABLE_EX_W gEvexMap_mmmmm_01_opcode_10_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gEvexMap_mmmmm_01_opcode_10_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_00_w, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_01_w, + /* 02 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_02_modrmmod, + /* 03 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp_03_modrmmod, + } +}; + +const ND_TABLE_OPCODE gEvexMap_mmmmm_01_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gEvexMap_mmmmm_01_opcode_10_pp, + /* 11 */ (const void *)&gEvexMap_mmmmm_01_opcode_11_pp, + /* 12 */ (const void *)&gEvexMap_mmmmm_01_opcode_12_pp, + /* 13 */ (const void *)&gEvexMap_mmmmm_01_opcode_13_pp, + /* 14 */ (const void *)&gEvexMap_mmmmm_01_opcode_14_pp, + /* 15 */ (const void *)&gEvexMap_mmmmm_01_opcode_15_pp, + /* 16 */ (const void *)&gEvexMap_mmmmm_01_opcode_16_pp, + /* 17 */ (const void *)&gEvexMap_mmmmm_01_opcode_17_pp, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gEvexMap_mmmmm_01_opcode_28_pp, + /* 29 */ (const void *)&gEvexMap_mmmmm_01_opcode_29_pp, + /* 2a */ (const void *)&gEvexMap_mmmmm_01_opcode_2a_pp, + /* 2b */ (const void *)&gEvexMap_mmmmm_01_opcode_2b_pp, + /* 2c */ (const void *)&gEvexMap_mmmmm_01_opcode_2c_pp, + /* 2d */ (const void *)&gEvexMap_mmmmm_01_opcode_2d_pp, + /* 2e */ (const void *)&gEvexMap_mmmmm_01_opcode_2e_pp, + /* 2f */ (const void *)&gEvexMap_mmmmm_01_opcode_2f_pp, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)&gEvexMap_mmmmm_01_opcode_51_pp, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)&gEvexMap_mmmmm_01_opcode_54_pp, + /* 55 */ (const void *)&gEvexMap_mmmmm_01_opcode_55_pp, + /* 56 */ (const void *)&gEvexMap_mmmmm_01_opcode_56_pp, + /* 57 */ (const void *)&gEvexMap_mmmmm_01_opcode_57_pp, + /* 58 */ (const void *)&gEvexMap_mmmmm_01_opcode_58_pp, + /* 59 */ (const void *)&gEvexMap_mmmmm_01_opcode_59_pp, + /* 5a */ (const void *)&gEvexMap_mmmmm_01_opcode_5a_pp, + /* 5b */ (const void *)&gEvexMap_mmmmm_01_opcode_5b_pp, + /* 5c */ (const void *)&gEvexMap_mmmmm_01_opcode_5c_pp, + /* 5d */ (const void *)&gEvexMap_mmmmm_01_opcode_5d_pp, + /* 5e */ (const void *)&gEvexMap_mmmmm_01_opcode_5e_pp, + /* 5f */ (const void *)&gEvexMap_mmmmm_01_opcode_5f_pp, + /* 60 */ (const void *)&gEvexMap_mmmmm_01_opcode_60_pp, + /* 61 */ (const void *)&gEvexMap_mmmmm_01_opcode_61_pp, + /* 62 */ (const void *)&gEvexMap_mmmmm_01_opcode_62_pp, + /* 63 */ (const void *)&gEvexMap_mmmmm_01_opcode_63_pp, + /* 64 */ (const void *)&gEvexMap_mmmmm_01_opcode_64_pp, + /* 65 */ (const void *)&gEvexMap_mmmmm_01_opcode_65_pp, + /* 66 */ (const void *)&gEvexMap_mmmmm_01_opcode_66_pp, + /* 67 */ (const void *)&gEvexMap_mmmmm_01_opcode_67_pp, + /* 68 */ (const void *)&gEvexMap_mmmmm_01_opcode_68_pp, + /* 69 */ (const void *)&gEvexMap_mmmmm_01_opcode_69_pp, + /* 6a */ (const void *)&gEvexMap_mmmmm_01_opcode_6a_pp, + /* 6b */ (const void *)&gEvexMap_mmmmm_01_opcode_6b_pp, + /* 6c */ (const void *)&gEvexMap_mmmmm_01_opcode_6c_pp, + /* 6d */ (const void *)&gEvexMap_mmmmm_01_opcode_6d_pp, + /* 6e */ (const void *)&gEvexMap_mmmmm_01_opcode_6e_pp, + /* 6f */ (const void *)&gEvexMap_mmmmm_01_opcode_6f_pp, + /* 70 */ (const void *)&gEvexMap_mmmmm_01_opcode_70_pp, + /* 71 */ (const void *)&gEvexMap_mmmmm_01_opcode_71_pp, + /* 72 */ (const void *)&gEvexMap_mmmmm_01_opcode_72_pp, + /* 73 */ (const void *)&gEvexMap_mmmmm_01_opcode_73_pp, + /* 74 */ (const void *)&gEvexMap_mmmmm_01_opcode_74_pp, + /* 75 */ (const void *)&gEvexMap_mmmmm_01_opcode_75_pp, + /* 76 */ (const void *)&gEvexMap_mmmmm_01_opcode_76_pp, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)&gEvexMap_mmmmm_01_opcode_78_pp, + /* 79 */ (const void *)&gEvexMap_mmmmm_01_opcode_79_pp, + /* 7a */ (const void *)&gEvexMap_mmmmm_01_opcode_7a_pp, + /* 7b */ (const void *)&gEvexMap_mmmmm_01_opcode_7b_pp, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)&gEvexMap_mmmmm_01_opcode_7e_pp, + /* 7f */ (const void *)&gEvexMap_mmmmm_01_opcode_7f_pp, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)&gEvexMap_mmmmm_01_opcode_90_pp, + /* 91 */ (const void *)&gEvexMap_mmmmm_01_opcode_91_pp, + /* 92 */ (const void *)&gEvexMap_mmmmm_01_opcode_92_pp, + /* 93 */ (const void *)&gEvexMap_mmmmm_01_opcode_93_pp, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)&gEvexMap_mmmmm_01_opcode_c2_pp, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)&gEvexMap_mmmmm_01_opcode_c4_pp, + /* c5 */ (const void *)&gEvexMap_mmmmm_01_opcode_c5_pp, + /* c6 */ (const void *)&gEvexMap_mmmmm_01_opcode_c6_pp, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)&gEvexMap_mmmmm_01_opcode_d1_pp, + /* d2 */ (const void *)&gEvexMap_mmmmm_01_opcode_d2_pp, + /* d3 */ (const void *)&gEvexMap_mmmmm_01_opcode_d3_pp, + /* d4 */ (const void *)&gEvexMap_mmmmm_01_opcode_d4_pp, + /* d5 */ (const void *)&gEvexMap_mmmmm_01_opcode_d5_pp, + /* d6 */ (const void *)&gEvexMap_mmmmm_01_opcode_d6_pp, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)&gEvexMap_mmmmm_01_opcode_d8_pp, + /* d9 */ (const void *)&gEvexMap_mmmmm_01_opcode_d9_pp, + /* da */ (const void *)&gEvexMap_mmmmm_01_opcode_da_pp, + /* db */ (const void *)&gEvexMap_mmmmm_01_opcode_db_pp, + /* dc */ (const void *)&gEvexMap_mmmmm_01_opcode_dc_pp, + /* dd */ (const void *)&gEvexMap_mmmmm_01_opcode_dd_pp, + /* de */ (const void *)&gEvexMap_mmmmm_01_opcode_de_pp, + /* df */ (const void *)&gEvexMap_mmmmm_01_opcode_df_pp, + /* e0 */ (const void *)&gEvexMap_mmmmm_01_opcode_e0_pp, + /* e1 */ (const void *)&gEvexMap_mmmmm_01_opcode_e1_pp, + /* e2 */ (const void *)&gEvexMap_mmmmm_01_opcode_e2_pp, + /* e3 */ (const void *)&gEvexMap_mmmmm_01_opcode_e3_pp, + /* e4 */ (const void *)&gEvexMap_mmmmm_01_opcode_e4_pp, + /* e5 */ (const void *)&gEvexMap_mmmmm_01_opcode_e5_pp, + /* e6 */ (const void *)&gEvexMap_mmmmm_01_opcode_e6_pp, + /* e7 */ (const void *)&gEvexMap_mmmmm_01_opcode_e7_pp, + /* e8 */ (const void *)&gEvexMap_mmmmm_01_opcode_e8_pp, + /* e9 */ (const void *)&gEvexMap_mmmmm_01_opcode_e9_pp, + /* ea */ (const void *)&gEvexMap_mmmmm_01_opcode_ea_pp, + /* eb */ (const void *)&gEvexMap_mmmmm_01_opcode_eb_pp, + /* ec */ (const void *)&gEvexMap_mmmmm_01_opcode_ec_pp, + /* ed */ (const void *)&gEvexMap_mmmmm_01_opcode_ed_pp, + /* ee */ (const void *)&gEvexMap_mmmmm_01_opcode_ee_pp, + /* ef */ (const void *)&gEvexMap_mmmmm_01_opcode_ef_pp, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)&gEvexMap_mmmmm_01_opcode_f1_pp, + /* f2 */ (const void *)&gEvexMap_mmmmm_01_opcode_f2_pp, + /* f3 */ (const void *)&gEvexMap_mmmmm_01_opcode_f3_pp, + /* f4 */ (const void *)&gEvexMap_mmmmm_01_opcode_f4_pp, + /* f5 */ (const void *)&gEvexMap_mmmmm_01_opcode_f5_pp, + /* f6 */ (const void *)&gEvexMap_mmmmm_01_opcode_f6_pp, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)&gEvexMap_mmmmm_01_opcode_f8_pp, + /* f9 */ (const void *)&gEvexMap_mmmmm_01_opcode_f9_pp, + /* fa */ (const void *)&gEvexMap_mmmmm_01_opcode_fa_pp, + /* fb */ (const void *)&gEvexMap_mmmmm_01_opcode_fb_pp, + /* fc */ (const void *)&gEvexMap_mmmmm_01_opcode_fc_pp, + /* fd */ (const void *)&gEvexMap_mmmmm_01_opcode_fd_pp, + /* fe */ (const void *)&gEvexMap_mmmmm_01_opcode_fe_pp, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_M gEvexMap_mmmmm = +{ + ND_ILUT_EX_M, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gEvexMap_mmmmm_01_opcode, + /* 02 */ (const void *)&gEvexMap_mmmmm_02_opcode, + /* 03 */ (const void *)&gEvexMap_mmmmm_03_opcode, + /* 04 */ (const void *)&gEvexMap_mmmmm_04_opcode, + /* 05 */ (const void *)&gEvexMap_mmmmm_05_opcode, + /* 06 */ (const void *)&gEvexMap_mmmmm_06_opcode, + /* 07 */ (const void *)&gEvexMap_mmmmm_07_opcode, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + } +}; + + +#endif + diff --git a/bddisasm/include/bdx86_table_root.h b/bddisasm/include/bdx86_table_root.h new file mode 100644 index 0000000..79f2bfa --- /dev/null +++ b/bddisasm/include/bdx86_table_root.h @@ -0,0 +1,16820 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + +#ifndef BDX86_TABLE_ROOT_H +#define BDX86_TABLE_ROOT_H + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1975] // PUSH Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1194] // JMPF Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1189] // JMP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 251] // CALLF Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_ff_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 249] // CALL Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 881] // DEC Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ff_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1147] // INC Ev +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_ff_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_ff_modrmreg_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 880] // DEC Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fe_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1146] // INC Eb +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_fe_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_fe_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_fe_modrmreg_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2522] // STD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 561] // CLD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2524] // STI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_fa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 568] // CLI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2521] // STC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 560] // CLC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1086] // IDIV Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 890] // DIV Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1120] // IMUL Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1488] // MUL Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1510] // NEG Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1589] // NOT Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2619] // TEST Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f7_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2618] // TEST Ev,Iz +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_f7_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_f7_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1085] // IDIV Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 889] // DIV Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1119] // IMUL Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1487] // MUL Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1509] // NEG Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1588] // NOT Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2617] // TEST Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f6_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2616] // TEST Eb,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_f6_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_f6_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 574] // CMC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1075] // HLT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_f1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1161] // INT1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ef_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1649] // OUT DX,eAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ee_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1648] // OUT DX,AL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ed_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1125] // IN eAX,DX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ec_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1124] // IN AL,DX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_eb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1188] // JMP Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ea_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1193] // JMPF Ap +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1187] // JMP Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 248] // CALL Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1647] // OUT Ib,eAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1646] // OUT Ib,AL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1123] // IN eAX,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1122] // IN AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1215] // JRCXZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1182] // JECXZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e3_asize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1181] // JCXZ Jb +}; + +const ND_TABLE_ASIZE gLegacyMap_opcode_e3_asize = +{ + ND_ILUT_ASIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_e3_asize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_e3_asize_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_e3_asize_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1339] // LOOP Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1341] // LOOPZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_e0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1340] // LOOPNZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1023] // FRINEAR +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 982] // FISTP Mq,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 940] // FCOMIP ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 925] // FBSTP Mfa,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1055] // FUCOMIP ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 974] // FILD ST(0),Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1041] // FSTSG AX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1033] // FSTDW AX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1018] // FNSTSW AX +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 924] // FBLD ST(0),Mfa +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1039] // FSTP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 981] // FISTP Mw,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1038] // FSTP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 979] // FIST Mw,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1061] // FXCH ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 985] // FISTTP Mw,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 961] // FFREEP ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_df_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 973] // FILD ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_df_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_df_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_df_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_df_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_df_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_df_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_df_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_df_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_df_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_df_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 953] // FDIVP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 971] // FIDIVR ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 958] // FDIVRP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 969] // FIDIV ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1046] // FSUBP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 989] // FISUBR ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1051] // FSUBRP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 987] // FISUB ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 946] // FCOMPP +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 967] // FICOMP ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 945] // FCOMP ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 965] // FICOM ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1007] // FMULP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 976] // FIMUL ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 923] // FADDP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_de_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 963] // FIADD ST(0),Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_de_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_de_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_de_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_de_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_de_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_de_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_de_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_de_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_de_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_de_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1017] // FNSTSW Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1014] // FNSAVE Mfs +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1056] // FUCOMP ST(0),ST(i) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1053] // FUCOM ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1025] // FRSTOR Mfs +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1037] // FSTP ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1036] // FSTP Mfq,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1032] // FST ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1031] // FST Mfq,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1060] // FXCH ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 984] // FISTTP Mq,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 960] // FFREE ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dd_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 993] // FLD ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dd_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_dd_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_dd_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 952] // FDIV ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 956] // FDIVR ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 957] // FDIVR ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 951] // FDIV ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1045] // FSUB ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1049] // FSUBR ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1050] // FSUBR ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1044] // FSUB ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 944] // FCOMP ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 943] // FCOMP ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 938] // FCOM ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 937] // FCOM ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1006] // FMUL ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1005] // FMUL ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 922] // FADD ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_dc_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 921] // FADD ST(0),Mfq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_dc_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_dc_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_dc_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1035] // FSTP Mft,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 939] // FCOMI ST(0),ST(i) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1054] // FUCOMI ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 992] // FLD ST(0),Mft +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1013] // FNOP +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1010] // FNINIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1008] // FNCLEX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1009] // FNDISI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1012] // FNOP +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 933] // FCMOVNU ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 980] // FISTP Md,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 931] // FCMOVNBE ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 978] // FIST Md,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 932] // FCMOVNE ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 983] // FISTTP Md,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 930] // FCMOVNB ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_db_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 972] // FILD ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_db_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_db_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_db_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_db_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_db_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_db_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_db_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_db_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_db_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_db_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 970] // FIDIVR ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 968] // FIDIV ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1057] // FUCOMPP +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 988] // FISUBR ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 986] // FISUB ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 934] // FCMOVU ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 966] // FICOMP ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 928] // FCMOVBE ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 964] // FICOM ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 929] // FCMOVE ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 975] // FIMUL ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 927] // FCMOVB ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_da_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 962] // FIADD ST(0),Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_da_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_da_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_da_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_da_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_da_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_da_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_da_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_da_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_da_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_da_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 947] // FCOS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1027] // FSIN +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1026] // FSCALE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1024] // FRNDINT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1028] // FSINCOS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1029] // FSQRT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1068] // FYL2XP1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1020] // FPREM +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1015] // FNSTCW Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 977] // FINCSTP +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 948] // FDECSTP +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1021] // FPREM1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1066] // FXTRACT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1019] // FPATAN +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1022] // FPTAN +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1067] // FYL2X +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 917] // F2XM1 +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1016] // FNSTENV Mfe +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1002] // FLDZ +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1000] // FLDLN2 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 999] // FLDLG2 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1001] // FLDPI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 997] // FLDL2E +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 998] // FLDL2T +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 994] // FLD1 +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 995] // FLDCW Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1058] // FXAM +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1052] // FTST +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 918] // FABS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 926] // FCHS +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 996] // FLDENV Mfe +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1040] // FSTPNCE ST(i),ST(0) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1034] // FSTP Mfd,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1011] // FNOP +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1030] // FST Mfd,ST(0) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1059] // FXCH ST(0),ST(i) +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 991] // FLD ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d9_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 990] // FLD ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d9_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d9_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_d9_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 955] // FDIVR ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 954] // FDIVR ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 950] // FDIV ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 949] // FDIV ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1048] // FSUBR ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1047] // FSUBR ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1043] // FSUB ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1042] // FSUB ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 942] // FCOMP ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 941] // FCOMP ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 936] // FCOM ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 935] // FCOM ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1004] // FMUL ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1003] // FMUL ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 920] // FADD ST(0),ST(i) +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d8_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 919] // FADD ST(0),Mfd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_d8_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d8_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_d8_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4002] // XLATB +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2242] // SALC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1] // AAD Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4] // AAM Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2284] // SAR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2241] // SAL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2485] // SHR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2423] // SHL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2081] // RCR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2037] // RCL Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2188] // ROR Ev,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d3_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2146] // ROL Ev,CL +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d3_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d3_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2283] // SAR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2240] // SAL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2484] // SHR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2422] // SHL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2080] // RCR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2036] // RCL Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2187] // ROR Eb,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d2_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2145] // ROL Eb,CL +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d2_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d2_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2282] // SAR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2239] // SAL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2483] // SHR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2421] // SHL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2079] // RCR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2035] // RCL Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2186] // ROR Ev,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d1_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2144] // ROL Ev,1 +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d1_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d1_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2281] // SAR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2238] // SAL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2482] // SHR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2420] // SHL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2078] // RCR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2034] // RCL Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2185] // ROR Eb,1 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_d0_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2143] // ROL Eb,1 +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_d0_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_d0_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1175] // IRETQ +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1174] // IRETD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cf_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1176] // IRETW +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_cf_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_cf_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_cf_dsize_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_cf_dsize_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1163] // INTO +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1160] // INT Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1162] // INT3 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2099] // RETF +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ca_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2098] // RETF Iw +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1318] // LEAVE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 911] // ENTER Iw,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3989] // XBEGIN Jz +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c7_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c7_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1396] // MOV Ev,Iz +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_c7_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gLegacyMap_opcode_c7_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3986] // XABORT Ib +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c6_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c6_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1395] // MOV Eb,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_c6_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gLegacyMap_opcode_c6_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c5_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1314] // LDS Gz,Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c5_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c4_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1319] // LES Gz,Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_c4_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c4_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2101] // RETN +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2100] // RETN Iw +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2280] // SAR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2237] // SAL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2481] // SHR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2419] // SHL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2077] // RCR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2033] // RCL Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2184] // ROR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c1_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2142] // ROL Ev,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_c1_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_c1_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2279] // SAR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2236] // SAL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2480] // SHR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2418] // SHL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2076] // RCR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2032] // RCL Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2183] // ROR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_c0_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2141] // ROL Eb,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_c0_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_c0_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1394] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_be_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1393] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1392] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1391] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1390] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ba_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1389] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1388] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1387] // MOV Zv,Iv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1386] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1385] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1384] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1383] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1382] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1381] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1380] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1379] // MOV Zb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2325] // SCASQ RAX,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2324] // SCASQ RAX,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2323] // SCASD EAX,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2322] // SCASD EAX,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2327] // SCASW AX,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2326] // SCASW AX,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_af_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_af_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_af_dsize_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_af_dsize_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_af_dsize_03_auxiliary, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2321] // SCASB AL,Yb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ae_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2320] // SCASB AL,Yb +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ae_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ae_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ae_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1336] // LODSQ RAX,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1335] // LODSQ RAX,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1334] // LODSD EAX,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1333] // LODSD EAX,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1338] // LODSW AX,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ad_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1337] // LODSW AX,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ad_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_ad_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_ad_dsize_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_ad_dsize_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_ad_dsize_03_auxiliary, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1332] // LODSB AL,Xb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ac_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1331] // LODSB AL,Xb +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ac_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ac_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ac_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2531] // STOSQ Yv,RAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2530] // STOSQ Yv,RAX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2529] // STOSD Yv,EAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2528] // STOSD Yv,EAX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2533] // STOSW Yv,AX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2532] // STOSW Yv,AX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_ab_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_ab_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_ab_dsize_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_ab_dsize_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_ab_dsize_03_auxiliary, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2527] // STOSB Yb,AL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_aa_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2526] // STOSB Yb,AL +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_aa_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_aa_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_aa_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2615] // TEST rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2614] // TEST AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 669] // CMPSQ Xv,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 668] // CMPSQ Xv,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 666] // CMPSD Xv,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 665] // CMPSD Xv,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 672] // CMPSW Xv,Yv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a7_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 671] // CMPSW Xv,Yv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a7_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_a7_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_a7_dsize_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_a7_dsize_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_a7_dsize_03_auxiliary, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 664] // CMPSB Xb,Yb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a6_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 663] // CMPSB Xb,Yb +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a6_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a6_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a6_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1466] // MOVSQ Yv,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1465] // MOVSQ Yv,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1460] // MOVSD Yv,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1459] // MOVSD Yv,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1470] // MOVSW Yv,Xv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1469] // MOVSW Yv,Xv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a5_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_a5_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_a5_dsize_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_a5_dsize_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_a5_dsize_03_auxiliary, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1458] // MOVSB Yb,Xb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a4_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1457] // MOVSB Yb,Xb +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a4_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a4_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_a4_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1378] // MOV Ov,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1377] // MOV Ob,AL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_07_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1190] // JMPABS Aq +}; + +const ND_TABLE_EX_W gLegacyMap_opcode_a1_auxiliary_07_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_07_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a1_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1376] // MOV rAX,Ov +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_a1_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gLegacyMap_opcode_a1_auxiliary_07_w, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1375] // MOV AL,Ob +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1309] // LAHF +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2199] // SAHF +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1849] // POPFQ Fv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1848] // POPFD Fv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9d_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1850] // POPFW Fv +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_9d_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_9d_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_9d_dsize_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_9d_dsize_04_leaf, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1983] // PUSHFQ Fv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1982] // PUSHFD Fv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9c_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1984] // PUSHFW Fv +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_9c_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_9c_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_9c_dsize_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_9c_dsize_04_leaf, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3969] // WAIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 250] // CALLF Ap +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 684] // CQO +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 429] // CDQ +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_99_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 856] // CWD +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_99_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_99_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_99_dsize_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_99_dsize_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 430] // CDQE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 857] // CWDE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_98_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 252] // CBW +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_98_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_98_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_98_dsize_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_98_dsize_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3999] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3998] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3997] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3996] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_93_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3995] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_92_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3994] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_91_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3993] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1691] // PAUSE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3992] // XCHG Zv,rAX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_90_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1511] // NOP +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_90_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_90_auxiliary_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_90_auxiliary_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_90_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8f_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1836] // POP Ev +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_8f_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_8f_modrmreg_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1374] // MOV Sw,Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8e_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1373] // MOV Sw,Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8e_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_8e_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_8e_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8d_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1317] // LEA Gv,M0 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8d_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_8d_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1372] // MOV Rv,Sw +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8c_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1371] // MOV Mw,Sw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_8c_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_8c_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_8c_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1370] // MOV Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1369] // MOV Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_89_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1368] // MOV Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_88_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1367] // MOV Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3991] // XCHG Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3990] // XCHG Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2613] // TEST Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_84_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2612] // TEST Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 632] // CMP Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4056] // XOR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2592] // SUB Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 181] // AND Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2319] // SBB Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 39] // ADC Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1643] // OR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_83_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 96] // ADD Ev,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_83_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_83_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_83_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_83_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_83_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_83_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_83_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_83_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_83_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 631] // CMP Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4055] // XOR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2591] // SUB Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 180] // AND Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2318] // SBB Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 38] // ADC Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1642] // OR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_82_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 95] // ADD Eb,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_82_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_82_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_82_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_82_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_82_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_82_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_82_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_82_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_82_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 630] // CMP Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4054] // XOR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2590] // SUB Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 179] // AND Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2317] // SBB Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 37] // ADC Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1641] // OR Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_81_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 94] // ADD Ev,Iz +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_81_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_81_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_81_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_81_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_81_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_81_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_81_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_81_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_81_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 629] // CMP Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4053] // XOR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2589] // SUB Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 178] // AND Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2316] // SBB Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 36] // ADC Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1640] // OR Eb,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_80_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 93] // ADD Eb,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_80_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_80_modrmreg_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_80_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_80_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_80_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_80_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_80_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_80_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_80_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1201] // JNLE Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1185] // JLE Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1199] // JNL Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1183] // JL Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1205] // JNP Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_7a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1213] // JP Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_79_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1207] // JNS Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_78_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1216] // JS Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_77_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1195] // JNBE Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_76_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1177] // JBE Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_75_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1209] // JNZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_74_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1218] // JZ Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_73_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1197] // JNC Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_72_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1179] // JC Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_71_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1203] // JNO Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_70_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1211] // JO Jb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1655] // OUTSW DX,Xz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1654] // OUTSW DX,Xz +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1653] // OUTSD DX,Xz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1652] // OUTSD DX,Xz +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6f_dsize_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_6f_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6f_dsize_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_6f_dsize_01_auxiliary, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1651] // OUTSB DX,Xb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6e_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1650] // OUTSB DX,Xb +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6e_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6e_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6e_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1159] // INSW Yz,DX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1158] // INSW Yz,DX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1153] // INSD Yz,DX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6d_dsize_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1152] // INSD Yz,DX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6d_dsize_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_6d_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6d_dsize_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_6d_dsize_01_auxiliary, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1151] // INSB Yb,DX +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6c_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1150] // INSB Yb,DX +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_6c_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_6c_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_6c_auxiliary_05_leaf, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1118] // IMUL Gv,Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_6a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1974] // PUSH Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_69_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1117] // IMUL Gv,Ev,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_68_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1973] // PUSH Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1473] // MOVSXD Gv,Ez +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_63_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 191] // ARPL Ew,Gw +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_63_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_63_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_63_auxiliary_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_62_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 226] // BOUND Gv,Ma +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_62_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_62_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1842] // POPAD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_61_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1841] // POPA +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_61_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_61_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_61_dsize_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1981] // PUSHAD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_60_dsize_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1980] // PUSHA +}; + +const ND_TABLE_DSIZE gLegacyMap_opcode_60_dsize = +{ + ND_ILUT_DSIZE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_60_dsize_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_60_dsize_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1858] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5f_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1835] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5f_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5f_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5f_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1857] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5e_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1834] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5e_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5e_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5e_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1856] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5d_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1833] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5d_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5d_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5d_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1855] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5c_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1832] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5c_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5c_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5c_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1854] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5b_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1831] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5b_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5b_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5b_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1853] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_5a_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1830] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_5a_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_5a_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_5a_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1852] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_59_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1829] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_59_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_59_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_59_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1851] // POPP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_58_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1828] // POP Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_58_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_58_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_58_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1992] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_57_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1972] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_57_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_57_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_57_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1991] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_56_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1971] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_56_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_56_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_56_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1990] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_55_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1970] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_55_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_55_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_55_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1989] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_54_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1969] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_54_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_54_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_54_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1988] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_53_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1968] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_53_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_53_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_53_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1987] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_52_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1967] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_52_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_52_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_52_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1986] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_51_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1966] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_51_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_51_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_51_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1985] // PUSHP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_50_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1965] // PUSH Zv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_50_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_50_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_50_auxiliary_08_leaf, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 879] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 878] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 877] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 876] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 875] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_4a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 874] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_49_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 873] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_48_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 872] // DEC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_47_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1145] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_46_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1144] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_45_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1143] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_44_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1142] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_43_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1141] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_42_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1140] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_41_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1139] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_40_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1138] // INC Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 7] // AAS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 628] // CMP rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 627] // CMP AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 626] // CMP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_3a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 625] // CMP Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_39_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 624] // CMP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_38_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 623] // CMP Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_37_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 0] // AAA +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_35_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4052] // XOR rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_34_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4051] // XOR AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_33_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4050] // XOR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4049] // XOR Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_31_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4048] // XOR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_30_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4047] // XOR Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 859] // DAS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2588] // SUB rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2587] // SUB AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2586] // SUB Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_2a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2585] // SUB Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_29_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2584] // SUB Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_28_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2583] // SUB Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_27_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 858] // DAA +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_25_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 177] // AND rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_24_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 176] // AND AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_23_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 175] // AND Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_22_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 174] // AND Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_21_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 173] // AND Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_20_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 172] // AND Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1827] // POP DS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1964] // PUSH DS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2315] // SBB rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2314] // SBB AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2313] // SBB Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_1a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2312] // SBB Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_19_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2311] // SBB Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_18_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2310] // SBB Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_17_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1826] // POP SS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_16_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1963] // PUSH SS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_15_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 35] // ADC rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_14_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 34] // ADC AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_13_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 33] // ADC Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_12_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 32] // ADC Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_11_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 31] // ADC Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_10_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 30] // ADC Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ff_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2639] // UD0 Gd,Ed +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1672] // PADDD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1671] // PADDD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fe_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1684] // PADDW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1683] // PADDW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fd_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1670] // PADDB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1669] // PADDB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1933] // PSUBQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1932] // PSUBQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fb_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1931] // PSUBD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1930] // PSUBD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_fa_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1943] // PSUBW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1942] // PSUBW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f9_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1929] // PSUBB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1928] // PSUBB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1353] // MASKMOVDQU Vdq,Udq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1354] // MASKMOVQ Pq,Nq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f7_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1880] // PSADBW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1879] // PSADBW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f6_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1781] // PMADDWD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1780] // PMADDWD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f5_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1824] // PMULUDQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1823] // PMULUDQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f4_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1901] // PSLLQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1900] // PSLLQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f3_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1896] // PSLLD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1895] // PSLLD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f2_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1905] // PSLLW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1904] // PSLLW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f1_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1312] // LDDQU Vx,Mx +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_f0_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1995] // PXOR Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1994] // PXOR Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ef_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1785] // PMAXSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1784] // PMAXSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ee_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1678] // PADDSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1677] // PADDSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ed_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1676] // PADDSB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1675] // PADDSB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ec_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1860] // POR Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1859] // POR Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_eb_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1793] // PMINSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1792] // PMINSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ea_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1937] // PSUBSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1936] // PSUBSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e9_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1935] // PSUBSB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1934] // PSUBSB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1440] // MOVNTDQ Mx,Vx +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1445] // MOVNTQ Mq,Pq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e7_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 836] // CVTPD2DQ Vx,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 834] // CVTDQ2PD Vx,Wq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e6_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 850] // CVTTPD2DQ Vx,Wpd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e6_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1819] // PMULHW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1818] // PMULHW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e5_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1817] // PMULHUW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1816] // PMULHUW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e4_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1696] // PAVGW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1695] // PAVGW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e3_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1910] // PSRAD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1909] // PSRAD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e2_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1914] // PSRAW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1913] // PSRAW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e1_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1693] // PAVGB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1692] // PAVGB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_e0_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1690] // PANDN Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1689] // PANDN Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_df_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1787] // PMAXUB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1786] // PMAXUB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_de_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1682] // PADDUSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1681] // PADDUSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dd_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1680] // PADDUSB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1679] // PADDUSB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_dc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1688] // PAND Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1687] // PAND Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_db_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1795] // PMINUB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1794] // PMINUB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_da_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1941] // PSUBUSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1940] // PSUBUSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d9_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1939] // PSUBUSB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1938] // PSUBUSB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1799] // PMOVMSKB Gy,Ux +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1798] // PMOVMSKB Gy,Nq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d7_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1424] // MOVDQ2Q Pq,Uq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1456] // MOVQ2DQ Vdq,Nq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d6_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1455] // MOVQ Wq,Vq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d6_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1822] // PMULLW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1821] // PMULLW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d5_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1674] // PADDQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1673] // PADDQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d4_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1923] // PSRLQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1922] // PSRLQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d3_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1918] // PSRLD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1917] // PSRLD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d2_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1927] // PSRLW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1926] // PSRLW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d1_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d0_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 102] // ADDSUBPS Vps,Wps +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_d0_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 101] // ADDSUBPD Vpd,Wpd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_d0_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 236] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 235] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 234] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 233] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 232] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ca_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 231] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 230] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 229] // BSWAP Zv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2086] // RDPID Ryf +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2093] // RDSEED Rv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2092] // RDSEED Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3283] // VMPTRST Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2331] // SENDUIPI Rq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3300] // VMXON Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2091] // RDRAND Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3156] // VMCLEAR Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2090] // RDRAND Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3282] // VMPTRLD Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4071] // XSAVES64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4070] // XSAVES M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4067] // XSAVEC64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4066] // XSAVEC M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4063] // XRSTORS64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4062] // XRSTORS M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 677] // CMPXCHG16B Mdq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 678] // CMPXCHG8B Mq +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_c7_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_03_prefix, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_04_prefix, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_05_prefix, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_06_prefix, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg_07_prefix, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2506] // SHUFPD Vpd,Wpd,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2507] // SHUFPS Vps,Wps,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c6_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1731] // PEXTRW Gy,Udq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1730] // PEXTRW Gy,Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c5_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1776] // PINSRW Vdq,Rd,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1777] // PINSRW Vdq,Mw,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1774] // PINSRW Pq,Rd,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1775] // PINSRW Pq,Mw,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c4_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1442] // MOVNTI My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c3_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 667] // CMPSD Vsd,Wsd,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 670] // CMPSS Vss,Wss,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 659] // CMPPD Vpd,Wpd,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c2_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 660] // CMPPS Vps,Wps,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_c2_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3988] // XADD Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_c0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3987] // XADD Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1472] // MOVSX Gv,Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_be_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1471] // MOVSX Gv,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1352] // LZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bd_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 228] // BSR Gv,Ev +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bd_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2635] // TZCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 227] // BSF Gv,Ev +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_bc_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 240] // BTC Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 239] // BTC Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 242] // BTR Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 244] // BTS Ev,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ba_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 238] // BT Ev,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ba_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2640] // UD1 Gd,Ed +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1847] // POPCNT Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1192] // JMPE Jz +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_b8_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1479] // MOVZX Gv,Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1478] // MOVZX Gv,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1323] // LGS Gv,Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b5_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b5_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b4_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1321] // LFS Gv,Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b4_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b4_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 241] // BTR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b2_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1344] // LSS Gv,Mp +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_b2_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_b2_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 676] // CMPXCHG Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 675] // CMPXCHG Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_af_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1121] // IMUL Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2644] // UMWAIT Ry +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2643] // UMONITOR mMb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 569] // CLRSSBSY Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1149] // INCSSPQ Rq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1148] // INCSSPD Rd +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1946] // PTWRITE Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3973] // WRGSBASE Ry +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3972] // WRFSBASE Ry +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2083] // RDGSBASE Ry +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2082] // RDFSBASE Ry +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 566] // CLFLUSHOPT Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2630] // TPAUSE Ry +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 572] // CLWB Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2366] // SFENCE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 565] // CLFLUSH Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1360] // MFENCE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4069] // XSAVEOPT64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4068] // XSAVEOPT M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1320] // LFENCE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4061] // XRSTOR64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4060] // XRSTOR M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4065] // XSAVE64 M? +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4064] // XSAVE M? +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2525] // STMXCSR Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1313] // LDMXCSR Md +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1063] // FXRSTOR64 Mrx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1062] // FXRSTOR Mrx +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1065] // FXSAVE64 Mrx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1064] // FXSAVE Mrx +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_ae_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_00_modrmreg, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_01_modrmreg, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_02_modrmreg, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix_03_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ad_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2503] // SHRD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ac_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2502] // SHRD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_ab_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 243] // BTS Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_aa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2195] // RSM +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a9_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1838] // POP GS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a8_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1977] // PUSH GS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a5_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2441] // SHLD Ev,Gv,CL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2440] // SHLD Ev,Gv,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 237] // BT Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 683] // CPUID +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1837] // POP FS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1976] // PUSH FS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2348] // SETNLE Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2340] // SETLE Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2346] // SETNL Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2338] // SETL Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2352] // SETNP Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2360] // SETP Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_99_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2354] // SETNS Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_98_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2362] // SETS Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2342] // SETNBE Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2334] // SETBE Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2356] // SETNZ Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2365] // SETZ Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_93_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2344] // SETNC Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_92_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2336] // SETC Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_91_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2350] // SETNO Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_90_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2358] // SETO Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1202] // JNLE Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1186] // JLE Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1200] // JNL Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1184] // JL Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1206] // JNP Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1214] // JP Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_89_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1208] // JNS Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_88_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1217] // JS Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1196] // JNBE Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1178] // JBE Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1210] // JNZ Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_84_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1219] // JZ Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_83_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1198] // JNC Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_82_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1180] // JC Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_81_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1204] // JNO Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_80_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1212] // JO Jz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1428] // MOVDQU Wx,Vx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1426] // MOVDQA Wx,Vx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7f_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1454] // MOVQ Qq,Pq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1453] // MOVQ Vdq,Wq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1452] // MOVQ Ey,Vdq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1418] // MOVD Ey,Vdq +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1451] // MOVQ Ey,Pq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1417] // MOVD Ey,Pd +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_01_auxiliary, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1078] // HSUBPS Vps,Wps +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1077] // HSUBPD Vpd,Wpd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1074] // HADDPS Vps,Wps +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_7c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1073] // HADDPD Vpd,Wpd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_7c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1157] // INSERTQ Vdq,Udq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 916] // EXTRQ Vdq,Uq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3298] // VMWRITE Gy,Ey +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_79_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1156] // INSERTQ Vdq,Udq,Ib,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 915] // EXTRQ Uq,Ib,Ib +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3284] // VMREAD Ey,Gy +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_78_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_77_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 897] // EMMS +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_77_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_77_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1704] // PCMPEQD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1703] // PCMPEQD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_76_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1707] // PCMPEQW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1706] // PCMPEQW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_75_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1702] // PCMPEQB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1701] // PCMPEQB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_74_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1897] // PSLLDQ Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1899] // PSLLQ Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1919] // PSRLDQ Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1921] // PSRLQ Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1898] // PSLLQ Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1920] // PSRLQ Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_73_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_00_modrmreg, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1894] // PSLLD Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1908] // PSRAD Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1916] // PSRLD Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1893] // PSLLD Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1907] // PSRAD Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1915] // PSRLD Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_72_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_00_modrmreg, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1903] // PSLLW Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1912] // PSRAW Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1925] // PSRLW Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1902] // PSLLW Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1911] // PSRAW Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1924] // PSRLW Nq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_71_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_00_modrmreg, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1885] // PSHUFLW Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1884] // PSHUFHW Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1883] // PSHUFD Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1886] // PSHUFW Pq,Qq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_70_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1427] // MOVDQU Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1425] // MOVDQA Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6f_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1450] // MOVQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1449] // MOVQ Vdq,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1416] // MOVD Vdq,Ey +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1448] // MOVQ Pq,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1415] // MOVD Pq,Ey +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix_01_auxiliary, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1951] // PUNPCKHQDQ Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6d_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1958] // PUNPCKLQDQ Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6c_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1663] // PACKSSDW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1662] // PACKSSDW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1950] // PUNPCKHDQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1949] // PUNPCKHDQ Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_6a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1953] // PUNPCKHWD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1952] // PUNPCKHWD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_69_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1948] // PUNPCKHBW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1947] // PUNPCKHBW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_68_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1668] // PACKUSWB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1667] // PACKUSWB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_67_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1713] // PCMPGTD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1712] // PCMPGTD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_66_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1716] // PCMPGTW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1715] // PCMPGTW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_65_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1711] // PCMPGTB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1710] // PCMPGTB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_64_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1665] // PACKSSWB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1664] // PACKSSWB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_63_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1957] // PUNPCKLDQ Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1956] // PUNPCKLDQ Pq,Qd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_62_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1960] // PUNPCKLWD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1959] // PUNPCKLWD Pq,Qd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_61_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1955] // PUNPCKLBW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1954] // PUNPCKLBW Pq,Qd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_60_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1357] // MAXSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1358] // MAXSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1355] // MAXPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5f_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1356] // MAXPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 893] // DIVSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 894] // DIVSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 891] // DIVPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5e_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 892] // DIVPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1363] // MINSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1364] // MINSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1361] // MINPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5d_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1362] // MINPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2595] // SUBSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2596] // SUBSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2593] // SUBPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2594] // SUBPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 852] // CVTTPS2DQ Vdq,Wps +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 841] // CVTPS2DQ Vdq,Wps +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5b_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 835] // CVTDQ2PS Vps,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 845] // CVTSD2SS Vss,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 848] // CVTSS2SD Vsd,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 838] // CVTPD2PS Vps,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_5a_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 842] // CVTPS2PD Vpd,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_5a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1491] // MULSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1492] // MULSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1489] // MULPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1490] // MULPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_59_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 99] // ADDSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 100] // ADDSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 97] // ADDPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_58_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 98] // ADDPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_58_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4057] // XORPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4058] // XORPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_57_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1644] // ORPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1645] // ORPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_56_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 185] // ANDNPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_55_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 186] // ANDNPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_55_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 187] // ANDPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_54_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 188] // ANDPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_54_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2039] // RCPSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2038] // RCPPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_53_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2197] // RSQRTSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2196] // RSQRTPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_52_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2518] // SQRTSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2519] // SQRTSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2516] // SQRTPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2517] // SQRTPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_51_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1438] // MOVMSKPD Gy,Upd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1439] // MOVMSKPS Gy,Ups +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_50_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 598] // CMOVNLE Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 586] // CMOVLE Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 595] // CMOVNL Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 583] // CMOVL Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 604] // CMOVNP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_4a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 616] // CMOVP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_49_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 607] // CMOVNS Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_48_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 619] // CMOVS Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_47_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 589] // CMOVNBE Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_46_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 577] // CMOVBE Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_45_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 610] // CMOVNZ Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_44_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 622] // CMOVZ Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_43_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 592] // CMOVNC Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_42_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 580] // CMOVC Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_41_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 601] // CMOVNO Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_40_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 613] // CMOVO Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1076] // HRESET Ib +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix_02_modrmreg, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 127] // AESKEYGENASSIST Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1070] // GF2P8AFFINEINVQB Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1071] // GF2P8AFFINEQB Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2375] // SHA1RNDS4 Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1717] // PCMPISTRI Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1718] // PCMPISTRM Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1708] // PCMPESTRI Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1709] // PCMPESTRM Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1700] // PCLMULQDQ Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1480] // MPSADBW Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 895] // DPPD Vdq,Wdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 896] // DPPS Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1773] // PINSRQ Vdq,Eq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1772] // PINSRD Vdq,Ed,Ib +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix_01_auxiliary, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1155] // INSERTPS Vdq,Udq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1154] // INSERTPS Vdq,Md,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1771] // PINSRB Vdq,Ry,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1770] // PINSRB Vdq,Mb,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 914] // EXTRACTPS Ed,Vdq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1729] // PEXTRQ Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1727] // PEXTRD Ry,Vdq,Ib +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1728] // PEXTRQ Mq,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1726] // PEXTRD Md,Vdq,Ib +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1733] // PEXTRW Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1732] // PEXTRW Mw,Vdq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1725] // PEXTRB Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1724] // PEXTRB Mb,Vdq,Ib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1686] // PALIGNR Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1685] // PALIGNR Pq,Qq,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1698] // PBLENDW Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 203] // BLENDPD Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 204] // BLENDPS Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2193] // ROUNDSD Vsd,Wsd,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2194] // ROUNDSS Vss,Wss,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2191] // ROUNDPD Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2192] // ROUNDPS Vx,Wx,Ib +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_3a_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_08_prefix, + /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_09_prefix, + /* 0a */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0a_prefix, + /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0b_prefix, + /* 0c */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0c_prefix, + /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0d_prefix, + /* 0e */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0e_prefix, + /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_0f_prefix, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_14_prefix, + /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_15_prefix, + /* 16 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_16_prefix, + /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_17_prefix, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_20_prefix, + /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_21_prefix, + /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_22_prefix, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_40_prefix, + /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_41_prefix, + /* 42 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_42_prefix, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_44_prefix, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_60_prefix, + /* 61 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_61_prefix, + /* 62 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_62_prefix, + /* 63 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_63_prefix, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cc_prefix, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_ce_prefix, + /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_cf_prefix, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_df_prefix, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode_f0_prefix, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 190] // AOR My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 193] // AXOR My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 6] // AAND My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3] // AADD My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 904] // ENCODEKEY256 Gd,Rd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 902] // ENCODEKEY128 Gd,Rd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1423] // MOVDIRI My,Gy +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2651] // URDMSR Rq,Gq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 908] // ENQCMD rM?,Moq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2655] // UWRMSR Gq,Rq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 910] // ENQCMDS rM?,Moq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1421] // MOVDIR64B rMoq,Moq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 105] // ADOX Gy,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 42] // ADCX Gy,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3981] // WRSSQ My,Gy +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3979] // WRSSD My,Gy +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3985] // WRUSSQ My,Gy +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3983] // WRUSSD My,Gy +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod_00_auxiliary, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 689] // CRC32 Gy,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1414] // MOVBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1413] // MOVBE Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 688] // CRC32 Gy,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1412] // MOVBE Gv,Mv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1411] // MOVBE Gv,Mv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 110] // AESDEC256KL Vdq,M512 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 111] // AESDECLAST Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 120] // AESENC256KL Vdq,M512 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 106] // AESDEC Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 108] // AESDEC128KL Vdq,M384 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 121] // AESENCLAST Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1330] // LOADIWKEY Vdq,Udq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 118] // AESENC128KL Vdq,M384 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 116] // AESENC Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 126] // AESIMC Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 115] // AESDECWIDE256KL M512 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 125] // AESENCWIDE256KL M512 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 113] // AESDECWIDE128KL M384 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 123] // AESENCWIDE128KL M384 +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix_02_modrmreg, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1072] // GF2P8MULB Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2379] // SHA256MSG2 Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2377] // SHA256MSG1 Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2381] // SHA256RNDS2 Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2371] // SHA1MSG2 Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2369] // SHA1MSG1 Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2373] // SHA1NEXTE Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1171] // INVPCID Gy,Mdq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1173] // INVVPID Gy,Mdq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1166] // INVEPT Gy,Mdq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1761] // PHMINPOSUW Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1820] // PMULLD Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1788] // PMAXUD Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1789] // PMAXUW Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1783] // PMAXSD Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1782] // PMAXSB Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1796] // PMINUD Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1797] // PMINUW Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1791] // PMINSD Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1790] // PMINSB Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1714] // PCMPGTQ Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1809] // PMOVZXDQ Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1811] // PMOVZXWQ Vdq,Wd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1810] // PMOVZXWD Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1807] // PMOVZXBQ Vdq,Ww +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1806] // PMOVZXBD Vdq,Wd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1808] // PMOVZXBW Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1666] // PACKUSDW Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1441] // MOVNTDQA Vx,Mx +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1705] // PCMPEQQ Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1812] // PMULDQ Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1803] // PMOVSXDQ Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1805] // PMOVSXWQ Vdq,Wd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1804] // PMOVSXWD Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1801] // PMOVSXBQ Vdq,Ww +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1800] // PMOVSXBD Vdq,Wd +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1802] // PMOVSXBW Vdq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1659] // PABSD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1658] // PABSD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1661] // PABSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1660] // PABSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1657] // PABSB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1656] // PABSB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1945] // PTEST Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 205] // BLENDVPD Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 206] // BLENDVPS Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1697] // PBLENDVB Vdq,Wdq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1814] // PMULHRSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1813] // PMULHRSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1890] // PSIGND Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1889] // PSIGND Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1892] // PSIGNW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1891] // PSIGNW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1888] // PSIGNB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1887] // PSIGNB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1765] // PHSUBSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1764] // PHSUBSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1763] // PHSUBD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1762] // PHSUBD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1767] // PHSUBW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1766] // PHSUBW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1779] // PMADDUBSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1778] // PMADDUBSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1758] // PHADDSW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1757] // PHADDSW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1756] // PHADDD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1755] // PHADDD Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1760] // PHADDW Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1759] // PHADDW Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1882] // PSHUFB Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1881] // PSHUFB Pq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_38_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_00_prefix, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_01_prefix, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_02_prefix, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_03_prefix, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_04_prefix, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_05_prefix, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_06_prefix, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_07_prefix, + /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_08_prefix, + /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_09_prefix, + /* 0a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0a_prefix, + /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_0b_prefix, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_10_prefix, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_14_prefix, + /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_15_prefix, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_17_prefix, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1c_prefix, + /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1d_prefix, + /* 1e */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_1e_prefix, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_20_prefix, + /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_21_prefix, + /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_22_prefix, + /* 23 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_23_prefix, + /* 24 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_24_prefix, + /* 25 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_25_prefix, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_28_prefix, + /* 29 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_29_prefix, + /* 2a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2a_prefix, + /* 2b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_2b_prefix, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_30_prefix, + /* 31 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_31_prefix, + /* 32 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_32_prefix, + /* 33 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_33_prefix, + /* 34 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_34_prefix, + /* 35 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_35_prefix, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_37_prefix, + /* 38 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_38_prefix, + /* 39 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_39_prefix, + /* 3a */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3a_prefix, + /* 3b */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3b_prefix, + /* 3c */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3c_prefix, + /* 3d */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3d_prefix, + /* 3e */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3e_prefix, + /* 3f */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_3f_prefix, + /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_40_prefix, + /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_41_prefix, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_80_prefix, + /* 81 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_81_prefix, + /* 82 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_82_prefix, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c8_prefix, + /* c9 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_c9_prefix, + /* ca */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_ca_prefix, + /* cb */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cb_prefix, + /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cc_prefix, + /* cd */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cd_prefix, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_cf_prefix, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_d8_prefix, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_db_prefix, + /* dc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dc_prefix, + /* dd */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_dd_prefix, + /* de */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_de_prefix, + /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_df_prefix, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f0_prefix, + /* f1 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f1_prefix, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f5_prefix, + /* f6 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f6_prefix, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f8_prefix, + /* f9 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_f9_prefix, + /* fa */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fa_prefix, + /* fb */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fb_prefix, + /* fc */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode_fc_prefix, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_37_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1069] // GETSEC +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_37_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_37_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_35_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2600] // SYSEXIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_34_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2599] // SYSENTER +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_33_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2088] // RDPMC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_32_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2084] // RDMSR +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_31_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2096] // RDTSC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_30_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3974] // WRMSR +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 681] // COMISD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2f_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 682] // COMISS Vss,Wss +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2f_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2637] // UCOMISD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2638] // UCOMISS Vss,Wss +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2e_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 844] // CVTSD2SI Gy,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 849] // CVTSS2SI Gy,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 837] // CVTPD2PI Pq,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2d_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 843] // CVTPS2PI Pq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2d_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 854] // CVTTSD2SI Gy,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 855] // CVTTSS2SI Gy,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 851] // CVTTPD2PI Pq,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2c_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 853] // CVTTPS2PI Pq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2c_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1446] // MOVNTSD Msd,Vsd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1447] // MOVNTSS Mss,Vss +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1443] // MOVNTPD Mpd,Vpd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1444] // MOVNTPS Mps,Vps +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2b_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 846] // CVTSI2SD Vsd,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 847] // CVTSI2SS Vss,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 839] // CVTPI2PD Vpd,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_2a_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 840] // CVTPI2PS Vq,Qq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_2a_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1404] // MOVAPD Wpd,Vpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_29_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1406] // MOVAPS Wps,Vps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_29_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1403] // MOVAPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_28_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1405] // MOVAPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_28_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_26_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1402] // MOV Ty,Ry +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_24_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1401] // MOV Ry,Ty +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_23_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1400] // MOV Dy,Ry +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_22_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1399] // MOV Cy,Ry +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_21_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1398] // MOV Ry,Dy +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_20_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1397] // MOV Ry,Cy +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1544] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1581] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1580] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1579] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1578] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 905] // ENDBR32 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1577] // NOP Rv,Gv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 906] // ENDBR64 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1576] // NOP Rv,Gv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1575] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1574] // NOP Rv,Gv +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_02_auxiliary, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_03_auxiliary, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1573] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1572] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1571] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1570] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1569] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1568] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1567] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1566] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1565] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1564] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1563] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2095] // RDSSPQ Rq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2094] // RDSSPD Rd +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1562] // NOP Rv,Gv +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary_04_auxiliary, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1561] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod_01_auxiliary, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1560] // NOP Rv,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1559] // NOP Mv,Gv +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1543] // NOP Ev,Gv +}; + +const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1e_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature_02_modrmreg, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1542] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1558] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1557] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1556] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1555] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1554] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1553] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1552] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1551] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1550] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1549] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1548] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 562] // CLDEMOTE Mb +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix_03_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_00_prefix, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1541] // NOP Ev,Gv +}; + +const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1c_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature_03_modrmreg, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 219] // BNDCN rBl,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1547] // NOP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 222] // BNDMK rBl,My +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 224] // BNDMOV mBl,rBl +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1546] // NOP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 225] // BNDSTX Mmib,rBl +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1540] // NOP Gv,Ev +}; + +const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1b_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature_01_prefix, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 220] // BNDCU rBl,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 218] // BNDCL rBl,Ey +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 223] // BNDMOV rBl,mBl +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1545] // NOP Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 221] // BNDLDX rBl,Mmib +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1539] // NOP Ev,Gv +}; + +const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_1a_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature_01_prefix, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_19_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1528] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1538] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1866] // PREFETCHIT0 Mb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1537] // NOP Ev +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary_06_leaf, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1536] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1867] // PREFETCHIT1 Mb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1535] // NOP Ev +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary_06_leaf, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_00_auxiliary, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1534] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1533] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1532] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1876] // PREFETCHT2 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1531] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1874] // PREFETCHT1 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1530] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1872] // PREFETCHT0 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1529] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1870] // PREFETCHNTA Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1527] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1526] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1525] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1524] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1523] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1875] // PREFETCHT2 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1522] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1873] // PREFETCHT1 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1521] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1871] // PREFETCHT0 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1520] // NOP Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1869] // PREFETCHNTA Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg_07_leaf, + } +}; + +const ND_TABLE_FEATURE gLegacyMap_opcode_0f_opcode_18_feature = +{ + ND_ILUT_FEATURE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature_04_modrmreg, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1431] // MOVHPD Mq,Vq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1433] // MOVHPS Mq,Vq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_17_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1463] // MOVSHDUP Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1430] // MOVHPD Vq,Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1434] // MOVLHPS Vq,Uq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1432] // MOVHPS Vq,Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_16_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2645] // UNPCKHPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2646] // UNPCKHPS Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_15_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2647] // UNPCKLPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2648] // UNPCKLPS Vx,Wx +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_14_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1436] // MOVLPD Mq,Vpd +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1437] // MOVLPS Mq,Vps +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_13_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1419] // MOVDDUP Vdq,Wq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1464] // MOVSLDUP Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1435] // MOVLPD Vsd,Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_12_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1429] // MOVHLPS Vq,Wq +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_12_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1462] // MOVSD Wsd,Vsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1468] // MOVSS Wss,Vss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1475] // MOVUPD Wpd,Vpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1477] // MOVUPS Wps,Vps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_11_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1461] // MOVSD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1467] // MOVSS Vss,Wss +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1474] // MOVUPD Vpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1476] // MOVUPS Vps,Wps +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_10_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1694] // PAVGUSB Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1944] // PSWAPD Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1815] // PMULHRW Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1748] // PFRCPIT2 Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1743] // PFMUL Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1738] // PFCMPEQ Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1736] // PFACC Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1754] // PFSUBR Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1750] // PFRSQIT1 Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1747] // PFRCPIT1 Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1741] // PFMAX Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1740] // PFCMPGT Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1737] // PFADD Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1753] // PFSUB Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1751] // PFRSQRT Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1746] // PFRCP Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1742] // PFMIN Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1739] // PFCMPGE Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1745] // PFPNACC Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1744] // PFNACC Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1752] // PFRSQRTV Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1749] // PFRCPV Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1734] // PF2ID Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1735] // PF2IW Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1768] // PI2FD Pq,Qq +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1769] // PI2FW Pq,Qq +}; + +const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode_0f_opcode_last = +{ + ND_ILUT_OPCODE_LAST, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_0c_leaf, + /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_0d_leaf, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_1c_leaf, + /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_1d_leaf, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_86_leaf, + /* 87 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_87_leaf, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_8a_leaf, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_8e_leaf, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_90_leaf, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_94_leaf, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_96_leaf, + /* 97 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_97_leaf, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_9a_leaf, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_9e_leaf, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a0_leaf, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a4_leaf, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a6_leaf, + /* a7 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_a7_leaf, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_aa_leaf, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_ae_leaf, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b0_leaf, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b4_leaf, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b6_leaf, + /* b7 */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_b7_leaf, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_bb_leaf, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last_bf_leaf, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 959] // FEMMS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1519] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1864] // PREFETCH Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1518] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1863] // PREFETCH Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1517] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1862] // PREFETCH Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1516] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1861] // PREFETCH Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1515] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1868] // PREFETCHM Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1514] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1878] // PREFETCHWT1 Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1513] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1877] // PREFETCHW Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1512] // NOP Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1865] // PREFETCHE Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_0d_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_05_modrmmod, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2641] // UD2 +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3971] // WBNOINVD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3970] // WBINVD +}; + +const ND_TABLE_AUXILIARY gLegacyMap_opcode_0f_opcode_09_auxiliary = +{ + ND_ILUT_AUXILIARY, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary_04_leaf, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1164] // INVD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2601] // SYSRET +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 570] // CLTS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2598] // SYSCALL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1343] // LSL Gv,Rz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1342] // LSL Gv,Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1311] // LAR Gv,Rz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1310] // LAR Gv,Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1993] // PVALIDATE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1906] // PSMASH +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2629] // TLBSYNC +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2104] // RMPUPDATE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2102] // RMPADJUST +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1169] // INVLPGB +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2103] // RMPQUERY +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2089] // RDPRU +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 573] // CLZERO +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1496] // MWAITX +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1359] // MCOMMIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1366] // MONITORX +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2097] // RDTSCP +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2597] // SWAPGS +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_02_prefix, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_03_prefix, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_05_prefix, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_06_prefix, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm_07_prefix, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1167] // INVLPG Mb +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1329] // LMSW Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4059] // XRESLDTRK +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4073] // XSUSLDTRK +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2538] // STUI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 571] // CLUI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2620] // TESTUI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2642] // UIRET +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2287] // SAVEPREVSSP +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2363] // SETSSBSY +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2198] // RSTORSSP Mq +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3977] // WRPKRU +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2087] // RDPKRU +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2332] // SERIALIZE +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2514] // SMSW Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2513] // SMSW Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1168] // INVLPGA +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2509] // SKINIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 567] // CLGI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2523] // STGI +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3287] // VMSAVE +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3171] // VMLOAD +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3159] // VMGEXIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3158] // VMGEXIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3173] // VMMCALL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3172] // VMMCALL +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3286] // VMRUN +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_01_prefix, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1324] // LIDT Ms +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 899] // ENCLU +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4074] // XTEST +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4000] // XEND +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3157] // VMFUNC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4072] // XSETBV +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 4001] // XGETBV +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm_07_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix_00_modrmrm, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1322] // LGDT Ms +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod_01_prefix, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 912] // ERETS +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 913] // ERETU +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm_02_leaf, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2328] // SEAMCALL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2329] // SEAMOPS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2330] // SEAMRET +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2605] // TDCALL +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm_07_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 898] // ENCLS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2520] // STAC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 559] // CLAC +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1495] // MWAIT +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1365] // MONITOR +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_03_leaf, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm_07_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_00_modrmrm, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_01_modrmrm, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_02_modrmrm, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix_03_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2508] // SIDT Ms +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod_01_prefix, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2085] // RDMSRLIST +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3975] // WRMSRLIST +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1699] // PBNDKB +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3976] // WRMSRNS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1719] // PCONFIG +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3299] // VMXOFF +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3285] // VMRESUME +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3170] // VMLAUNCH +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3155] // VMCALL +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 900] // ENCLV +}; + +const ND_TABLE_MODRM_RM gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm_07_leaf, + } +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_00_modrmrm, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_02_modrmrm, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix_03_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2367] // SGDT Ms +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod_01_prefix, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_03_modrmmod, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_04_modrmmod, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_05_prefix, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1326] // LKGS Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1325] // LKGS Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1191] // JMPE Ev +}; + +const ND_TABLE_MPREFIX gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix = +{ + ND_ILUT_MAN_PREFIX, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2855] // VERW Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2854] // VERR Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1345] // LTR Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1327] // LLDT Ew +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2535] // STR Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2534] // STR Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2511] // SLDT Rv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2510] // SLDT Mw +}; + +const ND_TABLE_MODRM_MOD gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gLegacyMap_opcode_0f_opcode_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_01_modrmmod, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg_06_prefix, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gLegacyMap_opcode_0f_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_0f_opcode_00_modrmreg, + /* 01 */ (const void *)&gLegacyMap_opcode_0f_opcode_01_modrmreg, + /* 02 */ (const void *)&gLegacyMap_opcode_0f_opcode_02_modrmmod, + /* 03 */ (const void *)&gLegacyMap_opcode_0f_opcode_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)&gLegacyMap_opcode_0f_opcode_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_0f_opcode_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_0f_opcode_07_leaf, + /* 08 */ (const void *)&gLegacyMap_opcode_0f_opcode_08_leaf, + /* 09 */ (const void *)&gLegacyMap_opcode_0f_opcode_09_auxiliary, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)&gLegacyMap_opcode_0f_opcode_0b_leaf, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)&gLegacyMap_opcode_0f_opcode_0d_modrmreg, + /* 0e */ (const void *)&gLegacyMap_opcode_0f_opcode_0e_leaf, + /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode_0f_opcode_last, + /* 10 */ (const void *)&gLegacyMap_opcode_0f_opcode_10_prefix, + /* 11 */ (const void *)&gLegacyMap_opcode_0f_opcode_11_prefix, + /* 12 */ (const void *)&gLegacyMap_opcode_0f_opcode_12_prefix, + /* 13 */ (const void *)&gLegacyMap_opcode_0f_opcode_13_prefix, + /* 14 */ (const void *)&gLegacyMap_opcode_0f_opcode_14_prefix, + /* 15 */ (const void *)&gLegacyMap_opcode_0f_opcode_15_prefix, + /* 16 */ (const void *)&gLegacyMap_opcode_0f_opcode_16_prefix, + /* 17 */ (const void *)&gLegacyMap_opcode_0f_opcode_17_prefix, + /* 18 */ (const void *)&gLegacyMap_opcode_0f_opcode_18_feature, + /* 19 */ (const void *)&gLegacyMap_opcode_0f_opcode_19_leaf, + /* 1a */ (const void *)&gLegacyMap_opcode_0f_opcode_1a_feature, + /* 1b */ (const void *)&gLegacyMap_opcode_0f_opcode_1b_feature, + /* 1c */ (const void *)&gLegacyMap_opcode_0f_opcode_1c_feature, + /* 1d */ (const void *)&gLegacyMap_opcode_0f_opcode_1d_leaf, + /* 1e */ (const void *)&gLegacyMap_opcode_0f_opcode_1e_feature, + /* 1f */ (const void *)&gLegacyMap_opcode_0f_opcode_1f_leaf, + /* 20 */ (const void *)&gLegacyMap_opcode_0f_opcode_20_leaf, + /* 21 */ (const void *)&gLegacyMap_opcode_0f_opcode_21_leaf, + /* 22 */ (const void *)&gLegacyMap_opcode_0f_opcode_22_leaf, + /* 23 */ (const void *)&gLegacyMap_opcode_0f_opcode_23_leaf, + /* 24 */ (const void *)&gLegacyMap_opcode_0f_opcode_24_leaf, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)&gLegacyMap_opcode_0f_opcode_26_leaf, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gLegacyMap_opcode_0f_opcode_28_prefix, + /* 29 */ (const void *)&gLegacyMap_opcode_0f_opcode_29_prefix, + /* 2a */ (const void *)&gLegacyMap_opcode_0f_opcode_2a_prefix, + /* 2b */ (const void *)&gLegacyMap_opcode_0f_opcode_2b_prefix, + /* 2c */ (const void *)&gLegacyMap_opcode_0f_opcode_2c_prefix, + /* 2d */ (const void *)&gLegacyMap_opcode_0f_opcode_2d_prefix, + /* 2e */ (const void *)&gLegacyMap_opcode_0f_opcode_2e_prefix, + /* 2f */ (const void *)&gLegacyMap_opcode_0f_opcode_2f_prefix, + /* 30 */ (const void *)&gLegacyMap_opcode_0f_opcode_30_leaf, + /* 31 */ (const void *)&gLegacyMap_opcode_0f_opcode_31_leaf, + /* 32 */ (const void *)&gLegacyMap_opcode_0f_opcode_32_leaf, + /* 33 */ (const void *)&gLegacyMap_opcode_0f_opcode_33_leaf, + /* 34 */ (const void *)&gLegacyMap_opcode_0f_opcode_34_leaf, + /* 35 */ (const void *)&gLegacyMap_opcode_0f_opcode_35_leaf, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)&gLegacyMap_opcode_0f_opcode_37_prefix, + /* 38 */ (const void *)&gLegacyMap_opcode_0f_opcode_38_opcode, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)&gLegacyMap_opcode_0f_opcode_3a_opcode, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)&gLegacyMap_opcode_0f_opcode_40_leaf, + /* 41 */ (const void *)&gLegacyMap_opcode_0f_opcode_41_leaf, + /* 42 */ (const void *)&gLegacyMap_opcode_0f_opcode_42_leaf, + /* 43 */ (const void *)&gLegacyMap_opcode_0f_opcode_43_leaf, + /* 44 */ (const void *)&gLegacyMap_opcode_0f_opcode_44_leaf, + /* 45 */ (const void *)&gLegacyMap_opcode_0f_opcode_45_leaf, + /* 46 */ (const void *)&gLegacyMap_opcode_0f_opcode_46_leaf, + /* 47 */ (const void *)&gLegacyMap_opcode_0f_opcode_47_leaf, + /* 48 */ (const void *)&gLegacyMap_opcode_0f_opcode_48_leaf, + /* 49 */ (const void *)&gLegacyMap_opcode_0f_opcode_49_leaf, + /* 4a */ (const void *)&gLegacyMap_opcode_0f_opcode_4a_leaf, + /* 4b */ (const void *)&gLegacyMap_opcode_0f_opcode_4b_leaf, + /* 4c */ (const void *)&gLegacyMap_opcode_0f_opcode_4c_leaf, + /* 4d */ (const void *)&gLegacyMap_opcode_0f_opcode_4d_leaf, + /* 4e */ (const void *)&gLegacyMap_opcode_0f_opcode_4e_leaf, + /* 4f */ (const void *)&gLegacyMap_opcode_0f_opcode_4f_leaf, + /* 50 */ (const void *)&gLegacyMap_opcode_0f_opcode_50_prefix, + /* 51 */ (const void *)&gLegacyMap_opcode_0f_opcode_51_prefix, + /* 52 */ (const void *)&gLegacyMap_opcode_0f_opcode_52_prefix, + /* 53 */ (const void *)&gLegacyMap_opcode_0f_opcode_53_prefix, + /* 54 */ (const void *)&gLegacyMap_opcode_0f_opcode_54_prefix, + /* 55 */ (const void *)&gLegacyMap_opcode_0f_opcode_55_prefix, + /* 56 */ (const void *)&gLegacyMap_opcode_0f_opcode_56_prefix, + /* 57 */ (const void *)&gLegacyMap_opcode_0f_opcode_57_prefix, + /* 58 */ (const void *)&gLegacyMap_opcode_0f_opcode_58_prefix, + /* 59 */ (const void *)&gLegacyMap_opcode_0f_opcode_59_prefix, + /* 5a */ (const void *)&gLegacyMap_opcode_0f_opcode_5a_prefix, + /* 5b */ (const void *)&gLegacyMap_opcode_0f_opcode_5b_prefix, + /* 5c */ (const void *)&gLegacyMap_opcode_0f_opcode_5c_prefix, + /* 5d */ (const void *)&gLegacyMap_opcode_0f_opcode_5d_prefix, + /* 5e */ (const void *)&gLegacyMap_opcode_0f_opcode_5e_prefix, + /* 5f */ (const void *)&gLegacyMap_opcode_0f_opcode_5f_prefix, + /* 60 */ (const void *)&gLegacyMap_opcode_0f_opcode_60_prefix, + /* 61 */ (const void *)&gLegacyMap_opcode_0f_opcode_61_prefix, + /* 62 */ (const void *)&gLegacyMap_opcode_0f_opcode_62_prefix, + /* 63 */ (const void *)&gLegacyMap_opcode_0f_opcode_63_prefix, + /* 64 */ (const void *)&gLegacyMap_opcode_0f_opcode_64_prefix, + /* 65 */ (const void *)&gLegacyMap_opcode_0f_opcode_65_prefix, + /* 66 */ (const void *)&gLegacyMap_opcode_0f_opcode_66_prefix, + /* 67 */ (const void *)&gLegacyMap_opcode_0f_opcode_67_prefix, + /* 68 */ (const void *)&gLegacyMap_opcode_0f_opcode_68_prefix, + /* 69 */ (const void *)&gLegacyMap_opcode_0f_opcode_69_prefix, + /* 6a */ (const void *)&gLegacyMap_opcode_0f_opcode_6a_prefix, + /* 6b */ (const void *)&gLegacyMap_opcode_0f_opcode_6b_prefix, + /* 6c */ (const void *)&gLegacyMap_opcode_0f_opcode_6c_prefix, + /* 6d */ (const void *)&gLegacyMap_opcode_0f_opcode_6d_prefix, + /* 6e */ (const void *)&gLegacyMap_opcode_0f_opcode_6e_prefix, + /* 6f */ (const void *)&gLegacyMap_opcode_0f_opcode_6f_prefix, + /* 70 */ (const void *)&gLegacyMap_opcode_0f_opcode_70_prefix, + /* 71 */ (const void *)&gLegacyMap_opcode_0f_opcode_71_prefix, + /* 72 */ (const void *)&gLegacyMap_opcode_0f_opcode_72_prefix, + /* 73 */ (const void *)&gLegacyMap_opcode_0f_opcode_73_prefix, + /* 74 */ (const void *)&gLegacyMap_opcode_0f_opcode_74_prefix, + /* 75 */ (const void *)&gLegacyMap_opcode_0f_opcode_75_prefix, + /* 76 */ (const void *)&gLegacyMap_opcode_0f_opcode_76_prefix, + /* 77 */ (const void *)&gLegacyMap_opcode_0f_opcode_77_prefix, + /* 78 */ (const void *)&gLegacyMap_opcode_0f_opcode_78_prefix, + /* 79 */ (const void *)&gLegacyMap_opcode_0f_opcode_79_prefix, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)&gLegacyMap_opcode_0f_opcode_7c_prefix, + /* 7d */ (const void *)&gLegacyMap_opcode_0f_opcode_7d_prefix, + /* 7e */ (const void *)&gLegacyMap_opcode_0f_opcode_7e_prefix, + /* 7f */ (const void *)&gLegacyMap_opcode_0f_opcode_7f_prefix, + /* 80 */ (const void *)&gLegacyMap_opcode_0f_opcode_80_leaf, + /* 81 */ (const void *)&gLegacyMap_opcode_0f_opcode_81_leaf, + /* 82 */ (const void *)&gLegacyMap_opcode_0f_opcode_82_leaf, + /* 83 */ (const void *)&gLegacyMap_opcode_0f_opcode_83_leaf, + /* 84 */ (const void *)&gLegacyMap_opcode_0f_opcode_84_leaf, + /* 85 */ (const void *)&gLegacyMap_opcode_0f_opcode_85_leaf, + /* 86 */ (const void *)&gLegacyMap_opcode_0f_opcode_86_leaf, + /* 87 */ (const void *)&gLegacyMap_opcode_0f_opcode_87_leaf, + /* 88 */ (const void *)&gLegacyMap_opcode_0f_opcode_88_leaf, + /* 89 */ (const void *)&gLegacyMap_opcode_0f_opcode_89_leaf, + /* 8a */ (const void *)&gLegacyMap_opcode_0f_opcode_8a_leaf, + /* 8b */ (const void *)&gLegacyMap_opcode_0f_opcode_8b_leaf, + /* 8c */ (const void *)&gLegacyMap_opcode_0f_opcode_8c_leaf, + /* 8d */ (const void *)&gLegacyMap_opcode_0f_opcode_8d_leaf, + /* 8e */ (const void *)&gLegacyMap_opcode_0f_opcode_8e_leaf, + /* 8f */ (const void *)&gLegacyMap_opcode_0f_opcode_8f_leaf, + /* 90 */ (const void *)&gLegacyMap_opcode_0f_opcode_90_leaf, + /* 91 */ (const void *)&gLegacyMap_opcode_0f_opcode_91_leaf, + /* 92 */ (const void *)&gLegacyMap_opcode_0f_opcode_92_leaf, + /* 93 */ (const void *)&gLegacyMap_opcode_0f_opcode_93_leaf, + /* 94 */ (const void *)&gLegacyMap_opcode_0f_opcode_94_leaf, + /* 95 */ (const void *)&gLegacyMap_opcode_0f_opcode_95_leaf, + /* 96 */ (const void *)&gLegacyMap_opcode_0f_opcode_96_leaf, + /* 97 */ (const void *)&gLegacyMap_opcode_0f_opcode_97_leaf, + /* 98 */ (const void *)&gLegacyMap_opcode_0f_opcode_98_leaf, + /* 99 */ (const void *)&gLegacyMap_opcode_0f_opcode_99_leaf, + /* 9a */ (const void *)&gLegacyMap_opcode_0f_opcode_9a_leaf, + /* 9b */ (const void *)&gLegacyMap_opcode_0f_opcode_9b_leaf, + /* 9c */ (const void *)&gLegacyMap_opcode_0f_opcode_9c_leaf, + /* 9d */ (const void *)&gLegacyMap_opcode_0f_opcode_9d_leaf, + /* 9e */ (const void *)&gLegacyMap_opcode_0f_opcode_9e_leaf, + /* 9f */ (const void *)&gLegacyMap_opcode_0f_opcode_9f_leaf, + /* a0 */ (const void *)&gLegacyMap_opcode_0f_opcode_a0_leaf, + /* a1 */ (const void *)&gLegacyMap_opcode_0f_opcode_a1_leaf, + /* a2 */ (const void *)&gLegacyMap_opcode_0f_opcode_a2_leaf, + /* a3 */ (const void *)&gLegacyMap_opcode_0f_opcode_a3_leaf, + /* a4 */ (const void *)&gLegacyMap_opcode_0f_opcode_a4_leaf, + /* a5 */ (const void *)&gLegacyMap_opcode_0f_opcode_a5_leaf, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)&gLegacyMap_opcode_0f_opcode_a8_leaf, + /* a9 */ (const void *)&gLegacyMap_opcode_0f_opcode_a9_leaf, + /* aa */ (const void *)&gLegacyMap_opcode_0f_opcode_aa_leaf, + /* ab */ (const void *)&gLegacyMap_opcode_0f_opcode_ab_leaf, + /* ac */ (const void *)&gLegacyMap_opcode_0f_opcode_ac_leaf, + /* ad */ (const void *)&gLegacyMap_opcode_0f_opcode_ad_leaf, + /* ae */ (const void *)&gLegacyMap_opcode_0f_opcode_ae_prefix, + /* af */ (const void *)&gLegacyMap_opcode_0f_opcode_af_leaf, + /* b0 */ (const void *)&gLegacyMap_opcode_0f_opcode_b0_leaf, + /* b1 */ (const void *)&gLegacyMap_opcode_0f_opcode_b1_leaf, + /* b2 */ (const void *)&gLegacyMap_opcode_0f_opcode_b2_modrmmod, + /* b3 */ (const void *)&gLegacyMap_opcode_0f_opcode_b3_leaf, + /* b4 */ (const void *)&gLegacyMap_opcode_0f_opcode_b4_modrmmod, + /* b5 */ (const void *)&gLegacyMap_opcode_0f_opcode_b5_modrmmod, + /* b6 */ (const void *)&gLegacyMap_opcode_0f_opcode_b6_leaf, + /* b7 */ (const void *)&gLegacyMap_opcode_0f_opcode_b7_leaf, + /* b8 */ (const void *)&gLegacyMap_opcode_0f_opcode_b8_auxiliary, + /* b9 */ (const void *)&gLegacyMap_opcode_0f_opcode_b9_leaf, + /* ba */ (const void *)&gLegacyMap_opcode_0f_opcode_ba_modrmreg, + /* bb */ (const void *)&gLegacyMap_opcode_0f_opcode_bb_leaf, + /* bc */ (const void *)&gLegacyMap_opcode_0f_opcode_bc_auxiliary, + /* bd */ (const void *)&gLegacyMap_opcode_0f_opcode_bd_auxiliary, + /* be */ (const void *)&gLegacyMap_opcode_0f_opcode_be_leaf, + /* bf */ (const void *)&gLegacyMap_opcode_0f_opcode_bf_leaf, + /* c0 */ (const void *)&gLegacyMap_opcode_0f_opcode_c0_leaf, + /* c1 */ (const void *)&gLegacyMap_opcode_0f_opcode_c1_leaf, + /* c2 */ (const void *)&gLegacyMap_opcode_0f_opcode_c2_prefix, + /* c3 */ (const void *)&gLegacyMap_opcode_0f_opcode_c3_prefix, + /* c4 */ (const void *)&gLegacyMap_opcode_0f_opcode_c4_prefix, + /* c5 */ (const void *)&gLegacyMap_opcode_0f_opcode_c5_prefix, + /* c6 */ (const void *)&gLegacyMap_opcode_0f_opcode_c6_prefix, + /* c7 */ (const void *)&gLegacyMap_opcode_0f_opcode_c7_modrmreg, + /* c8 */ (const void *)&gLegacyMap_opcode_0f_opcode_c8_leaf, + /* c9 */ (const void *)&gLegacyMap_opcode_0f_opcode_c9_leaf, + /* ca */ (const void *)&gLegacyMap_opcode_0f_opcode_ca_leaf, + /* cb */ (const void *)&gLegacyMap_opcode_0f_opcode_cb_leaf, + /* cc */ (const void *)&gLegacyMap_opcode_0f_opcode_cc_leaf, + /* cd */ (const void *)&gLegacyMap_opcode_0f_opcode_cd_leaf, + /* ce */ (const void *)&gLegacyMap_opcode_0f_opcode_ce_leaf, + /* cf */ (const void *)&gLegacyMap_opcode_0f_opcode_cf_leaf, + /* d0 */ (const void *)&gLegacyMap_opcode_0f_opcode_d0_prefix, + /* d1 */ (const void *)&gLegacyMap_opcode_0f_opcode_d1_prefix, + /* d2 */ (const void *)&gLegacyMap_opcode_0f_opcode_d2_prefix, + /* d3 */ (const void *)&gLegacyMap_opcode_0f_opcode_d3_prefix, + /* d4 */ (const void *)&gLegacyMap_opcode_0f_opcode_d4_prefix, + /* d5 */ (const void *)&gLegacyMap_opcode_0f_opcode_d5_prefix, + /* d6 */ (const void *)&gLegacyMap_opcode_0f_opcode_d6_prefix, + /* d7 */ (const void *)&gLegacyMap_opcode_0f_opcode_d7_prefix, + /* d8 */ (const void *)&gLegacyMap_opcode_0f_opcode_d8_prefix, + /* d9 */ (const void *)&gLegacyMap_opcode_0f_opcode_d9_prefix, + /* da */ (const void *)&gLegacyMap_opcode_0f_opcode_da_prefix, + /* db */ (const void *)&gLegacyMap_opcode_0f_opcode_db_prefix, + /* dc */ (const void *)&gLegacyMap_opcode_0f_opcode_dc_prefix, + /* dd */ (const void *)&gLegacyMap_opcode_0f_opcode_dd_prefix, + /* de */ (const void *)&gLegacyMap_opcode_0f_opcode_de_prefix, + /* df */ (const void *)&gLegacyMap_opcode_0f_opcode_df_prefix, + /* e0 */ (const void *)&gLegacyMap_opcode_0f_opcode_e0_prefix, + /* e1 */ (const void *)&gLegacyMap_opcode_0f_opcode_e1_prefix, + /* e2 */ (const void *)&gLegacyMap_opcode_0f_opcode_e2_prefix, + /* e3 */ (const void *)&gLegacyMap_opcode_0f_opcode_e3_prefix, + /* e4 */ (const void *)&gLegacyMap_opcode_0f_opcode_e4_prefix, + /* e5 */ (const void *)&gLegacyMap_opcode_0f_opcode_e5_prefix, + /* e6 */ (const void *)&gLegacyMap_opcode_0f_opcode_e6_prefix, + /* e7 */ (const void *)&gLegacyMap_opcode_0f_opcode_e7_prefix, + /* e8 */ (const void *)&gLegacyMap_opcode_0f_opcode_e8_prefix, + /* e9 */ (const void *)&gLegacyMap_opcode_0f_opcode_e9_prefix, + /* ea */ (const void *)&gLegacyMap_opcode_0f_opcode_ea_prefix, + /* eb */ (const void *)&gLegacyMap_opcode_0f_opcode_eb_prefix, + /* ec */ (const void *)&gLegacyMap_opcode_0f_opcode_ec_prefix, + /* ed */ (const void *)&gLegacyMap_opcode_0f_opcode_ed_prefix, + /* ee */ (const void *)&gLegacyMap_opcode_0f_opcode_ee_prefix, + /* ef */ (const void *)&gLegacyMap_opcode_0f_opcode_ef_prefix, + /* f0 */ (const void *)&gLegacyMap_opcode_0f_opcode_f0_prefix, + /* f1 */ (const void *)&gLegacyMap_opcode_0f_opcode_f1_prefix, + /* f2 */ (const void *)&gLegacyMap_opcode_0f_opcode_f2_prefix, + /* f3 */ (const void *)&gLegacyMap_opcode_0f_opcode_f3_prefix, + /* f4 */ (const void *)&gLegacyMap_opcode_0f_opcode_f4_prefix, + /* f5 */ (const void *)&gLegacyMap_opcode_0f_opcode_f5_prefix, + /* f6 */ (const void *)&gLegacyMap_opcode_0f_opcode_f6_prefix, + /* f7 */ (const void *)&gLegacyMap_opcode_0f_opcode_f7_prefix, + /* f8 */ (const void *)&gLegacyMap_opcode_0f_opcode_f8_prefix, + /* f9 */ (const void *)&gLegacyMap_opcode_0f_opcode_f9_prefix, + /* fa */ (const void *)&gLegacyMap_opcode_0f_opcode_fa_prefix, + /* fb */ (const void *)&gLegacyMap_opcode_0f_opcode_fb_prefix, + /* fc */ (const void *)&gLegacyMap_opcode_0f_opcode_fc_prefix, + /* fd */ (const void *)&gLegacyMap_opcode_0f_opcode_fd_prefix, + /* fe */ (const void *)&gLegacyMap_opcode_0f_opcode_fe_prefix, + /* ff */ (const void *)&gLegacyMap_opcode_0f_opcode_ff_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1962] // PUSH CS +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0d_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1639] // OR rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0c_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1638] // OR AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0b_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1637] // OR Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_0a_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1636] // OR Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_09_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1635] // OR Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_08_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1634] // OR Eb,Gb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1825] // POP ES +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1961] // PUSH ES +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 92] // ADD rAX,Iz +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 91] // ADD AL,Ib +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 90] // ADD Gv,Ev +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 89] // ADD Gb,Eb +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 88] // ADD Ev,Gv +}; + +const ND_TABLE_INSTRUCTION gLegacyMap_opcode_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 87] // ADD Eb,Gb +}; + +const ND_TABLE_OPCODE gLegacyMap_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gLegacyMap_opcode_00_leaf, + /* 01 */ (const void *)&gLegacyMap_opcode_01_leaf, + /* 02 */ (const void *)&gLegacyMap_opcode_02_leaf, + /* 03 */ (const void *)&gLegacyMap_opcode_03_leaf, + /* 04 */ (const void *)&gLegacyMap_opcode_04_leaf, + /* 05 */ (const void *)&gLegacyMap_opcode_05_leaf, + /* 06 */ (const void *)&gLegacyMap_opcode_06_leaf, + /* 07 */ (const void *)&gLegacyMap_opcode_07_leaf, + /* 08 */ (const void *)&gLegacyMap_opcode_08_leaf, + /* 09 */ (const void *)&gLegacyMap_opcode_09_leaf, + /* 0a */ (const void *)&gLegacyMap_opcode_0a_leaf, + /* 0b */ (const void *)&gLegacyMap_opcode_0b_leaf, + /* 0c */ (const void *)&gLegacyMap_opcode_0c_leaf, + /* 0d */ (const void *)&gLegacyMap_opcode_0d_leaf, + /* 0e */ (const void *)&gLegacyMap_opcode_0e_leaf, + /* 0f */ (const void *)&gLegacyMap_opcode_0f_opcode, + /* 10 */ (const void *)&gLegacyMap_opcode_10_leaf, + /* 11 */ (const void *)&gLegacyMap_opcode_11_leaf, + /* 12 */ (const void *)&gLegacyMap_opcode_12_leaf, + /* 13 */ (const void *)&gLegacyMap_opcode_13_leaf, + /* 14 */ (const void *)&gLegacyMap_opcode_14_leaf, + /* 15 */ (const void *)&gLegacyMap_opcode_15_leaf, + /* 16 */ (const void *)&gLegacyMap_opcode_16_leaf, + /* 17 */ (const void *)&gLegacyMap_opcode_17_leaf, + /* 18 */ (const void *)&gLegacyMap_opcode_18_leaf, + /* 19 */ (const void *)&gLegacyMap_opcode_19_leaf, + /* 1a */ (const void *)&gLegacyMap_opcode_1a_leaf, + /* 1b */ (const void *)&gLegacyMap_opcode_1b_leaf, + /* 1c */ (const void *)&gLegacyMap_opcode_1c_leaf, + /* 1d */ (const void *)&gLegacyMap_opcode_1d_leaf, + /* 1e */ (const void *)&gLegacyMap_opcode_1e_leaf, + /* 1f */ (const void *)&gLegacyMap_opcode_1f_leaf, + /* 20 */ (const void *)&gLegacyMap_opcode_20_leaf, + /* 21 */ (const void *)&gLegacyMap_opcode_21_leaf, + /* 22 */ (const void *)&gLegacyMap_opcode_22_leaf, + /* 23 */ (const void *)&gLegacyMap_opcode_23_leaf, + /* 24 */ (const void *)&gLegacyMap_opcode_24_leaf, + /* 25 */ (const void *)&gLegacyMap_opcode_25_leaf, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)&gLegacyMap_opcode_27_leaf, + /* 28 */ (const void *)&gLegacyMap_opcode_28_leaf, + /* 29 */ (const void *)&gLegacyMap_opcode_29_leaf, + /* 2a */ (const void *)&gLegacyMap_opcode_2a_leaf, + /* 2b */ (const void *)&gLegacyMap_opcode_2b_leaf, + /* 2c */ (const void *)&gLegacyMap_opcode_2c_leaf, + /* 2d */ (const void *)&gLegacyMap_opcode_2d_leaf, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)&gLegacyMap_opcode_2f_leaf, + /* 30 */ (const void *)&gLegacyMap_opcode_30_leaf, + /* 31 */ (const void *)&gLegacyMap_opcode_31_leaf, + /* 32 */ (const void *)&gLegacyMap_opcode_32_leaf, + /* 33 */ (const void *)&gLegacyMap_opcode_33_leaf, + /* 34 */ (const void *)&gLegacyMap_opcode_34_leaf, + /* 35 */ (const void *)&gLegacyMap_opcode_35_leaf, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)&gLegacyMap_opcode_37_leaf, + /* 38 */ (const void *)&gLegacyMap_opcode_38_leaf, + /* 39 */ (const void *)&gLegacyMap_opcode_39_leaf, + /* 3a */ (const void *)&gLegacyMap_opcode_3a_leaf, + /* 3b */ (const void *)&gLegacyMap_opcode_3b_leaf, + /* 3c */ (const void *)&gLegacyMap_opcode_3c_leaf, + /* 3d */ (const void *)&gLegacyMap_opcode_3d_leaf, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)&gLegacyMap_opcode_3f_leaf, + /* 40 */ (const void *)&gLegacyMap_opcode_40_leaf, + /* 41 */ (const void *)&gLegacyMap_opcode_41_leaf, + /* 42 */ (const void *)&gLegacyMap_opcode_42_leaf, + /* 43 */ (const void *)&gLegacyMap_opcode_43_leaf, + /* 44 */ (const void *)&gLegacyMap_opcode_44_leaf, + /* 45 */ (const void *)&gLegacyMap_opcode_45_leaf, + /* 46 */ (const void *)&gLegacyMap_opcode_46_leaf, + /* 47 */ (const void *)&gLegacyMap_opcode_47_leaf, + /* 48 */ (const void *)&gLegacyMap_opcode_48_leaf, + /* 49 */ (const void *)&gLegacyMap_opcode_49_leaf, + /* 4a */ (const void *)&gLegacyMap_opcode_4a_leaf, + /* 4b */ (const void *)&gLegacyMap_opcode_4b_leaf, + /* 4c */ (const void *)&gLegacyMap_opcode_4c_leaf, + /* 4d */ (const void *)&gLegacyMap_opcode_4d_leaf, + /* 4e */ (const void *)&gLegacyMap_opcode_4e_leaf, + /* 4f */ (const void *)&gLegacyMap_opcode_4f_leaf, + /* 50 */ (const void *)&gLegacyMap_opcode_50_auxiliary, + /* 51 */ (const void *)&gLegacyMap_opcode_51_auxiliary, + /* 52 */ (const void *)&gLegacyMap_opcode_52_auxiliary, + /* 53 */ (const void *)&gLegacyMap_opcode_53_auxiliary, + /* 54 */ (const void *)&gLegacyMap_opcode_54_auxiliary, + /* 55 */ (const void *)&gLegacyMap_opcode_55_auxiliary, + /* 56 */ (const void *)&gLegacyMap_opcode_56_auxiliary, + /* 57 */ (const void *)&gLegacyMap_opcode_57_auxiliary, + /* 58 */ (const void *)&gLegacyMap_opcode_58_auxiliary, + /* 59 */ (const void *)&gLegacyMap_opcode_59_auxiliary, + /* 5a */ (const void *)&gLegacyMap_opcode_5a_auxiliary, + /* 5b */ (const void *)&gLegacyMap_opcode_5b_auxiliary, + /* 5c */ (const void *)&gLegacyMap_opcode_5c_auxiliary, + /* 5d */ (const void *)&gLegacyMap_opcode_5d_auxiliary, + /* 5e */ (const void *)&gLegacyMap_opcode_5e_auxiliary, + /* 5f */ (const void *)&gLegacyMap_opcode_5f_auxiliary, + /* 60 */ (const void *)&gLegacyMap_opcode_60_dsize, + /* 61 */ (const void *)&gLegacyMap_opcode_61_dsize, + /* 62 */ (const void *)&gLegacyMap_opcode_62_modrmmod, + /* 63 */ (const void *)&gLegacyMap_opcode_63_auxiliary, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)&gLegacyMap_opcode_68_leaf, + /* 69 */ (const void *)&gLegacyMap_opcode_69_leaf, + /* 6a */ (const void *)&gLegacyMap_opcode_6a_leaf, + /* 6b */ (const void *)&gLegacyMap_opcode_6b_leaf, + /* 6c */ (const void *)&gLegacyMap_opcode_6c_auxiliary, + /* 6d */ (const void *)&gLegacyMap_opcode_6d_dsize, + /* 6e */ (const void *)&gLegacyMap_opcode_6e_auxiliary, + /* 6f */ (const void *)&gLegacyMap_opcode_6f_dsize, + /* 70 */ (const void *)&gLegacyMap_opcode_70_leaf, + /* 71 */ (const void *)&gLegacyMap_opcode_71_leaf, + /* 72 */ (const void *)&gLegacyMap_opcode_72_leaf, + /* 73 */ (const void *)&gLegacyMap_opcode_73_leaf, + /* 74 */ (const void *)&gLegacyMap_opcode_74_leaf, + /* 75 */ (const void *)&gLegacyMap_opcode_75_leaf, + /* 76 */ (const void *)&gLegacyMap_opcode_76_leaf, + /* 77 */ (const void *)&gLegacyMap_opcode_77_leaf, + /* 78 */ (const void *)&gLegacyMap_opcode_78_leaf, + /* 79 */ (const void *)&gLegacyMap_opcode_79_leaf, + /* 7a */ (const void *)&gLegacyMap_opcode_7a_leaf, + /* 7b */ (const void *)&gLegacyMap_opcode_7b_leaf, + /* 7c */ (const void *)&gLegacyMap_opcode_7c_leaf, + /* 7d */ (const void *)&gLegacyMap_opcode_7d_leaf, + /* 7e */ (const void *)&gLegacyMap_opcode_7e_leaf, + /* 7f */ (const void *)&gLegacyMap_opcode_7f_leaf, + /* 80 */ (const void *)&gLegacyMap_opcode_80_modrmreg, + /* 81 */ (const void *)&gLegacyMap_opcode_81_modrmreg, + /* 82 */ (const void *)&gLegacyMap_opcode_82_modrmreg, + /* 83 */ (const void *)&gLegacyMap_opcode_83_modrmreg, + /* 84 */ (const void *)&gLegacyMap_opcode_84_leaf, + /* 85 */ (const void *)&gLegacyMap_opcode_85_leaf, + /* 86 */ (const void *)&gLegacyMap_opcode_86_leaf, + /* 87 */ (const void *)&gLegacyMap_opcode_87_leaf, + /* 88 */ (const void *)&gLegacyMap_opcode_88_leaf, + /* 89 */ (const void *)&gLegacyMap_opcode_89_leaf, + /* 8a */ (const void *)&gLegacyMap_opcode_8a_leaf, + /* 8b */ (const void *)&gLegacyMap_opcode_8b_leaf, + /* 8c */ (const void *)&gLegacyMap_opcode_8c_modrmmod, + /* 8d */ (const void *)&gLegacyMap_opcode_8d_modrmmod, + /* 8e */ (const void *)&gLegacyMap_opcode_8e_modrmmod, + /* 8f */ (const void *)&gLegacyMap_opcode_8f_modrmreg, + /* 90 */ (const void *)&gLegacyMap_opcode_90_auxiliary, + /* 91 */ (const void *)&gLegacyMap_opcode_91_leaf, + /* 92 */ (const void *)&gLegacyMap_opcode_92_leaf, + /* 93 */ (const void *)&gLegacyMap_opcode_93_leaf, + /* 94 */ (const void *)&gLegacyMap_opcode_94_leaf, + /* 95 */ (const void *)&gLegacyMap_opcode_95_leaf, + /* 96 */ (const void *)&gLegacyMap_opcode_96_leaf, + /* 97 */ (const void *)&gLegacyMap_opcode_97_leaf, + /* 98 */ (const void *)&gLegacyMap_opcode_98_dsize, + /* 99 */ (const void *)&gLegacyMap_opcode_99_dsize, + /* 9a */ (const void *)&gLegacyMap_opcode_9a_leaf, + /* 9b */ (const void *)&gLegacyMap_opcode_9b_leaf, + /* 9c */ (const void *)&gLegacyMap_opcode_9c_dsize, + /* 9d */ (const void *)&gLegacyMap_opcode_9d_dsize, + /* 9e */ (const void *)&gLegacyMap_opcode_9e_leaf, + /* 9f */ (const void *)&gLegacyMap_opcode_9f_leaf, + /* a0 */ (const void *)&gLegacyMap_opcode_a0_leaf, + /* a1 */ (const void *)&gLegacyMap_opcode_a1_auxiliary, + /* a2 */ (const void *)&gLegacyMap_opcode_a2_leaf, + /* a3 */ (const void *)&gLegacyMap_opcode_a3_leaf, + /* a4 */ (const void *)&gLegacyMap_opcode_a4_auxiliary, + /* a5 */ (const void *)&gLegacyMap_opcode_a5_dsize, + /* a6 */ (const void *)&gLegacyMap_opcode_a6_auxiliary, + /* a7 */ (const void *)&gLegacyMap_opcode_a7_dsize, + /* a8 */ (const void *)&gLegacyMap_opcode_a8_leaf, + /* a9 */ (const void *)&gLegacyMap_opcode_a9_leaf, + /* aa */ (const void *)&gLegacyMap_opcode_aa_auxiliary, + /* ab */ (const void *)&gLegacyMap_opcode_ab_dsize, + /* ac */ (const void *)&gLegacyMap_opcode_ac_auxiliary, + /* ad */ (const void *)&gLegacyMap_opcode_ad_dsize, + /* ae */ (const void *)&gLegacyMap_opcode_ae_auxiliary, + /* af */ (const void *)&gLegacyMap_opcode_af_dsize, + /* b0 */ (const void *)&gLegacyMap_opcode_b0_leaf, + /* b1 */ (const void *)&gLegacyMap_opcode_b1_leaf, + /* b2 */ (const void *)&gLegacyMap_opcode_b2_leaf, + /* b3 */ (const void *)&gLegacyMap_opcode_b3_leaf, + /* b4 */ (const void *)&gLegacyMap_opcode_b4_leaf, + /* b5 */ (const void *)&gLegacyMap_opcode_b5_leaf, + /* b6 */ (const void *)&gLegacyMap_opcode_b6_leaf, + /* b7 */ (const void *)&gLegacyMap_opcode_b7_leaf, + /* b8 */ (const void *)&gLegacyMap_opcode_b8_leaf, + /* b9 */ (const void *)&gLegacyMap_opcode_b9_leaf, + /* ba */ (const void *)&gLegacyMap_opcode_ba_leaf, + /* bb */ (const void *)&gLegacyMap_opcode_bb_leaf, + /* bc */ (const void *)&gLegacyMap_opcode_bc_leaf, + /* bd */ (const void *)&gLegacyMap_opcode_bd_leaf, + /* be */ (const void *)&gLegacyMap_opcode_be_leaf, + /* bf */ (const void *)&gLegacyMap_opcode_bf_leaf, + /* c0 */ (const void *)&gLegacyMap_opcode_c0_modrmreg, + /* c1 */ (const void *)&gLegacyMap_opcode_c1_modrmreg, + /* c2 */ (const void *)&gLegacyMap_opcode_c2_leaf, + /* c3 */ (const void *)&gLegacyMap_opcode_c3_leaf, + /* c4 */ (const void *)&gLegacyMap_opcode_c4_modrmmod, + /* c5 */ (const void *)&gLegacyMap_opcode_c5_modrmmod, + /* c6 */ (const void *)&gLegacyMap_opcode_c6_modrmreg, + /* c7 */ (const void *)&gLegacyMap_opcode_c7_modrmreg, + /* c8 */ (const void *)&gLegacyMap_opcode_c8_leaf, + /* c9 */ (const void *)&gLegacyMap_opcode_c9_leaf, + /* ca */ (const void *)&gLegacyMap_opcode_ca_leaf, + /* cb */ (const void *)&gLegacyMap_opcode_cb_leaf, + /* cc */ (const void *)&gLegacyMap_opcode_cc_leaf, + /* cd */ (const void *)&gLegacyMap_opcode_cd_leaf, + /* ce */ (const void *)&gLegacyMap_opcode_ce_leaf, + /* cf */ (const void *)&gLegacyMap_opcode_cf_dsize, + /* d0 */ (const void *)&gLegacyMap_opcode_d0_modrmreg, + /* d1 */ (const void *)&gLegacyMap_opcode_d1_modrmreg, + /* d2 */ (const void *)&gLegacyMap_opcode_d2_modrmreg, + /* d3 */ (const void *)&gLegacyMap_opcode_d3_modrmreg, + /* d4 */ (const void *)&gLegacyMap_opcode_d4_leaf, + /* d5 */ (const void *)&gLegacyMap_opcode_d5_leaf, + /* d6 */ (const void *)&gLegacyMap_opcode_d6_leaf, + /* d7 */ (const void *)&gLegacyMap_opcode_d7_leaf, + /* d8 */ (const void *)&gLegacyMap_opcode_d8_modrmreg, + /* d9 */ (const void *)&gLegacyMap_opcode_d9_modrmreg, + /* da */ (const void *)&gLegacyMap_opcode_da_modrmreg, + /* db */ (const void *)&gLegacyMap_opcode_db_modrmreg, + /* dc */ (const void *)&gLegacyMap_opcode_dc_modrmreg, + /* dd */ (const void *)&gLegacyMap_opcode_dd_modrmreg, + /* de */ (const void *)&gLegacyMap_opcode_de_modrmreg, + /* df */ (const void *)&gLegacyMap_opcode_df_modrmreg, + /* e0 */ (const void *)&gLegacyMap_opcode_e0_leaf, + /* e1 */ (const void *)&gLegacyMap_opcode_e1_leaf, + /* e2 */ (const void *)&gLegacyMap_opcode_e2_leaf, + /* e3 */ (const void *)&gLegacyMap_opcode_e3_asize, + /* e4 */ (const void *)&gLegacyMap_opcode_e4_leaf, + /* e5 */ (const void *)&gLegacyMap_opcode_e5_leaf, + /* e6 */ (const void *)&gLegacyMap_opcode_e6_leaf, + /* e7 */ (const void *)&gLegacyMap_opcode_e7_leaf, + /* e8 */ (const void *)&gLegacyMap_opcode_e8_leaf, + /* e9 */ (const void *)&gLegacyMap_opcode_e9_leaf, + /* ea */ (const void *)&gLegacyMap_opcode_ea_leaf, + /* eb */ (const void *)&gLegacyMap_opcode_eb_leaf, + /* ec */ (const void *)&gLegacyMap_opcode_ec_leaf, + /* ed */ (const void *)&gLegacyMap_opcode_ed_leaf, + /* ee */ (const void *)&gLegacyMap_opcode_ee_leaf, + /* ef */ (const void *)&gLegacyMap_opcode_ef_leaf, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)&gLegacyMap_opcode_f1_leaf, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)&gLegacyMap_opcode_f4_leaf, + /* f5 */ (const void *)&gLegacyMap_opcode_f5_leaf, + /* f6 */ (const void *)&gLegacyMap_opcode_f6_modrmreg, + /* f7 */ (const void *)&gLegacyMap_opcode_f7_modrmreg, + /* f8 */ (const void *)&gLegacyMap_opcode_f8_leaf, + /* f9 */ (const void *)&gLegacyMap_opcode_f9_leaf, + /* fa */ (const void *)&gLegacyMap_opcode_fa_leaf, + /* fb */ (const void *)&gLegacyMap_opcode_fb_leaf, + /* fc */ (const void *)&gLegacyMap_opcode_fc_leaf, + /* fd */ (const void *)&gLegacyMap_opcode_fd_leaf, + /* fe */ (const void *)&gLegacyMap_opcode_fe_modrmreg, + /* ff */ (const void *)&gLegacyMap_opcode_ff_modrmreg, + } +}; + + +#endif + diff --git a/bddisasm/include/bdx86_table_vex.h b/bddisasm/include/bdx86_table_vex.h new file mode 100644 index 0000000..6a0261c --- /dev/null +++ b/bddisasm/include/bdx86_table_vex.h @@ -0,0 +1,13464 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + +#ifndef BDX86_TABLE_VEX_H +#define BDX86_TABLE_VEX_H + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2652] // URDMSR Rq,Id +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2656] // UWRMSR Id,Rq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod_01_l, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_07_opcode_f8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_02_modrmreg, + /* 03 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp_03_modrmreg, + } +}; + +const ND_TABLE_OPCODE gVexMap_mmmmm_07_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)&gVexMap_mmmmm_07_opcode_f8_pp, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2190] // RORX Gy,Ey,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_f0_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_f0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2682] // VAESKEYGENASSIST Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_df_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3924] // VSM3RNDS2 Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_de_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3115] // VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_cf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_cf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3117] // VGF2P8AFFINEQB Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_ce_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_ce_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3073] // VFNMSUBSD Vdq,Hdq,Ldq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3072] // VFNMSUBSD Vdq,Hdq,Wsd,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3075] // VFNMSUBSS Vdq,Hdq,Ldq,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3074] // VFNMSUBSS Vdq,Hdq,Wss,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3069] // VFNMSUBPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3068] // VFNMSUBPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3071] // VFNMSUBPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3070] // VFNMSUBPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3035] // VFNMADDSD Vdq,Hdq,Ldq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3034] // VFNMADDSD Vdq,Hdq,Wsd,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3037] // VFNMADDSS Vdq,Hdq,Ldq,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3036] // VFNMADDSS Vdq,Hdq,Wss,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_7a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_7a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3031] // VFNMADDPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3030] // VFNMADDPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_79_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_79_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3033] // VFNMADDPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3032] // VFNMADDPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_78_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_78_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2995] // VFMSUBSD Vdq,Hdq,Ldq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2994] // VFMSUBSD Vdq,Hdq,Wsd,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2997] // VFMSUBSS Vdq,Hdq,Ldq,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2996] // VFMSUBSS Vdq,Hdq,Wss,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2991] // VFMSUBPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2990] // VFMSUBPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2993] // VFMSUBPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2992] // VFMSUBPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2919] // VFMADDSD Vdq,Hdq,Ldq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2918] // VFMADDSD Vdq,Hdq,Wsd,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2921] // VFMADDSS Vdq,Hdq,Ldq,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2920] // VFMADDSS Vdq,Hdq,Wss,Ldq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_6a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_6a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2915] // VFMADDPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2914] // VFMADDPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_69_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_69_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2917] // VFMADDPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2916] // VFMADDPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_68_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_68_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3397] // VPCMPISTRI Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_63_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_63_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3398] // VPCMPISTRM Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_62_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_62_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3387] // VPCMPESTRI Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_61_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_61_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3388] // VPCMPESTRM Vdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_60_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_60_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2987] // VFMSUBADDPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2986] // VFMSUBADDPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2989] // VFMSUBADDPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2988] // VFMSUBADDPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2938] // VFMADDSUBPD Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2937] // VFMADDSUBPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2940] // VFMADDSUBPS Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2939] // VFMADDSUBPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_5c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3357] // VPBLENDVB Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2699] // VBLENDVPD Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2700] // VBLENDVPS Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_4a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3451] // VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3450] // VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_49_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_49_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3453] // VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3452] // VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_48_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_48_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3440] // VPERM2I128 Vqq,Hqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_46_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_46_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_44_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3374] // VPCLMULQDQ Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_44_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_42_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3281] // VMPSADBW Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2852] // VDPPD Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_41_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_41_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_40_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2853] // VDPPS Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_40_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2865] // VEXTRACTI128 Wdq,Vqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_39_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_39_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3129] // VINSERTI128 Vqq,Hqq,Wdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_38_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_38_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1288] // KSHIFTLQ rKq,mKq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1287] // KSHIFTLD rKd,mKd,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_33_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1289] // KSHIFTLW rKw,mKw,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1286] // KSHIFTLB rKb,mKb,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_32_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1292] // KSHIFTRQ rKq,mKq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1291] // KSHIFTRD rKd,mKd,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_31_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1293] // KSHIFTRW rKw,mKw,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1290] // KSHIFTRB rKb,mKb,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_30_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3538] // VPINSRQ Vdq,Hdq,Ey,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3536] // VPINSRD Vdq,Hdq,Ey,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_22_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_22_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3137] // VINSERTPS Vdq,Hdq,Udq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3136] // VINSERTPS Vdq,Hdq,Md,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_21_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3534] // VPINSRB Vdq,Hdq,Rd,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3533] // VPINSRB Vdq,Hdq,Mb,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_20_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2774] // VCVTPS2PH Wdq,Vqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2773] // VCVTPS2PH Wq,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_1d_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_1d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2860] // VEXTRACTF128 Wdq,Vqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_19_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_19_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3124] // VINSERTF128 Vqq,Hqq,Wdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_18_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2873] // VEXTRACTPS Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2872] // VEXTRACTPS Md,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3494] // VPEXTRQ Ry,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3490] // VPEXTRD Ry,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3493] // VPEXTRQ Mq,Vdq,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3489] // VPEXTRD Md,Vdq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3500] // VPEXTRW Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3499] // VPEXTRW Mw,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3486] // VPEXTRB Ry,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3485] // VPEXTRB Mb,Vdq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3341] // VPALIGNR Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3358] // VPBLENDW Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2697] // VBLENDPD Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2698] // VBLENDPS Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3879] // VROUNDSD Vsd,Hsd,Wsd,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_0a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3880] // VROUNDSS Vss,Hss,Wss,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_0a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_09_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3877] // VROUNDPD Vx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_09_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_08_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3878] // VROUNDPS Vx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_08_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3439] // VPERM2F128 Vqq,Hqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_06_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_06_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3457] // VPERMILPD Vx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_05_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_05_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3461] // VPERMILPS Vx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_04_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_04_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3352] // VPBLENDD Vx,Hx,Wx,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_02_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_02_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3465] // VPERMPD Vqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_01_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_01_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3471] // VPERMQ Vqq,Wqq,Ib +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_03_opcode_00_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_03_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gVexMap_mmmmm_03_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gVexMap_mmmmm_03_opcode_00_pp, + /* 01 */ (const void *)&gVexMap_mmmmm_03_opcode_01_pp, + /* 02 */ (const void *)&gVexMap_mmmmm_03_opcode_02_pp, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gVexMap_mmmmm_03_opcode_04_pp, + /* 05 */ (const void *)&gVexMap_mmmmm_03_opcode_05_pp, + /* 06 */ (const void *)&gVexMap_mmmmm_03_opcode_06_pp, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gVexMap_mmmmm_03_opcode_08_pp, + /* 09 */ (const void *)&gVexMap_mmmmm_03_opcode_09_pp, + /* 0a */ (const void *)&gVexMap_mmmmm_03_opcode_0a_pp, + /* 0b */ (const void *)&gVexMap_mmmmm_03_opcode_0b_pp, + /* 0c */ (const void *)&gVexMap_mmmmm_03_opcode_0c_pp, + /* 0d */ (const void *)&gVexMap_mmmmm_03_opcode_0d_pp, + /* 0e */ (const void *)&gVexMap_mmmmm_03_opcode_0e_pp, + /* 0f */ (const void *)&gVexMap_mmmmm_03_opcode_0f_pp, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)&gVexMap_mmmmm_03_opcode_14_pp, + /* 15 */ (const void *)&gVexMap_mmmmm_03_opcode_15_pp, + /* 16 */ (const void *)&gVexMap_mmmmm_03_opcode_16_pp, + /* 17 */ (const void *)&gVexMap_mmmmm_03_opcode_17_pp, + /* 18 */ (const void *)&gVexMap_mmmmm_03_opcode_18_pp, + /* 19 */ (const void *)&gVexMap_mmmmm_03_opcode_19_pp, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)&gVexMap_mmmmm_03_opcode_1d_pp, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gVexMap_mmmmm_03_opcode_20_pp, + /* 21 */ (const void *)&gVexMap_mmmmm_03_opcode_21_pp, + /* 22 */ (const void *)&gVexMap_mmmmm_03_opcode_22_pp, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)&gVexMap_mmmmm_03_opcode_30_pp, + /* 31 */ (const void *)&gVexMap_mmmmm_03_opcode_31_pp, + /* 32 */ (const void *)&gVexMap_mmmmm_03_opcode_32_pp, + /* 33 */ (const void *)&gVexMap_mmmmm_03_opcode_33_pp, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)&gVexMap_mmmmm_03_opcode_38_pp, + /* 39 */ (const void *)&gVexMap_mmmmm_03_opcode_39_pp, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)&gVexMap_mmmmm_03_opcode_40_pp, + /* 41 */ (const void *)&gVexMap_mmmmm_03_opcode_41_pp, + /* 42 */ (const void *)&gVexMap_mmmmm_03_opcode_42_pp, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)&gVexMap_mmmmm_03_opcode_44_pp, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)&gVexMap_mmmmm_03_opcode_46_pp, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)&gVexMap_mmmmm_03_opcode_48_pp, + /* 49 */ (const void *)&gVexMap_mmmmm_03_opcode_49_pp, + /* 4a */ (const void *)&gVexMap_mmmmm_03_opcode_4a_pp, + /* 4b */ (const void *)&gVexMap_mmmmm_03_opcode_4b_pp, + /* 4c */ (const void *)&gVexMap_mmmmm_03_opcode_4c_pp, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)&gVexMap_mmmmm_03_opcode_5c_pp, + /* 5d */ (const void *)&gVexMap_mmmmm_03_opcode_5d_pp, + /* 5e */ (const void *)&gVexMap_mmmmm_03_opcode_5e_pp, + /* 5f */ (const void *)&gVexMap_mmmmm_03_opcode_5f_pp, + /* 60 */ (const void *)&gVexMap_mmmmm_03_opcode_60_pp, + /* 61 */ (const void *)&gVexMap_mmmmm_03_opcode_61_pp, + /* 62 */ (const void *)&gVexMap_mmmmm_03_opcode_62_pp, + /* 63 */ (const void *)&gVexMap_mmmmm_03_opcode_63_pp, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)&gVexMap_mmmmm_03_opcode_68_pp, + /* 69 */ (const void *)&gVexMap_mmmmm_03_opcode_69_pp, + /* 6a */ (const void *)&gVexMap_mmmmm_03_opcode_6a_pp, + /* 6b */ (const void *)&gVexMap_mmmmm_03_opcode_6b_pp, + /* 6c */ (const void *)&gVexMap_mmmmm_03_opcode_6c_pp, + /* 6d */ (const void *)&gVexMap_mmmmm_03_opcode_6d_pp, + /* 6e */ (const void *)&gVexMap_mmmmm_03_opcode_6e_pp, + /* 6f */ (const void *)&gVexMap_mmmmm_03_opcode_6f_pp, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)&gVexMap_mmmmm_03_opcode_78_pp, + /* 79 */ (const void *)&gVexMap_mmmmm_03_opcode_79_pp, + /* 7a */ (const void *)&gVexMap_mmmmm_03_opcode_7a_pp, + /* 7b */ (const void *)&gVexMap_mmmmm_03_opcode_7b_pp, + /* 7c */ (const void *)&gVexMap_mmmmm_03_opcode_7c_pp, + /* 7d */ (const void *)&gVexMap_mmmmm_03_opcode_7d_pp, + /* 7e */ (const void *)&gVexMap_mmmmm_03_opcode_7e_pp, + /* 7f */ (const void *)&gVexMap_mmmmm_03_opcode_7f_pp, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)&gVexMap_mmmmm_03_opcode_ce_pp, + /* cf */ (const void *)&gVexMap_mmmmm_03_opcode_cf_pp, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)&gVexMap_mmmmm_03_opcode_de_pp, + /* df */ (const void *)&gVexMap_mmmmm_03_opcode_df_pp, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)&gVexMap_mmmmm_03_opcode_f0_pp, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2505] // SHRX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2286] // SARX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2443] // SHLX Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 196] // BEXTR Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f7_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1494] // MULX Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f6_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1721] // PDEP Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1723] // PEXT Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 247] // BZHI Gy,Ey,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f5_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 210] // BLSI By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 214] // BLSMSK By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 217] // BLSR By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg_03_l, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 184] // ANDN Gy,By,Ey +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_f2_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 646] // CMPNLEXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ef_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 638] // CMPLEXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ee_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 648] // CMPNLXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ed_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 640] // CMPLXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ec_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 652] // CMPNPXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_eb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 662] // CMPPXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ea_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 654] // CMPNSXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 674] // CMPSXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 642] // CMPNBEXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 634] // CMPBEXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 656] // CMPNZXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 680] // CMPZXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 644] // CMPNCXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 636] // CMPCXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 650] // CMPNOXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 658] // CMPOXADD My,Gy,By +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_e0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_df_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2676] // VAESDECLAST Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_de_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2674] // VAESDEC Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2680] // VAESENCLAST Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_dc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2678] // VAESENC Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_dc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2681] // VAESIMC Vdq,Wdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_db_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_db_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3926] // VSM4RNDS4 Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3925] // VSM4KEY4 Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3923] // VSM3MSG2 Vdq,Hdq,Wdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3922] // VSM3MSG1 Vdq,Hdq,Wdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_da_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_da_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_02_w, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3434] // VPDPWSUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3436] // VPDPWUSDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3438] // VPDPWUUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d3_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3433] // VPDPWSUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3435] // VPDPWUSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3437] // VPDPWUUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_d2_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3119] // VGF2P8MULB Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3912] // VSHA512MSG2 Vqq,Uqq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3911] // VSHA512MSG1 Vqq,Udq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3913] // VSHA512RNDS2 Vqq,Hqq,Udq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_cb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3064] // VFNMSUB231SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3067] // VFNMSUB231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bf_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bf_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3059] // VFNMSUB231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3062] // VFNMSUB231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_be_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_be_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3026] // VFNMADD231SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3029] // VFNMADD231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bd_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3021] // VFNMADD231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3024] // VFNMADD231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bc_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2967] // VFMSUB231SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2970] // VFMSUB231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_bb_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_bb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2962] // VFMSUB231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2965] // VFMSUB231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ba_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ba_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2908] // VFMADD231SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2911] // VFMADD231SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2903] // VFMADD231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2906] // VFMADD231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2982] // VFMSUBADD231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2985] // VFMSUBADD231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2933] // VFMADDSUB231PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2936] // VFMADDSUB231PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3558] // VPMADD52HUQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b5_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3560] // VPMADD52LUQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b4_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2693] // VBCSTNEBF162PS Vx,Mw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2694] // VBCSTNESH2PS Vx,Mw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2743] // VCVTNEOBF162PS Vx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2741] // VCVTNEEBF162PS Vx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2742] // VCVTNEEPH2PS Vx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2744] // VCVTNEOPH2PS Vx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_b0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3054] // VFNMSUB213SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3057] // VFNMSUB213SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_af_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_af_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3049] // VFNMSUB213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3052] // VFNMSUB213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ae_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ae_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3016] // VFNMADD213SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3019] // VFNMADD213SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ad_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ad_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3011] // VFNMADD213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3014] // VFNMADD213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ac_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ac_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2957] // VFMSUB213SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2960] // VFMSUB213SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_ab_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_ab_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2952] // VFMSUB213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2955] // VFMSUB213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_aa_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_aa_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2898] // VFMADD213SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2901] // VFMADD213SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a9_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2893] // VFMADD213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2896] // VFMADD213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a8_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2977] // VFMSUBADD213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2980] // VFMSUBADD213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a7_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2928] // VFMADDSUB213PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2931] // VFMADDSUB213PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_a6_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_a6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3044] // VFNMSUB132SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3047] // VFNMSUB132SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3039] // VFNMSUB132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3042] // VFNMSUB132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3006] // VFNMADD132SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3009] // VFNMADD132SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3001] // VFNMADD132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3004] // VFNMADD132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2947] // VFMSUB132SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2950] // VFMSUB132SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9b_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2942] // VFMSUB132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2945] // VFMSUB132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_9a_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_9a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2888] // VFMADD132SD Vdq,Hdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2891] // VFMADD132SS Vdq,Hdq,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_99_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_99_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2883] // VFMADD132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2886] // VFMADD132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_98_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_98_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2972] // VFMSUBADD132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2975] // VFMSUBADD132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_97_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_97_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2923] // VFMADDSUB132PD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2926] // VFMADDSUB132PS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_96_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_96_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3099] // VGATHERQPD Vx,Mvm64n,Hx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3101] // VGATHERQPS Vdq,Mvm64n,Hdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_93_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3087] // VGATHERDPD Vx,Mvm32h,Hx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3089] // VGATHERDPS Vx,Mvm32n,Hx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_92_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3508] // VPGATHERQQ Vx,Mvm64n,Hx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3506] // VPGATHERQD Vdq,Mvm64n,Hdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_91_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3504] // VPGATHERDQ Vx,Mvm32h,Hx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3502] // VPGATHERDD Vx,Mvm32n,Hx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_90_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3568] // VPMASKMOVQ Mx,Hx,Vx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3566] // VPMASKMOVD Mx,Hx,Vx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3567] // VPMASKMOVQ Vx,Hx,Mx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3565] // VPMASKMOVD Vx,Hx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w_01_leaf, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_8c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3372] // VPBROADCASTW Vx,Ww +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_79_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_79_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3361] // VPBROADCASTB Vx,Wb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_78_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_78_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2746] // VCVTNEPS2BF16 Vx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_72_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_72_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp_02_w, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2603] // TCMMIMFP16PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2604] // TCMMRLFP16PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_6c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2607] // TDPBSSD rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2608] // TDPBSUD rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2609] // TDPBUSD rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2610] // TDPBUUD rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2611] // TDPFP16PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2606] // TDPBF16PS rTt,mTt,vTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2707] // VBROADCASTI128 Vqq,Mdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_5a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3369] // VPBROADCASTQ Vx,Wq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_59_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_59_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3364] // VPBROADCASTD Vx,Wd +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_58_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_58_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3432] // VPDPWSSDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_53_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_53_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3430] // VPDPWSSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_52_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_52_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3420] // VPDPBSSDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3422] // VPDPBSUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3426] // VPDPBUSDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3428] // VPDPBUUDS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_51_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_02_w, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3419] // VPDPBSSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_03_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_03_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3421] // VPDPBSUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_02_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_02_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3424] // VPDPBUSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3427] // VPDPBUUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_50_pp_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_50_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_01_w, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_02_w, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp_03_w, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2622] // TILELOADD rTt,Mt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2627] // TILESTORED Mt,rTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2624] // TILELOADDT1 rTt,Mt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_4b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2628] // TILEZERO rTt +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_RM gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2537] // STTILECFG Moq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2625] // TILERELEASE +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_RM gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm = +{ + ND_ILUT_MODRM_RM, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1316] // LDTILECFG Moq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod_01_modrmrm, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_49_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_00_modrmreg, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3764] // VPSLLVQ Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3762] // VPSLLVD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_47_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_47_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3777] // VPSRAVD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_46_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_46_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3797] // VPSRLVQ Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3795] // VPSRLVD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_45_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_45_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3524] // VPHMINPOSUW Vdq,Wdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_41_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_41_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_40_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3669] // VPMULLD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_40_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_40_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3579] // VPMAXUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3f_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3582] // VPMAXUW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3572] // VPMAXSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3570] // VPMAXSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3593] // VPMINUD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_3a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3596] // VPMINUW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_3a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_3a_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_39_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3586] // VPMINSD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_39_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_39_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_38_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3584] // VPMINSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_38_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_38_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_37_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3394] // VPCMPGTQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_37_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_37_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3443] // VPERMD Vqq,Hqq,Wqq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_36_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_36_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3653] // VPMOVZXDQ Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3652] // VPMOVZXDQ Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_35_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_35_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3659] // VPMOVZXWQ Vqq,Wq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3658] // VPMOVZXWQ Vdq,Wd +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_34_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_34_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3656] // VPMOVZXWD Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3655] // VPMOVZXWD Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_33_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_33_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3647] // VPMOVZXBQ Vqq,Wd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3646] // VPMOVZXBQ Vdq,Ww +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_32_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_32_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3644] // VPMOVZXBD Vqq,Wq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3643] // VPMOVZXBD Vdq,Wd +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_31_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_31_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3650] // VPMOVZXBW Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3649] // VPMOVZXBW Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_30_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_30_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3142] // VMASKMOVPD Mx,Hx,Vx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3144] // VMASKMOVPS Mx,Hx,Vx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3141] // VMASKMOVPD Vx,Hx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3143] // VMASKMOVPS Vx,Hx,Mx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod_00_w, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3321] // VPACKUSDW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3232] // VMOVNTDQA Vx,Mx +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_29_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3384] // VPCMPEQQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_29_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_29_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_28_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3661] // VPMULDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_28_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_28_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3627] // VPMOVSXDQ Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3626] // VPMOVSXDQ Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_25_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_25_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3633] // VPMOVSXWQ Vqq,Wq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3632] // VPMOVSXWQ Vdq,Wd +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_24_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_24_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3630] // VPMOVSXWD Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3629] // VPMOVSXWD Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_23_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_23_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3621] // VPMOVSXBQ Vqq,Wd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3620] // VPMOVSXBQ Vdq,Ww +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_22_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_22_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3618] // VPMOVSXBD Vqq,Wq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3617] // VPMOVSXBD Vdq,Wd +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_21_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_21_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3624] // VPMOVSXBW Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3623] // VPMOVSXBW Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_20_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_20_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3312] // VPABSD Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3315] // VPABSW Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3310] // VPABSB Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2701] // VBROADCASTF128 Vqq,Mdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_1a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2714] // VBROADCASTSD Vqq,Wsd +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_19_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_19_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2716] // VBROADCASTSS Vx,Wss +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_18_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_18_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_17_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3821] // VPTEST Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_17_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3468] // VPERMPS Vqq,Hqq,Wqq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_16_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2760] // VCVTPH2PS Vqq,Wdq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2759] // VCVTPH2PS Vdq,Wq +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_02_opcode_13_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_00_w, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3948] // VTESTPD Vx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0f_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3949] // VTESTPS Vx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0e_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3456] // VPERMILPD Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0d_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3460] // VPERMILPS Vx,Hx,Wx +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_02_opcode_0c_pp_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3663] // VPMULHRSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_0a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3749] // VPSIGND Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_0a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_0a_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_09_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3750] // VPSIGNW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_09_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_09_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_08_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3748] // VPSIGNB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_08_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_08_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_07_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3528] // VPHSUBSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_07_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_07_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_06_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3526] // VPHSUBD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_06_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_06_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_05_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3529] // VPHSUBW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_05_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_05_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_04_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3562] // VPMADDUBSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_04_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_04_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_03_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3514] // VPHADDSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_03_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_03_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_02_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3512] // VPHADDD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_02_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_02_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_01_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3521] // VPHADDW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_01_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_01_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_02_opcode_00_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3740] // VPSHUFB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_02_opcode_00_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_00_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_OPCODE gVexMap_mmmmm_02_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)&gVexMap_mmmmm_02_opcode_00_pp, + /* 01 */ (const void *)&gVexMap_mmmmm_02_opcode_01_pp, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode_02_pp, + /* 03 */ (const void *)&gVexMap_mmmmm_02_opcode_03_pp, + /* 04 */ (const void *)&gVexMap_mmmmm_02_opcode_04_pp, + /* 05 */ (const void *)&gVexMap_mmmmm_02_opcode_05_pp, + /* 06 */ (const void *)&gVexMap_mmmmm_02_opcode_06_pp, + /* 07 */ (const void *)&gVexMap_mmmmm_02_opcode_07_pp, + /* 08 */ (const void *)&gVexMap_mmmmm_02_opcode_08_pp, + /* 09 */ (const void *)&gVexMap_mmmmm_02_opcode_09_pp, + /* 0a */ (const void *)&gVexMap_mmmmm_02_opcode_0a_pp, + /* 0b */ (const void *)&gVexMap_mmmmm_02_opcode_0b_pp, + /* 0c */ (const void *)&gVexMap_mmmmm_02_opcode_0c_pp, + /* 0d */ (const void *)&gVexMap_mmmmm_02_opcode_0d_pp, + /* 0e */ (const void *)&gVexMap_mmmmm_02_opcode_0e_pp, + /* 0f */ (const void *)&gVexMap_mmmmm_02_opcode_0f_pp, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)&gVexMap_mmmmm_02_opcode_13_pp, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)&gVexMap_mmmmm_02_opcode_16_pp, + /* 17 */ (const void *)&gVexMap_mmmmm_02_opcode_17_pp, + /* 18 */ (const void *)&gVexMap_mmmmm_02_opcode_18_pp, + /* 19 */ (const void *)&gVexMap_mmmmm_02_opcode_19_pp, + /* 1a */ (const void *)&gVexMap_mmmmm_02_opcode_1a_pp, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)&gVexMap_mmmmm_02_opcode_1c_pp, + /* 1d */ (const void *)&gVexMap_mmmmm_02_opcode_1d_pp, + /* 1e */ (const void *)&gVexMap_mmmmm_02_opcode_1e_pp, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)&gVexMap_mmmmm_02_opcode_20_pp, + /* 21 */ (const void *)&gVexMap_mmmmm_02_opcode_21_pp, + /* 22 */ (const void *)&gVexMap_mmmmm_02_opcode_22_pp, + /* 23 */ (const void *)&gVexMap_mmmmm_02_opcode_23_pp, + /* 24 */ (const void *)&gVexMap_mmmmm_02_opcode_24_pp, + /* 25 */ (const void *)&gVexMap_mmmmm_02_opcode_25_pp, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gVexMap_mmmmm_02_opcode_28_pp, + /* 29 */ (const void *)&gVexMap_mmmmm_02_opcode_29_pp, + /* 2a */ (const void *)&gVexMap_mmmmm_02_opcode_2a_pp, + /* 2b */ (const void *)&gVexMap_mmmmm_02_opcode_2b_pp, + /* 2c */ (const void *)&gVexMap_mmmmm_02_opcode_2c_pp, + /* 2d */ (const void *)&gVexMap_mmmmm_02_opcode_2d_pp, + /* 2e */ (const void *)&gVexMap_mmmmm_02_opcode_2e_pp, + /* 2f */ (const void *)&gVexMap_mmmmm_02_opcode_2f_pp, + /* 30 */ (const void *)&gVexMap_mmmmm_02_opcode_30_pp, + /* 31 */ (const void *)&gVexMap_mmmmm_02_opcode_31_pp, + /* 32 */ (const void *)&gVexMap_mmmmm_02_opcode_32_pp, + /* 33 */ (const void *)&gVexMap_mmmmm_02_opcode_33_pp, + /* 34 */ (const void *)&gVexMap_mmmmm_02_opcode_34_pp, + /* 35 */ (const void *)&gVexMap_mmmmm_02_opcode_35_pp, + /* 36 */ (const void *)&gVexMap_mmmmm_02_opcode_36_pp, + /* 37 */ (const void *)&gVexMap_mmmmm_02_opcode_37_pp, + /* 38 */ (const void *)&gVexMap_mmmmm_02_opcode_38_pp, + /* 39 */ (const void *)&gVexMap_mmmmm_02_opcode_39_pp, + /* 3a */ (const void *)&gVexMap_mmmmm_02_opcode_3a_pp, + /* 3b */ (const void *)&gVexMap_mmmmm_02_opcode_3b_pp, + /* 3c */ (const void *)&gVexMap_mmmmm_02_opcode_3c_pp, + /* 3d */ (const void *)&gVexMap_mmmmm_02_opcode_3d_pp, + /* 3e */ (const void *)&gVexMap_mmmmm_02_opcode_3e_pp, + /* 3f */ (const void *)&gVexMap_mmmmm_02_opcode_3f_pp, + /* 40 */ (const void *)&gVexMap_mmmmm_02_opcode_40_pp, + /* 41 */ (const void *)&gVexMap_mmmmm_02_opcode_41_pp, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)&gVexMap_mmmmm_02_opcode_45_pp, + /* 46 */ (const void *)&gVexMap_mmmmm_02_opcode_46_pp, + /* 47 */ (const void *)&gVexMap_mmmmm_02_opcode_47_pp, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)&gVexMap_mmmmm_02_opcode_49_pp, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)&gVexMap_mmmmm_02_opcode_4b_pp, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)&gVexMap_mmmmm_02_opcode_50_pp, + /* 51 */ (const void *)&gVexMap_mmmmm_02_opcode_51_pp, + /* 52 */ (const void *)&gVexMap_mmmmm_02_opcode_52_pp, + /* 53 */ (const void *)&gVexMap_mmmmm_02_opcode_53_pp, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)&gVexMap_mmmmm_02_opcode_58_pp, + /* 59 */ (const void *)&gVexMap_mmmmm_02_opcode_59_pp, + /* 5a */ (const void *)&gVexMap_mmmmm_02_opcode_5a_pp, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)&gVexMap_mmmmm_02_opcode_5c_pp, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)&gVexMap_mmmmm_02_opcode_5e_pp, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)&gVexMap_mmmmm_02_opcode_6c_pp, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)&gVexMap_mmmmm_02_opcode_72_pp, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)&gVexMap_mmmmm_02_opcode_78_pp, + /* 79 */ (const void *)&gVexMap_mmmmm_02_opcode_79_pp, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)&gVexMap_mmmmm_02_opcode_8c_pp, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)&gVexMap_mmmmm_02_opcode_8e_pp, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)&gVexMap_mmmmm_02_opcode_90_pp, + /* 91 */ (const void *)&gVexMap_mmmmm_02_opcode_91_pp, + /* 92 */ (const void *)&gVexMap_mmmmm_02_opcode_92_pp, + /* 93 */ (const void *)&gVexMap_mmmmm_02_opcode_93_pp, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)&gVexMap_mmmmm_02_opcode_96_pp, + /* 97 */ (const void *)&gVexMap_mmmmm_02_opcode_97_pp, + /* 98 */ (const void *)&gVexMap_mmmmm_02_opcode_98_pp, + /* 99 */ (const void *)&gVexMap_mmmmm_02_opcode_99_pp, + /* 9a */ (const void *)&gVexMap_mmmmm_02_opcode_9a_pp, + /* 9b */ (const void *)&gVexMap_mmmmm_02_opcode_9b_pp, + /* 9c */ (const void *)&gVexMap_mmmmm_02_opcode_9c_pp, + /* 9d */ (const void *)&gVexMap_mmmmm_02_opcode_9d_pp, + /* 9e */ (const void *)&gVexMap_mmmmm_02_opcode_9e_pp, + /* 9f */ (const void *)&gVexMap_mmmmm_02_opcode_9f_pp, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)&gVexMap_mmmmm_02_opcode_a6_pp, + /* a7 */ (const void *)&gVexMap_mmmmm_02_opcode_a7_pp, + /* a8 */ (const void *)&gVexMap_mmmmm_02_opcode_a8_pp, + /* a9 */ (const void *)&gVexMap_mmmmm_02_opcode_a9_pp, + /* aa */ (const void *)&gVexMap_mmmmm_02_opcode_aa_pp, + /* ab */ (const void *)&gVexMap_mmmmm_02_opcode_ab_pp, + /* ac */ (const void *)&gVexMap_mmmmm_02_opcode_ac_pp, + /* ad */ (const void *)&gVexMap_mmmmm_02_opcode_ad_pp, + /* ae */ (const void *)&gVexMap_mmmmm_02_opcode_ae_pp, + /* af */ (const void *)&gVexMap_mmmmm_02_opcode_af_pp, + /* b0 */ (const void *)&gVexMap_mmmmm_02_opcode_b0_pp, + /* b1 */ (const void *)&gVexMap_mmmmm_02_opcode_b1_pp, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)&gVexMap_mmmmm_02_opcode_b4_pp, + /* b5 */ (const void *)&gVexMap_mmmmm_02_opcode_b5_pp, + /* b6 */ (const void *)&gVexMap_mmmmm_02_opcode_b6_pp, + /* b7 */ (const void *)&gVexMap_mmmmm_02_opcode_b7_pp, + /* b8 */ (const void *)&gVexMap_mmmmm_02_opcode_b8_pp, + /* b9 */ (const void *)&gVexMap_mmmmm_02_opcode_b9_pp, + /* ba */ (const void *)&gVexMap_mmmmm_02_opcode_ba_pp, + /* bb */ (const void *)&gVexMap_mmmmm_02_opcode_bb_pp, + /* bc */ (const void *)&gVexMap_mmmmm_02_opcode_bc_pp, + /* bd */ (const void *)&gVexMap_mmmmm_02_opcode_bd_pp, + /* be */ (const void *)&gVexMap_mmmmm_02_opcode_be_pp, + /* bf */ (const void *)&gVexMap_mmmmm_02_opcode_bf_pp, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)&gVexMap_mmmmm_02_opcode_cb_pp, + /* cc */ (const void *)&gVexMap_mmmmm_02_opcode_cc_pp, + /* cd */ (const void *)&gVexMap_mmmmm_02_opcode_cd_pp, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)&gVexMap_mmmmm_02_opcode_cf_pp, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)&gVexMap_mmmmm_02_opcode_d2_pp, + /* d3 */ (const void *)&gVexMap_mmmmm_02_opcode_d3_pp, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)&gVexMap_mmmmm_02_opcode_da_pp, + /* db */ (const void *)&gVexMap_mmmmm_02_opcode_db_pp, + /* dc */ (const void *)&gVexMap_mmmmm_02_opcode_dc_pp, + /* dd */ (const void *)&gVexMap_mmmmm_02_opcode_dd_pp, + /* de */ (const void *)&gVexMap_mmmmm_02_opcode_de_pp, + /* df */ (const void *)&gVexMap_mmmmm_02_opcode_df_pp, + /* e0 */ (const void *)&gVexMap_mmmmm_02_opcode_e0_pp, + /* e1 */ (const void *)&gVexMap_mmmmm_02_opcode_e1_pp, + /* e2 */ (const void *)&gVexMap_mmmmm_02_opcode_e2_pp, + /* e3 */ (const void *)&gVexMap_mmmmm_02_opcode_e3_pp, + /* e4 */ (const void *)&gVexMap_mmmmm_02_opcode_e4_pp, + /* e5 */ (const void *)&gVexMap_mmmmm_02_opcode_e5_pp, + /* e6 */ (const void *)&gVexMap_mmmmm_02_opcode_e6_pp, + /* e7 */ (const void *)&gVexMap_mmmmm_02_opcode_e7_pp, + /* e8 */ (const void *)&gVexMap_mmmmm_02_opcode_e8_pp, + /* e9 */ (const void *)&gVexMap_mmmmm_02_opcode_e9_pp, + /* ea */ (const void *)&gVexMap_mmmmm_02_opcode_ea_pp, + /* eb */ (const void *)&gVexMap_mmmmm_02_opcode_eb_pp, + /* ec */ (const void *)&gVexMap_mmmmm_02_opcode_ec_pp, + /* ed */ (const void *)&gVexMap_mmmmm_02_opcode_ed_pp, + /* ee */ (const void *)&gVexMap_mmmmm_02_opcode_ee_pp, + /* ef */ (const void *)&gVexMap_mmmmm_02_opcode_ef_pp, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)&gVexMap_mmmmm_02_opcode_f2_pp, + /* f3 */ (const void *)&gVexMap_mmmmm_02_opcode_f3_pp, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)&gVexMap_mmmmm_02_opcode_f5_pp, + /* f6 */ (const void *)&gVexMap_mmmmm_02_opcode_f6_pp, + /* f7 */ (const void *)&gVexMap_mmmmm_02_opcode_f7_pp, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fe_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3327] // VPADDD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fe_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fe_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3339] // VPADDW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3325] // VPADDB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fb_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3808] // VPSUBQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fb_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_fa_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3806] // VPSUBD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_fa_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_fa_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3818] // VPSUBW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3804] // VPSUBB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3140] // VMASKMOVDQU Vdq,Udq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f6_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3706] // VPSADBW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f6_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3564] // VPMADDWD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f4_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3675] // VPMULUDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f4_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f3_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3760] // VPSLLQ Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f3_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f2_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3754] // VPSLLD Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f2_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3769] // VPSLLW Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_f1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3138] // VLDDQU Vx,Mx +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_f0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ef_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3846] // VPXOR Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ef_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ef_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ee_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3575] // VPMAXSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ee_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ee_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ed_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3333] // VPADDSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ed_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ed_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ec_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3331] // VPADDSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ec_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ec_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_eb_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3680] // VPOR Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_eb_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_eb_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ea_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3589] // VPMINSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ea_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ea_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3812] // VPSUBSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3810] // VPSUBSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3230] // VMOVNTDQ Mx,Vx +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2748] // VCVTPD2DQ Vdq,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2736] // VCVTDQ2PD Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2735] // VCVTDQ2PD Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_e6_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e6_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2805] // VCVTTPD2DQ Vdq,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_02_l, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3667] // VPMULHW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e4_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3665] // VPMULHUW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e4_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e3_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3351] // VPAVGW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e3_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e2_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3773] // VPSRAD Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e2_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3783] // VPSRAW Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_e0_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3349] // VPAVGB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_e0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_e0_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_df_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3344] // VPANDN Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_df_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_df_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_de_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3577] // VPMAXUB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_de_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_de_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dd_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3337] // VPADDUSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dd_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_dd_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_dc_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3335] // VPADDUSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_dc_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_dc_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_db_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3342] // VPAND Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_db_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_db_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_da_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3591] // VPMINUB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_da_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_da_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d9_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3816] // VPSUBUSW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d9_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d9_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d8_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3814] // VPSUBUSB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d8_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d8_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3605] // VPMOVMSKB Gy,Ux +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d7_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3244] // VMOVQ Wq,Vdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_d6_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d5_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3672] // VPMULLW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d5_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d4_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3329] // VPADDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d4_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d3_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3793] // VPSRLQ Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d3_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d3_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d2_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3787] // VPSRLD Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d2_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d1_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3802] // VPSRLW Vx,Hx,Wdq +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d1_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d1_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2672] // VADDSUBPS Vps,Hps,Wps +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_d0_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2671] // VADDSUBPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_d0_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3919] // VSHUFPD Vpd,Hpd,Wpd,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c6_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3921] // VSHUFPS Vps,Hps,Wps,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c6_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3498] // VPEXTRW Gy,Udq,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c5_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3542] // VPINSRW Vdq,Hdq,Rd,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3541] // VPINSRW Vdq,Hdq,Mw,Ib +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c4_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2723] // VCMPSD Vsd,Hsd,Wsd,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2726] // VCMPSS Vss,Hss,Wss,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2718] // VCMPPD Vpd,Hpd,Wpd,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_c2_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2721] // VCMPPS Vss,Hss,Wss,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_c2_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 563] // CLEVICT0 M? +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2515] // SPFLT Ry +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 564] // CLEVICT1 M? +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 882] // DELAY Ry +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3937] // VSTMXCSR Md +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3139] // VLDMXCSR Md +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_ae_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_00_modrmreg, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_02_modrmreg, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp_03_modrmreg, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1295] // KTESTD rKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1294] // KTESTB rKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1296] // KTESTQ rKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1297] // KTESTW rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_99_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1282] // KORTESTD rKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1281] // KORTESTB rKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1283] // KORTESTQ rKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1284] // KORTESTW rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_98_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1263] // KMOVQ Gy,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1253] // KMOVD Gy,mKd +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1243] // KMOVB Gy,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1273] // KMOVW Gy,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_93_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1262] // KMOVQ rKq,Ry +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1252] // KMOVD rKd,Ry +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1242] // KMOVB rKb,Ry +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1272] // KMOVW rKw,Ry +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_92_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1251] // KMOVD Md,rKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1241] // KMOVB Mb,rKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1261] // KMOVQ Mq,rKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1271] // KMOVW Mw,rKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_91_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1250] // KMOVD rKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1240] // KMOVB rKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1249] // KMOVD rKd,Md +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1239] // KMOVB rKb,Mb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1260] // KMOVQ rKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1270] // KMOVW rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1259] // KMOVQ rKq,Mq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1269] // KMOVW rKw,Mw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_90_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3198] // VMOVDQU Wx,Vx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3192] // VMOVDQA Wx,Vx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3243] // VMOVQ Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_02_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_02_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3242] // VMOVQ Ey,Vq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3185] // VMOVD Ey,Vd +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_7e_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp_02_l, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3123] // VHSUBPS Vps,Hps,Wps +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3122] // VHSUBPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3121] // VHADDPS Vps,Hps,Wps +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_7c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3120] // VHADDPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_7c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3967] // VZEROALL +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3968] // VZEROUPPER +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_77_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_77_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp_00_l, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_76_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3382] // VPCMPEQD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_76_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_76_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_75_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3386] // VPCMPEQW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_75_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_75_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_74_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3380] // VPCMPEQB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_74_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_74_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3756] // VPSLLDQ Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3759] // VPSLLQ Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3789] // VPSRLDQ Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3792] // VPSRLQ Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_03_modrmmod, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg_07_modrmmod, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_73_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3753] // VPSLLD Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3772] // VPSRAD Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3786] // VPSRLD Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_72_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3768] // VPSLLW Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3782] // VPSRAW Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3801] // VPSRLW Hx,Ux,Ib +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_02_modrmmod, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_04_modrmmod, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg_06_modrmmod, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_71_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp_01_modrmreg, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3747] // VPSHUFLW Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3745] // VPSHUFHW Vx,Wx,Ib +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_70_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3743] // VPSHUFD Vx,Wx,Ib +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_70_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3197] // VMOVDQU Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3191] // VMOVDQA Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3241] // VMOVQ Vdq,Ey +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3184] // VMOVD Vdq,Ey +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi = +{ + ND_ILUT_EX_WI, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_6e_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l_00_wi, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp_01_l, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3835] // VPUNPCKHQDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6d_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3843] // VPUNPCKLQDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6c_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3317] // VPACKSSDW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6b_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_6a_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3833] // VPUNPCKHDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_6a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_6a_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_69_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3837] // VPUNPCKHWD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_69_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_69_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_68_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3831] // VPUNPCKHBW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_68_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_68_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_67_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3323] // VPACKUSWB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_67_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_67_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_66_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3392] // VPCMPGTD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_66_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_66_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_65_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3396] // VPCMPGTW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_65_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_65_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_64_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3390] // VPCMPGTB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_64_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_64_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_63_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3319] // VPACKSSWB Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_63_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_63_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_62_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3841] // VPUNPCKLDQ Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_62_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_62_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_61_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3845] // VPUNPCKLWD Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_61_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_61_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_60_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3839] // VPUNPCKLBW Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_60_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_60_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3151] // VMAXSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3154] // VMAXSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3146] // VMAXPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5f_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3149] // VMAXPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2847] // VDIVSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2850] // VDIVSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2842] // VDIVPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5e_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2845] // VDIVPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3166] // VMINSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3169] // VMINSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3161] // VMINPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5d_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3164] // VMINPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3944] // VSUBSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3947] // VSUBSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3939] // VSUBPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5c_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3942] // VSUBPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2816] // VCVTTPS2DQ Vps,Wps +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2768] // VCVTPS2DQ Vps,Wps +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5b_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2739] // VCVTDQ2PS Vps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2786] // VCVTSD2SS Vss,Hx,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2799] // VCVTSS2SD Vsd,Hx,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2752] // VCVTPD2PS Vdq,Wqq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2751] // VCVTPD2PS Vdq,Wdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2771] // VCVTPS2PD Vqq,Wdq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2770] // VCVTPS2PD Vpd,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_5a_pp_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_5a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_01_l, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3294] // VMULSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3297] // VMULSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3289] // VMULPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_59_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3292] // VMULPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_59_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2667] // VADDSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2670] // VADDSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2662] // VADDPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_58_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2665] // VADDPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_58_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3964] // VXORPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_57_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3966] // VXORPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_57_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3302] // VORPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_56_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3304] // VORPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_56_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2686] // VANDNPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_55_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2688] // VANDNPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_55_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2690] // VANDPD Vpd,Hpd,Wpd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_54_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2692] // VANDPS Vps,Hps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_54_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3864] // VRCPSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_53_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3862] // VRCPPS Vps,Wps +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_53_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3892] // VRSQRTSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_52_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3890] // VRSQRTPS Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_52_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3933] // VSQRTSD Vsd,Hsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3936] // VSQRTSS Vss,Hss,Wss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3928] // VSQRTPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_51_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3931] // VSQRTPS Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_51_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3227] // VMOVMSKPD Gy,Ux +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3228] // VMOVMSKPS Gy,Ux +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_50_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1298] // KUNPCKBW rKw,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1299] // KUNPCKDQ rKq,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1300] // KUNPCKWD rKd,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1221] // KADDD rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1220] // KADDB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1222] // KADDQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1223] // KADDW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_4a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1233] // KMERGE2L1L rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_49_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1232] // KMERGE2L1H rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_48_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp_00_modrmmod, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1306] // KXORD rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1305] // KXORB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1307] // KXORQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1308] // KXORW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_47_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1302] // KXNORD rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1301] // KXNORB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1303] // KXNORQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1304] // KXNORW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_46_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1279] // KORD rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1278] // KORB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1280] // KORQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1285] // KORW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_45_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1275] // KNOTD rKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1274] // KNOTB rKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1276] // KNOTQ rKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1277] // KNOTW rKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l_00_w, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_44_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1227] // KANDND rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1226] // KANDNB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1228] // KANDNQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1229] // KANDNW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_42_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1225] // KANDD rKd,vKd,mKd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1224] // KANDB rKb,vKb,mKb +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod_01_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1230] // KANDQ rKq,vKq,mKq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1231] // KANDW rKw,vKw,mKw +}; + +const ND_TABLE_EX_W gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w_01_leaf, + } +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l_01_w, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_41_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2728] // VCOMISD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2f_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2731] // VCOMISS Vss,Wss +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2f_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3951] // VUCOMISD Vsd,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2e_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3954] // VUCOMISS Vss,Wss +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2e_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2784] // VCVTSD2SI Gy,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2d_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2802] // VCVTSS2SI Gy,Wss +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2d_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2821] // VCVTTSD2SI Gy,Wsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2c_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2826] // VCVTTSS2SI Gy,Wss +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2c_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3234] // VMOVNTPD Mx,Vx +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3236] // VMOVNTPS Mx,Vx +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod_00_leaf, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2b_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2794] // VCVTSI2SD Vsd,Hsd,Ey +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_2a_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2797] // VCVTSI2SS Vss,Hss,Ey +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_2a_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp_03_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3177] // VMOVAPD Wx,Vx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_29_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3181] // VMOVAPS Wx,Vx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_29_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3176] // VMOVAPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_28_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3180] // VMOVAPS Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_28_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3212] // VMOVHPD Mq,Vdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3216] // VMOVHPS Mq,Vdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_17_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3258] // VMOVSHDUP Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3211] // VMOVHPD Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3218] // VMOVLHPS Vdq,Hdq,Udq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3215] // VMOVHPS Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_16_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp_02_leaf, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3956] // VUNPCKHPD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_15_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3958] // VUNPCKHPS Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_15_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3960] // VUNPCKLPD Vx,Hx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_14_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3962] // VUNPCKLPS Vx,Hx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_14_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3222] // VMOVLPD Mq,Vdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3226] // VMOVLPS Mq,Vdq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_13_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3190] // VMOVDDUP Vqq,Wqq +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3189] // VMOVDDUP Vdq,Wq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_03_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3260] // VMOVSLDUP Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3221] // VMOVLPD Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod_00_l, + /* 01 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3208] // VMOVHLPS Vdq,Hdq,Udq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3225] // VMOVLPS Vdq,Hdq,Mq +}; + +const ND_TABLE_EX_L gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l = +{ + ND_ILUT_EX_L, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l_00_leaf, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_00_l, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod_01_l, + } +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_12_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_00_modrmmod, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_01_modrmmod, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_02_leaf, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp_03_l, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3251] // VMOVSD Usd,Hsd,Vsd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3252] // VMOVSD Mq,Vsd +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3267] // VMOVSS Uss,Hss,Vss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3268] // VMOVSS Md,Vss +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3272] // VMOVUPD Wx,Vx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_11_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3276] // VMOVUPS Wx,Vx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_11_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp_03_modrmmod, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3249] // VMOVSD Vdq,Hdq,Usd +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3250] // VMOVSD Vdq,Mq +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3265] // VMOVSS Vdq,Hdq,Uss +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3266] // VMOVSS Vdq,Md +}; + +const ND_TABLE_MODRM_MOD gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3271] // VMOVUPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gVexMap_mmmmm_01_opcode_10_pp_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3275] // VMOVUPS Vx,Wx +}; + +const ND_TABLE_EX_PP gVexMap_mmmmm_01_opcode_10_pp = +{ + ND_ILUT_EX_PP, + { + /* 00 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_00_leaf, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_01_leaf, + /* 02 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_02_modrmmod, + /* 03 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp_03_modrmmod, + } +}; + +const ND_TABLE_OPCODE gVexMap_mmmmm_01_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gVexMap_mmmmm_01_opcode_10_pp, + /* 11 */ (const void *)&gVexMap_mmmmm_01_opcode_11_pp, + /* 12 */ (const void *)&gVexMap_mmmmm_01_opcode_12_pp, + /* 13 */ (const void *)&gVexMap_mmmmm_01_opcode_13_pp, + /* 14 */ (const void *)&gVexMap_mmmmm_01_opcode_14_pp, + /* 15 */ (const void *)&gVexMap_mmmmm_01_opcode_15_pp, + /* 16 */ (const void *)&gVexMap_mmmmm_01_opcode_16_pp, + /* 17 */ (const void *)&gVexMap_mmmmm_01_opcode_17_pp, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)&gVexMap_mmmmm_01_opcode_28_pp, + /* 29 */ (const void *)&gVexMap_mmmmm_01_opcode_29_pp, + /* 2a */ (const void *)&gVexMap_mmmmm_01_opcode_2a_pp, + /* 2b */ (const void *)&gVexMap_mmmmm_01_opcode_2b_pp, + /* 2c */ (const void *)&gVexMap_mmmmm_01_opcode_2c_pp, + /* 2d */ (const void *)&gVexMap_mmmmm_01_opcode_2d_pp, + /* 2e */ (const void *)&gVexMap_mmmmm_01_opcode_2e_pp, + /* 2f */ (const void *)&gVexMap_mmmmm_01_opcode_2f_pp, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)&gVexMap_mmmmm_01_opcode_41_pp, + /* 42 */ (const void *)&gVexMap_mmmmm_01_opcode_42_pp, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)&gVexMap_mmmmm_01_opcode_44_pp, + /* 45 */ (const void *)&gVexMap_mmmmm_01_opcode_45_pp, + /* 46 */ (const void *)&gVexMap_mmmmm_01_opcode_46_pp, + /* 47 */ (const void *)&gVexMap_mmmmm_01_opcode_47_pp, + /* 48 */ (const void *)&gVexMap_mmmmm_01_opcode_48_pp, + /* 49 */ (const void *)&gVexMap_mmmmm_01_opcode_49_pp, + /* 4a */ (const void *)&gVexMap_mmmmm_01_opcode_4a_pp, + /* 4b */ (const void *)&gVexMap_mmmmm_01_opcode_4b_pp, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)&gVexMap_mmmmm_01_opcode_50_pp, + /* 51 */ (const void *)&gVexMap_mmmmm_01_opcode_51_pp, + /* 52 */ (const void *)&gVexMap_mmmmm_01_opcode_52_pp, + /* 53 */ (const void *)&gVexMap_mmmmm_01_opcode_53_pp, + /* 54 */ (const void *)&gVexMap_mmmmm_01_opcode_54_pp, + /* 55 */ (const void *)&gVexMap_mmmmm_01_opcode_55_pp, + /* 56 */ (const void *)&gVexMap_mmmmm_01_opcode_56_pp, + /* 57 */ (const void *)&gVexMap_mmmmm_01_opcode_57_pp, + /* 58 */ (const void *)&gVexMap_mmmmm_01_opcode_58_pp, + /* 59 */ (const void *)&gVexMap_mmmmm_01_opcode_59_pp, + /* 5a */ (const void *)&gVexMap_mmmmm_01_opcode_5a_pp, + /* 5b */ (const void *)&gVexMap_mmmmm_01_opcode_5b_pp, + /* 5c */ (const void *)&gVexMap_mmmmm_01_opcode_5c_pp, + /* 5d */ (const void *)&gVexMap_mmmmm_01_opcode_5d_pp, + /* 5e */ (const void *)&gVexMap_mmmmm_01_opcode_5e_pp, + /* 5f */ (const void *)&gVexMap_mmmmm_01_opcode_5f_pp, + /* 60 */ (const void *)&gVexMap_mmmmm_01_opcode_60_pp, + /* 61 */ (const void *)&gVexMap_mmmmm_01_opcode_61_pp, + /* 62 */ (const void *)&gVexMap_mmmmm_01_opcode_62_pp, + /* 63 */ (const void *)&gVexMap_mmmmm_01_opcode_63_pp, + /* 64 */ (const void *)&gVexMap_mmmmm_01_opcode_64_pp, + /* 65 */ (const void *)&gVexMap_mmmmm_01_opcode_65_pp, + /* 66 */ (const void *)&gVexMap_mmmmm_01_opcode_66_pp, + /* 67 */ (const void *)&gVexMap_mmmmm_01_opcode_67_pp, + /* 68 */ (const void *)&gVexMap_mmmmm_01_opcode_68_pp, + /* 69 */ (const void *)&gVexMap_mmmmm_01_opcode_69_pp, + /* 6a */ (const void *)&gVexMap_mmmmm_01_opcode_6a_pp, + /* 6b */ (const void *)&gVexMap_mmmmm_01_opcode_6b_pp, + /* 6c */ (const void *)&gVexMap_mmmmm_01_opcode_6c_pp, + /* 6d */ (const void *)&gVexMap_mmmmm_01_opcode_6d_pp, + /* 6e */ (const void *)&gVexMap_mmmmm_01_opcode_6e_pp, + /* 6f */ (const void *)&gVexMap_mmmmm_01_opcode_6f_pp, + /* 70 */ (const void *)&gVexMap_mmmmm_01_opcode_70_pp, + /* 71 */ (const void *)&gVexMap_mmmmm_01_opcode_71_pp, + /* 72 */ (const void *)&gVexMap_mmmmm_01_opcode_72_pp, + /* 73 */ (const void *)&gVexMap_mmmmm_01_opcode_73_pp, + /* 74 */ (const void *)&gVexMap_mmmmm_01_opcode_74_pp, + /* 75 */ (const void *)&gVexMap_mmmmm_01_opcode_75_pp, + /* 76 */ (const void *)&gVexMap_mmmmm_01_opcode_76_pp, + /* 77 */ (const void *)&gVexMap_mmmmm_01_opcode_77_pp, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)&gVexMap_mmmmm_01_opcode_7c_pp, + /* 7d */ (const void *)&gVexMap_mmmmm_01_opcode_7d_pp, + /* 7e */ (const void *)&gVexMap_mmmmm_01_opcode_7e_pp, + /* 7f */ (const void *)&gVexMap_mmmmm_01_opcode_7f_pp, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)&gVexMap_mmmmm_01_opcode_90_pp, + /* 91 */ (const void *)&gVexMap_mmmmm_01_opcode_91_pp, + /* 92 */ (const void *)&gVexMap_mmmmm_01_opcode_92_pp, + /* 93 */ (const void *)&gVexMap_mmmmm_01_opcode_93_pp, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)&gVexMap_mmmmm_01_opcode_98_pp, + /* 99 */ (const void *)&gVexMap_mmmmm_01_opcode_99_pp, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)&gVexMap_mmmmm_01_opcode_ae_pp, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)&gVexMap_mmmmm_01_opcode_c2_pp, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)&gVexMap_mmmmm_01_opcode_c4_pp, + /* c5 */ (const void *)&gVexMap_mmmmm_01_opcode_c5_pp, + /* c6 */ (const void *)&gVexMap_mmmmm_01_opcode_c6_pp, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)&gVexMap_mmmmm_01_opcode_d0_pp, + /* d1 */ (const void *)&gVexMap_mmmmm_01_opcode_d1_pp, + /* d2 */ (const void *)&gVexMap_mmmmm_01_opcode_d2_pp, + /* d3 */ (const void *)&gVexMap_mmmmm_01_opcode_d3_pp, + /* d4 */ (const void *)&gVexMap_mmmmm_01_opcode_d4_pp, + /* d5 */ (const void *)&gVexMap_mmmmm_01_opcode_d5_pp, + /* d6 */ (const void *)&gVexMap_mmmmm_01_opcode_d6_pp, + /* d7 */ (const void *)&gVexMap_mmmmm_01_opcode_d7_pp, + /* d8 */ (const void *)&gVexMap_mmmmm_01_opcode_d8_pp, + /* d9 */ (const void *)&gVexMap_mmmmm_01_opcode_d9_pp, + /* da */ (const void *)&gVexMap_mmmmm_01_opcode_da_pp, + /* db */ (const void *)&gVexMap_mmmmm_01_opcode_db_pp, + /* dc */ (const void *)&gVexMap_mmmmm_01_opcode_dc_pp, + /* dd */ (const void *)&gVexMap_mmmmm_01_opcode_dd_pp, + /* de */ (const void *)&gVexMap_mmmmm_01_opcode_de_pp, + /* df */ (const void *)&gVexMap_mmmmm_01_opcode_df_pp, + /* e0 */ (const void *)&gVexMap_mmmmm_01_opcode_e0_pp, + /* e1 */ (const void *)&gVexMap_mmmmm_01_opcode_e1_pp, + /* e2 */ (const void *)&gVexMap_mmmmm_01_opcode_e2_pp, + /* e3 */ (const void *)&gVexMap_mmmmm_01_opcode_e3_pp, + /* e4 */ (const void *)&gVexMap_mmmmm_01_opcode_e4_pp, + /* e5 */ (const void *)&gVexMap_mmmmm_01_opcode_e5_pp, + /* e6 */ (const void *)&gVexMap_mmmmm_01_opcode_e6_pp, + /* e7 */ (const void *)&gVexMap_mmmmm_01_opcode_e7_pp, + /* e8 */ (const void *)&gVexMap_mmmmm_01_opcode_e8_pp, + /* e9 */ (const void *)&gVexMap_mmmmm_01_opcode_e9_pp, + /* ea */ (const void *)&gVexMap_mmmmm_01_opcode_ea_pp, + /* eb */ (const void *)&gVexMap_mmmmm_01_opcode_eb_pp, + /* ec */ (const void *)&gVexMap_mmmmm_01_opcode_ec_pp, + /* ed */ (const void *)&gVexMap_mmmmm_01_opcode_ed_pp, + /* ee */ (const void *)&gVexMap_mmmmm_01_opcode_ee_pp, + /* ef */ (const void *)&gVexMap_mmmmm_01_opcode_ef_pp, + /* f0 */ (const void *)&gVexMap_mmmmm_01_opcode_f0_pp, + /* f1 */ (const void *)&gVexMap_mmmmm_01_opcode_f1_pp, + /* f2 */ (const void *)&gVexMap_mmmmm_01_opcode_f2_pp, + /* f3 */ (const void *)&gVexMap_mmmmm_01_opcode_f3_pp, + /* f4 */ (const void *)&gVexMap_mmmmm_01_opcode_f4_pp, + /* f5 */ (const void *)&gVexMap_mmmmm_01_opcode_f5_pp, + /* f6 */ (const void *)&gVexMap_mmmmm_01_opcode_f6_pp, + /* f7 */ (const void *)&gVexMap_mmmmm_01_opcode_f7_pp, + /* f8 */ (const void *)&gVexMap_mmmmm_01_opcode_f8_pp, + /* f9 */ (const void *)&gVexMap_mmmmm_01_opcode_f9_pp, + /* fa */ (const void *)&gVexMap_mmmmm_01_opcode_fa_pp, + /* fb */ (const void *)&gVexMap_mmmmm_01_opcode_fb_pp, + /* fc */ (const void *)&gVexMap_mmmmm_01_opcode_fc_pp, + /* fd */ (const void *)&gVexMap_mmmmm_01_opcode_fd_pp, + /* fe */ (const void *)&gVexMap_mmmmm_01_opcode_fe_pp, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_M gVexMap_mmmmm = +{ + ND_ILUT_EX_M, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gVexMap_mmmmm_01_opcode, + /* 02 */ (const void *)&gVexMap_mmmmm_02_opcode, + /* 03 */ (const void *)&gVexMap_mmmmm_03_opcode, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)&gVexMap_mmmmm_07_opcode, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + } +}; + + +#endif + diff --git a/bddisasm/include/bdx86_table_xop.h b/bddisasm/include/bdx86_table_xop.h new file mode 100644 index 0000000..b19d0a8 --- /dev/null +++ b/bddisasm/include/bdx86_table_xop.h @@ -0,0 +1,1557 @@ +/* + * Copyright (c) 2024 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ + +// +// This file was auto-generated by generate_tables.py. DO NOT MODIFY! +// + +#ifndef BDX86_TABLE_XOP_H +#define BDX86_TABLE_XOP_H + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1347] // LWPVAL By,Ed,Id +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1346] // LWPINS By,Ed,Id +}; + +const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_10_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 197] // BEXTR Gy,Ey,Id +}; + +const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)&gXopMap_mmmmm_0a_opcode_10_leaf, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)&gXopMap_mmmmm_0a_opcode_12_modrmreg, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)ND_NULL, + /* 96 */ (const void *)ND_NULL, + /* 97 */ (const void *)ND_NULL, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)ND_NULL, + /* c2 */ (const void *)ND_NULL, + /* c3 */ (const void *)ND_NULL, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3527] // VPHSUBDQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3530] // VPHSUBWD Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3525] // VPHSUBBW Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3518] // VPHADDUDQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3520] // VPHADDUWQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3519] // VPHADDUWD Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3516] // VPHADDUBQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3515] // VPHADDUBD Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3517] // VPHADDUBW Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3513] // VPHADDDQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3523] // VPHADDWQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3522] // VPHADDWD Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3510] // VPHADDBQ Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3509] // VPHADDBD Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3511] // VPHADDBW Vdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3716] // VPSHAQ Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3715] // VPSHAQ Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3714] // VPSHAD Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3713] // VPSHAD Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3718] // VPSHAW Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3717] // VPSHAW Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3712] // VPSHAB Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3711] // VPSHAB Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3731] // VPSHLQ Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3730] // VPSHLQ Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3722] // VPSHLB Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3723] // VPSHLD Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3721] // VPSHLB Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3732] // VPSHLW Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3720] // VPSHLB Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3719] // VPSHLB Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3701] // VPROTQ Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3700] // VPROTQ Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3698] // VPROTD Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3697] // VPROTD Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3704] // VPROTW Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3703] // VPROTW Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3695] // VPROTB Vdq,Hdq,Wdq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3694] // VPROTB Vdq,Wdq,Hdq +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3084] // VFRCZSD Vdq,Wsd +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3085] // VFRCZSS Vdq,Wss +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3082] // VFRCZPD Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3083] // VFRCZPS Vx,Wx +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2512] // SLWPCB Ry +}; + +const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 1328] // LLWPCB Ry +}; + +const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod = +{ + ND_ILUT_MODRM_MOD, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf, + } +}; + +const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_12_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 199] // BLCI By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 201] // BLCMSK By,Ey +}; + +const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf, + /* 07 */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2602] // T1MSKC By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 211] // BLSIC By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 200] // BLCIC By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 2636] // TZMSK By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 202] // BLCS By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 207] // BLSFILL By,Ey +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 198] // BLCFILL By,Ey +}; + +const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_01_modrmreg = +{ + ND_ILUT_MODRM_REG, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf, + /* 02 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf, + /* 03 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf, + /* 04 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf, + /* 05 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf, + /* 06 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf, + /* 07 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf, + } +}; + +const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)&gXopMap_mmmmm_09_opcode_01_modrmreg, + /* 02 */ (const void *)&gXopMap_mmmmm_09_opcode_02_modrmreg, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)&gXopMap_mmmmm_09_opcode_12_modrmreg, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)&gXopMap_mmmmm_09_opcode_80_leaf, + /* 81 */ (const void *)&gXopMap_mmmmm_09_opcode_81_leaf, + /* 82 */ (const void *)&gXopMap_mmmmm_09_opcode_82_leaf, + /* 83 */ (const void *)&gXopMap_mmmmm_09_opcode_83_leaf, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)ND_NULL, + /* 86 */ (const void *)ND_NULL, + /* 87 */ (const void *)ND_NULL, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)ND_NULL, + /* 8f */ (const void *)ND_NULL, + /* 90 */ (const void *)&gXopMap_mmmmm_09_opcode_90_w, + /* 91 */ (const void *)&gXopMap_mmmmm_09_opcode_91_w, + /* 92 */ (const void *)&gXopMap_mmmmm_09_opcode_92_w, + /* 93 */ (const void *)&gXopMap_mmmmm_09_opcode_93_w, + /* 94 */ (const void *)&gXopMap_mmmmm_09_opcode_94_w, + /* 95 */ (const void *)&gXopMap_mmmmm_09_opcode_95_w, + /* 96 */ (const void *)&gXopMap_mmmmm_09_opcode_96_w, + /* 97 */ (const void *)&gXopMap_mmmmm_09_opcode_97_w, + /* 98 */ (const void *)&gXopMap_mmmmm_09_opcode_98_w, + /* 99 */ (const void *)&gXopMap_mmmmm_09_opcode_99_w, + /* 9a */ (const void *)&gXopMap_mmmmm_09_opcode_9a_w, + /* 9b */ (const void *)&gXopMap_mmmmm_09_opcode_9b_w, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)ND_NULL, + /* 9f */ (const void *)ND_NULL, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)ND_NULL, + /* a3 */ (const void *)ND_NULL, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)ND_NULL, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)ND_NULL, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)ND_NULL, + /* c1 */ (const void *)&gXopMap_mmmmm_09_opcode_c1_leaf, + /* c2 */ (const void *)&gXopMap_mmmmm_09_opcode_c2_leaf, + /* c3 */ (const void *)&gXopMap_mmmmm_09_opcode_c3_leaf, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)&gXopMap_mmmmm_09_opcode_c6_leaf, + /* c7 */ (const void *)&gXopMap_mmmmm_09_opcode_c7_leaf, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)&gXopMap_mmmmm_09_opcode_cb_leaf, + /* cc */ (const void *)ND_NULL, + /* cd */ (const void *)ND_NULL, + /* ce */ (const void *)ND_NULL, + /* cf */ (const void *)ND_NULL, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)&gXopMap_mmmmm_09_opcode_d1_leaf, + /* d2 */ (const void *)&gXopMap_mmmmm_09_opcode_d2_leaf, + /* d3 */ (const void *)&gXopMap_mmmmm_09_opcode_d3_leaf, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)&gXopMap_mmmmm_09_opcode_d6_leaf, + /* d7 */ (const void *)&gXopMap_mmmmm_09_opcode_d7_leaf, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)&gXopMap_mmmmm_09_opcode_db_leaf, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)&gXopMap_mmmmm_09_opcode_e1_leaf, + /* e2 */ (const void *)&gXopMap_mmmmm_09_opcode_e2_leaf, + /* e3 */ (const void *)&gXopMap_mmmmm_09_opcode_e3_leaf, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)ND_NULL, + /* ed */ (const void *)ND_NULL, + /* ee */ (const void *)ND_NULL, + /* ef */ (const void *)ND_NULL, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3414] // VPCOMUQ Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3413] // VPCOMUD Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3415] // VPCOMUW Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3412] // VPCOMUB Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3411] // VPCOMQ Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3406] // VPCOMD Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3416] // VPCOMW Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3405] // VPCOMB Vdq,Hdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3699] // VPROTQ Vdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3696] // VPROTD Vdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3702] // VPROTW Vdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3693] // VPROTB Vdq,Wdq,Ib +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3556] // VPMADCSWD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3555] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3684] // VPPERM Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3683] // VPPERM Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3376] // VPCMOV Vx,Hx,Lx,Wx +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3375] // VPCMOV Vx,Hx,Wx,Lx +}; + +const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w = +{ + ND_ILUT_EX_W, + { + /* 00 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w_00_leaf, + /* 01 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w_01_leaf, + } +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3546] // VPMACSDQH Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3545] // VPMACSDD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3547] // VPMACSDQL Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3553] // VPMACSWD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3554] // VPMACSWW Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3549] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3548] // VPMACSSDD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3550] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3551] // VPMACSSWD Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf = +{ + ND_ILUT_INSTRUCTION, + (const void *)&gInstructions[ 3552] // VPMACSSWW Vdq,Hdq,Wdq,Ldq +}; + +const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode = +{ + ND_ILUT_OPCODE, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)ND_NULL, + /* 09 */ (const void *)ND_NULL, + /* 0a */ (const void *)ND_NULL, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + /* 20 */ (const void *)ND_NULL, + /* 21 */ (const void *)ND_NULL, + /* 22 */ (const void *)ND_NULL, + /* 23 */ (const void *)ND_NULL, + /* 24 */ (const void *)ND_NULL, + /* 25 */ (const void *)ND_NULL, + /* 26 */ (const void *)ND_NULL, + /* 27 */ (const void *)ND_NULL, + /* 28 */ (const void *)ND_NULL, + /* 29 */ (const void *)ND_NULL, + /* 2a */ (const void *)ND_NULL, + /* 2b */ (const void *)ND_NULL, + /* 2c */ (const void *)ND_NULL, + /* 2d */ (const void *)ND_NULL, + /* 2e */ (const void *)ND_NULL, + /* 2f */ (const void *)ND_NULL, + /* 30 */ (const void *)ND_NULL, + /* 31 */ (const void *)ND_NULL, + /* 32 */ (const void *)ND_NULL, + /* 33 */ (const void *)ND_NULL, + /* 34 */ (const void *)ND_NULL, + /* 35 */ (const void *)ND_NULL, + /* 36 */ (const void *)ND_NULL, + /* 37 */ (const void *)ND_NULL, + /* 38 */ (const void *)ND_NULL, + /* 39 */ (const void *)ND_NULL, + /* 3a */ (const void *)ND_NULL, + /* 3b */ (const void *)ND_NULL, + /* 3c */ (const void *)ND_NULL, + /* 3d */ (const void *)ND_NULL, + /* 3e */ (const void *)ND_NULL, + /* 3f */ (const void *)ND_NULL, + /* 40 */ (const void *)ND_NULL, + /* 41 */ (const void *)ND_NULL, + /* 42 */ (const void *)ND_NULL, + /* 43 */ (const void *)ND_NULL, + /* 44 */ (const void *)ND_NULL, + /* 45 */ (const void *)ND_NULL, + /* 46 */ (const void *)ND_NULL, + /* 47 */ (const void *)ND_NULL, + /* 48 */ (const void *)ND_NULL, + /* 49 */ (const void *)ND_NULL, + /* 4a */ (const void *)ND_NULL, + /* 4b */ (const void *)ND_NULL, + /* 4c */ (const void *)ND_NULL, + /* 4d */ (const void *)ND_NULL, + /* 4e */ (const void *)ND_NULL, + /* 4f */ (const void *)ND_NULL, + /* 50 */ (const void *)ND_NULL, + /* 51 */ (const void *)ND_NULL, + /* 52 */ (const void *)ND_NULL, + /* 53 */ (const void *)ND_NULL, + /* 54 */ (const void *)ND_NULL, + /* 55 */ (const void *)ND_NULL, + /* 56 */ (const void *)ND_NULL, + /* 57 */ (const void *)ND_NULL, + /* 58 */ (const void *)ND_NULL, + /* 59 */ (const void *)ND_NULL, + /* 5a */ (const void *)ND_NULL, + /* 5b */ (const void *)ND_NULL, + /* 5c */ (const void *)ND_NULL, + /* 5d */ (const void *)ND_NULL, + /* 5e */ (const void *)ND_NULL, + /* 5f */ (const void *)ND_NULL, + /* 60 */ (const void *)ND_NULL, + /* 61 */ (const void *)ND_NULL, + /* 62 */ (const void *)ND_NULL, + /* 63 */ (const void *)ND_NULL, + /* 64 */ (const void *)ND_NULL, + /* 65 */ (const void *)ND_NULL, + /* 66 */ (const void *)ND_NULL, + /* 67 */ (const void *)ND_NULL, + /* 68 */ (const void *)ND_NULL, + /* 69 */ (const void *)ND_NULL, + /* 6a */ (const void *)ND_NULL, + /* 6b */ (const void *)ND_NULL, + /* 6c */ (const void *)ND_NULL, + /* 6d */ (const void *)ND_NULL, + /* 6e */ (const void *)ND_NULL, + /* 6f */ (const void *)ND_NULL, + /* 70 */ (const void *)ND_NULL, + /* 71 */ (const void *)ND_NULL, + /* 72 */ (const void *)ND_NULL, + /* 73 */ (const void *)ND_NULL, + /* 74 */ (const void *)ND_NULL, + /* 75 */ (const void *)ND_NULL, + /* 76 */ (const void *)ND_NULL, + /* 77 */ (const void *)ND_NULL, + /* 78 */ (const void *)ND_NULL, + /* 79 */ (const void *)ND_NULL, + /* 7a */ (const void *)ND_NULL, + /* 7b */ (const void *)ND_NULL, + /* 7c */ (const void *)ND_NULL, + /* 7d */ (const void *)ND_NULL, + /* 7e */ (const void *)ND_NULL, + /* 7f */ (const void *)ND_NULL, + /* 80 */ (const void *)ND_NULL, + /* 81 */ (const void *)ND_NULL, + /* 82 */ (const void *)ND_NULL, + /* 83 */ (const void *)ND_NULL, + /* 84 */ (const void *)ND_NULL, + /* 85 */ (const void *)&gXopMap_mmmmm_08_opcode_85_leaf, + /* 86 */ (const void *)&gXopMap_mmmmm_08_opcode_86_leaf, + /* 87 */ (const void *)&gXopMap_mmmmm_08_opcode_87_leaf, + /* 88 */ (const void *)ND_NULL, + /* 89 */ (const void *)ND_NULL, + /* 8a */ (const void *)ND_NULL, + /* 8b */ (const void *)ND_NULL, + /* 8c */ (const void *)ND_NULL, + /* 8d */ (const void *)ND_NULL, + /* 8e */ (const void *)&gXopMap_mmmmm_08_opcode_8e_leaf, + /* 8f */ (const void *)&gXopMap_mmmmm_08_opcode_8f_leaf, + /* 90 */ (const void *)ND_NULL, + /* 91 */ (const void *)ND_NULL, + /* 92 */ (const void *)ND_NULL, + /* 93 */ (const void *)ND_NULL, + /* 94 */ (const void *)ND_NULL, + /* 95 */ (const void *)&gXopMap_mmmmm_08_opcode_95_leaf, + /* 96 */ (const void *)&gXopMap_mmmmm_08_opcode_96_leaf, + /* 97 */ (const void *)&gXopMap_mmmmm_08_opcode_97_leaf, + /* 98 */ (const void *)ND_NULL, + /* 99 */ (const void *)ND_NULL, + /* 9a */ (const void *)ND_NULL, + /* 9b */ (const void *)ND_NULL, + /* 9c */ (const void *)ND_NULL, + /* 9d */ (const void *)ND_NULL, + /* 9e */ (const void *)&gXopMap_mmmmm_08_opcode_9e_leaf, + /* 9f */ (const void *)&gXopMap_mmmmm_08_opcode_9f_leaf, + /* a0 */ (const void *)ND_NULL, + /* a1 */ (const void *)ND_NULL, + /* a2 */ (const void *)&gXopMap_mmmmm_08_opcode_a2_w, + /* a3 */ (const void *)&gXopMap_mmmmm_08_opcode_a3_w, + /* a4 */ (const void *)ND_NULL, + /* a5 */ (const void *)ND_NULL, + /* a6 */ (const void *)&gXopMap_mmmmm_08_opcode_a6_leaf, + /* a7 */ (const void *)ND_NULL, + /* a8 */ (const void *)ND_NULL, + /* a9 */ (const void *)ND_NULL, + /* aa */ (const void *)ND_NULL, + /* ab */ (const void *)ND_NULL, + /* ac */ (const void *)ND_NULL, + /* ad */ (const void *)ND_NULL, + /* ae */ (const void *)ND_NULL, + /* af */ (const void *)ND_NULL, + /* b0 */ (const void *)ND_NULL, + /* b1 */ (const void *)ND_NULL, + /* b2 */ (const void *)ND_NULL, + /* b3 */ (const void *)ND_NULL, + /* b4 */ (const void *)ND_NULL, + /* b5 */ (const void *)ND_NULL, + /* b6 */ (const void *)&gXopMap_mmmmm_08_opcode_b6_leaf, + /* b7 */ (const void *)ND_NULL, + /* b8 */ (const void *)ND_NULL, + /* b9 */ (const void *)ND_NULL, + /* ba */ (const void *)ND_NULL, + /* bb */ (const void *)ND_NULL, + /* bc */ (const void *)ND_NULL, + /* bd */ (const void *)ND_NULL, + /* be */ (const void *)ND_NULL, + /* bf */ (const void *)ND_NULL, + /* c0 */ (const void *)&gXopMap_mmmmm_08_opcode_c0_leaf, + /* c1 */ (const void *)&gXopMap_mmmmm_08_opcode_c1_leaf, + /* c2 */ (const void *)&gXopMap_mmmmm_08_opcode_c2_leaf, + /* c3 */ (const void *)&gXopMap_mmmmm_08_opcode_c3_leaf, + /* c4 */ (const void *)ND_NULL, + /* c5 */ (const void *)ND_NULL, + /* c6 */ (const void *)ND_NULL, + /* c7 */ (const void *)ND_NULL, + /* c8 */ (const void *)ND_NULL, + /* c9 */ (const void *)ND_NULL, + /* ca */ (const void *)ND_NULL, + /* cb */ (const void *)ND_NULL, + /* cc */ (const void *)&gXopMap_mmmmm_08_opcode_cc_leaf, + /* cd */ (const void *)&gXopMap_mmmmm_08_opcode_cd_leaf, + /* ce */ (const void *)&gXopMap_mmmmm_08_opcode_ce_leaf, + /* cf */ (const void *)&gXopMap_mmmmm_08_opcode_cf_leaf, + /* d0 */ (const void *)ND_NULL, + /* d1 */ (const void *)ND_NULL, + /* d2 */ (const void *)ND_NULL, + /* d3 */ (const void *)ND_NULL, + /* d4 */ (const void *)ND_NULL, + /* d5 */ (const void *)ND_NULL, + /* d6 */ (const void *)ND_NULL, + /* d7 */ (const void *)ND_NULL, + /* d8 */ (const void *)ND_NULL, + /* d9 */ (const void *)ND_NULL, + /* da */ (const void *)ND_NULL, + /* db */ (const void *)ND_NULL, + /* dc */ (const void *)ND_NULL, + /* dd */ (const void *)ND_NULL, + /* de */ (const void *)ND_NULL, + /* df */ (const void *)ND_NULL, + /* e0 */ (const void *)ND_NULL, + /* e1 */ (const void *)ND_NULL, + /* e2 */ (const void *)ND_NULL, + /* e3 */ (const void *)ND_NULL, + /* e4 */ (const void *)ND_NULL, + /* e5 */ (const void *)ND_NULL, + /* e6 */ (const void *)ND_NULL, + /* e7 */ (const void *)ND_NULL, + /* e8 */ (const void *)ND_NULL, + /* e9 */ (const void *)ND_NULL, + /* ea */ (const void *)ND_NULL, + /* eb */ (const void *)ND_NULL, + /* ec */ (const void *)&gXopMap_mmmmm_08_opcode_ec_leaf, + /* ed */ (const void *)&gXopMap_mmmmm_08_opcode_ed_leaf, + /* ee */ (const void *)&gXopMap_mmmmm_08_opcode_ee_leaf, + /* ef */ (const void *)&gXopMap_mmmmm_08_opcode_ef_leaf, + /* f0 */ (const void *)ND_NULL, + /* f1 */ (const void *)ND_NULL, + /* f2 */ (const void *)ND_NULL, + /* f3 */ (const void *)ND_NULL, + /* f4 */ (const void *)ND_NULL, + /* f5 */ (const void *)ND_NULL, + /* f6 */ (const void *)ND_NULL, + /* f7 */ (const void *)ND_NULL, + /* f8 */ (const void *)ND_NULL, + /* f9 */ (const void *)ND_NULL, + /* fa */ (const void *)ND_NULL, + /* fb */ (const void *)ND_NULL, + /* fc */ (const void *)ND_NULL, + /* fd */ (const void *)ND_NULL, + /* fe */ (const void *)ND_NULL, + /* ff */ (const void *)ND_NULL, + } +}; + +const ND_TABLE_EX_M gXopMap_mmmmm = +{ + ND_ILUT_EX_M, + { + /* 00 */ (const void *)ND_NULL, + /* 01 */ (const void *)ND_NULL, + /* 02 */ (const void *)ND_NULL, + /* 03 */ (const void *)ND_NULL, + /* 04 */ (const void *)ND_NULL, + /* 05 */ (const void *)ND_NULL, + /* 06 */ (const void *)ND_NULL, + /* 07 */ (const void *)ND_NULL, + /* 08 */ (const void *)&gXopMap_mmmmm_08_opcode, + /* 09 */ (const void *)&gXopMap_mmmmm_09_opcode, + /* 0a */ (const void *)&gXopMap_mmmmm_0a_opcode, + /* 0b */ (const void *)ND_NULL, + /* 0c */ (const void *)ND_NULL, + /* 0d */ (const void *)ND_NULL, + /* 0e */ (const void *)ND_NULL, + /* 0f */ (const void *)ND_NULL, + /* 10 */ (const void *)ND_NULL, + /* 11 */ (const void *)ND_NULL, + /* 12 */ (const void *)ND_NULL, + /* 13 */ (const void *)ND_NULL, + /* 14 */ (const void *)ND_NULL, + /* 15 */ (const void *)ND_NULL, + /* 16 */ (const void *)ND_NULL, + /* 17 */ (const void *)ND_NULL, + /* 18 */ (const void *)ND_NULL, + /* 19 */ (const void *)ND_NULL, + /* 1a */ (const void *)ND_NULL, + /* 1b */ (const void *)ND_NULL, + /* 1c */ (const void *)ND_NULL, + /* 1d */ (const void *)ND_NULL, + /* 1e */ (const void *)ND_NULL, + /* 1f */ (const void *)ND_NULL, + } +}; + + +#endif + diff --git a/bddisasm/include/tabledefs.h b/bddisasm/include/bdx86_tabledefs.h similarity index 76% rename from bddisasm/include/tabledefs.h rename to bddisasm/include/bdx86_tabledefs.h index ce4ffc1..d6b6724 100644 --- a/bddisasm/include/tabledefs.h +++ b/bddisasm/include/bdx86_tabledefs.h @@ -2,10 +2,10 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#ifndef TABLEDEFS_H -#define TABLEDEFS_H +#ifndef BDX86_TABLEDEFS_H +#define BDX86_TABLEDEFS_H -#include "../inc/disasmtypes.h" +#include "../inc/bddisasm_types.h" // // Types of tables. @@ -14,27 +14,29 @@ typedef enum _ND_ILUT_TYPE { ND_ILUT_INSTRUCTION = 0,// Table contains one entry that directly points to an instruction. ND_ILUT_OPCODE, // Table contains 256 entries. Next entry is selected using an opcode. - ND_ILUT_OPCODE_3DNOW, // Table contains 256 entries. Next entry is selected using an opcode, but the - // opcode follows the instruction. - ND_ILUT_MODRM_MOD, // Table contains 2 entries. Next entry is selected using modrm.mod (0 - mem, 1 - reg) + ND_ILUT_OPCODE_LAST, // Table contains 256 entries. Next entry is selected using an opcode, but the + // opcode follows the instruction as the last byte. ND_ILUT_MODRM_REG, // Table contains 8 entries. Next entry is selected using modrm.reg. + ND_ILUT_MODRM_MOD, // Table contains 2 entries. Next entry is selected using modrm.mod (0 - mem, 1 - reg) ND_ILUT_MODRM_RM, // Table contains 8 entries. Next entry is selected using modrm.rm. ND_ILUT_MAN_PREFIX, // Table contains 4 entries. Next entry is 0 (no prefix), 1 (0x66), 2 (0xF3), 3 (0xF2). ND_ILUT_MODE, // Table contains 4 entries. Next entry is 0 (16 bit mode), 1 (32 bit mode), 2 (64 bit mode). ND_ILUT_DSIZE, // Table contains 4 entries. Next entry is 0 (16 bit size), 1 (32 bit size), 2 (64 bit size). // This DOES NOT take into consideration forced/default sizes. ND_ILUT_ASIZE, // Default addressing mode is used to transition - ND_ILUT_AUXILIARY, // Table contains 8 entries. Next entry is 0 (no prefix), 1 (rex), 2 (rex.w), 3 (64 bit), - // 4 (default op size 16), 5 (default op size 32), 6 (default op size 64), + ND_ILUT_AUXILIARY, // Table contains 10 entries. Next entry is 0 (no prefix), 1 (rex), 2 (rex.w), etc. ND_ILUT_VENDOR, // Preferred vendor is used to transition. Default is entry 0. Otherwise, preferred // vendor selects an alternate entry. ND_ILUT_FEATURE, // Some instructions are mapped onto wide NOP space. They will be decoded only if the // associated feature is set during decoding. - ND_ILUT_VEX_MMMMM, // Table contains 32 entries. Next entry is vex/xop/evex.mmmmm - ND_ILUT_VEX_PP, // Table contains 4 entries. Next entry is vex/xop/evex.pp - ND_ILUT_VEX_L, // Table contains 4 entries. Next entry is vex/xop.l or evex.l'l - ND_ILUT_VEX_W, // Table contains 2 entries. Next entry is vex/xop/evex.w - ND_ILUT_VEX_WI, // Table contains 2 entries. Next entry is vex/xop/evex.w. If not in 64 bit, next entry is 0. + ND_ILUT_EX_M, // Table contains 32 entries. Next entry is vex/xop/evex.mmmmm + ND_ILUT_EX_PP, // Table contains 4 entries. Next entry is vex/xop/evex.pp + ND_ILUT_EX_L, // Table contains 4 entries. Next entry is vex/xop.l or evex.l'l + ND_ILUT_EX_W, // Table contains 2 entries. Next entry is vex/xop/evex.w + ND_ILUT_EX_WI, // Table contains 2 entries. Next entry is vex/xop/evex.w. If not in 64 bit, next entry is 0. + ND_ILUT_EX_ND, // Table contains 2 entries. Next entry is evex.ND. + ND_ILUT_EX_NF, // Table contains 2 entries. Next entry is evex.NF. + ND_ILUT_EX_SC, // Table contains 16 entries. Next entry is evex.SC. } ND_ILUT_TYPE; @@ -43,7 +45,7 @@ typedef enum _ND_ILUT_TYPE #define ND_ILUT_INDEX_MOD_REG 1 // Mandatory prefixes. -#define ND_ILUT_INDEX_MAN_PREF_NONE 0 +#define ND_ILUT_INDEX_MAN_PREF_NP 0 #define ND_ILUT_INDEX_MAN_PREF_66 1 #define ND_ILUT_INDEX_MAN_PREF_F3 2 #define ND_ILUT_INDEX_MAN_PREF_F2 3 @@ -72,10 +74,12 @@ typedef enum _ND_ILUT_TYPE #define ND_ILUT_INDEX_AUX_NONE 0 #define ND_ILUT_INDEX_AUX_REXB 1 #define ND_ILUT_INDEX_AUX_REXW 2 -#define ND_ILUT_INDEX_AUX_O64 3 -#define ND_ILUT_INDEX_AUX_F3 4 +#define ND_ILUT_INDEX_AUX_MO64 3 +#define ND_ILUT_INDEX_AUX_REPZ 4 #define ND_ILUT_INDEX_AUX_REP 5 #define ND_ILUT_INDEX_AUX_RIPREL 6 +#define ND_ILUT_INDEX_AUX_REX2 7 +#define ND_ILUT_INDEX_AUX_REX2W 8 // Specific features for instructions that map on the wide NOP space. #define ND_ILUT_FEATURE_NONE 0 @@ -85,9 +89,6 @@ typedef enum _ND_ILUT_TYPE #define ND_ILUT_FEATURE_PITI 4 - - - typedef struct _ND_TABLE { ND_UINT32 Type; @@ -130,11 +131,10 @@ typedef struct _ND_TABLE_MPREFIX const void *Table[4]; } ND_TABLE_MPREFIX, *PND_TABLE_MPREFIX; - typedef struct _ND_TABLE_AUXILIARY { ND_UINT32 Type; - const void *Table[8]; + const void *Table[10]; } ND_TABLE_AUXILIARY, *PND_TABLE_AUXILIARY; typedef struct _ND_TABLE_VENDOR @@ -167,65 +167,66 @@ typedef struct _ND_TABLE_MODE const void *Table[4]; } ND_TABLE_MODE, *PND_TABLE_MODE; -typedef struct _ND_TABLE_VEX_MMMMM +typedef struct _ND_TABLE_EX_M { ND_UINT32 Type; const void *Table[32]; -} ND_TABLE_VEX_MMMMM, *PND_TABLE_VEX_MMMMM; +} ND_TABLE_EX_M, *PND_TABLE_EX_M; -typedef struct _ND_TABLE_VEX_PP +typedef struct _ND_TABLE_EX_PP { ND_UINT32 Type; const void *Table[4]; -} ND_TABLE_VEX_PP, *PND_TABLE_VEX_PP; +} ND_TABLE_EX_PP, *PND_TABLE_EX_PP; -typedef struct _ND_TABLE_VEX_L +typedef struct _ND_TABLE_EX_L { ND_UINT32 Type; const void *Table[4]; -} ND_TABLE_VEX_L, *PND_TABLE_VEX_L; +} ND_TABLE_EX_L, *PND_TABLE_EX_L; -typedef struct _ND_TABLE_VEX_W +typedef struct _ND_TABLE_EX_W { ND_UINT32 Type; - const void *Table[8]; -} ND_TABLE_VEX_W, *PND_TABLE_VEX_W; + const void *Table[2]; +} ND_TABLE_EX_W, *PND_TABLE_EX_W; + +typedef struct _ND_TABLE_EX_ND +{ + ND_UINT32 Type; + const void *Table[2]; +} ND_TABLE_EX_ND, *PND_TABLE_EX_ND; + +typedef struct _ND_TABLE_EX_NF +{ + ND_UINT32 Type; + const void *Table[2]; +} ND_TABLE_EX_NF, *PND_TABLE_EX_NF; + +typedef struct _ND_TABLE_EX_SC +{ + ND_UINT32 Type; + const void *Table[16]; +} ND_TABLE_EX_SC, *PND_TABLE_EX_SC; // -// One instruction entry. This structure should be maintained bellow 2 cache lines in size (128 bytes). +// One instruction database entry. // -#ifdef _MSC_VER -__declspec(align(128)) -#pragma warning(push) -#pragma warning(disable: 4214) -#else -__attribute__((aligned(128))) -#endif -typedef struct _ND_INSTRUCTION +typedef struct _ND_IDBE { ND_UINT16 Instruction; // Instruction identifier. Check ND_INS_CLASS definitions. ND_UINT8 Category; // Instruction category. Check ND_INS_TYPE. ND_UINT8 IsaSet; // Instruction set. Check ND_INS_SET. ND_UINT16 Mnemonic; // Mnemonic (index inside the global mnemonic table). - ND_UINT16 ValidPrefixes; // Accepted prefixes. ND_UINT32 ValidModes; // Valid operating modes for the instruction. ND_UINT8 ValidDecorators;// Accepted decorators (valid for EVEX instructions). - ND_UINT8 OpsCount; // Low 4 bits: explicit operands count; high 4 bits: implicit ops count. - ND_UINT8 TupleType; // EVEX tuple type. - ND_UINT8 ExcType : 5; // SSE/VEX/EVEX/OPMASK/AMX exception type. - ND_UINT8 ExcClass : 3; // Indicates the exception class (SSE/AVX, EVEX, OPMASK or AMX). - + ND_UINT8 ExcType; // SSE/VEX/EVEX/OPMASK/AMX/APX exception type. ND_UINT8 FpuFlags; // FPU status word C0, C1, C2 & C3 access type. - - ND_UINT8 Reserved2; - ND_UINT16 Reserved3; - - ND_UINT32 Attributes; // Instruction attributes. - ND_UINT64 CpuidFlag; // Required CPUID feature flag. + ND_UINT8 EvexMode; // EVEX prefix extension type. // Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag // cannot be both cleared and set. @@ -234,11 +235,14 @@ typedef struct _ND_INSTRUCTION ND_UINT32 SetFlags; // Flags that are always set to 1. ND_UINT32 ClearedFlags; // Flags that are always cleared. + ND_UINT64 Attributes; // Instruction attributes. + ND_UINT64 CpuidFlag; // Required CPUID feature flag. + + // List of operands. Up to 10 implicit and explicit operands stored in DB. ND_UINT64 Operands[10]; -} ND_INSTRUCTION, *PND_INSTRUCTION; -#ifdef _MSC_VER -#pragma warning(pop) -#endif + +} ND_IDBE, *PND_IDBE; + // // The following definitions are per-operand specific. @@ -376,7 +380,6 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_I, ND_OPT_J, ND_OPT_K, - ND_OPT_L, ND_OPT_M, ND_OPT_N, @@ -387,7 +390,6 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_S, ND_OPT_T, ND_OPT_U, - ND_OPT_V, ND_OPT_W, ND_OPT_X, @@ -404,91 +406,92 @@ typedef enum _ND_OPERAND_TYPE_SPEC ND_OPT_rT, ND_OPT_mT, ND_OPT_vT, - ND_OPT_CONST_1, + ND_OPT_dfv, + ND_OPT_1, // These are implicit arguments inside instructions. // Special registers. - ND_OPT_RIP, + ND_OPT_rIP, ND_OPT_MXCSR, ND_OPT_PKRU, ND_OPT_SSP, ND_OPT_UIF, // General Purpose REgisters. - ND_OPT_GPR_AH, - ND_OPT_GPR_rAX, - ND_OPT_GPR_rCX, - ND_OPT_GPR_rDX, - ND_OPT_GPR_rBX, - ND_OPT_GPR_rSP, - ND_OPT_GPR_rBP, - ND_OPT_GPR_rSI, - ND_OPT_GPR_rDI, - ND_OPT_GPR_rR8, - ND_OPT_GPR_rR9, - ND_OPT_GPR_rR11, + ND_OPT_AH, + ND_OPT_rAX, + ND_OPT_rCX, + ND_OPT_rDX, + ND_OPT_rBX, + ND_OPT_rSP, + ND_OPT_rBP, + ND_OPT_rSI, + ND_OPT_rDI, + ND_OPT_rR8, + ND_OPT_rR9, + ND_OPT_rR11, // Segment registers. - ND_OPT_SEG_CS, - ND_OPT_SEG_SS, - ND_OPT_SEG_DS, - ND_OPT_SEG_ES, - ND_OPT_SEG_FS, - ND_OPT_SEG_GS, + ND_OPT_CS, + ND_OPT_SS, + ND_OPT_DS, + ND_OPT_ES, + ND_OPT_FS, + ND_OPT_GS, // FPU registers. - ND_OPT_FPU_ST0, - ND_OPT_FPU_STX, + ND_OPT_ST0, + ND_OPT_STi, // SSE registers. - ND_OPT_SSE_XMM0, - ND_OPT_SSE_XMM1, - ND_OPT_SSE_XMM2, - ND_OPT_SSE_XMM3, - ND_OPT_SSE_XMM4, - ND_OPT_SSE_XMM5, - ND_OPT_SSE_XMM6, - ND_OPT_SSE_XMM7, + ND_OPT_XMM0, + ND_OPT_XMM1, + ND_OPT_XMM2, + ND_OPT_XMM3, + ND_OPT_XMM4, + ND_OPT_XMM5, + ND_OPT_XMM6, + ND_OPT_XMM7, // Implicit memory operands. - ND_OPT_MEM_rAX, // [rAX] - ND_OPT_MEM_rCX, // [rCX] - ND_OPT_MEM_rBX_AL, // [rBX + AL] - ND_OPT_MEM_rDI, // [rDI] - ND_OPT_MEM_SHS, // Shadow stack. - ND_OPT_MEM_SHSP, // Shadow stack pointed by the SSP. - ND_OPT_MEM_SHS0, - ND_OPT_MEM_SMSRT, // Source MSR table, encoded in [RSI]. - ND_OPT_MEM_DMSRT, // Destination MSR table, encoded in [RDI]. + ND_OPT_pAX, // [rAX] + ND_OPT_pCX, // [rCX] + ND_OPT_pBXAL, // [rBX + AL] + ND_OPT_pDI, // [rDI] + ND_OPT_SHS, // Shadow stack. + ND_OPT_SHSP, // Shadow stack pointed by the SSP. + ND_OPT_SHS0, // Shadow stack pointed by the SSP. + ND_OPT_SMT, // Source MSR table, encoded in [RSI]. + ND_OPT_DMT, // Destination MSR table, encoded in [RDI]. // Special immediates. - ND_OPT_Im2z, + ND_OPT_m2zI, // Misc CR/XCR/MSR/SYS registers. - ND_OPT_CR_0, - ND_OPT_SYS_IDTR, - ND_OPT_SYS_GDTR, - ND_OPT_SYS_LDTR, - ND_OPT_SYS_TR, - ND_OPT_X87_CONTROL, - ND_OPT_X87_TAG, - ND_OPT_X87_STATUS, + ND_OPT_CR0, + ND_OPT_IDTR, + ND_OPT_GDTR, + ND_OPT_LDTR, + ND_OPT_TR, + ND_OPT_X87CONTROL, + ND_OPT_X87TAG, + ND_OPT_X87STATUS, ND_OPT_MSR, ND_OPT_XCR, - ND_OPT_MSR_TSC, - ND_OPT_MSR_TSCAUX, - ND_OPT_MSR_SEIP, - ND_OPT_MSR_SESP, - ND_OPT_MSR_SCS, - ND_OPT_MSR_STAR, - ND_OPT_MSR_LSTAR, - ND_OPT_MSR_FMASK, - ND_OPT_MSR_FSBASE, - ND_OPT_MSR_GSBASE, - ND_OPT_MSR_KGSBASE, - ND_OPT_XCR_0, - ND_OPT_REG_BANK, + ND_OPT_TSC, + ND_OPT_TSCAUX, + ND_OPT_SEIP, + ND_OPT_SESP, + ND_OPT_SCS, + ND_OPT_STAR, + ND_OPT_LSTAR, + ND_OPT_FMASK, + ND_OPT_FSBASE, + ND_OPT_GSBASE, + ND_OPT_KGSBASE, + ND_OPT_XCR0, + ND_OPT_BANK, } ND_OPERAND_TYPE_SPEC; @@ -496,9 +499,9 @@ typedef enum _ND_OPERAND_TYPE_SPEC // // Operand flags. // -#define ND_OPF_DEFAULT 0x01 // The operand is default, no need to show it in disassembly. -#define ND_OPF_SEX_OP1 0x02 // The operand is sign-extended to the first operands' size. -#define ND_OPF_SEX_DWS 0x04 // The operand is sign-extended to the default word size. +#define ND_OPF_OPDEF 0x01 // The operand is default, no need to show it in disassembly. +#define ND_OPF_OPSIGNEXO1 0x02 // The operand is sign-extended to the first operands' size. +#define ND_OPF_OPSIGNEXDW 0x04 // The operand is sign-extended to the default word size. // @@ -520,7 +523,7 @@ typedef enum _ND_OPERAND_TYPE_SPEC // Operand decorator flags. // #define ND_OPD_MASK 0x01 // Mask accepted. -#define ND_OPD_Z 0x02 // Zeroing accepted. +#define ND_OPD_ZERO 0x02 // Zeroing accepted. #define ND_OPD_B32 0x04 // 32 bit broadcast supported. #define ND_OPD_B64 0x08 // 64 bit broadcast supported. #define ND_OPD_SAE 0x10 // Suppress all exceptions supported. @@ -533,13 +536,13 @@ typedef enum _ND_OPERAND_TYPE_SPEC // // Include auto-generated stuff. // -#include "mnemonics.h" -#include "../../inc/constants.h" -#include "instructions.h" -#include "prefixes.h" -#include "table_root.h" -#include "table_xop.h" -#include "table_vex.h" -#include "table_evex.h" +#include "../../inc/bdx86_constants.h" +#include "bdx86_mnemonics.h" +#include "bdx86_instructions.h" +#include "bdx86_prefixes.h" +#include "bdx86_table_root.h" +#include "bdx86_table_xop.h" +#include "bdx86_table_vex.h" +#include "bdx86_table_evex.h" -#endif // TABLEDEFS_H +#endif // BDX86_TABLEDEFS_H diff --git a/bddisasm/include/instructions.h b/bddisasm/include/instructions.h deleted file mode 100644 index 8b810a9..0000000 --- a/bddisasm/include/instructions.h +++ /dev/null @@ -1,46975 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ - -// -// This file was auto-generated by generate_tables.py. DO NOT MODIFY! -// - -#ifndef INSTRUCTIONS_H -#define INSTRUCTIONS_H - -const ND_INSTRUCTION gInstructions[2780] = -{ - // Pos:0 Instruction:"AAA" Encoding:"0x37"/"" - { - ND_INS_AAA, ND_CAT_DECIMAL, ND_SET_I86, 0, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1 Instruction:"AAD Ib" Encoding:"0xD5 ib"/"I" - { - ND_INS_AAD, ND_CAT_DECIMAL, ND_SET_I86, 1, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" - { - ND_INS_AADD, ND_CAT_RAOINT, ND_SET_RAOINT, 2, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:3 Instruction:"AAM Ib" Encoding:"0xD4 ib"/"I" - { - ND_INS_AAM, ND_CAT_DECIMAL, ND_SET_I86, 3, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:4 Instruction:"AAND My,Gy" Encoding:"0x66 0x0F 0x38 0xFC /r:mem"/"MR" - { - ND_INS_AAND, ND_CAT_RAOINT, ND_SET_RAOINT, 4, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:5 Instruction:"AAS" Encoding:"0x3F"/"" - { - ND_INS_AAS, ND_CAT_DECIMAL, ND_SET_I86, 5, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:6 Instruction:"ADC Eb,Gb" Encoding:"0x10 /r"/"MR" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:7 Instruction:"ADC Ev,Gv" Encoding:"0x11 /r"/"MR" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:8 Instruction:"ADC Gb,Eb" Encoding:"0x12 /r"/"RM" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:9 Instruction:"ADC Gv,Ev" Encoding:"0x13 /r"/"RM" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:10 Instruction:"ADC AL,Ib" Encoding:"0x14 ib"/"I" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:11 Instruction:"ADC rAX,Iz" Encoding:"0x15 iz"/"I" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:12 Instruction:"ADC Eb,Ib" Encoding:"0x80 /2 ib"/"MI" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:13 Instruction:"ADC Ev,Iz" Encoding:"0x81 /2 iz"/"MI" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:14 Instruction:"ADC Eb,Ib" Encoding:"0x82 /2 iz"/"MI" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:15 Instruction:"ADC Ev,Ib" Encoding:"0x83 /2 ib"/"MI" - { - ND_INS_ADC, ND_CAT_ARITH, ND_SET_I86, 6, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:16 Instruction:"ADCX Gy,Ey" Encoding:"0x66 0x0F 0x38 0xF6 /r"/"RM" - { - ND_INS_ADCX, ND_CAT_ARITH, ND_SET_ADX, 7, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, - 0, - 0|NDR_RFLAG_CF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:17 Instruction:"ADD Eb,Gb" Encoding:"0x00 /r"/"MR" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:18 Instruction:"ADD Ev,Gv" Encoding:"0x01 /r"/"MR" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:19 Instruction:"ADD Gb,Eb" Encoding:"0x02 /r"/"RM" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:20 Instruction:"ADD Gv,Ev" Encoding:"0x03 /r"/"RM" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:21 Instruction:"ADD AL,Ib" Encoding:"0x04 ib"/"I" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:22 Instruction:"ADD rAX,Iz" Encoding:"0x05 iz"/"I" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:23 Instruction:"ADD Eb,Ib" Encoding:"0x80 /0 ib"/"MI" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:24 Instruction:"ADD Ev,Iz" Encoding:"0x81 /0 iz"/"MI" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:25 Instruction:"ADD Eb,Ib" Encoding:"0x82 /0 iz"/"MI" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:26 Instruction:"ADD Ev,Ib" Encoding:"0x83 /0 ib"/"MI" - { - ND_INS_ADD, ND_CAT_ARITH, ND_SET_I86, 8, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:27 Instruction:"ADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x58 /r"/"RM" - { - ND_INS_ADDPD, ND_CAT_SSE, ND_SET_SSE2, 9, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:28 Instruction:"ADDPS Vps,Wps" Encoding:"NP 0x0F 0x58 /r"/"RM" - { - ND_INS_ADDPS, ND_CAT_SSE, ND_SET_SSE, 10, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:29 Instruction:"ADDSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x58 /r"/"RM" - { - ND_INS_ADDSD, ND_CAT_SSE, ND_SET_SSE2, 11, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:30 Instruction:"ADDSS Vss,Wss" Encoding:"0xF3 0x0F 0x58 /r"/"RM" - { - ND_INS_ADDSS, ND_CAT_SSE, ND_SET_SSE, 12, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:31 Instruction:"ADDSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0xD0 /r"/"RM" - { - ND_INS_ADDSUBPD, ND_CAT_SSE, ND_SET_SSE3, 13, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:32 Instruction:"ADDSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0xD0 /r"/"RM" - { - ND_INS_ADDSUBPS, ND_CAT_SSE, ND_SET_SSE3, 14, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:33 Instruction:"ADOX Gy,Ey" Encoding:"0xF3 0x0F 0x38 0xF6 /r"/"RM" - { - ND_INS_ADOX, ND_CAT_ARITH, ND_SET_ADX, 15, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ADX, - 0, - 0|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:34 Instruction:"AESDEC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDE /r"/"RM" - { - ND_INS_AESDEC, ND_CAT_AES, ND_SET_AES, 16, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:35 Instruction:"AESDEC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDD /r:mem"/"RM" - { - ND_INS_AESDEC128KL, ND_CAT_AESKL, ND_SET_KL, 17, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:36 Instruction:"AESDEC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDF /r:mem"/"RM" - { - ND_INS_AESDEC256KL, ND_CAT_AESKL, ND_SET_KL, 18, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:37 Instruction:"AESDECLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDF /r"/"RM" - { - ND_INS_AESDECLAST, ND_CAT_AES, ND_SET_AES, 19, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:38 Instruction:"AESDECWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /1:mem"/"M" - { - ND_INS_AESDECWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 20, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:39 Instruction:"AESDECWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /3:mem"/"M" - { - ND_INS_AESDECWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 21, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:40 Instruction:"AESENC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDC /r"/"RM" - { - ND_INS_AESENC, ND_CAT_AES, ND_SET_AES, 22, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:41 Instruction:"AESENC128KL Vdq,M384" Encoding:"0xF3 0x0F 0x38 0xDC /r:mem"/"RM" - { - ND_INS_AESENC128KL, ND_CAT_AESKL, ND_SET_KL, 23, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:42 Instruction:"AESENC256KL Vdq,M512" Encoding:"0xF3 0x0F 0x38 0xDE /r:mem"/"RM" - { - ND_INS_AESENC256KL, ND_CAT_AESKL, ND_SET_KL, 24, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:43 Instruction:"AESENCLAST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDD /r"/"RM" - { - ND_INS_AESENCLAST, ND_CAT_AES, ND_SET_AES, 25, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:44 Instruction:"AESENCWIDE128KL M384" Encoding:"0xF3 0x0F 0x38 0xD8 /0:mem"/"M" - { - ND_INS_AESENCWIDE128KL, ND_CAT_WIDE_KL, ND_SET_KL, 26, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_384, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:45 Instruction:"AESENCWIDE256KL M512" Encoding:"0xF3 0x0F 0x38 0xD8 /2:mem"/"M" - { - ND_INS_AESENCWIDE256KL, ND_CAT_WIDE_KL, ND_SET_KL, 27, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_512, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 8), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:46 Instruction:"AESIMC Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xDB /r"/"RM" - { - ND_INS_AESIMC, ND_CAT_AES, ND_SET_AES, 28, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:47 Instruction:"AESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xDF /r ib"/"RMI" - { - ND_INS_AESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 29, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:48 Instruction:"ALTINST" Encoding:"0x0F 0x3F"/"" - { - ND_INS_ALTINST, ND_CAT_SYSTEM, ND_SET_CYRIX, 30, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:49 Instruction:"AND Eb,Gb" Encoding:"0x20 /r"/"MR" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:50 Instruction:"AND Ev,Gv" Encoding:"0x21 /r"/"MR" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:51 Instruction:"AND Gb,Eb" Encoding:"0x22 /r"/"RM" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:52 Instruction:"AND Gv,Ev" Encoding:"0x23 /r"/"RM" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:53 Instruction:"AND AL,Ib" Encoding:"0x24 ib"/"I" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:54 Instruction:"AND rAX,Iz" Encoding:"0x25 iz"/"I" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:55 Instruction:"AND Eb,Ib" Encoding:"0x80 /4 ib"/"MI" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:56 Instruction:"AND Ev,Iz" Encoding:"0x81 /4 iz"/"MI" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:57 Instruction:"AND Eb,Ib" Encoding:"0x82 /4 iz"/"MI" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:58 Instruction:"AND Ev,Ib" Encoding:"0x83 /4 ib"/"MI" - { - ND_INS_AND, ND_CAT_LOGIC, ND_SET_I86, 31, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:59 Instruction:"ANDN Gy,By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF2 /r"/"RVM" - { - ND_INS_ANDN, ND_CAT_BMI1, ND_SET_BMI1, 32, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:60 Instruction:"ANDNPD Vpd,Wpd" Encoding:"0x66 0x0F 0x55 /r"/"RM" - { - ND_INS_ANDNPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 33, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:61 Instruction:"ANDNPS Vps,Wps" Encoding:"NP 0x0F 0x55 /r"/"RM" - { - ND_INS_ANDNPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 34, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:62 Instruction:"ANDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x54 /r"/"RM" - { - ND_INS_ANDPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 35, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:63 Instruction:"ANDPS Vps,Wps" Encoding:"NP 0x0F 0x54 /r"/"RM" - { - ND_INS_ANDPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 36, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:64 Instruction:"AOR My,Gy" Encoding:"0xF2 0x0F 0x38 0xFC /r:mem"/"MR" - { - ND_INS_AOR, ND_CAT_RAOINT, ND_SET_RAOINT, 37, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:65 Instruction:"ARPL Ew,Gw" Encoding:"0x63 /r"/"MR" - { - ND_INS_ARPL, ND_CAT_SYSTEM, ND_SET_I286PROT, 38, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:66 Instruction:"AXOR My,Gy" Encoding:"0xF3 0x0F 0x38 0xFC /r:mem"/"MR" - { - ND_INS_AXOR, ND_CAT_RAOINT, ND_SET_RAOINT, 39, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RAOINT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:67 Instruction:"BEXTR Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF7 /r"/"RMV" - { - ND_INS_BEXTR, ND_CAT_BMI1, ND_SET_BMI1, 40, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_ZF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:68 Instruction:"BEXTR Gy,Ey,Id" Encoding:"xop m:A 0x10 /r id"/"RMI" - { - ND_INS_BEXTR, ND_CAT_BITBYTE, ND_SET_TBM, 40, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:69 Instruction:"BLCFILL By,Ey" Encoding:"xop m:9 0x01 /1"/"VM" - { - ND_INS_BLCFILL, ND_CAT_BITBYTE, ND_SET_TBM, 41, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:70 Instruction:"BLCI By,Ey" Encoding:"xop m:9 0x02 /6"/"VM" - { - ND_INS_BLCI, ND_CAT_BITBYTE, ND_SET_TBM, 42, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:71 Instruction:"BLCIC By,Ey" Encoding:"xop m:9 0x01 /5"/"VM" - { - ND_INS_BLCIC, ND_CAT_BITBYTE, ND_SET_TBM, 43, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:72 Instruction:"BLCMSK By,Ey" Encoding:"xop m:9 0x02 /1"/"VM" - { - ND_INS_BLCMSK, ND_CAT_BITBYTE, ND_SET_TBM, 44, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:73 Instruction:"BLCS By,Ey" Encoding:"xop m:9 0x01 /3"/"VM" - { - ND_INS_BLCS, ND_CAT_BITBYTE, ND_SET_TBM, 45, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:74 Instruction:"BLENDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0D /r ib"/"RMI" - { - ND_INS_BLENDPD, ND_CAT_SSE, ND_SET_SSE4, 46, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:75 Instruction:"BLENDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0C /r ib"/"RMI" - { - ND_INS_BLENDPS, ND_CAT_SSE, ND_SET_SSE4, 47, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:76 Instruction:"BLENDVPD Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x15 /r"/"RM" - { - ND_INS_BLENDVPD, ND_CAT_SSE, ND_SET_SSE4, 48, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:77 Instruction:"BLENDVPS Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x14 /r"/"RM" - { - ND_INS_BLENDVPS, ND_CAT_SSE, ND_SET_SSE4, 49, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:78 Instruction:"BLSFILL By,Ey" Encoding:"xop m:9 0x01 /2"/"VM" - { - ND_INS_BLSFILL, ND_CAT_BITBYTE, ND_SET_TBM, 50, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:79 Instruction:"BLSI By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /3"/"VM" - { - ND_INS_BLSI, ND_CAT_BMI1, ND_SET_BMI1, 51, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:80 Instruction:"BLSIC By,Ey" Encoding:"xop m:9 0x01 /6"/"VM" - { - ND_INS_BLSIC, ND_CAT_BITBYTE, ND_SET_TBM, 52, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:81 Instruction:"BLSMSK By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /2"/"VM" - { - ND_INS_BLSMSK, ND_CAT_BMI1, ND_SET_BMI1, 53, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - 0|NDR_RFLAG_ZF|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:82 Instruction:"BLSR By,Ey" Encoding:"vex m:2 p:0 l:0 w:x 0xF3 /1"/"VM" - { - ND_INS_BLSR, ND_CAT_BMI1, ND_SET_BMI1, 54, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:83 Instruction:"BNDCL rBl,Ey" Encoding:"mpx 0xF3 0x0F 0x1A /r"/"RM" - { - ND_INS_BNDCL, ND_CAT_MPX, ND_SET_MPX, 55, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:84 Instruction:"BNDCN rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1B /r"/"RM" - { - ND_INS_BNDCN, ND_CAT_MPX, ND_SET_MPX, 56, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:85 Instruction:"BNDCU rBl,Ey" Encoding:"mpx 0xF2 0x0F 0x1A /r"/"RM" - { - ND_INS_BNDCU, ND_CAT_MPX, ND_SET_MPX, 57, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_F64|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:86 Instruction:"BNDLDX rBl,Mmib" Encoding:"mpx 0x0F 0x1A /r:mem mib"/"RM" - { - ND_INS_BNDLDX, ND_CAT_MPX, ND_SET_MPX, 58, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:87 Instruction:"BNDMK rBl,My" Encoding:"mpx 0xF3 0x0F 0x1B /r:mem"/"RM" - { - ND_INS_BNDMK, ND_CAT_MPX, ND_SET_MPX, 59, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:88 Instruction:"BNDMOV rBl,mBl" Encoding:"mpx 0x66 0x0F 0x1A /r"/"RM" - { - ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:89 Instruction:"BNDMOV mBl,rBl" Encoding:"mpx 0x66 0x0F 0x1B /r"/"MR" - { - ND_INS_BNDMOV, ND_CAT_MPX, ND_SET_MPX, 60, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NOA16|ND_FLAG_I67|ND_FLAG_MODRM, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_mB, ND_OPS_l, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:90 Instruction:"BNDSTX Mmib,rBl" Encoding:"mpx 0x0F 0x1B /r:mem mib"/"MR" - { - ND_INS_BNDSTX, ND_CAT_MPX, ND_SET_MPX, 61, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_NOA16|ND_FLAG_NO_RIP_REL|ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_MIB, ND_CFF_MPX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_mib, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rB, ND_OPS_l, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:91 Instruction:"BOUND Gv,Ma" Encoding:"0x62 /r:mem"/"RM" - { - ND_INS_BOUND, ND_CAT_INTERRUPT, ND_SET_I186, 62, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_a, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:92 Instruction:"BSF Gv,Ev" Encoding:"0x0F 0xBC /r"/"RM" - { - ND_INS_BSF, ND_CAT_I386, ND_SET_I386, 63, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:93 Instruction:"BSR Gv,Ev" Encoding:"0x0F 0xBD /r"/"RM" - { - ND_INS_BSR, ND_CAT_BITBYTE, ND_SET_I386, 64, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:94 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC8"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:95 Instruction:"BSWAP Zv" Encoding:"0x0F 0xC9"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:96 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCA"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:97 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCB"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:98 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCC"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:99 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCD"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:100 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCE"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:101 Instruction:"BSWAP Zv" Encoding:"0x0F 0xCF"/"O" - { - ND_INS_BSWAP, ND_CAT_DATAXFER, ND_SET_I486REAL, 65, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:102 Instruction:"BT Ev,Gv" Encoding:"0x0F 0xA3 /r bitbase"/"MR" - { - ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:103 Instruction:"BT Ev,Ib" Encoding:"0x0F 0xBA /4 ib"/"MI" - { - ND_INS_BT, ND_CAT_BITBYTE, ND_SET_I386, 66, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:104 Instruction:"BTC Ev,Ib" Encoding:"0x0F 0xBA /7 ib"/"MI" - { - ND_INS_BTC, ND_CAT_BITBYTE, ND_SET_I386, 67, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:105 Instruction:"BTC Ev,Gv" Encoding:"0x0F 0xBB /r bitbase"/"MR" - { - ND_INS_BTC, ND_CAT_I386, ND_SET_I386, 67, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:106 Instruction:"BTR Ev,Gv" Encoding:"0x0F 0xB3 /r bitbase"/"MR" - { - ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:107 Instruction:"BTR Ev,Ib" Encoding:"0x0F 0xBA /6 ib"/"MI" - { - ND_INS_BTR, ND_CAT_BITBYTE, ND_SET_I386, 68, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:108 Instruction:"BTS Ev,Gv" Encoding:"0x0F 0xAB /r bitbase"/"MR" - { - ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_BITBASE, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:109 Instruction:"BTS Ev,Ib" Encoding:"0x0F 0xBA /5 ib"/"MI" - { - ND_INS_BTS, ND_CAT_BITBYTE, ND_SET_I386, 69, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:110 Instruction:"BZHI Gy,Ey,By" Encoding:"vex m:2 p:0 l:0 w:x 0xF5 /r"/"RMV" - { - ND_INS_BZHI, ND_CAT_BMI2, ND_SET_BMI2, 70, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - 0|NDR_RFLAG_OF|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:111 Instruction:"CALL Jz" Encoding:"0xE8 cz"/"D" - { - ND_INS_CALLNR, ND_CAT_CALL, ND_SET_I86, 71, - ND_PREF_BND, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:112 Instruction:"CALL Ev" Encoding:"0xFF /2"/"M" - { - ND_INS_CALLNI, ND_CAT_CALL, ND_SET_I86, 71, - ND_PREF_BND|ND_PREF_DNT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:113 Instruction:"CALLF Ap" Encoding:"0x9A cp"/"D" - { - ND_INS_CALLFD, ND_CAT_CALL, ND_SET_I86, 72, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:114 Instruction:"CALLF Mp" Encoding:"0xFF /3:mem"/"M" - { - ND_INS_CALLFI, ND_CAT_CALL, ND_SET_I86, 72, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:115 Instruction:"CBW" Encoding:"ds16 0x98"/"" - { - ND_INS_CBW, ND_CAT_CONVERT, ND_SET_I386, 73, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:116 Instruction:"CDQ" Encoding:"ds32 0x99"/"" - { - ND_INS_CDQ, ND_CAT_CONVERT, ND_SET_I386, 74, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:117 Instruction:"CDQE" Encoding:"ds64 0x98"/"" - { - ND_INS_CDQE, ND_CAT_CONVERT, ND_SET_I386, 75, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:118 Instruction:"CLAC" Encoding:"NP 0x0F 0x01 /0xCA"/"" - { - ND_INS_CLAC, ND_CAT_SMAP, ND_SET_SMAP, 76, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, - 0, - 0, - 0, - 0|NDR_RFLAG_AC, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:119 Instruction:"CLC" Encoding:"0xF8"/"" - { - ND_INS_CLC, ND_CAT_FLAGOP, ND_SET_I86, 77, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0|NDR_RFLAG_CF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:120 Instruction:"CLD" Encoding:"0xFC"/"" - { - ND_INS_CLD, ND_CAT_FLAGOP, ND_SET_I86, 78, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0|NDR_RFLAG_DF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:121 Instruction:"CLDEMOTE Mb" Encoding:"cldm NP 0x0F 0x1C /0:mem"/"M" - { - ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 79, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLDEMOTE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:122 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M" - { - ND_INS_CLEVICT0, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 80, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:123 Instruction:"CLEVICT1 M?" Encoding:"vex m:1 p:2 0xAE /7:mem"/"M" - { - ND_INS_CLEVICT1, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 81, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:124 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M" - { - ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 82, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSH, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:125 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M" - { - ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 83, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLFSHOPT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:126 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/"" - { - ND_INS_CLGI, ND_CAT_SYSTEM, ND_SET_SVM, 84, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:127 Instruction:"CLI" Encoding:"0xFA"/"" - { - ND_INS_CLI, ND_CAT_FLAGOP, ND_SET_I86, 85, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0|NDR_RFLAG_IF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:128 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M" - { - ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 86, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:129 Instruction:"CLTS" Encoding:"0x0F 0x06"/"" - { - ND_INS_CLTS, ND_CAT_SYSTEM, ND_SET_I286REAL, 87, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:130 Instruction:"CLUI" Encoding:"0xF3 0x0F 0x01 /0xEE"/"" - { - ND_INS_CLUI, ND_CAT_UINTR, ND_SET_UINTR, 88, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:131 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M" - { - ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 89, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CLWB, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:132 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/"" - { - ND_INS_CLZERO, ND_CAT_MISC, ND_SET_CLZERO, 90, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:133 Instruction:"CMC" Encoding:"0xF5"/"" - { - ND_INS_CMC, ND_CAT_FLAGOP, ND_SET_I86, 91, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:134 Instruction:"CMOVBE Gv,Ev" Encoding:"0x0F 0x46 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 92, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:135 Instruction:"CMOVC Gv,Ev" Encoding:"0x0F 0x42 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 93, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:136 Instruction:"CMOVL Gv,Ev" Encoding:"0x0F 0x4C /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 94, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:137 Instruction:"CMOVLE Gv,Ev" Encoding:"0x0F 0x4E /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 95, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:138 Instruction:"CMOVNBE Gv,Ev" Encoding:"0x0F 0x47 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 96, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:139 Instruction:"CMOVNC Gv,Ev" Encoding:"0x0F 0x43 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 97, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:140 Instruction:"CMOVNL Gv,Ev" Encoding:"0x0F 0x4D /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 98, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:141 Instruction:"CMOVNLE Gv,Ev" Encoding:"0x0F 0x4F /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 99, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:142 Instruction:"CMOVNO Gv,Ev" Encoding:"0x0F 0x41 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 100, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:143 Instruction:"CMOVNP Gv,Ev" Encoding:"0x0F 0x4B /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 101, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:144 Instruction:"CMOVNS Gv,Ev" Encoding:"0x0F 0x49 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 102, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:145 Instruction:"CMOVNZ Gv,Ev" Encoding:"0x0F 0x45 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 103, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:146 Instruction:"CMOVO Gv,Ev" Encoding:"0x0F 0x40 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 104, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:147 Instruction:"CMOVP Gv,Ev" Encoding:"0x0F 0x4A /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 105, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:148 Instruction:"CMOVS Gv,Ev" Encoding:"0x0F 0x48 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 106, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:149 Instruction:"CMOVZ Gv,Ev" Encoding:"0x0F 0x44 /r"/"RM" - { - ND_INS_CMOVcc, ND_CAT_CMOV, ND_SET_PPRO, 107, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMOV, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:150 Instruction:"CMP Eb,Gb" Encoding:"0x38 /r"/"MR" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:151 Instruction:"CMP Ev,Gv" Encoding:"0x39 /r"/"MR" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:152 Instruction:"CMP Gb,Eb" Encoding:"0x3A /r"/"RM" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:153 Instruction:"CMP Gv,Ev" Encoding:"0x3B /r"/"RM" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:154 Instruction:"CMP AL,Ib" Encoding:"0x3C ib"/"I" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:155 Instruction:"CMP rAX,Iz" Encoding:"0x3D iz"/"I" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:156 Instruction:"CMP Eb,Ib" Encoding:"0x80 /7 ib"/"MI" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:157 Instruction:"CMP Ev,Iz" Encoding:"0x81 /7 iz"/"MI" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:158 Instruction:"CMP Eb,Ib" Encoding:"0x82 /7 iz"/"MI" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:159 Instruction:"CMP Ev,Ib" Encoding:"0x83 /7 ib"/"MI" - { - ND_INS_CMP, ND_CAT_ARITH, ND_SET_I86, 108, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:160 Instruction:"CMPBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE6 /r:mem"/"MRV" - { - ND_INS_CMPBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 109, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:161 Instruction:"CMPCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE2 /r:mem"/"MRV" - { - ND_INS_CMPCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 110, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:162 Instruction:"CMPLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEE /r:mem"/"MRV" - { - ND_INS_CMPLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 111, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:163 Instruction:"CMPLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEC /r:mem"/"MRV" - { - ND_INS_CMPLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 112, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:164 Instruction:"CMPNBEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE7 /r:mem"/"MRV" - { - ND_INS_CMPNBEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 113, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:165 Instruction:"CMPNCXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE3 /r:mem"/"MRV" - { - ND_INS_CMPNCXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 114, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:166 Instruction:"CMPNLEXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEF /r:mem"/"MRV" - { - ND_INS_CMPNLEXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 115, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:167 Instruction:"CMPNLXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xED /r:mem"/"MRV" - { - ND_INS_CMPNLXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 116, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:168 Instruction:"CMPNOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE1 /r:mem"/"MRV" - { - ND_INS_CMPNOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 117, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:169 Instruction:"CMPNPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEB /r:mem"/"MRV" - { - ND_INS_CMPNPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 118, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:170 Instruction:"CMPNSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE9 /r:mem"/"MRV" - { - ND_INS_CMPNSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 119, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:171 Instruction:"CMPNZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE5 /r:mem"/"MRV" - { - ND_INS_CMPNZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 120, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:172 Instruction:"CMPOXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE0 /r:mem"/"MRV" - { - ND_INS_CMPOXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 121, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:173 Instruction:"CMPPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC2 /r ib"/"RMI" - { - ND_INS_CMPPD, ND_CAT_SSE, ND_SET_SSE2, 122, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:174 Instruction:"CMPPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC2 /r ib"/"RMI" - { - ND_INS_CMPPS, ND_CAT_SSE, ND_SET_SSE, 123, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:175 Instruction:"CMPPXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xEA /r:mem"/"MRV" - { - ND_INS_CMPPXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 124, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:176 Instruction:"CMPSB Xb,Yb" Encoding:"0xA6"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:177 Instruction:"CMPSB Xb,Yb" Encoding:"rep 0xA6"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 125, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:178 Instruction:"CMPSD Vsd,Wsd,Ib" Encoding:"0xF2 0x0F 0xC2 /r ib"/"RMI" - { - ND_INS_CMPSD, ND_CAT_SSE, ND_SET_SSE2, 126, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:179 Instruction:"CMPSD Xv,Yv" Encoding:"ds32 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:180 Instruction:"CMPSD Xv,Yv" Encoding:"rep ds32 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 126, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:181 Instruction:"CMPSQ Xv,Yv" Encoding:"ds64 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:182 Instruction:"CMPSQ Xv,Yv" Encoding:"rep ds64 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 127, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:183 Instruction:"CMPSS Vss,Wss,Ib" Encoding:"0xF3 0x0F 0xC2 /r ib"/"RMI" - { - ND_INS_CMPSS, ND_CAT_SSE, ND_SET_SSE, 128, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:184 Instruction:"CMPSW Xv,Yv" Encoding:"ds16 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:185 Instruction:"CMPSW Xv,Yv" Encoding:"rep ds16 0xA7"/"" - { - ND_INS_CMPS, ND_CAT_STRINGOP, ND_SET_I86, 129, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:186 Instruction:"CMPSXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE8 /r:mem"/"MRV" - { - ND_INS_CMPSXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 130, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:187 Instruction:"CMPXCHG Eb,Gb" Encoding:"0x0F 0xB0 /r"/"MR" - { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:188 Instruction:"CMPXCHG Ev,Gv" Encoding:"0x0F 0xB1 /r"/"MR" - { - ND_INS_CMPXCHG, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 131, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:189 Instruction:"CMPXCHG16B Mdq" Encoding:"rexw 0x0F 0xC7 /1:mem"/"M" - { - ND_INS_CMPXCHG16B, ND_CAT_SEMAPHORE, ND_SET_CMPXCHG16B, 132, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:190 Instruction:"CMPXCHG8B Mq" Encoding:"0x0F 0xC7 /1:mem"/"M" - { - ND_INS_CMPXCHG8B, ND_CAT_SEMAPHORE, ND_SET_PENTIUMREAL, 133, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CX8, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:191 Instruction:"CMPZXADD My,Gy,By" Encoding:"vex m:2 p:1 l:0 w:x 0xE4 /r:mem"/"MRV" - { - ND_INS_CMPZXADD, ND_CAT_CMPCCXADD, ND_SET_CMPCCXADD, 134, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_14, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, ND_CFF_CMPCCXADD, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:192 Instruction:"COMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2F /r"/"RM" - { - ND_INS_COMISD, ND_CAT_SSE2, ND_SET_SSE2, 135, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:193 Instruction:"COMISS Vss,Wss" Encoding:"NP 0x0F 0x2F /r"/"RM" - { - ND_INS_COMISS, ND_CAT_SSE, ND_SET_SSE, 136, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:194 Instruction:"CPUID" Encoding:"0x0F 0xA2"/"" - { - ND_INS_CPUID, ND_CAT_MISC, ND_SET_I486REAL, 137, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:195 Instruction:"CPU_READ" Encoding:"0x0F 0x3D"/"" - { - ND_INS_CPU_READ, ND_CAT_SYSTEM, ND_SET_CYRIX, 138, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:196 Instruction:"CPU_WRITE" Encoding:"0x0F 0x3C"/"" - { - ND_INS_CPU_WRITE, ND_CAT_SYSTEM, ND_SET_CYRIX, 139, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:197 Instruction:"CQO" Encoding:"ds64 0x99"/"" - { - ND_INS_CQO, ND_CAT_CONVERT, ND_SET_I386, 140, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:198 Instruction:"CRC32 Gy,Eb" Encoding:"0xF2 0x0F 0x38 0xF0 /r"/"RM" - { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:199 Instruction:"CRC32 Gy,Eb" Encoding:"0x66 0xF2 0x0F 0x38 0xF0 /r"/"RM" - { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:200 Instruction:"CRC32 Gy,Ev" Encoding:"0xF2 0x0F 0x38 0xF1 /r"/"RM" - { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE42, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:201 Instruction:"CRC32 Gy,Ev" Encoding:"0x66 0xF2 0x0F 0x38 0xF1 /r"/"RM" - { - ND_INS_CRC32, ND_CAT_SSE, ND_SET_SSE42, 141, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_SSE42, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:202 Instruction:"CVTDQ2PD Vx,Wq" Encoding:"0xF3 0x0F 0xE6 /r"/"RM" - { - ND_INS_CVTDQ2PD, ND_CAT_CONVERT, ND_SET_SSE2, 142, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:203 Instruction:"CVTDQ2PS Vps,Wdq" Encoding:"NP 0x0F 0x5B /r"/"RM" - { - ND_INS_CVTDQ2PS, ND_CAT_CONVERT, ND_SET_SSE2, 143, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:204 Instruction:"CVTPD2DQ Vx,Wpd" Encoding:"0xF2 0x0F 0xE6 /r"/"RM" - { - ND_INS_CVTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 144, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:205 Instruction:"CVTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2D /r"/"RM" - { - ND_INS_CVTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 145, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:206 Instruction:"CVTPD2PS Vps,Wpd" Encoding:"0x66 0x0F 0x5A /r"/"RM" - { - ND_INS_CVTPD2PS, ND_CAT_CONVERT, ND_SET_SSE2, 146, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:207 Instruction:"CVTPI2PD Vpd,Qq" Encoding:"0x66 0x0F 0x2A /r"/"RM" - { - ND_INS_CVTPI2PD, ND_CAT_CONVERT, ND_SET_SSE2, 147, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:208 Instruction:"CVTPI2PS Vq,Qq" Encoding:"NP 0x0F 0x2A /r"/"RM" - { - ND_INS_CVTPI2PS, ND_CAT_CONVERT, ND_SET_SSE, 148, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:209 Instruction:"CVTPS2DQ Vdq,Wps" Encoding:"0x66 0x0F 0x5B /r"/"RM" - { - ND_INS_CVTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 149, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:210 Instruction:"CVTPS2PD Vpd,Wq" Encoding:"NP 0x0F 0x5A /r"/"RM" - { - ND_INS_CVTPS2PD, ND_CAT_CONVERT, ND_SET_SSE2, 150, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:211 Instruction:"CVTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2D /r"/"RM" - { - ND_INS_CVTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 151, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:212 Instruction:"CVTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2D /r"/"RM" - { - ND_INS_CVTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 152, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:213 Instruction:"CVTSD2SS Vss,Wsd" Encoding:"0xF2 0x0F 0x5A /r"/"RM" - { - ND_INS_CVTSD2SS, ND_CAT_CONVERT, ND_SET_SSE2, 153, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:214 Instruction:"CVTSI2SD Vsd,Ey" Encoding:"0xF2 0x0F 0x2A /r"/"RM" - { - ND_INS_CVTSI2SD, ND_CAT_CONVERT, ND_SET_SSE2, 154, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:215 Instruction:"CVTSI2SS Vss,Ey" Encoding:"0xF3 0x0F 0x2A /r"/"RM" - { - ND_INS_CVTSI2SS, ND_CAT_CONVERT, ND_SET_SSE, 155, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:216 Instruction:"CVTSS2SD Vsd,Wss" Encoding:"0xF3 0x0F 0x5A /r"/"RM" - { - ND_INS_CVTSS2SD, ND_CAT_CONVERT, ND_SET_SSE2, 156, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:217 Instruction:"CVTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2D /r"/"RM" - { - ND_INS_CVTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 157, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:218 Instruction:"CVTTPD2DQ Vx,Wpd" Encoding:"0x66 0x0F 0xE6 /r"/"RM" - { - ND_INS_CVTTPD2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 158, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:219 Instruction:"CVTTPD2PI Pq,Wpd" Encoding:"0x66 0x0F 0x2C /r"/"RM" - { - ND_INS_CVTTPD2PI, ND_CAT_CONVERT, ND_SET_SSE2, 159, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:220 Instruction:"CVTTPS2DQ Vdq,Wps" Encoding:"0xF3 0x0F 0x5B /r"/"RM" - { - ND_INS_CVTTPS2DQ, ND_CAT_CONVERT, ND_SET_SSE2, 160, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:221 Instruction:"CVTTPS2PI Pq,Wq" Encoding:"NP 0x0F 0x2C /r"/"RM" - { - ND_INS_CVTTPS2PI, ND_CAT_CONVERT, ND_SET_SSE, 161, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:222 Instruction:"CVTTSD2SI Gy,Wsd" Encoding:"0xF2 0x0F 0x2C /r"/"RM" - { - ND_INS_CVTTSD2SI, ND_CAT_CONVERT, ND_SET_SSE2, 162, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:223 Instruction:"CVTTSS2SI Gy,Wss" Encoding:"0xF3 0x0F 0x2C /r"/"RM" - { - ND_INS_CVTTSS2SI, ND_CAT_CONVERT, ND_SET_SSE, 163, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:224 Instruction:"CWD" Encoding:"ds16 0x99"/"" - { - ND_INS_CWD, ND_CAT_CONVERT, ND_SET_I386, 164, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:225 Instruction:"CWDE" Encoding:"ds32 0x98"/"" - { - ND_INS_CWDE, ND_CAT_CONVERT, ND_SET_I386, 165, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:226 Instruction:"DAA" Encoding:"0x27"/"" - { - ND_INS_DAA, ND_CAT_DECIMAL, ND_SET_I86, 166, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF, - 0|NDR_RFLAG_OF, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:227 Instruction:"DAS" Encoding:"0x2F"/"" - { - ND_INS_DAS, ND_CAT_DECIMAL, ND_SET_I86, 167, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_OF, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:228 Instruction:"DEC Zv" Encoding:"0x48"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:229 Instruction:"DEC Zv" Encoding:"0x49"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:230 Instruction:"DEC Zv" Encoding:"0x4A"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:231 Instruction:"DEC Zv" Encoding:"0x4B"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:232 Instruction:"DEC Zv" Encoding:"0x4C"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:233 Instruction:"DEC Zv" Encoding:"0x4D"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:234 Instruction:"DEC Zv" Encoding:"0x4E"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:235 Instruction:"DEC Zv" Encoding:"0x4F"/"O" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:236 Instruction:"DEC Eb" Encoding:"0xFE /1"/"M" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:237 Instruction:"DEC Ev" Encoding:"0xFF /1"/"M" - { - ND_INS_DEC, ND_CAT_ARITH, ND_SET_I86, 168, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:238 Instruction:"DELAY Ry" Encoding:"vex m:1 p:2 0xAE /6:reg"/"M" - { - ND_INS_DELAY, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 169, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:239 Instruction:"DIV Eb" Encoding:"0xF6 /6"/"M" - { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:240 Instruction:"DIV Ev" Encoding:"0xF7 /6"/"M" - { - ND_INS_DIV, ND_CAT_ARITH, ND_SET_I86, 170, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:241 Instruction:"DIVPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5E /r"/"RM" - { - ND_INS_DIVPD, ND_CAT_SSE, ND_SET_SSE2, 171, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:242 Instruction:"DIVPS Vps,Wps" Encoding:"NP 0x0F 0x5E /r"/"RM" - { - ND_INS_DIVPS, ND_CAT_SSE, ND_SET_SSE, 172, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:243 Instruction:"DIVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5E /r"/"RM" - { - ND_INS_DIVSD, ND_CAT_SSE, ND_SET_SSE2, 173, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:244 Instruction:"DIVSS Vss,Wss" Encoding:"0xF3 0x0F 0x5E /r"/"RM" - { - ND_INS_DIVSS, ND_CAT_SSE, ND_SET_SSE, 174, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:245 Instruction:"DMINT" Encoding:"0x0F 0x39"/"" - { - ND_INS_DMINT, ND_CAT_SYSTEM, ND_SET_CYRIX, 175, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:246 Instruction:"DPPD Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x41 /r ib"/"RMI" - { - ND_INS_DPPD, ND_CAT_SSE, ND_SET_SSE4, 176, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:247 Instruction:"DPPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x40 /r ib"/"RMI" - { - ND_INS_DPPS, ND_CAT_SSE, ND_SET_SSE4, 177, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:248 Instruction:"EMMS" Encoding:"NP 0x0F 0x77"/"" - { - ND_INS_EMMS, ND_CAT_MMX, ND_SET_MMX, 178, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:249 Instruction:"ENCLS" Encoding:"NP 0x0F 0x01 /0xCF"/"" - { - ND_INS_ENCLS, ND_CAT_SGX, ND_SET_SGX, 179, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - }, - }, - - // Pos:250 Instruction:"ENCLU" Encoding:"NP 0x0F 0x01 /0xD7"/"" - { - ND_INS_ENCLU, ND_CAT_SGX, ND_SET_SGX, 180, - 0, - ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - }, - }, - - // Pos:251 Instruction:"ENCLV" Encoding:"NP 0x0F 0x01 /0xC0"/"" - { - ND_INS_ENCLV, ND_CAT_SGX, ND_SET_SGX, 181, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SGX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CRW, 0, 0), - }, - }, - - // Pos:252 Instruction:"ENCODEKEY128 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFA /r:reg"/"RM" - { - ND_INS_ENCODEKEY128, ND_CAT_AESKL, ND_SET_KL, 182, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), - OP(ND_OPT_SSE_XMM4, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 3), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:253 Instruction:"ENCODEKEY256 Gd,Rd" Encoding:"0xF3 0x0F 0x38 0xFB /r:reg"/"RM" - { - ND_INS_ENCODEKEY256, ND_CAT_AESKL, ND_SET_KL, 183, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_KL, - 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_RW, 0, 2), - OP(ND_OPT_SSE_XMM2, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 5), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:254 Instruction:"ENDBR32" Encoding:"cet a0xF3 0x0F 0x1E /0xFB"/"" - { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 184, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:255 Instruction:"ENDBR64" Encoding:"cet a0xF3 0x0F 0x1E /0xFA"/"" - { - ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 185, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:256 Instruction:"ENQCMD rM?,Moq" Encoding:"0xF2 0x0F 0x38 0xF8 /r:mem"/"M" - { - ND_INS_ENQCMD, ND_CAT_ENQCMD, ND_SET_ENQCMD, 186, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:257 Instruction:"ENQCMDS rM?,Moq" Encoding:"0xF3 0x0F 0x38 0xF8 /r:mem"/"M" - { - ND_INS_ENQCMDS, ND_CAT_ENQCMD, ND_SET_ENQCMD, 187, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_ENQCMD, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rM, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:258 Instruction:"ENTER Iw,Ib" Encoding:"0xC8 iw ib"/"II" - { - ND_INS_ENTER, ND_CAT_MISC, ND_SET_I186, 188, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:259 Instruction:"ERETS" Encoding:"0xF2 0x0F 0x01 /0xCA"/"" - { - ND_INS_ERETS, ND_CAT_RET, ND_SET_FRED, 189, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - }, - }, - - // Pos:260 Instruction:"ERETU" Encoding:"0xF3 0x0F 0x01 /0xCA"/"" - { - ND_INS_ERETU, ND_CAT_RET, ND_SET_FRED, 190, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_FRED, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v5, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:261 Instruction:"EXTRACTPS Ed,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x17 /r ib"/"MRI" - { - ND_INS_EXTRACTPS, ND_CAT_SSE, ND_SET_SSE4, 191, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:262 Instruction:"EXTRQ Uq,Ib,Ib" Encoding:"0x66 0x0F 0x78 /0 modrmpmp ib ib"/"MII" - { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:263 Instruction:"EXTRQ Vdq,Uq" Encoding:"0x66 0x0F 0x79 /r:reg"/"RM" - { - ND_INS_EXTRQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 192, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:264 Instruction:"F2XM1" Encoding:"0xD9 /0xF0"/"" - { - ND_INS_F2XM1, ND_CAT_X87_ALU, ND_SET_X87, 193, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:265 Instruction:"FABS" Encoding:"0xD9 /0xE1"/"" - { - ND_INS_FABS, ND_CAT_X87_ALU, ND_SET_X87, 194, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:266 Instruction:"FADD ST(0),Mfd" Encoding:"0xD8 /0:mem"/"M" - { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:267 Instruction:"FADD ST(0),ST(i)" Encoding:"0xD8 /0:reg"/"M" - { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:268 Instruction:"FADD ST(0),Mfq" Encoding:"0xDC /0:mem"/"M" - { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:269 Instruction:"FADD ST(i),ST(0)" Encoding:"0xDC /0:reg"/"M" - { - ND_INS_FADD, ND_CAT_X87_ALU, ND_SET_X87, 195, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:270 Instruction:"FADDP ST(i),ST(0)" Encoding:"0xDE /0:reg"/"M" - { - ND_INS_FADDP, ND_CAT_X87_ALU, ND_SET_X87, 196, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:271 Instruction:"FBLD ST(0),Mfa" Encoding:"0xDF /4:mem"/"M" - { - ND_INS_FBLD, ND_CAT_X87_ALU, ND_SET_X87, 197, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:272 Instruction:"FBSTP Mfa,ST(0)" Encoding:"0xDF /6:mem"/"M" - { - ND_INS_FBSTP, ND_CAT_X87_ALU, ND_SET_X87, 198, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fa, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:273 Instruction:"FCHS" Encoding:"0xD9 /0xE0"/"" - { - ND_INS_FCHS, ND_CAT_X87_ALU, ND_SET_X87, 199, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:274 Instruction:"FCMOVB ST(0),ST(i)" Encoding:"0xDA /0:reg"/"M" - { - ND_INS_FCMOVB, ND_CAT_X87_ALU, ND_SET_X87, 200, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:275 Instruction:"FCMOVBE ST(0),ST(i)" Encoding:"0xDA /2:reg"/"M" - { - ND_INS_FCMOVBE, ND_CAT_X87_ALU, ND_SET_X87, 201, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:276 Instruction:"FCMOVE ST(0),ST(i)" Encoding:"0xDA /1:reg"/"M" - { - ND_INS_FCMOVE, ND_CAT_X87_ALU, ND_SET_X87, 202, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:277 Instruction:"FCMOVNB ST(0),ST(i)" Encoding:"0xDB /0:reg"/"M" - { - ND_INS_FCMOVNB, ND_CAT_X87_ALU, ND_SET_X87, 203, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:278 Instruction:"FCMOVNBE ST(0),ST(i)" Encoding:"0xDB /2:reg"/"M" - { - ND_INS_FCMOVNBE, ND_CAT_X87_ALU, ND_SET_X87, 204, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:279 Instruction:"FCMOVNE ST(0),ST(i)" Encoding:"0xDB /1:reg"/"M" - { - ND_INS_FCMOVNE, ND_CAT_X87_ALU, ND_SET_X87, 205, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:280 Instruction:"FCMOVNU ST(0),ST(i)" Encoding:"0xDB /3:reg"/"M" - { - ND_INS_FCMOVNU, ND_CAT_X87_ALU, ND_SET_X87, 206, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:281 Instruction:"FCMOVU ST(0),ST(i)" Encoding:"0xDA /3:reg"/"M" - { - ND_INS_FCMOVU, ND_CAT_X87_ALU, ND_SET_X87, 207, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:282 Instruction:"FCOM ST(0),Mfd" Encoding:"0xD8 /2:mem"/"M" - { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:283 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xD8 /2:reg"/"M" - { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:284 Instruction:"FCOM ST(0),Mfq" Encoding:"0xDC /2:mem"/"M" - { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:285 Instruction:"FCOM ST(0),ST(i)" Encoding:"0xDC /2:reg"/"M" - { - ND_INS_FCOM, ND_CAT_X87_ALU, ND_SET_X87, 208, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:286 Instruction:"FCOMI ST(0),ST(i)" Encoding:"0xDB /6:reg"/"M" - { - ND_INS_FCOMI, ND_CAT_X87_ALU, ND_SET_X87, 209, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:287 Instruction:"FCOMIP ST(0),ST(i)" Encoding:"0xDF /6:reg"/"M" - { - ND_INS_FCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 210, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:288 Instruction:"FCOMP ST(0),Mfd" Encoding:"0xD8 /3:mem"/"M" - { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:289 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xD8 /3:reg"/"M" - { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:290 Instruction:"FCOMP ST(0),Mfq" Encoding:"0xDC /3:mem"/"M" - { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:291 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDC /3:reg"/"M" - { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:292 Instruction:"FCOMP ST(0),ST(i)" Encoding:"0xDE /2:reg"/"M" - { - ND_INS_FCOMP, ND_CAT_X87_ALU, ND_SET_X87, 211, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:293 Instruction:"FCOMPP" Encoding:"0xDE /0xD9"/"" - { - ND_INS_FCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 212, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:294 Instruction:"FCOS" Encoding:"0xD9 /0xFF"/"" - { - ND_INS_FCOS, ND_CAT_X87_ALU, ND_SET_X87, 213, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:295 Instruction:"FDECSTP" Encoding:"0xD9 /0xF6"/"" - { - ND_INS_FDECSTP, ND_CAT_X87_ALU, ND_SET_X87, 214, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:296 Instruction:"FDIV ST(0),Mfd" Encoding:"0xD8 /6:mem"/"M" - { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:297 Instruction:"FDIV ST(0),ST(i)" Encoding:"0xD8 /6:reg"/"M" - { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:298 Instruction:"FDIV ST(0),Mfq" Encoding:"0xDC /6:mem"/"M" - { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:299 Instruction:"FDIV ST(i),ST(0)" Encoding:"0xDC /7:reg"/"M" - { - ND_INS_FDIV, ND_CAT_X87_ALU, ND_SET_X87, 215, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:300 Instruction:"FDIVP ST(i),ST(0)" Encoding:"0xDE /7:reg"/"M" - { - ND_INS_FDIVP, ND_CAT_X87_ALU, ND_SET_X87, 216, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:301 Instruction:"FDIVR ST(0),Mfd" Encoding:"0xD8 /7:mem"/"M" - { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:302 Instruction:"FDIVR ST(0),ST(i)" Encoding:"0xD8 /7:reg"/"M" - { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:303 Instruction:"FDIVR ST(0),Mfq" Encoding:"0xDC /7:mem"/"M" - { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:304 Instruction:"FDIVR ST(i),ST(0)" Encoding:"0xDC /6:reg"/"M" - { - ND_INS_FDIVR, ND_CAT_X87_ALU, ND_SET_X87, 217, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:305 Instruction:"FDIVRP ST(i),ST(0)" Encoding:"0xDE /6:reg"/"M" - { - ND_INS_FDIVRP, ND_CAT_X87_ALU, ND_SET_X87, 218, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:306 Instruction:"FEMMS" Encoding:"0x0F 0x0E"/"" - { - ND_INS_FEMMS, ND_CAT_MMX, ND_SET_3DNOW, 219, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:307 Instruction:"FFREE ST(i)" Encoding:"0xDD /0:reg"/"M" - { - ND_INS_FFREE, ND_CAT_X87_ALU, ND_SET_X87, 220, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:308 Instruction:"FFREEP ST(i)" Encoding:"0xDF /0:reg"/"M" - { - ND_INS_FFREEP, ND_CAT_X87_ALU, ND_SET_X87, 221, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:309 Instruction:"FIADD ST(0),Md" Encoding:"0xDA /0:mem"/"M" - { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:310 Instruction:"FIADD ST(0),Mw" Encoding:"0xDE /0:mem"/"M" - { - ND_INS_FIADD, ND_CAT_X87_ALU, ND_SET_X87, 222, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:311 Instruction:"FICOM ST(0),Md" Encoding:"0xDA /2:mem"/"M" - { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:312 Instruction:"FICOM ST(0),Mw" Encoding:"0xDE /2:mem"/"M" - { - ND_INS_FICOM, ND_CAT_X87_ALU, ND_SET_X87, 223, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:313 Instruction:"FICOMP ST(0),Md" Encoding:"0xDA /3:mem"/"M" - { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:314 Instruction:"FICOMP ST(0),Mw" Encoding:"0xDE /3:mem"/"M" - { - ND_INS_FICOMP, ND_CAT_X87_ALU, ND_SET_X87, 224, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:315 Instruction:"FIDIV ST(0),Md" Encoding:"0xDA /6:mem"/"M" - { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:316 Instruction:"FIDIV ST(0),Mw" Encoding:"0xDE /6:mem"/"M" - { - ND_INS_FIDIV, ND_CAT_X87_ALU, ND_SET_X87, 225, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:317 Instruction:"FIDIVR ST(0),Md" Encoding:"0xDA /7:mem"/"M" - { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:318 Instruction:"FIDIVR ST(0),Mw" Encoding:"0xDE /7:mem"/"M" - { - ND_INS_FIDIVR, ND_CAT_X87_ALU, ND_SET_X87, 226, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:319 Instruction:"FILD ST(0),Md" Encoding:"0xDB /0:mem"/"M" - { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:320 Instruction:"FILD ST(0),Mw" Encoding:"0xDF /0:mem"/"M" - { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:321 Instruction:"FILD ST(0),Mq" Encoding:"0xDF /5:mem"/"M" - { - ND_INS_FILD, ND_CAT_X87_ALU, ND_SET_X87, 227, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:322 Instruction:"FIMUL ST(0),Md" Encoding:"0xDA /1:mem"/"M" - { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:323 Instruction:"FIMUL ST(0),Mw" Encoding:"0xDE /1:mem"/"M" - { - ND_INS_FIMUL, ND_CAT_X87_ALU, ND_SET_X87, 228, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:324 Instruction:"FINCSTP" Encoding:"0xD9 /0xF7"/"" - { - ND_INS_FINCSTP, ND_CAT_X87_ALU, ND_SET_X87, 229, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:325 Instruction:"FIST Md,ST(0)" Encoding:"0xDB /2:mem"/"M" - { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:326 Instruction:"FIST Mw,ST(0)" Encoding:"0xDF /2:mem"/"M" - { - ND_INS_FIST, ND_CAT_X87_ALU, ND_SET_X87, 230, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:327 Instruction:"FISTP Md,ST(0)" Encoding:"0xDB /3:mem"/"M" - { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:328 Instruction:"FISTP Mw,ST(0)" Encoding:"0xDF /3:mem"/"M" - { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:329 Instruction:"FISTP Mq,ST(0)" Encoding:"0xDF /7:mem"/"M" - { - ND_INS_FISTP, ND_CAT_X87_ALU, ND_SET_X87, 231, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:330 Instruction:"FISTTP Md,ST(0)" Encoding:"0xDB /1:mem"/"M" - { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:331 Instruction:"FISTTP Mq,ST(0)" Encoding:"0xDD /1:mem"/"M" - { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:332 Instruction:"FISTTP Mw,ST(0)" Encoding:"0xDF /1:mem"/"M" - { - ND_INS_FISTTP, ND_CAT_X87_ALU, ND_SET_X87, 232, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:333 Instruction:"FISUB ST(0),Md" Encoding:"0xDA /4:mem"/"M" - { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:334 Instruction:"FISUB ST(0),Mw" Encoding:"0xDE /4:mem"/"M" - { - ND_INS_FISUB, ND_CAT_X87_ALU, ND_SET_X87, 233, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:335 Instruction:"FISUBR ST(0),Md" Encoding:"0xDA /5:mem"/"M" - { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:336 Instruction:"FISUBR ST(0),Mw" Encoding:"0xDE /5:mem"/"M" - { - ND_INS_FISUBR, ND_CAT_X87_ALU, ND_SET_X87, 234, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:337 Instruction:"FLD ST(0),Mfd" Encoding:"0xD9 /0:mem"/"M" - { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:338 Instruction:"FLD ST(0),ST(i)" Encoding:"0xD9 /0:reg"/"M" - { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:339 Instruction:"FLD ST(0),Mft" Encoding:"0xDB /5:mem"/"M" - { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:340 Instruction:"FLD ST(0),Mfq" Encoding:"0xDD /0:mem"/"M" - { - ND_INS_FLD, ND_CAT_X87_ALU, ND_SET_X87, 235, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:341 Instruction:"FLD1" Encoding:"0xD9 /0xE8"/"" - { - ND_INS_FLD1, ND_CAT_X87_ALU, ND_SET_X87, 236, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:342 Instruction:"FLDCW Mw" Encoding:"0xD9 /5:mem"/"M" - { - ND_INS_FLDCW, ND_CAT_X87_ALU, ND_SET_X87, 237, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:343 Instruction:"FLDENV Mfe" Encoding:"0xD9 /4:mem"/"M" - { - ND_INS_FLDENV, ND_CAT_X87_ALU, ND_SET_X87, 238, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:344 Instruction:"FLDL2E" Encoding:"0xD9 /0xEA"/"" - { - ND_INS_FLDL2E, ND_CAT_X87_ALU, ND_SET_X87, 239, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:345 Instruction:"FLDL2T" Encoding:"0xD9 /0xE9"/"" - { - ND_INS_FLDL2T, ND_CAT_X87_ALU, ND_SET_X87, 240, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:346 Instruction:"FLDLG2" Encoding:"0xD9 /0xEC"/"" - { - ND_INS_FLDLG2, ND_CAT_X87_ALU, ND_SET_X87, 241, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:347 Instruction:"FLDLN2" Encoding:"0xD9 /0xED"/"" - { - ND_INS_FLDLN2, ND_CAT_X87_ALU, ND_SET_X87, 242, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:348 Instruction:"FLDPI" Encoding:"0xD9 /0xEB"/"" - { - ND_INS_FLDPI, ND_CAT_X87_ALU, ND_SET_X87, 243, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:349 Instruction:"FLDZ" Encoding:"0xD9 /0xEE"/"" - { - ND_INS_FLDZ, ND_CAT_X87_ALU, ND_SET_X87, 244, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:350 Instruction:"FMUL ST(0),Mfd" Encoding:"0xD8 /1:mem"/"M" - { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:351 Instruction:"FMUL ST(0),ST(i)" Encoding:"0xD8 /1:reg"/"M" - { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:352 Instruction:"FMUL ST(0),Mfq" Encoding:"0xDC /1:mem"/"M" - { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:353 Instruction:"FMUL ST(i),ST(0)" Encoding:"0xDC /1:reg"/"M" - { - ND_INS_FMUL, ND_CAT_X87_ALU, ND_SET_X87, 245, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:354 Instruction:"FMULP ST(i),ST(0)" Encoding:"0xDE /1:reg"/"M" - { - ND_INS_FMULP, ND_CAT_X87_ALU, ND_SET_X87, 246, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:355 Instruction:"FNCLEX" Encoding:"0xDB /0xE2"/"" - { - ND_INS_FNCLEX, ND_CAT_X87_ALU, ND_SET_X87, 247, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:356 Instruction:"FNDISI" Encoding:"0xDB /0xE1"/"" - { - ND_INS_FNDISI, ND_CAT_X87_ALU, ND_SET_X87, 248, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:357 Instruction:"FNINIT" Encoding:"0xDB /0xE3"/"" - { - ND_INS_FNINIT, ND_CAT_X87_ALU, ND_SET_X87, 249, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:358 Instruction:"FNOP" Encoding:"0xD9 /0xD0"/"" - { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:359 Instruction:"FNOP" Encoding:"0xDB /0xE0"/"" - { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:360 Instruction:"FNOP" Encoding:"0xDB /0xE4"/"" - { - ND_INS_FNOP, ND_CAT_X87_ALU, ND_SET_X87, 250, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:361 Instruction:"FNSAVE Mfs" Encoding:"0xDD /6:mem"/"M" - { - ND_INS_FNSAVE, ND_CAT_X87_ALU, ND_SET_X87, 251, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0x00, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:362 Instruction:"FNSTCW Mw" Encoding:"0xD9 /7:mem"/"M" - { - ND_INS_FNSTCW, ND_CAT_X87_ALU, ND_SET_X87, 252, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:363 Instruction:"FNSTENV Mfe" Encoding:"0xD9 /6:mem"/"M" - { - ND_INS_FNSTENV, ND_CAT_X87_ALU, ND_SET_X87, 253, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fe, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:364 Instruction:"FNSTSW Mw" Encoding:"0xDD /7:mem"/"M" - { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:365 Instruction:"FNSTSW AX" Encoding:"0xDF /0xE0"/"" - { - ND_INS_FNSTSW, ND_CAT_X87_ALU, ND_SET_X87, 254, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:366 Instruction:"FPATAN" Encoding:"0xD9 /0xF3"/"" - { - ND_INS_FPATAN, ND_CAT_X87_ALU, ND_SET_X87, 255, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:367 Instruction:"FPREM" Encoding:"0xD9 /0xF8"/"" - { - ND_INS_FPREM, ND_CAT_X87_ALU, ND_SET_X87, 256, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:368 Instruction:"FPREM1" Encoding:"0xD9 /0xF5"/"" - { - ND_INS_FPREM1, ND_CAT_X87_ALU, ND_SET_X87, 257, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:369 Instruction:"FPTAN" Encoding:"0xD9 /0xF2"/"" - { - ND_INS_FPTAN, ND_CAT_X87_ALU, ND_SET_X87, 258, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:370 Instruction:"FRINEAR" Encoding:"0xDF /0xFC"/"" - { - ND_INS_FRINEAR, ND_CAT_X87_ALU, ND_SET_X87, 259, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:371 Instruction:"FRNDINT" Encoding:"0xD9 /0xFC"/"" - { - ND_INS_FRNDINT, ND_CAT_X87_ALU, ND_SET_X87, 260, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:372 Instruction:"FRSTOR Mfs" Encoding:"0xDD /4:mem"/"M" - { - ND_INS_FRSTOR, ND_CAT_X87_ALU, ND_SET_X87, 261, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fs, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_CONTROL, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:373 Instruction:"FSCALE" Encoding:"0xD9 /0xFD"/"" - { - ND_INS_FSCALE, ND_CAT_X87_ALU, ND_SET_X87, 262, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:374 Instruction:"FSIN" Encoding:"0xD9 /0xFE"/"" - { - ND_INS_FSIN, ND_CAT_X87_ALU, ND_SET_X87, 263, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:375 Instruction:"FSINCOS" Encoding:"0xD9 /0xFB"/"" - { - ND_INS_FSINCOS, ND_CAT_X87_ALU, ND_SET_X87, 264, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xeb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:376 Instruction:"FSQRT" Encoding:"0xD9 /0xFA"/"" - { - ND_INS_FSQRT, ND_CAT_X87_ALU, ND_SET_X87, 265, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:377 Instruction:"FST Mfd,ST(0)" Encoding:"0xD9 /2:mem"/"M" - { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:378 Instruction:"FST Mfq,ST(0)" Encoding:"0xDD /2:mem"/"M" - { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:379 Instruction:"FST ST(i),ST(0)" Encoding:"0xDD /2:reg"/"M" - { - ND_INS_FST, ND_CAT_X87_ALU, ND_SET_X87, 266, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:380 Instruction:"FSTDW AX" Encoding:"0xDF /0xE1"/"" - { - ND_INS_FSTDW, ND_CAT_X87_ALU, ND_SET_X87, 267, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:381 Instruction:"FSTP Mfd,ST(0)" Encoding:"0xD9 /3:mem"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:382 Instruction:"FSTP Mft,ST(0)" Encoding:"0xDB /7:mem"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:383 Instruction:"FSTP Mfq,ST(0)" Encoding:"0xDD /3:mem"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:384 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDD /3:reg"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:385 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /2:reg"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:386 Instruction:"FSTP ST(i),ST(0)" Encoding:"0xDF /3:reg"/"M" - { - ND_INS_FSTP, ND_CAT_X87_ALU, ND_SET_X87, 268, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:387 Instruction:"FSTPNCE ST(i),ST(0)" Encoding:"0xD9 /3:reg"/"M" - { - ND_INS_FSTPNCE, ND_CAT_X87_ALU, ND_SET_X87, 269, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:388 Instruction:"FSTSG AX" Encoding:"0xDF /0xE2"/"" - { - ND_INS_FSTSG, ND_CAT_X87_ALU, ND_SET_X87, 270, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0xff, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:389 Instruction:"FSUB ST(0),Mfd" Encoding:"0xD8 /4:mem"/"M" - { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:390 Instruction:"FSUB ST(0),ST(i)" Encoding:"0xD8 /4:reg"/"M" - { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:391 Instruction:"FSUB ST(0),Mfq" Encoding:"0xDC /4:mem"/"M" - { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:392 Instruction:"FSUB ST(i),ST(0)" Encoding:"0xDC /5:reg"/"M" - { - ND_INS_FSUB, ND_CAT_X87_ALU, ND_SET_X87, 271, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:393 Instruction:"FSUBP ST(i),ST(0)" Encoding:"0xDE /5:reg"/"M" - { - ND_INS_FSUBP, ND_CAT_X87_ALU, ND_SET_X87, 272, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:394 Instruction:"FSUBR ST(0),Mfd" Encoding:"0xD8 /5:mem"/"M" - { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:395 Instruction:"FSUBR ST(0),ST(i)" Encoding:"0xD8 /5:reg"/"M" - { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:396 Instruction:"FSUBR ST(0),Mfq" Encoding:"0xDC /5:mem"/"M" - { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_fq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:397 Instruction:"FSUBR ST(i),ST(0)" Encoding:"0xDC /4:reg"/"M" - { - ND_INS_FSUBR, ND_CAT_X87_ALU, ND_SET_X87, 273, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:398 Instruction:"FSUBRP ST(i),ST(0)" Encoding:"0xDE /4:reg"/"M" - { - ND_INS_FSUBRP, ND_CAT_X87_ALU, ND_SET_X87, 274, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:399 Instruction:"FTST" Encoding:"0xD9 /0xE4"/"" - { - ND_INS_FTST, ND_CAT_X87_ALU, ND_SET_X87, 275, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:400 Instruction:"FUCOM ST(0),ST(i)" Encoding:"0xDD /4:reg"/"M" - { - ND_INS_FUCOM, ND_CAT_X87_ALU, ND_SET_X87, 276, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:401 Instruction:"FUCOMI ST(0),ST(i)" Encoding:"0xDB /5:reg"/"M" - { - ND_INS_FUCOMI, ND_CAT_X87_ALU, ND_SET_X87, 277, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:402 Instruction:"FUCOMIP ST(0),ST(i)" Encoding:"0xDF /5:reg"/"M" - { - ND_INS_FUCOMIP, ND_CAT_X87_ALU, ND_SET_X87, 278, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0xa2, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_OF, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:403 Instruction:"FUCOMP ST(0),ST(i)" Encoding:"0xDD /5:reg"/"M" - { - ND_INS_FUCOMP, ND_CAT_X87_ALU, ND_SET_X87, 279, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:404 Instruction:"FUCOMPP" Encoding:"0xDA /0xE9"/"" - { - ND_INS_FUCOMPP, ND_CAT_X87_ALU, ND_SET_X87, 280, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:405 Instruction:"FXAM" Encoding:"0xD9 /0xE5"/"" - { - ND_INS_FXAM, ND_CAT_X87_ALU, ND_SET_X87, 281, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xaa, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:406 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xD9 /1:reg"/"M" - { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:407 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDD /1:reg"/"M" - { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:408 Instruction:"FXCH ST(0),ST(i)" Encoding:"0xDF /1:reg"/"M" - { - ND_INS_FXCH, ND_CAT_X87_ALU, ND_SET_X87, 282, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0xf3, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_FPU_ST0, ND_OPS_ft, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_FPU_STX, ND_OPS_ft, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_X87_TAG, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:409 Instruction:"FXRSTOR Mrx" Encoding:"NP 0x0F 0xAE /1:mem"/"M" - { - ND_INS_FXRSTOR, ND_CAT_SSE, ND_SET_FXSAVE, 283, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:410 Instruction:"FXRSTOR64 Mrx" Encoding:"rexw NP 0x0F 0xAE /1:mem"/"M" - { - ND_INS_FXRSTOR64, ND_CAT_SSE, ND_SET_FXSAVE, 284, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:411 Instruction:"FXSAVE Mrx" Encoding:"NP 0x0F 0xAE /0:mem"/"M" - { - ND_INS_FXSAVE, ND_CAT_SSE, ND_SET_FXSAVE, 285, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:412 Instruction:"FXSAVE64 Mrx" Encoding:"rexw NP 0x0F 0xAE /0:mem"/"M" - { - ND_INS_FXSAVE64, ND_CAT_SSE, ND_SET_FXSAVE, 286, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_FXSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_rx, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:413 Instruction:"FXTRACT" Encoding:"0xD9 /0xF4"/"" - { - ND_INS_FXTRACT, ND_CAT_X87_ALU, ND_SET_X87, 287, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:414 Instruction:"FYL2X" Encoding:"0xD9 /0xF1"/"" - { - ND_INS_FYL2X, ND_CAT_X87_ALU, ND_SET_X87, 288, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:415 Instruction:"FYL2XP1" Encoding:"0xD9 /0xF9"/"" - { - ND_INS_FYL2XP1, ND_CAT_X87_ALU, ND_SET_X87, 289, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0xfb, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_X87_STATUS, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:416 Instruction:"GETSEC" Encoding:"NP 0x0F 0x37"/"" - { - ND_INS_GETSEC, ND_CAT_SYSTEM, ND_SET_SMX, 290, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, ND_CFF_SMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:417 Instruction:"GF2P8AFFINEINVQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCF /r ib"/"RMI" - { - ND_INS_GF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 291, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:418 Instruction:"GF2P8AFFINEQB Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0xCE /r ib"/"RMI" - { - ND_INS_GF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 292, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:419 Instruction:"GF2P8MULB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0xCF /r"/"RM" - { - ND_INS_GF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 293, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:420 Instruction:"HADDPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7C /r"/"RM" - { - ND_INS_HADDPD, ND_CAT_SSE, ND_SET_SSE3, 294, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:421 Instruction:"HADDPS Vps,Wps" Encoding:"0xF2 0x0F 0x7C /r"/"RM" - { - ND_INS_HADDPS, ND_CAT_SSE, ND_SET_SSE3, 295, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:422 Instruction:"HLT" Encoding:"0xF4"/"" - { - ND_INS_HLT, ND_CAT_SYSTEM, ND_SET_I86, 296, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:423 Instruction:"HRESET Ib" Encoding:"0xF3 0x0F 0x3A 0xF0 /0xC0 ib"/"I" - { - ND_INS_HRESET, ND_CAT_HRESET, ND_SET_HRESET, 297, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_HRESET, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:424 Instruction:"HSUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x7D /r"/"RM" - { - ND_INS_HSUBPD, ND_CAT_SSE, ND_SET_SSE3, 298, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:425 Instruction:"HSUBPS Vps,Wps" Encoding:"0xF2 0x0F 0x7D /r"/"RM" - { - ND_INS_HSUBPS, ND_CAT_SSE, ND_SET_SSE3, 299, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:426 Instruction:"IDIV Eb" Encoding:"0xF6 /7"/"M" - { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:427 Instruction:"IDIV Ev" Encoding:"0xF7 /7"/"M" - { - ND_INS_IDIV, ND_CAT_ARITH, ND_SET_I86, 300, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:428 Instruction:"IMUL Gv,Ev" Encoding:"0x0F 0xAF /r"/"RM" - { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:429 Instruction:"IMUL Gv,Ev,Iz" Encoding:"0x69 /r iz"/"RMI" - { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:430 Instruction:"IMUL Gv,Ev,Ib" Encoding:"0x6B /r ib"/"RMI" - { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:431 Instruction:"IMUL Eb" Encoding:"0xF6 /5"/"M" - { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:432 Instruction:"IMUL Ev" Encoding:"0xF7 /5"/"M" - { - ND_INS_IMUL, ND_CAT_ARITH, ND_SET_I86, 301, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:433 Instruction:"IN AL,Ib" Encoding:"0xE4 ib"/"I" - { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:434 Instruction:"IN eAX,Ib" Encoding:"0xE5 ib"/"I" - { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:435 Instruction:"IN AL,DX" Encoding:"0xEC"/"" - { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:436 Instruction:"IN eAX,DX" Encoding:"0xED"/"" - { - ND_INS_IN, ND_CAT_IO, ND_SET_I86, 302, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:437 Instruction:"INC Zv" Encoding:"0x40"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:438 Instruction:"INC Zv" Encoding:"0x41"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:439 Instruction:"INC Zv" Encoding:"0x42"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:440 Instruction:"INC Zv" Encoding:"0x43"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:441 Instruction:"INC Zv" Encoding:"0x44"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:442 Instruction:"INC Zv" Encoding:"0x45"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:443 Instruction:"INC Zv" Encoding:"0x46"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:444 Instruction:"INC Zv" Encoding:"0x47"/"O" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:445 Instruction:"INC Eb" Encoding:"0xFE /0"/"M" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:446 Instruction:"INC Ev" Encoding:"0xFF /0"/"M" - { - ND_INS_INC, ND_CAT_ARITH, ND_SET_I86, 303, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:447 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M" - { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 304, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:448 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M" - { - ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 305, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHS, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:449 Instruction:"INSB Yb,DX" Encoding:"0x6C"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:450 Instruction:"INSB Yb,DX" Encoding:"rep 0x6C"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 306, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:451 Instruction:"INSD Yz,DX" Encoding:"0x6D"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:452 Instruction:"INSD Yz,DX" Encoding:"rep 0x6D"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 307, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:453 Instruction:"INSERTPS Vdq,Md,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:mem ib"/"RMI" - { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:454 Instruction:"INSERTPS Vdq,Udq,Ib" Encoding:"0x66 0x0F 0x3A 0x21 /r:reg ib"/"RMI" - { - ND_INS_INSERTPS, ND_CAT_SSE, ND_SET_SSE4, 308, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:455 Instruction:"INSERTQ Vdq,Udq,Ib,Ib" Encoding:"0xF2 0x0F 0x78 /r ib ib"/"RMII" - { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:456 Instruction:"INSERTQ Vdq,Udq" Encoding:"0xF2 0x0F 0x79 /r:reg"/"RM" - { - ND_INS_INSERTQ, ND_CAT_BITBYTE, ND_SET_SSE4A, 309, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:457 Instruction:"INSW Yz,DX" Encoding:"ds16 0x6D"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:458 Instruction:"INSW Yz,DX" Encoding:"rep ds16 0x6D"/"" - { - ND_INS_INS, ND_CAT_IOSTRINGOP, ND_SET_I86, 310, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:459 Instruction:"INT Ib" Encoding:"0xCD ib"/"I" - { - ND_INS_INT, ND_CAT_INTERRUPT, ND_SET_I86, 311, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, - 0|NDR_RFLAG_VM, - 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:460 Instruction:"INT1" Encoding:"0xF1"/"" - { - ND_INS_INT1, ND_CAT_INTERRUPT, ND_SET_I86, 312, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_VM, - 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:461 Instruction:"INT3" Encoding:"0xCC"/"" - { - ND_INS_INT3, ND_CAT_INTERRUPT, ND_SET_I86, 313, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, 0, - 0|NDR_RFLAG_VM, - 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:462 Instruction:"INTO" Encoding:"0xCE"/"" - { - ND_INS_INTO, ND_CAT_INTERRUPT, ND_SET_I86, 314, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_I64, 0, - 0|NDR_RFLAG_VM, - 0|NDR_RFLAG_VM|NDR_RFLAG_IF|NDR_RFLAG_NT|NDR_RFLAG_AC|NDR_RFLAG_RF|NDR_RFLAG_TF, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:463 Instruction:"INVD" Encoding:"0x0F 0x08"/"" - { - ND_INS_INVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 315, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:464 Instruction:"INVEPT Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x80 /r:mem"/"RM" - { - ND_INS_INVEPT, ND_CAT_VTX, ND_SET_VTX, 316, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:465 Instruction:"INVLPG Mb" Encoding:"0x0F 0x01 /7:mem"/"M" - { - ND_INS_INVLPG, ND_CAT_SYSTEM, ND_SET_I486REAL, 317, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:466 Instruction:"INVLPGA" Encoding:"0x0F 0x01 /0xDF"/"" - { - ND_INS_INVLPGA, ND_CAT_SYSTEM, ND_SET_SVM, 318, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:467 Instruction:"INVLPGB" Encoding:"0x0F 0x01 /0xFE"/"" - { - ND_INS_INVLPGB, ND_CAT_SYSTEM, ND_SET_INVLPGB, 319, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:468 Instruction:"INVPCID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x82 /r:mem"/"RM" - { - ND_INS_INVPCID, ND_CAT_MISC, ND_SET_INVPCID, 320, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_INVPCID, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:469 Instruction:"INVVPID Gy,Mdq" Encoding:"0x66 0x0F 0x38 0x81 /r:mem"/"RM" - { - ND_INS_INVVPID, ND_CAT_VTX, ND_SET_VTX, 321, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:470 Instruction:"IRETD" Encoding:"ds32 0xCF"/"" - { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 322, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:471 Instruction:"IRETQ" Encoding:"ds64 0xCF"/"" - { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 323, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:472 Instruction:"IRETW" Encoding:"ds16 0xCF"/"" - { - ND_INS_IRET, ND_CAT_RET, ND_SET_I86, 324, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:473 Instruction:"JBE Jz" Encoding:"0x0F 0x86 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:474 Instruction:"JBE Jb" Encoding:"0x76 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 325, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:475 Instruction:"JC Jz" Encoding:"0x0F 0x82 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:476 Instruction:"JC Jb" Encoding:"0x72 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 326, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:477 Instruction:"JCXZ Jb" Encoding:"as16 0xE3 cb"/"D" - { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 327, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - }, - }, - - // Pos:478 Instruction:"JECXZ Jb" Encoding:"as32 0xE3 cb"/"D" - { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 328, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - }, - }, - - // Pos:479 Instruction:"JL Jz" Encoding:"0x0F 0x8C cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:480 Instruction:"JL Jb" Encoding:"0x7C cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 329, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:481 Instruction:"JLE Jz" Encoding:"0x0F 0x8E cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:482 Instruction:"JLE Jb" Encoding:"0x7E cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 330, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:483 Instruction:"JMP Jz" Encoding:"0xE9 cz"/"D" - { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, - ND_PREF_BND, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:484 Instruction:"JMP Jb" Encoding:"0xEB cb"/"D" - { - ND_INS_JMPNR, ND_CAT_UNCOND_BR, ND_SET_I86, 331, - ND_PREF_BND, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:485 Instruction:"JMP Ev" Encoding:"0xFF /4"/"M" - { - ND_INS_JMPNI, ND_CAT_UNCOND_BR, ND_SET_I86, 331, - ND_PREF_BND|ND_PREF_DNT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:486 Instruction:"JMPE Ev" Encoding:"NP 0x0F 0x00 /6"/"M" - { - ND_INS_JMPE, ND_CAT_SYSTEM, ND_SET_I64, 332, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:487 Instruction:"JMPE Jz" Encoding:"0x0F 0xB8 cz"/"D" - { - ND_INS_JMPE, ND_CAT_UNCOND_BR, ND_SET_I64, 332, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:488 Instruction:"JMPF Ap" Encoding:"0xEA cp"/"D" - { - ND_INS_JMPFD, ND_CAT_UNCOND_BR, ND_SET_I86, 333, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_A, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:489 Instruction:"JMPF Mp" Encoding:"0xFF /5:mem"/"M" - { - ND_INS_JMPFI, ND_CAT_UNCOND_BR, ND_SET_I86, 333, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:490 Instruction:"JNBE Jz" Encoding:"0x0F 0x87 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:491 Instruction:"JNBE Jb" Encoding:"0x77 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 334, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:492 Instruction:"JNC Jz" Encoding:"0x0F 0x83 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:493 Instruction:"JNC Jb" Encoding:"0x73 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 335, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:494 Instruction:"JNL Jz" Encoding:"0x0F 0x8D cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:495 Instruction:"JNL Jb" Encoding:"0x7D cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 336, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:496 Instruction:"JNLE Jz" Encoding:"0x0F 0x8F cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:497 Instruction:"JNLE Jb" Encoding:"0x7F cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 337, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:498 Instruction:"JNO Jz" Encoding:"0x0F 0x81 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:499 Instruction:"JNO Jb" Encoding:"0x71 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 338, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:500 Instruction:"JNP Jz" Encoding:"0x0F 0x8B cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:501 Instruction:"JNP Jb" Encoding:"0x7B cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 339, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:502 Instruction:"JNS Jz" Encoding:"0x0F 0x89 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:503 Instruction:"JNS Jb" Encoding:"0x79 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 340, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:504 Instruction:"JNZ Jz" Encoding:"0x0F 0x85 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:505 Instruction:"JNZ Jb" Encoding:"0x75 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 341, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:506 Instruction:"JO Jz" Encoding:"0x0F 0x80 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:507 Instruction:"JO Jb" Encoding:"0x70 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 342, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:508 Instruction:"JP Jz" Encoding:"0x0F 0x8A cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:509 Instruction:"JP Jb" Encoding:"0x7A cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 343, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:510 Instruction:"JRCXZ Jb" Encoding:"as64 0xE3 cb"/"D" - { - ND_INS_JrCXZ, ND_CAT_COND_BR, ND_SET_I86, 344, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - }, - }, - - // Pos:511 Instruction:"JS Jz" Encoding:"0x0F 0x88 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:512 Instruction:"JS Jb" Encoding:"0x78 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 345, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:513 Instruction:"JZ Jz" Encoding:"0x0F 0x84 cz"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:514 Instruction:"JZ Jb" Encoding:"0x74 cb"/"D" - { - ND_INS_Jcc, ND_CAT_COND_BR, ND_SET_I86, 346, - ND_PREF_BND|ND_PREF_BHINT, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_COND, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:515 Instruction:"KADDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4A /r:reg"/"RVM" - { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 347, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:516 Instruction:"KADDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x4A /r:reg"/"RVM" - { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 348, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:517 Instruction:"KADDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x4A /r:reg"/"RVM" - { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512BW, 349, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:518 Instruction:"KADDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4A /r:reg"/"RVM" - { - ND_INS_KADD, ND_CAT_KMASK, ND_SET_AVX512DQ, 350, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:519 Instruction:"KANDB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x41 /r:reg"/"RVM" - { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512DQ, 351, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:520 Instruction:"KANDD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x41 /r:reg"/"RVM" - { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 352, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:521 Instruction:"KANDNB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x42 /r:reg"/"RVM" - { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512DQ, 353, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:522 Instruction:"KANDND rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x42 /r:reg"/"RVM" - { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 354, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:523 Instruction:"KANDNQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x42 /r:reg"/"RVM" - { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512BW, 355, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:524 Instruction:"KANDNW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x42 /r:reg"/"RVM" - { - ND_INS_KANDN, ND_CAT_KMASK, ND_SET_AVX512F, 356, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:525 Instruction:"KANDQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x41 /r:reg"/"RVM" - { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512BW, 357, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:526 Instruction:"KANDW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x41 /r:reg"/"RVM" - { - ND_INS_KAND, ND_CAT_KMASK, ND_SET_AVX512F, 358, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:527 Instruction:"KMERGE2L1H rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x48 /r:reg"/"RM" - { - ND_INS_KMERGE2L1H, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 359, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:528 Instruction:"KMERGE2L1L rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x49 /r:reg"/"RM" - { - ND_INS_KMERGE2L1L, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 360, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:529 Instruction:"KMOVB rKb,Mb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:mem"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:530 Instruction:"KMOVB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x90 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:531 Instruction:"KMOVB Mb,rKb" Encoding:"vex m:1 p:1 l:0 w:0 0x91 /r:mem"/"MR" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:532 Instruction:"KMOVB rKb,Ry" Encoding:"vex m:1 p:1 l:0 w:0 0x92 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:533 Instruction:"KMOVB Gy,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x93 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512DQ, 361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:534 Instruction:"KMOVD rKd,Md" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:mem"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:535 Instruction:"KMOVD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x90 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:536 Instruction:"KMOVD Md,rKd" Encoding:"vex m:1 p:1 l:0 w:1 0x91 /r:mem"/"MR" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:537 Instruction:"KMOVD rKd,Ry" Encoding:"vex m:1 p:3 l:0 w:0 0x92 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:538 Instruction:"KMOVD Gy,mKd" Encoding:"vex m:1 p:3 l:0 w:0 0x93 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:539 Instruction:"KMOVQ rKq,Mq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:mem"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:540 Instruction:"KMOVQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x90 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:541 Instruction:"KMOVQ Mq,rKq" Encoding:"vex m:1 p:0 l:0 w:1 0x91 /r:mem"/"MR" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:542 Instruction:"KMOVQ rKq,Ry" Encoding:"vex m:1 p:3 l:0 w:1 0x92 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:543 Instruction:"KMOVQ Gy,mKq" Encoding:"vex m:1 p:3 l:0 w:1 0x93 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512BW, 363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:544 Instruction:"KMOVW rKw,Mw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:mem"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:545 Instruction:"KMOVW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x90 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:546 Instruction:"KMOVW Mw,rKw" Encoding:"vex m:1 p:0 l:0 w:0 0x91 /r:mem"/"MR" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K21, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:547 Instruction:"KMOVW rKw,Ry" Encoding:"vex m:1 p:0 l:0 w:0 0x92 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:548 Instruction:"KMOVW Gy,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x93 /r:reg"/"RM" - { - ND_INS_KMOV, ND_CAT_KMASK, ND_SET_AVX512F, 364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:549 Instruction:"KNOTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x44 /r:reg"/"RM" - { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512DQ, 365, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:550 Instruction:"KNOTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x44 /r:reg"/"RM" - { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 366, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:551 Instruction:"KNOTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x44 /r:reg"/"RM" - { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512BW, 367, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:552 Instruction:"KNOTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x44 /r:reg"/"RM" - { - ND_INS_KNOT, ND_CAT_KMASK, ND_SET_AVX512F, 368, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:553 Instruction:"KORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x45 /r:reg"/"RVM" - { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 369, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:554 Instruction:"KORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x45 /r:reg"/"RVM" - { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 370, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:555 Instruction:"KORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x45 /r:reg"/"RVM" - { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512BW, 371, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:556 Instruction:"KORTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x98 /r:reg"/"RM" - { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 372, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:557 Instruction:"KORTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x98 /r:reg"/"RM" - { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 373, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:558 Instruction:"KORTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x98 /r:reg"/"RM" - { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 374, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:559 Instruction:"KORTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x98 /r:reg"/"RM" - { - ND_INS_KORTEST, ND_CAT_KMASK, ND_SET_AVX512F, 375, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:560 Instruction:"KORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x45 /r:reg"/"RVM" - { - ND_INS_KOR, ND_CAT_KMASK, ND_SET_AVX512F, 376, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:561 Instruction:"KSHIFTLB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x32 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512DQ, 377, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:562 Instruction:"KSHIFTLD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x33 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 378, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:563 Instruction:"KSHIFTLQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x33 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512BW, 379, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:564 Instruction:"KSHIFTLW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x32 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTL, ND_CAT_KMASK, ND_SET_AVX512F, 380, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:565 Instruction:"KSHIFTRB rKb,mKb,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x30 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512DQ, 381, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:566 Instruction:"KSHIFTRD rKd,mKd,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x31 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 382, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:567 Instruction:"KSHIFTRQ rKq,mKq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x31 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512BW, 383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:568 Instruction:"KSHIFTRW rKw,mKw,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x30 /r:reg ib"/"RMI" - { - ND_INS_KSHIFTR, ND_CAT_KMASK, ND_SET_AVX512F, 384, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:569 Instruction:"KTESTB rKb,mKb" Encoding:"vex m:1 p:1 l:0 w:0 0x99 /r:reg"/"RM" - { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 385, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:570 Instruction:"KTESTD rKd,mKd" Encoding:"vex m:1 p:1 l:0 w:1 0x99 /r:reg"/"RM" - { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 386, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:571 Instruction:"KTESTQ rKq,mKq" Encoding:"vex m:1 p:0 l:0 w:1 0x99 /r:reg"/"RM" - { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512BW, 387, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:572 Instruction:"KTESTW rKw,mKw" Encoding:"vex m:1 p:0 l:0 w:0 0x99 /r:reg"/"RM" - { - ND_INS_KTEST, ND_CAT_KMASK, ND_SET_AVX512DQ, 388, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:573 Instruction:"KUNPCKBW rKw,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x4B /r:reg"/"RVM" - { - ND_INS_KUNPCKBW, ND_CAT_KMASK, ND_SET_AVX512F, 389, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:574 Instruction:"KUNPCKDQ rKq,vKd,mKd" Encoding:"vex m:1 p:0 l:1 w:1 0x4B /r:reg"/"RVM" - { - ND_INS_KUNPCKDQ, ND_CAT_KMASK, ND_SET_AVX512BW, 390, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:575 Instruction:"KUNPCKWD rKd,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x4B /r:reg"/"RVM" - { - ND_INS_KUNPCKWD, ND_CAT_KMASK, ND_SET_AVX512BW, 391, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:576 Instruction:"KXNORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x46 /r:reg"/"RVM" - { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 392, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:577 Instruction:"KXNORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x46 /r:reg"/"RVM" - { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 393, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:578 Instruction:"KXNORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x46 /r:reg"/"RVM" - { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512BW, 394, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:579 Instruction:"KXNORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x46 /r:reg"/"RVM" - { - ND_INS_KXNOR, ND_CAT_KMASK, ND_SET_AVX512F, 395, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:580 Instruction:"KXORB rKb,vKb,mKb" Encoding:"vex m:1 p:1 l:1 w:0 0x47 /r:reg"/"RVM" - { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512DQ, 396, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:581 Instruction:"KXORD rKd,vKd,mKd" Encoding:"vex m:1 p:1 l:1 w:1 0x47 /r:reg"/"RVM" - { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 397, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:582 Instruction:"KXORQ rKq,vKq,mKq" Encoding:"vex m:1 p:0 l:1 w:1 0x47 /r:reg"/"RVM" - { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512BW, 398, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:583 Instruction:"KXORW rKw,vKw,mKw" Encoding:"vex m:1 p:0 l:1 w:0 0x47 /r:reg"/"RVM" - { - ND_INS_KXOR, ND_CAT_KMASK, ND_SET_AVX512F, 399, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_K20, ND_EXC_OPMASK, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_vK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_mK, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:584 Instruction:"LAHF" Encoding:"0x9F"/"" - { - ND_INS_LAHF, ND_CAT_FLAGOP, ND_SET_I86, 400, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:585 Instruction:"LAR Gv,Mw" Encoding:"0x0F 0x02 /r:mem"/"RM" - { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:586 Instruction:"LAR Gv,Rz" Encoding:"0x0F 0x02 /r:reg"/"RM" - { - ND_INS_LAR, ND_CAT_SYSTEM, ND_SET_I286PROT, 401, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_CW, 0, 0), - OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:587 Instruction:"LDDQU Vx,Mx" Encoding:"0xF2 0x0F 0xF0 /r:mem"/"RM" - { - ND_INS_LDDQU, ND_CAT_SSE, ND_SET_SSE3, 402, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:588 Instruction:"LDMXCSR Md" Encoding:"NP 0x0F 0xAE /2:mem"/"M" - { - ND_INS_LDMXCSR, ND_CAT_SSE, ND_SET_SSE, 403, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:589 Instruction:"LDS Gz,Mp" Encoding:"0xC5 /r:mem"/"RM" - { - ND_INS_LDS, ND_CAT_SEGOP, ND_SET_I86, 404, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_DS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:590 Instruction:"LDTILECFG Moq" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0:mem"/"M" - { - ND_INS_LDTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 405, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E1, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:591 Instruction:"LEA Gv,M0" Encoding:"0x8D /r:mem"/"RM" - { - ND_INS_LEA, ND_CAT_MISC, ND_SET_I86, 406, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_AG|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_0, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:592 Instruction:"LEAVE" Encoding:"0xC9"/"" - { - ND_INS_LEAVE, ND_CAT_MISC, ND_SET_I186, 407, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rBP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:593 Instruction:"LES Gz,Mp" Encoding:"0xC4 /r:mem"/"RM" - { - ND_INS_LES, ND_CAT_SEGOP, ND_SET_I86, 408, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_z, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_ES, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:594 Instruction:"LFENCE" Encoding:"NP 0x0F 0xAE /5:reg"/"" - { - ND_INS_LFENCE, ND_CAT_MISC, ND_SET_SSE2, 409, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:595 Instruction:"LFS Gv,Mp" Encoding:"0x0F 0xB4 /r:mem"/"RM" - { - ND_INS_LFS, ND_CAT_SEGOP, ND_SET_I386, 410, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_FS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:596 Instruction:"LGDT Ms" Encoding:"0x0F 0x01 /2:mem"/"M" - { - ND_INS_LGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 411, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:597 Instruction:"LGS Gv,Mp" Encoding:"0x0F 0xB5 /r:mem"/"RM" - { - ND_INS_LGS, ND_CAT_SEGOP, ND_SET_I386, 412, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_GS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:598 Instruction:"LIDT Ms" Encoding:"0x0F 0x01 /3:mem"/"M" - { - ND_INS_LIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 413, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:599 Instruction:"LKGS Mw" Encoding:"0xF2 0x0F 0x00 /6:mem"/"M" - { - ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:600 Instruction:"LKGS Rv" Encoding:"0xF2 0x0F 0x00 /6:reg"/"M" - { - ND_INS_LKGS, ND_CAT_LKGS, ND_SET_LKGS, 414, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_LKGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:601 Instruction:"LLDT Ew" Encoding:"0x0F 0x00 /2"/"M" - { - ND_INS_LLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 415, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:602 Instruction:"LLWPCB Ry" Encoding:"xop m:9 0x12 /0:reg"/"M" - { - ND_INS_LLWPCB, ND_CAT_LWP, ND_SET_LWP, 416, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:603 Instruction:"LMSW Ew" Encoding:"0x0F 0x01 /6"/"M" - { - ND_INS_LMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 417, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:604 Instruction:"LOADIWKEY Vdq,Udq" Encoding:"0xF3 0x0F 0x38 0xDC /r:reg"/"RM" - { - ND_INS_LOADIWKEY, ND_CAT_KL, ND_SET_KL, 418, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_KL, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:605 Instruction:"LODSB AL,Xb" Encoding:"0xAC"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:606 Instruction:"LODSB AL,Xb" Encoding:"rep 0xAC"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 419, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:607 Instruction:"LODSD EAX,Xv" Encoding:"ds32 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:608 Instruction:"LODSD EAX,Xv" Encoding:"rep ds32 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 420, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:609 Instruction:"LODSQ RAX,Xv" Encoding:"ds64 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:610 Instruction:"LODSQ RAX,Xv" Encoding:"rep ds64 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 421, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:611 Instruction:"LODSW AX,Xv" Encoding:"ds16 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:612 Instruction:"LODSW AX,Xv" Encoding:"rep ds16 0xAD"/"" - { - ND_INS_LODS, ND_CAT_STRINGOP, ND_SET_I86, 422, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:613 Instruction:"LOOP Jb" Encoding:"0xE2 cb"/"D" - { - ND_INS_LOOP, ND_CAT_COND_BR, ND_SET_I86, 423, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:614 Instruction:"LOOPNZ Jb" Encoding:"0xE0 cb"/"D" - { - ND_INS_LOOPNZ, ND_CAT_COND_BR, ND_SET_I86, 424, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:615 Instruction:"LOOPZ Jb" Encoding:"0xE1 cb"/"D" - { - ND_INS_LOOPZ, ND_CAT_COND_BR, ND_SET_I86, 425, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CRCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:616 Instruction:"LSL Gv,Mw" Encoding:"0x0F 0x03 /r:mem"/"RM" - { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:617 Instruction:"LSL Gv,Rz" Encoding:"0x0F 0x03 /r:reg"/"RM" - { - ND_INS_LSL, ND_CAT_SYSTEM, ND_SET_I286PROT, 426, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_R, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:618 Instruction:"LSS Gv,Mp" Encoding:"0x0F 0xB2 /r:mem"/"RM" - { - ND_INS_LSS, ND_CAT_SEGOP, ND_SET_I386, 427, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_p, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:619 Instruction:"LTR Ew" Encoding:"0x0F 0x00 /3"/"M" - { - ND_INS_LTR, ND_CAT_SYSTEM, ND_SET_I286PROT, 428, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:620 Instruction:"LWPINS By,Ed,Id" Encoding:"xop m:A 0x12 /0 id"/"VMI" - { - ND_INS_LWPINS, ND_CAT_LWP, ND_SET_LWP, 429, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:621 Instruction:"LWPVAL By,Ed,Id" Encoding:"xop m:A 0x12 /1 id"/"VMI" - { - ND_INS_LWPVAL, ND_CAT_LWP, ND_SET_LWP, 430, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:622 Instruction:"LZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBD /r"/"RM" - { - ND_INS_LZCNT, ND_CAT_LZCNT, ND_SET_LZCNT, 431, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LZCNT, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:623 Instruction:"MASKMOVDQU Vdq,Udq" Encoding:"0x66 0x0F 0xF7 /r:reg"/"RM" - { - ND_INS_MASKMOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 432, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:624 Instruction:"MASKMOVQ Pq,Nq" Encoding:"NP 0x0F 0xF7 /r:reg"/"RM" - { - ND_INS_MASKMOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 433, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_rDI, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:625 Instruction:"MAXPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5F /r"/"RM" - { - ND_INS_MAXPD, ND_CAT_SSE, ND_SET_SSE2, 434, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:626 Instruction:"MAXPS Vps,Wps" Encoding:"NP 0x0F 0x5F /r"/"RM" - { - ND_INS_MAXPS, ND_CAT_SSE, ND_SET_SSE, 435, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:627 Instruction:"MAXSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5F /r"/"RM" - { - ND_INS_MAXSD, ND_CAT_SSE, ND_SET_SSE2, 436, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:628 Instruction:"MAXSS Vss,Wss" Encoding:"0xF3 0x0F 0x5F /r"/"RM" - { - ND_INS_MAXSS, ND_CAT_SSE, ND_SET_SSE, 437, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:629 Instruction:"MCOMMIT" Encoding:"0xF3 0x0F 0x01 /0xFA"/"" - { - ND_INS_MCOMMIT, ND_CAT_MISC, ND_SET_MCOMMIT, 438, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MCOMMIT, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:630 Instruction:"MFENCE" Encoding:"NP 0x0F 0xAE /6:reg"/"" - { - ND_INS_MFENCE, ND_CAT_MISC, ND_SET_SSE2, 439, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:631 Instruction:"MINPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5D /r"/"RM" - { - ND_INS_MINPD, ND_CAT_SSE, ND_SET_SSE2, 440, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:632 Instruction:"MINPS Vps,Wps" Encoding:"NP 0x0F 0x5D /r"/"RM" - { - ND_INS_MINPS, ND_CAT_SSE, ND_SET_SSE, 441, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:633 Instruction:"MINSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5D /r"/"RM" - { - ND_INS_MINSD, ND_CAT_SSE, ND_SET_SSE2, 442, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:634 Instruction:"MINSS Vss,Wss" Encoding:"0xF3 0x0F 0x5D /r"/"RM" - { - ND_INS_MINSS, ND_CAT_SSE, ND_SET_SSE, 443, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:635 Instruction:"MONITOR" Encoding:"NP 0x0F 0x01 /0xC8"/"" - { - ND_INS_MONITOR, ND_CAT_MISC, ND_SET_SSE3, 444, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:636 Instruction:"MONITORX" Encoding:"NP 0x0F 0x01 /0xFA"/"" - { - ND_INS_MONITORX, ND_CAT_SYSTEM, ND_SET_MWAITT, 445, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:637 Instruction:"MONTMUL" Encoding:"0xF3 0x0F 0xA6 /0xC0"/"" - { - ND_INS_MONTMUL, ND_CAT_PADLOCK, ND_SET_CYRIX, 446, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:638 Instruction:"MOV Ry,Cy" Encoding:"0x0F 0x20 /r"/"MR" - { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:639 Instruction:"MOV Ry,Dy" Encoding:"0x0F 0x21 /r"/"MR" - { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:640 Instruction:"MOV Cy,Ry" Encoding:"0x0F 0x22 /r"/"RM" - { - ND_INS_MOV_CR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_LOCK_SPECIAL|ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_C, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:641 Instruction:"MOV Dy,Ry" Encoding:"0x0F 0x23 /r"/"RM" - { - ND_INS_MOV_DR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_SERIAL|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_D, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:642 Instruction:"MOV Ry,Ty" Encoding:"0x0F 0x24 /r"/"MR" - { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:643 Instruction:"MOV Ty,Ry" Encoding:"0x0F 0x26 /r"/"RM" - { - ND_INS_MOV_TR, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MFR|ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_T, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:644 Instruction:"MOV Eb,Gb" Encoding:"0x88 /r"/"MR" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:645 Instruction:"MOV Ev,Gv" Encoding:"0x89 /r"/"MR" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:646 Instruction:"MOV Gb,Eb" Encoding:"0x8A /r"/"RM" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:647 Instruction:"MOV Gv,Ev" Encoding:"0x8B /r"/"RM" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:648 Instruction:"MOV Mw,Sw" Encoding:"0x8C /r:mem"/"MR" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:649 Instruction:"MOV Rv,Sw" Encoding:"0x8C /r:reg"/"MR" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:650 Instruction:"MOV Sw,Mw" Encoding:"0x8E /r:mem"/"RM" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:651 Instruction:"MOV Sw,Rv" Encoding:"0x8E /r:reg"/"RM" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:652 Instruction:"MOV AL,Ob" Encoding:"0xA0"/"D" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:653 Instruction:"MOV rAX,Ov" Encoding:"0xA1"/"D" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:654 Instruction:"MOV Ob,AL" Encoding:"0xA2"/"D" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_O, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:655 Instruction:"MOV Ov,rAX" Encoding:"0xA3"/"D" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_O, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:656 Instruction:"MOV Zb,Ib" Encoding:"0xB0 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:657 Instruction:"MOV Zb,Ib" Encoding:"0xB1 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:658 Instruction:"MOV Zb,Ib" Encoding:"0xB2 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:659 Instruction:"MOV Zb,Ib" Encoding:"0xB3 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:660 Instruction:"MOV Zb,Ib" Encoding:"0xB4 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:661 Instruction:"MOV Zb,Ib" Encoding:"0xB5 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:662 Instruction:"MOV Zb,Ib" Encoding:"0xB6 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:663 Instruction:"MOV Zb,Ib" Encoding:"0xB7 ib"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:664 Instruction:"MOV Zv,Iv" Encoding:"0xB8 iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:665 Instruction:"MOV Zv,Iv" Encoding:"0xB9 iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:666 Instruction:"MOV Zv,Iv" Encoding:"0xBA iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:667 Instruction:"MOV Zv,Iv" Encoding:"0xBB iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:668 Instruction:"MOV Zv,Iv" Encoding:"0xBC iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:669 Instruction:"MOV Zv,Iv" Encoding:"0xBD iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:670 Instruction:"MOV Zv,Iv" Encoding:"0xBE iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:671 Instruction:"MOV Zv,Iv" Encoding:"0xBF iv"/"OI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:672 Instruction:"MOV Eb,Ib" Encoding:"0xC6 /0 ib"/"MI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:673 Instruction:"MOV Ev,Iz" Encoding:"0xC7 /0 iz"/"MI" - { - ND_INS_MOV, ND_CAT_DATAXFER, ND_SET_I86, 447, - ND_PREF_XRELEASE|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - }, - }, - - // Pos:674 Instruction:"MOVAPD Vpd,Wpd" Encoding:"0x66 0x0F 0x28 /r"/"RM" - { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:675 Instruction:"MOVAPD Wpd,Vpd" Encoding:"0x66 0x0F 0x29 /r"/"MR" - { - ND_INS_MOVAPD, ND_CAT_DATAXFER, ND_SET_SSE2, 448, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:676 Instruction:"MOVAPS Vps,Wps" Encoding:"NP 0x0F 0x28 /r"/"RM" - { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:677 Instruction:"MOVAPS Wps,Vps" Encoding:"NP 0x0F 0x29 /r"/"MR" - { - ND_INS_MOVAPS, ND_CAT_DATAXFER, ND_SET_SSE, 449, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:678 Instruction:"MOVBE Gv,Mv" Encoding:"0x0F 0x38 0xF0 /r:mem"/"RM" - { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:679 Instruction:"MOVBE Gv,Mv" Encoding:"0x66 0x0F 0x38 0xF0 /r:mem"/"RM" - { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:680 Instruction:"MOVBE Mv,Gv" Encoding:"0x0F 0x38 0xF1 /r:mem"/"MR" - { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVBE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:681 Instruction:"MOVBE Mv,Gv" Encoding:"0x66 0x0F 0x38 0xF1 /r:mem"/"MR" - { - ND_INS_MOVBE, ND_CAT_DATAXFER, ND_SET_MOVBE, 450, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_MOVBE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:682 Instruction:"MOVD Pq,Ey" Encoding:"NP 0x0F 0x6E /r"/"RM" - { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:683 Instruction:"MOVD Vdq,Ey" Encoding:"0x66 0x0F 0x6E /r"/"RM" - { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:684 Instruction:"MOVD Ey,Pd" Encoding:"NP 0x0F 0x7E /r"/"MR" - { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_MMX, 451, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_P, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:685 Instruction:"MOVD Ey,Vdq" Encoding:"0x66 0x0F 0x7E /r"/"MR" - { - ND_INS_MOVD, ND_CAT_DATAXFER, ND_SET_SSE2, 451, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:686 Instruction:"MOVDDUP Vdq,Wq" Encoding:"0xF2 0x0F 0x12 /r"/"RM" - { - ND_INS_MOVDDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 452, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:687 Instruction:"MOVDIR64B rMoq,Moq" Encoding:"0x66 0x0F 0x38 0xF8 /r:mem"/"M" - { - ND_INS_MOVDIR64B, ND_CAT_MOVDIR64B, ND_SET_MOVDIR64B, 453, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIR64B, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rM, ND_OPS_oq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:688 Instruction:"MOVDIRI My,Gy" Encoding:"NP 0x0F 0x38 0xF9 /r:mem"/"MR" - { - ND_INS_MOVDIRI, ND_CAT_MOVDIRI, ND_SET_MOVDIRI, 454, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MOVDIRI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:689 Instruction:"MOVDQ2Q Pq,Uq" Encoding:"0xF2 0x0F 0xD6 /r:reg"/"RM" - { - ND_INS_MOVDQ2Q, ND_CAT_DATAXFER, ND_SET_SSE2, 455, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:690 Instruction:"MOVDQA Vx,Wx" Encoding:"0x66 0x0F 0x6F /r"/"RM" - { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:691 Instruction:"MOVDQA Wx,Vx" Encoding:"0x66 0x0F 0x7F /r"/"MR" - { - ND_INS_MOVDQA, ND_CAT_DATAXFER, ND_SET_SSE2, 456, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:692 Instruction:"MOVDQU Vx,Wx" Encoding:"0xF3 0x0F 0x6F /r"/"RM" - { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:693 Instruction:"MOVDQU Wx,Vx" Encoding:"0xF3 0x0F 0x7F /r"/"MR" - { - ND_INS_MOVDQU, ND_CAT_DATAXFER, ND_SET_SSE2, 457, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:694 Instruction:"MOVHLPS Vq,Wq" Encoding:"NP 0x0F 0x12 /r"/"RM" - { - ND_INS_MOVHLPS, ND_CAT_DATAXFER, ND_SET_SSE, 458, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:695 Instruction:"MOVHPD Vq,Mq" Encoding:"0x66 0x0F 0x16 /r:mem"/"RM" - { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:696 Instruction:"MOVHPD Mq,Vq" Encoding:"0x66 0x0F 0x17 /r:mem"/"MR" - { - ND_INS_MOVHPD, ND_CAT_DATAXFER, ND_SET_SSE2, 459, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:697 Instruction:"MOVHPS Vq,Mq" Encoding:"NP 0x0F 0x16 /r:mem"/"RM" - { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:698 Instruction:"MOVHPS Mq,Vq" Encoding:"NP 0x0F 0x17 /r:mem"/"MR" - { - ND_INS_MOVHPS, ND_CAT_DATAXFER, ND_SET_SSE, 460, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:699 Instruction:"MOVLHPS Vq,Uq" Encoding:"NP 0x0F 0x16 /r:reg"/"RM" - { - ND_INS_MOVLHPS, ND_CAT_DATAXFER, ND_SET_SSE, 461, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:700 Instruction:"MOVLPD Vsd,Mq" Encoding:"0x66 0x0F 0x12 /r:mem"/"RM" - { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:701 Instruction:"MOVLPD Mq,Vpd" Encoding:"0x66 0x0F 0x13 /r:mem"/"MR" - { - ND_INS_MOVLPD, ND_CAT_DATAXFER, ND_SET_SSE2, 462, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:702 Instruction:"MOVLPS Mq,Vps" Encoding:"NP 0x0F 0x13 /r:mem"/"MR" - { - ND_INS_MOVLPS, ND_CAT_DATAXFER, ND_SET_SSE, 463, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:703 Instruction:"MOVMSKPD Gy,Upd" Encoding:"0x66 0x0F 0x50 /r:reg"/"RM" - { - ND_INS_MOVMSKPD, ND_CAT_DATAXFER, ND_SET_SSE2, 464, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:704 Instruction:"MOVMSKPS Gy,Ups" Encoding:"NP 0x0F 0x50 /r:reg"/"RM" - { - ND_INS_MOVMSKPS, ND_CAT_DATAXFER, ND_SET_SSE, 465, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:705 Instruction:"MOVNTDQ Mx,Vx" Encoding:"0x66 0x0F 0xE7 /r:mem"/"MR" - { - ND_INS_MOVNTDQ, ND_CAT_DATAXFER, ND_SET_SSE2, 466, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:706 Instruction:"MOVNTDQA Vx,Mx" Encoding:"0x66 0x0F 0x38 0x2A /r:mem"/"RM" - { - ND_INS_MOVNTDQA, ND_CAT_SSE, ND_SET_SSE4, 467, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:707 Instruction:"MOVNTI My,Gy" Encoding:"NP 0x0F 0xC3 /r:mem"/"MR" - { - ND_INS_MOVNTI, ND_CAT_DATAXFER, ND_SET_SSE2, 468, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:708 Instruction:"MOVNTPD Mpd,Vpd" Encoding:"0x66 0x0F 0x2B /r:mem"/"MR" - { - ND_INS_MOVNTPD, ND_CAT_DATAXFER, ND_SET_SSE2, 469, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:709 Instruction:"MOVNTPS Mps,Vps" Encoding:"NP 0x0F 0x2B /r:mem"/"MR" - { - ND_INS_MOVNTPS, ND_CAT_DATAXFER, ND_SET_SSE, 470, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:710 Instruction:"MOVNTQ Mq,Pq" Encoding:"NP 0x0F 0xE7 /r:mem"/"MR" - { - ND_INS_MOVNTQ, ND_CAT_DATAXFER, ND_SET_MMX, 471, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:711 Instruction:"MOVNTSD Msd,Vsd" Encoding:"0xF2 0x0F 0x2B /r:mem"/"MR" - { - ND_INS_MOVNTSD, ND_CAT_DATAXFER, ND_SET_SSE4A, 472, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:712 Instruction:"MOVNTSS Mss,Vss" Encoding:"0xF3 0x0F 0x2B /r:mem"/"MR" - { - ND_INS_MOVNTSS, ND_CAT_DATAXFER, ND_SET_SSE4A, 473, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4A, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:713 Instruction:"MOVQ Pq,Ey" Encoding:"rexw NP 0x0F 0x6E /r"/"RM" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:714 Instruction:"MOVQ Vdq,Ey" Encoding:"0x66 rexw 0x0F 0x6E /r"/"RM" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:715 Instruction:"MOVQ Pq,Qq" Encoding:"NP 0x0F 0x6F /r"/"RM" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:716 Instruction:"MOVQ Ey,Pq" Encoding:"rexw NP 0x0F 0x7E /r"/"MR" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:717 Instruction:"MOVQ Ey,Vdq" Encoding:"0x66 rexw 0x0F 0x7E /r"/"MR" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:718 Instruction:"MOVQ Vdq,Wq" Encoding:"0xF3 0x0F 0x7E /r"/"RM" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:719 Instruction:"MOVQ Qq,Pq" Encoding:"NP 0x0F 0x7F /r"/"MR" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_MMX, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:720 Instruction:"MOVQ Wq,Vq" Encoding:"0x66 0x0F 0xD6 /r"/"MR" - { - ND_INS_MOVQ, ND_CAT_DATAXFER, ND_SET_SSE2, 474, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:721 Instruction:"MOVQ2DQ Vdq,Nq" Encoding:"0xF3 0x0F 0xD6 /r:reg"/"RM" - { - ND_INS_MOVQ2DQ, ND_CAT_DATAXFER, ND_SET_SSE2, 475, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:722 Instruction:"MOVSB Yb,Xb" Encoding:"0xA4"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:723 Instruction:"MOVSB Yb,Xb" Encoding:"rep 0xA4"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 476, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:724 Instruction:"MOVSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x10 /r"/"RM" - { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:725 Instruction:"MOVSD Wsd,Vsd" Encoding:"0xF2 0x0F 0x11 /r"/"MR" - { - ND_INS_MOVSD, ND_CAT_DATAXFER, ND_SET_SSE2, 477, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:726 Instruction:"MOVSD Yv,Xv" Encoding:"ds32 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:727 Instruction:"MOVSD Yv,Xv" Encoding:"rep ds32 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 477, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:728 Instruction:"MOVSHDUP Vx,Wx" Encoding:"0xF3 0x0F 0x16 /r"/"RM" - { - ND_INS_MOVSHDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 478, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:729 Instruction:"MOVSLDUP Vx,Wx" Encoding:"0xF3 0x0F 0x12 /r"/"RM" - { - ND_INS_MOVSLDUP, ND_CAT_DATAXFER, ND_SET_SSE3, 479, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:730 Instruction:"MOVSQ Yv,Xv" Encoding:"ds64 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:731 Instruction:"MOVSQ Yv,Xv" Encoding:"rep ds64 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 480, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:732 Instruction:"MOVSS Vss,Wss" Encoding:"0xF3 0x0F 0x10 /r"/"RM" - { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:733 Instruction:"MOVSS Wss,Vss" Encoding:"0xF3 0x0F 0x11 /r"/"MR" - { - ND_INS_MOVSS, ND_CAT_DATAXFER, ND_SET_SSE, 481, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:734 Instruction:"MOVSW Yv,Xv" Encoding:"ds16 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:735 Instruction:"MOVSW Yv,Xv" Encoding:"rep ds16 0xA5"/"" - { - ND_INS_MOVS, ND_CAT_STRINGOP, ND_SET_I86, 482, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_X, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:736 Instruction:"MOVSX Gv,Eb" Encoding:"0x0F 0xBE /r"/"RM" - { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:737 Instruction:"MOVSX Gv,Ew" Encoding:"0x0F 0xBF /r"/"RM" - { - ND_INS_MOVSX, ND_CAT_DATAXFER, ND_SET_I386, 483, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:738 Instruction:"MOVSXD Gv,Ez" Encoding:"o64 0x63 /r"/"RM" - { - ND_INS_MOVSXD, ND_CAT_DATAXFER, ND_SET_LONGMODE, 484, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_z, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:739 Instruction:"MOVUPD Vpd,Wpd" Encoding:"0x66 0x0F 0x10 /r"/"RM" - { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:740 Instruction:"MOVUPD Wpd,Vpd" Encoding:"0x66 0x0F 0x11 /r"/"MR" - { - ND_INS_MOVUPD, ND_CAT_DATAXFER, ND_SET_SSE2, 485, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:741 Instruction:"MOVUPS Vps,Wps" Encoding:"NP 0x0F 0x10 /r"/"RM" - { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:742 Instruction:"MOVUPS Wps,Vps" Encoding:"NP 0x0F 0x11 /r"/"MR" - { - ND_INS_MOVUPS, ND_CAT_DATAXFER, ND_SET_SSE, 486, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:743 Instruction:"MOVZX Gv,Eb" Encoding:"0x0F 0xB6 /r"/"RM" - { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:744 Instruction:"MOVZX Gv,Ew" Encoding:"0x0F 0xB7 /r"/"RM" - { - ND_INS_MOVZX, ND_CAT_DATAXFER, ND_SET_I386, 487, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:745 Instruction:"MPSADBW Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x42 /r ib"/"RMI" - { - ND_INS_MPSADBW, ND_CAT_SSE, ND_SET_SSE4, 488, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:746 Instruction:"MUL Eb" Encoding:"0xF6 /4"/"M" - { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:747 Instruction:"MUL Ev" Encoding:"0xF7 /4"/"M" - { - ND_INS_MUL, ND_CAT_ARITH, ND_SET_I86, 489, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:748 Instruction:"MULPD Vpd,Wpd" Encoding:"0x66 0x0F 0x59 /r"/"RM" - { - ND_INS_MULPD, ND_CAT_SSE, ND_SET_SSE2, 490, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:749 Instruction:"MULPS Vps,Wps" Encoding:"NP 0x0F 0x59 /r"/"RM" - { - ND_INS_MULPS, ND_CAT_SSE, ND_SET_SSE, 491, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:750 Instruction:"MULSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x59 /r"/"RM" - { - ND_INS_MULSD, ND_CAT_SSE, ND_SET_SSE2, 492, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:751 Instruction:"MULSS Vss,Wss" Encoding:"0xF3 0x0F 0x59 /r"/"RM" - { - ND_INS_MULSS, ND_CAT_SSE, ND_SET_SSE, 493, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:752 Instruction:"MULX Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF6 /r"/"RVM" - { - ND_INS_MULX, ND_CAT_BMI2, ND_SET_BMI2, 494, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 1), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:753 Instruction:"MWAIT" Encoding:"NP 0x0F 0x01 /0xC9"/"" - { - ND_INS_MWAIT, ND_CAT_MISC, ND_SET_SSE3, 495, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MONITOR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:754 Instruction:"MWAITX" Encoding:"NP 0x0F 0x01 /0xFB"/"" - { - ND_INS_MWAITX, ND_CAT_SYSTEM, ND_SET_MWAITT, 496, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:755 Instruction:"NEG Eb" Encoding:"0xF6 /3"/"M" - { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:756 Instruction:"NEG Ev" Encoding:"0xF7 /3"/"M" - { - ND_INS_NEG, ND_CAT_LOGIC, ND_SET_I86, 497, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:757 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /0:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:758 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /1:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:759 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /2:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:760 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /3:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:761 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /4:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:762 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /5:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:763 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /6:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:764 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x0D /7:reg"/"MR" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:765 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /0:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:766 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /1:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:767 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /2:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:768 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /3:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:769 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /4"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:770 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /5"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:771 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /6"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:772 Instruction:"NOP Ev" Encoding:"0x0F 0x18 /7"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:773 Instruction:"NOP Ev" Encoding:"0x0F 0x19 /r"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:774 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /0:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:775 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /1:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:776 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /2:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:777 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /3:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:778 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /4"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:779 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /5"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:780 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:mem"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:781 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /6:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:782 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:mem"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:783 Instruction:"NOP Ev" Encoding:"piti 0x0F 0x18 /7:reg"/"M" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:784 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1A /r"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:785 Instruction:"NOP Gv,Ev" Encoding:"0x0F 0x1B /r"/"RM" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:786 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1C /r"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:787 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1D /r"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:788 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1E /r"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:789 Instruction:"NOP Ev,Gv" Encoding:"0x0F 0x1F /r"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:790 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1A /r:reg"/"RM" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:791 Instruction:"NOP Gv,Ev" Encoding:"mpx 0x0F 0x1B /r:reg"/"RM" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:792 Instruction:"NOP Gv,Ev" Encoding:"mpx 0xF3 0x0F 0x1B /r:reg"/"RM" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:793 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x66 0x0F 0x1C /0:mem"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:794 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF3 0x0F 0x1C /0:mem"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:795 Instruction:"NOP Ev,Gv" Encoding:"cldm 0xF2 0x0F 0x1C /0:mem"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:796 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /0:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:797 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /1"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:798 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /2"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:799 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /3"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:800 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /4"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:801 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /5"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:802 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /6"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:803 Instruction:"NOP Ev,Gv" Encoding:"cldm 0x0F 0x1C /7"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:804 Instruction:"NOP Mv,Gv" Encoding:"cet 0x0F 0x1E /r:mem"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:805 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:806 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /1:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:807 Instruction:"NOP Rv,Gv" Encoding:"cet rexw 0x0F 0x1E /1:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:808 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /2:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:809 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /3:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:810 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /4:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:811 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /5:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:812 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /6:reg"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:813 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF8"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:814 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xF9"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:815 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFA"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:816 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFB"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:817 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFC"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:818 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFD"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:819 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFE"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:820 Instruction:"NOP Rv,Gv" Encoding:"cet 0x0F 0x1E /0xFF"/"MR" - { - ND_INS_NOP, ND_CAT_WIDENOP, ND_SET_PPRO, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_N, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:821 Instruction:"NOP" Encoding:"0x90"/"" - { - ND_INS_NOP, ND_CAT_NOP, ND_SET_I86, 498, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:822 Instruction:"NOT Eb" Encoding:"0xF6 /2"/"M" - { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:823 Instruction:"NOT Ev" Encoding:"0xF7 /2"/"M" - { - ND_INS_NOT, ND_CAT_LOGIC, ND_SET_I86, 499, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:824 Instruction:"OR Eb,Gb" Encoding:"0x08 /r"/"MR" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:825 Instruction:"OR Ev,Gv" Encoding:"0x09 /r"/"MR" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:826 Instruction:"OR Gb,Eb" Encoding:"0x0A /r"/"RM" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:827 Instruction:"OR Gv,Ev" Encoding:"0x0B /r"/"RM" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:828 Instruction:"OR AL,Ib" Encoding:"0x0C ib"/"I" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:829 Instruction:"OR rAX,Iz" Encoding:"0x0D iz"/"I" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:830 Instruction:"OR Eb,Ib" Encoding:"0x80 /1 ib"/"MI" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:831 Instruction:"OR Ev,Iz" Encoding:"0x81 /1 iz"/"MI" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:832 Instruction:"OR Eb,Ib" Encoding:"0x82 /1 iz"/"MI" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:833 Instruction:"OR Ev,Ib" Encoding:"0x83 /1 ib"/"MI" - { - ND_INS_OR, ND_CAT_LOGIC, ND_SET_I86, 500, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:834 Instruction:"ORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x56 /r"/"RM" - { - ND_INS_ORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 501, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:835 Instruction:"ORPS Vps,Wps" Encoding:"NP 0x0F 0x56 /r"/"RM" - { - ND_INS_ORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 502, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:836 Instruction:"OUT Ib,AL" Encoding:"0xE6 ib"/"I" - { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:837 Instruction:"OUT Ib,eAX" Encoding:"0xE7 ib"/"I" - { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:838 Instruction:"OUT DX,AL" Encoding:"0xEE"/"" - { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:839 Instruction:"OUT DX,eAX" Encoding:"0xEF"/"" - { - ND_INS_OUT, ND_CAT_IO, ND_SET_I86, 503, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:840 Instruction:"OUTSB DX,Xb" Encoding:"0x6E"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:841 Instruction:"OUTSB DX,Xb" Encoding:"rep 0x6E"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 504, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:842 Instruction:"OUTSD DX,Xz" Encoding:"0x6F"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:843 Instruction:"OUTSD DX,Xz" Encoding:"rep 0x6F"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 505, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:844 Instruction:"OUTSW DX,Xz" Encoding:"ds16 0x6F"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:845 Instruction:"OUTSW DX,Xz" Encoding:"rep ds16 0x6F"/"" - { - ND_INS_OUTS, ND_CAT_IOSTRINGOP, ND_SET_I86, 506, - ND_PREF_REP, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0|NDR_RFLAG_DF|NDR_RFLAG_IOPL|NDR_RFLAG_VM, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_X, ND_OPS_z, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rSI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:846 Instruction:"PABSB Pq,Qq" Encoding:"NP 0x0F 0x38 0x1C /r"/"RM" - { - ND_INS_PABSB, ND_CAT_MMX, ND_SET_SSSE3, 507, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:847 Instruction:"PABSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1C /r"/"RM" - { - ND_INS_PABSB, ND_CAT_SSE, ND_SET_SSSE3, 507, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:848 Instruction:"PABSD Pq,Qq" Encoding:"NP 0x0F 0x38 0x1E /r"/"RM" - { - ND_INS_PABSD, ND_CAT_MMX, ND_SET_SSSE3, 508, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:849 Instruction:"PABSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1E /r"/"RM" - { - ND_INS_PABSD, ND_CAT_SSE, ND_SET_SSSE3, 508, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:850 Instruction:"PABSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x1D /r"/"RM" - { - ND_INS_PABSW, ND_CAT_MMX, ND_SET_SSSE3, 509, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:851 Instruction:"PABSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x1D /r"/"RM" - { - ND_INS_PABSW, ND_CAT_SSE, ND_SET_SSSE3, 509, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:852 Instruction:"PACKSSDW Pq,Qq" Encoding:"NP 0x0F 0x6B /r"/"RM" - { - ND_INS_PACKSSDW, ND_CAT_MMX, ND_SET_MMX, 510, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:853 Instruction:"PACKSSDW Vx,Wx" Encoding:"0x66 0x0F 0x6B /r"/"RM" - { - ND_INS_PACKSSDW, ND_CAT_SSE, ND_SET_SSE2, 510, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:854 Instruction:"PACKSSWB Pq,Qq" Encoding:"NP 0x0F 0x63 /r"/"RM" - { - ND_INS_PACKSSWB, ND_CAT_MMX, ND_SET_MMX, 511, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:855 Instruction:"PACKSSWB Vx,Wx" Encoding:"0x66 0x0F 0x63 /r"/"RM" - { - ND_INS_PACKSSWB, ND_CAT_SSE, ND_SET_SSE2, 511, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:856 Instruction:"PACKUSDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x2B /r"/"RM" - { - ND_INS_PACKUSDW, ND_CAT_SSE, ND_SET_SSE4, 512, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:857 Instruction:"PACKUSWB Pq,Qq" Encoding:"NP 0x0F 0x67 /r"/"RM" - { - ND_INS_PACKUSWB, ND_CAT_MMX, ND_SET_MMX, 513, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:858 Instruction:"PACKUSWB Vx,Wx" Encoding:"0x66 0x0F 0x67 /r"/"RM" - { - ND_INS_PACKUSWB, ND_CAT_SSE, ND_SET_SSE2, 513, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:859 Instruction:"PADDB Pq,Qq" Encoding:"NP 0x0F 0xFC /r"/"RM" - { - ND_INS_PADDB, ND_CAT_MMX, ND_SET_MMX, 514, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:860 Instruction:"PADDB Vx,Wx" Encoding:"0x66 0x0F 0xFC /r"/"RM" - { - ND_INS_PADDB, ND_CAT_SSE, ND_SET_SSE2, 514, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:861 Instruction:"PADDD Pq,Qq" Encoding:"NP 0x0F 0xFE /r"/"RM" - { - ND_INS_PADDD, ND_CAT_MMX, ND_SET_MMX, 515, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:862 Instruction:"PADDD Vx,Wx" Encoding:"0x66 0x0F 0xFE /r"/"RM" - { - ND_INS_PADDD, ND_CAT_SSE, ND_SET_SSE2, 515, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:863 Instruction:"PADDQ Pq,Qq" Encoding:"NP 0x0F 0xD4 /r"/"RM" - { - ND_INS_PADDQ, ND_CAT_MMX, ND_SET_SSE2, 516, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:864 Instruction:"PADDQ Vx,Wx" Encoding:"0x66 0x0F 0xD4 /r"/"RM" - { - ND_INS_PADDQ, ND_CAT_SSE, ND_SET_SSE2, 516, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:865 Instruction:"PADDSB Pq,Qq" Encoding:"NP 0x0F 0xEC /r"/"RM" - { - ND_INS_PADDSB, ND_CAT_MMX, ND_SET_MMX, 517, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:866 Instruction:"PADDSB Vx,Wx" Encoding:"0x66 0x0F 0xEC /r"/"RM" - { - ND_INS_PADDSB, ND_CAT_SSE, ND_SET_SSE2, 517, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:867 Instruction:"PADDSW Pq,Qq" Encoding:"NP 0x0F 0xED /r"/"RM" - { - ND_INS_PADDSW, ND_CAT_MMX, ND_SET_MMX, 518, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:868 Instruction:"PADDSW Vx,Wx" Encoding:"0x66 0x0F 0xED /r"/"RM" - { - ND_INS_PADDSW, ND_CAT_SSE, ND_SET_SSE2, 518, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:869 Instruction:"PADDUSB Pq,Qq" Encoding:"NP 0x0F 0xDC /r"/"RM" - { - ND_INS_PADDUSB, ND_CAT_MMX, ND_SET_MMX, 519, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:870 Instruction:"PADDUSB Vx,Wx" Encoding:"0x66 0x0F 0xDC /r"/"RM" - { - ND_INS_PADDUSB, ND_CAT_SSE, ND_SET_SSE2, 519, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:871 Instruction:"PADDUSW Pq,Qq" Encoding:"NP 0x0F 0xDD /r"/"RM" - { - ND_INS_PADDUSW, ND_CAT_MMX, ND_SET_MMX, 520, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:872 Instruction:"PADDUSW Vx,Wx" Encoding:"0x66 0x0F 0xDD /r"/"RM" - { - ND_INS_PADDUSW, ND_CAT_SSE, ND_SET_SSE2, 520, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:873 Instruction:"PADDW Pq,Qq" Encoding:"NP 0x0F 0xFD /r"/"RM" - { - ND_INS_PADDW, ND_CAT_MMX, ND_SET_MMX, 521, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:874 Instruction:"PADDW Vx,Wx" Encoding:"0x66 0x0F 0xFD /r"/"RM" - { - ND_INS_PADDW, ND_CAT_SSE, ND_SET_SSE2, 521, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:875 Instruction:"PALIGNR Pq,Qq,Ib" Encoding:"NP 0x0F 0x3A 0x0F /r ib"/"RMI" - { - ND_INS_PALIGNR, ND_CAT_MMX, ND_SET_SSSE3, 522, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:876 Instruction:"PALIGNR Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0F /r ib"/"RMI" - { - ND_INS_PALIGNR, ND_CAT_SSE, ND_SET_SSSE3, 522, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:877 Instruction:"PAND Pq,Qq" Encoding:"NP 0x0F 0xDB /r"/"RM" - { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_MMX, 523, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:878 Instruction:"PAND Vx,Wx" Encoding:"0x66 0x0F 0xDB /r"/"RM" - { - ND_INS_PAND, ND_CAT_LOGICAL, ND_SET_SSE2, 523, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:879 Instruction:"PANDN Pq,Qq" Encoding:"NP 0x0F 0xDF /r"/"RM" - { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_MMX, 524, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:880 Instruction:"PANDN Vx,Wx" Encoding:"0x66 0x0F 0xDF /r"/"RM" - { - ND_INS_PANDN, ND_CAT_LOGICAL, ND_SET_SSE2, 524, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:881 Instruction:"PAUSE" Encoding:"a0xF3 0x90"/"" - { - ND_INS_PAUSE, ND_CAT_MISC, ND_SET_PAUSE, 525, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:882 Instruction:"PAVGB Pq,Qq" Encoding:"NP 0x0F 0xE0 /r"/"RM" - { - ND_INS_PAVGB, ND_CAT_MMX, ND_SET_MMX, 526, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:883 Instruction:"PAVGB Vx,Wx" Encoding:"0x66 0x0F 0xE0 /r"/"RM" - { - ND_INS_PAVGB, ND_CAT_SSE, ND_SET_SSE2, 526, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:884 Instruction:"PAVGUSB Pq,Qq" Encoding:"0x0F 0x0F /r 0xBF"/"RM" - { - ND_INS_PAVGUSB, ND_CAT_3DNOW, ND_SET_3DNOW, 527, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:885 Instruction:"PAVGW Pq,Qq" Encoding:"NP 0x0F 0xE3 /r"/"RM" - { - ND_INS_PAVGW, ND_CAT_MMX, ND_SET_MMX, 528, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:886 Instruction:"PAVGW Vx,Wx" Encoding:"0x66 0x0F 0xE3 /r"/"RM" - { - ND_INS_PAVGW, ND_CAT_SSE, ND_SET_SSE2, 528, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:887 Instruction:"PBLENDVB Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x10 /r"/"RM" - { - ND_INS_PBLENDVB, ND_CAT_SSE, ND_SET_SSE4, 529, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:888 Instruction:"PBLENDW Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x0E /r ib"/"RMI" - { - ND_INS_PBLENDW, ND_CAT_SSE, ND_SET_SSE4, 530, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:889 Instruction:"PBNDKB" Encoding:"NP 0x0F 0x01 /0xC7"/"" - { - ND_INS_PBNDKB, ND_CAT_SYSTEM, ND_SET_TSE, 531, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_TSE, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:890 Instruction:"PCLMULQDQ Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x44 /r ib"/"RMI" - { - ND_INS_PCLMULQDQ, ND_CAT_PCLMULQDQ, ND_SET_PCLMULQDQ, 532, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_PCLMULQDQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:891 Instruction:"PCMPEQB Pq,Qq" Encoding:"NP 0x0F 0x74 /r"/"RM" - { - ND_INS_PCMPEQB, ND_CAT_MMX, ND_SET_MMX, 533, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:892 Instruction:"PCMPEQB Vx,Wx" Encoding:"0x66 0x0F 0x74 /r"/"RM" - { - ND_INS_PCMPEQB, ND_CAT_SSE, ND_SET_SSE2, 533, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:893 Instruction:"PCMPEQD Pq,Qq" Encoding:"NP 0x0F 0x76 /r"/"RM" - { - ND_INS_PCMPEQD, ND_CAT_MMX, ND_SET_MMX, 534, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:894 Instruction:"PCMPEQD Vx,Wx" Encoding:"0x66 0x0F 0x76 /r"/"RM" - { - ND_INS_PCMPEQD, ND_CAT_SSE, ND_SET_SSE2, 534, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:895 Instruction:"PCMPEQQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x29 /r"/"RM" - { - ND_INS_PCMPEQQ, ND_CAT_SSE, ND_SET_SSE4, 535, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:896 Instruction:"PCMPEQW Pq,Qq" Encoding:"NP 0x0F 0x75 /r"/"RM" - { - ND_INS_PCMPEQW, ND_CAT_MMX, ND_SET_MMX, 536, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:897 Instruction:"PCMPEQW Vx,Wx" Encoding:"0x66 0x0F 0x75 /r"/"RM" - { - ND_INS_PCMPEQW, ND_CAT_SSE, ND_SET_SSE2, 536, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:898 Instruction:"PCMPESTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x61 /r ib"/"RMI" - { - ND_INS_PCMPESTRI, ND_CAT_SSE, ND_SET_SSE42, 537, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:899 Instruction:"PCMPESTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x60 /r ib"/"RMI" - { - ND_INS_PCMPESTRM, ND_CAT_SSE, ND_SET_SSE42, 538, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:900 Instruction:"PCMPGTB Pq,Qq" Encoding:"NP 0x0F 0x64 /r"/"RM" - { - ND_INS_PCMPGTB, ND_CAT_MMX, ND_SET_MMX, 539, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:901 Instruction:"PCMPGTB Vx,Wx" Encoding:"0x66 0x0F 0x64 /r"/"RM" - { - ND_INS_PCMPGTB, ND_CAT_SSE, ND_SET_SSE2, 539, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:902 Instruction:"PCMPGTD Pq,Qq" Encoding:"NP 0x0F 0x66 /r"/"RM" - { - ND_INS_PCMPGTD, ND_CAT_MMX, ND_SET_MMX, 540, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:903 Instruction:"PCMPGTD Vx,Wx" Encoding:"0x66 0x0F 0x66 /r"/"RM" - { - ND_INS_PCMPGTD, ND_CAT_SSE, ND_SET_SSE2, 540, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:904 Instruction:"PCMPGTQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x37 /r"/"RM" - { - ND_INS_PCMPGTQ, ND_CAT_SSE, ND_SET_SSE42, 541, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:905 Instruction:"PCMPGTW Pq,Qq" Encoding:"NP 0x0F 0x65 /r"/"RM" - { - ND_INS_PCMPGTW, ND_CAT_MMX, ND_SET_MMX, 542, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:906 Instruction:"PCMPGTW Vx,Wx" Encoding:"0x66 0x0F 0x65 /r"/"RM" - { - ND_INS_PCMPGTW, ND_CAT_SSE, ND_SET_SSE2, 542, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:907 Instruction:"PCMPISTRI Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x63 /r ib"/"RMI" - { - ND_INS_PCMPISTRI, ND_CAT_SSE, ND_SET_SSE42, 543, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:908 Instruction:"PCMPISTRM Vdq,Wdq,Ib" Encoding:"0x66 0x0F 0x3A 0x62 /r ib"/"RMI" - { - ND_INS_PCMPISTRM, ND_CAT_SSE, ND_SET_SSE42, 544, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE42, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:909 Instruction:"PCONFIG" Encoding:"NP 0x0F 0x01 /0xC5"/"" - { - ND_INS_PCONFIG, ND_CAT_PCONFIG, ND_SET_PCONFIG, 545, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PCONFIG, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rBX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:910 Instruction:"PDEP Gy,By,Ey" Encoding:"vex m:2 p:3 l:0 w:x 0xF5 /r"/"RVM" - { - ND_INS_PDEP, ND_CAT_BMI2, ND_SET_BMI2, 546, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:911 Instruction:"PEXT Gy,By,Ey" Encoding:"vex m:2 p:2 l:0 w:x 0xF5 /r"/"RVM" - { - ND_INS_PEXT, ND_CAT_BMI2, ND_SET_BMI2, 547, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:912 Instruction:"PEXTRB Mb,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:mem ib"/"MRI" - { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:913 Instruction:"PEXTRB Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x14 /r:reg ib"/"MRI" - { - ND_INS_PEXTRB, ND_CAT_SSE, ND_SET_SSE4, 548, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:914 Instruction:"PEXTRD Md,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" - { - ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:915 Instruction:"PEXTRD Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" - { - ND_INS_PEXTRD, ND_CAT_SSE, ND_SET_SSE4, 549, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:916 Instruction:"PEXTRQ Mq,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:mem ib"/"MRI" - { - ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:917 Instruction:"PEXTRQ Ry,Vdq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x16 /r:reg ib"/"MRI" - { - ND_INS_PEXTRQ, ND_CAT_SSE, ND_SET_SSE4, 550, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:918 Instruction:"PEXTRW Gy,Nq,Ib" Encoding:"NP 0x0F 0xC5 /r:reg ib"/"RMI" - { - ND_INS_PEXTRW, ND_CAT_MMX, ND_SET_MMX, 551, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:919 Instruction:"PEXTRW Gy,Udq,Ib" Encoding:"0x66 0x0F 0xC5 /r:reg ib"/"RMI" - { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE2, 551, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:920 Instruction:"PEXTRW Mw,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:mem ib"/"MRI" - { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:921 Instruction:"PEXTRW Ry,Vdq,Ib" Encoding:"0x66 0x0F 0x3A 0x15 /r:reg ib"/"MRI" - { - ND_INS_PEXTRW, ND_CAT_SSE, ND_SET_SSE4, 551, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:922 Instruction:"PF2ID Pq,Qq" Encoding:"0x0F 0x0F /r 0x1D"/"RM" - { - ND_INS_PF2ID, ND_CAT_3DNOW, ND_SET_3DNOW, 552, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:923 Instruction:"PF2IW Pq,Qq" Encoding:"0x0F 0x0F /r 0x1C"/"RM" - { - ND_INS_PF2IW, ND_CAT_3DNOW, ND_SET_3DNOW, 553, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:924 Instruction:"PFACC Pq,Qq" Encoding:"0x0F 0x0F /r 0xAE"/"RM" - { - ND_INS_PFACC, ND_CAT_3DNOW, ND_SET_3DNOW, 554, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:925 Instruction:"PFADD Pq,Qq" Encoding:"0x0F 0x0F /r 0x9E"/"RM" - { - ND_INS_PFADD, ND_CAT_3DNOW, ND_SET_3DNOW, 555, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:926 Instruction:"PFCMPEQ Pq,Qq" Encoding:"0x0F 0x0F /r 0xB0"/"RM" - { - ND_INS_PFCMPEQ, ND_CAT_3DNOW, ND_SET_3DNOW, 556, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:927 Instruction:"PFCMPGE Pq,Qq" Encoding:"0x0F 0x0F /r 0x90"/"RM" - { - ND_INS_PFCMPGE, ND_CAT_3DNOW, ND_SET_3DNOW, 557, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:928 Instruction:"PFCMPGT Pq,Qq" Encoding:"0x0F 0x0F /r 0xA0"/"RM" - { - ND_INS_PFCMPGT, ND_CAT_3DNOW, ND_SET_3DNOW, 558, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:929 Instruction:"PFMAX Pq,Qq" Encoding:"0x0F 0x0F /r 0xA4"/"RM" - { - ND_INS_PFMAX, ND_CAT_3DNOW, ND_SET_3DNOW, 559, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:930 Instruction:"PFMIN Pq,Qq" Encoding:"0x0F 0x0F /r 0x94"/"RM" - { - ND_INS_PFMIN, ND_CAT_3DNOW, ND_SET_3DNOW, 560, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:931 Instruction:"PFMUL Pq,Qq" Encoding:"0x0F 0x0F /r 0xB4"/"RM" - { - ND_INS_PFMUL, ND_CAT_3DNOW, ND_SET_3DNOW, 561, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:932 Instruction:"PFNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8A"/"RM" - { - ND_INS_PFNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 562, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:933 Instruction:"PFPNACC Pq,Qq" Encoding:"0x0F 0x0F /r 0x8E"/"RM" - { - ND_INS_PFPNACC, ND_CAT_3DNOW, ND_SET_3DNOW, 563, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:934 Instruction:"PFRCP Pq,Qq" Encoding:"0x0F 0x0F /r 0x96"/"RM" - { - ND_INS_PFRCP, ND_CAT_3DNOW, ND_SET_3DNOW, 564, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:935 Instruction:"PFRCPIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA6"/"RM" - { - ND_INS_PFRCPIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 565, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:936 Instruction:"PFRCPIT2 Pq,Qq" Encoding:"0x0F 0x0F /r 0xB6"/"RM" - { - ND_INS_PFRCPIT2, ND_CAT_3DNOW, ND_SET_3DNOW, 566, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:937 Instruction:"PFRCPV Pq,Qq" Encoding:"0x0F 0x0F /r 0x86"/"RM" - { - ND_INS_PFRCPV, ND_CAT_3DNOW, ND_SET_3DNOW, 567, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:938 Instruction:"PFRSQIT1 Pq,Qq" Encoding:"0x0F 0x0F /r 0xA7"/"RM" - { - ND_INS_PFRSQIT1, ND_CAT_3DNOW, ND_SET_3DNOW, 568, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:939 Instruction:"PFRSQRT Pq,Qq" Encoding:"0x0F 0x0F /r 0x97"/"RM" - { - ND_INS_PFRSQRT, ND_CAT_3DNOW, ND_SET_3DNOW, 569, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:940 Instruction:"PFRSQRTV Pq,Qq" Encoding:"0x0F 0x0F /r 0x87"/"RM" - { - ND_INS_PFRSQRTV, ND_CAT_3DNOW, ND_SET_3DNOW, 570, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM|ND_FLAG_I64, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:941 Instruction:"PFSUB Pq,Qq" Encoding:"0x0F 0x0F /r 0x9A"/"RM" - { - ND_INS_PFSUB, ND_CAT_3DNOW, ND_SET_3DNOW, 571, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:942 Instruction:"PFSUBR Pq,Qq" Encoding:"0x0F 0x0F /r 0xAA"/"RM" - { - ND_INS_PFSUBR, ND_CAT_3DNOW, ND_SET_3DNOW, 572, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:943 Instruction:"PHADDD Pq,Qq" Encoding:"NP 0x0F 0x38 0x02 /r"/"RM" - { - ND_INS_PHADDD, ND_CAT_MMX, ND_SET_SSSE3, 573, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:944 Instruction:"PHADDD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x02 /r"/"RM" - { - ND_INS_PHADDD, ND_CAT_SSE, ND_SET_SSSE3, 573, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:945 Instruction:"PHADDSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x03 /r"/"RM" - { - ND_INS_PHADDSW, ND_CAT_MMX, ND_SET_SSSE3, 574, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:946 Instruction:"PHADDSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x03 /r"/"RM" - { - ND_INS_PHADDSW, ND_CAT_SSE, ND_SET_SSSE3, 574, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:947 Instruction:"PHADDW Pq,Qq" Encoding:"NP 0x0F 0x38 0x01 /r"/"RM" - { - ND_INS_PHADDW, ND_CAT_MMX, ND_SET_SSSE3, 575, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:948 Instruction:"PHADDW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x01 /r"/"RM" - { - ND_INS_PHADDW, ND_CAT_SSE, ND_SET_SSSE3, 575, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:949 Instruction:"PHMINPOSUW Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x41 /r"/"RM" - { - ND_INS_PHMINPOSUW, ND_CAT_SSE, ND_SET_SSE4, 576, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:950 Instruction:"PHSUBD Pq,Qq" Encoding:"NP 0x0F 0x38 0x06 /r"/"RM" - { - ND_INS_PHSUBD, ND_CAT_MMX, ND_SET_SSSE3, 577, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:951 Instruction:"PHSUBD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x06 /r"/"RM" - { - ND_INS_PHSUBD, ND_CAT_SSE, ND_SET_SSSE3, 577, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:952 Instruction:"PHSUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x07 /r"/"RM" - { - ND_INS_PHSUBSW, ND_CAT_MMX, ND_SET_SSSE3, 578, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:953 Instruction:"PHSUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x07 /r"/"RM" - { - ND_INS_PHSUBSW, ND_CAT_SSE, ND_SET_SSSE3, 578, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:954 Instruction:"PHSUBW Pq,Qq" Encoding:"NP 0x0F 0x38 0x05 /r"/"RM" - { - ND_INS_PHSUBW, ND_CAT_MMX, ND_SET_SSSE3, 579, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:955 Instruction:"PHSUBW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x05 /r"/"RM" - { - ND_INS_PHSUBW, ND_CAT_SSE, ND_SET_SSSE3, 579, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:956 Instruction:"PI2FD Pq,Qq" Encoding:"0x0F 0x0F /r 0x0D"/"RM" - { - ND_INS_PI2FD, ND_CAT_3DNOW, ND_SET_3DNOW, 580, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:957 Instruction:"PI2FW Pq,Qq" Encoding:"0x0F 0x0F /r 0x0C"/"RM" - { - ND_INS_PI2FW, ND_CAT_3DNOW, ND_SET_3DNOW, 581, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:958 Instruction:"PINSRB Vdq,Mb,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:mem ib"/"RMI" - { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:959 Instruction:"PINSRB Vdq,Ry,Ib" Encoding:"0x66 0x0F 0x3A 0x20 /r:reg ib"/"RMI" - { - ND_INS_PINSRB, ND_CAT_SSE, ND_SET_SSE4, 582, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:960 Instruction:"PINSRD Vdq,Ed,Ib" Encoding:"0x66 0x0F 0x3A 0x22 /r ib"/"RMI" - { - ND_INS_PINSRD, ND_CAT_SSE, ND_SET_SSE4, 583, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:961 Instruction:"PINSRQ Vdq,Eq,Ib" Encoding:"rexw 0x66 0x0F 0x3A 0x22 /r ib"/"RMI" - { - ND_INS_PINSRQ, ND_CAT_SSE, ND_SET_SSE4, 584, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:962 Instruction:"PINSRW Pq,Rd,Ib" Encoding:"NP 0x0F 0xC4 /r:reg ib"/"RMI" - { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:963 Instruction:"PINSRW Pq,Mw,Ib" Encoding:"NP 0x0F 0xC4 /r:mem ib"/"RMI" - { - ND_INS_PINSRW, ND_CAT_MMX, ND_SET_MMX, 585, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:964 Instruction:"PINSRW Vdq,Rd,Ib" Encoding:"0x66 0x0F 0xC4 /r:reg ib"/"RMI" - { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:965 Instruction:"PINSRW Vdq,Mw,Ib" Encoding:"0x66 0x0F 0xC4 /r:mem ib"/"RMI" - { - ND_INS_PINSRW, ND_CAT_SSE, ND_SET_SSE2, 585, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:966 Instruction:"PMADDUBSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x04 /r"/"RM" - { - ND_INS_PMADDUBSW, ND_CAT_MMX, ND_SET_SSSE3, 586, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:967 Instruction:"PMADDUBSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x04 /r"/"RM" - { - ND_INS_PMADDUBSW, ND_CAT_SSE, ND_SET_SSSE3, 586, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:968 Instruction:"PMADDWD Pq,Qq" Encoding:"NP 0x0F 0xF5 /r"/"RM" - { - ND_INS_PMADDWD, ND_CAT_MMX, ND_SET_MMX, 587, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:969 Instruction:"PMADDWD Vx,Wx" Encoding:"0x66 0x0F 0xF5 /r"/"RM" - { - ND_INS_PMADDWD, ND_CAT_SSE, ND_SET_SSE2, 587, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:970 Instruction:"PMAXSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3C /r"/"RM" - { - ND_INS_PMAXSB, ND_CAT_SSE, ND_SET_SSE4, 588, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:971 Instruction:"PMAXSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3D /r"/"RM" - { - ND_INS_PMAXSD, ND_CAT_SSE, ND_SET_SSE4, 589, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:972 Instruction:"PMAXSW Pq,Qq" Encoding:"NP 0x0F 0xEE /r"/"RM" - { - ND_INS_PMAXSW, ND_CAT_MMX, ND_SET_MMX, 590, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:973 Instruction:"PMAXSW Vx,Wx" Encoding:"0x66 0x0F 0xEE /r"/"RM" - { - ND_INS_PMAXSW, ND_CAT_SSE, ND_SET_SSE2, 590, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:974 Instruction:"PMAXUB Pq,Qq" Encoding:"NP 0x0F 0xDE /r"/"RM" - { - ND_INS_PMAXUB, ND_CAT_MMX, ND_SET_MMX, 591, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:975 Instruction:"PMAXUB Vx,Wx" Encoding:"0x66 0x0F 0xDE /r"/"RM" - { - ND_INS_PMAXUB, ND_CAT_SSE, ND_SET_SSE2, 591, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:976 Instruction:"PMAXUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3F /r"/"RM" - { - ND_INS_PMAXUD, ND_CAT_SSE, ND_SET_SSE4, 592, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:977 Instruction:"PMAXUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3E /r"/"RM" - { - ND_INS_PMAXUW, ND_CAT_SSE, ND_SET_SSE4, 593, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:978 Instruction:"PMINSB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x38 /r"/"RM" - { - ND_INS_PMINSB, ND_CAT_SSE, ND_SET_SSE4, 594, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:979 Instruction:"PMINSD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x39 /r"/"RM" - { - ND_INS_PMINSD, ND_CAT_SSE, ND_SET_SSE4, 595, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:980 Instruction:"PMINSW Pq,Qq" Encoding:"NP 0x0F 0xEA /r"/"RM" - { - ND_INS_PMINSW, ND_CAT_MMX, ND_SET_MMX, 596, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:981 Instruction:"PMINSW Vx,Wx" Encoding:"0x66 0x0F 0xEA /r"/"RM" - { - ND_INS_PMINSW, ND_CAT_SSE, ND_SET_SSE2, 596, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:982 Instruction:"PMINUB Pq,Qq" Encoding:"NP 0x0F 0xDA /r"/"RM" - { - ND_INS_PMINUB, ND_CAT_MMX, ND_SET_MMX, 597, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:983 Instruction:"PMINUB Vx,Wx" Encoding:"0x66 0x0F 0xDA /r"/"RM" - { - ND_INS_PMINUB, ND_CAT_SSE, ND_SET_SSE2, 597, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:984 Instruction:"PMINUD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3B /r"/"RM" - { - ND_INS_PMINUD, ND_CAT_SSE, ND_SET_SSE4, 598, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:985 Instruction:"PMINUW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x3A /r"/"RM" - { - ND_INS_PMINUW, ND_CAT_SSE, ND_SET_SSE4, 599, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:986 Instruction:"PMOVMSKB Gy,Nq" Encoding:"NP 0x0F 0xD7 /r:reg"/"RM" - { - ND_INS_PMOVMSKB, ND_CAT_MMX, ND_SET_SSE, 600, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:987 Instruction:"PMOVMSKB Gy,Ux" Encoding:"0x66 0x0F 0xD7 /r:reg"/"RM" - { - ND_INS_PMOVMSKB, ND_CAT_SSE, ND_SET_SSE2, 600, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:988 Instruction:"PMOVSXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x21 /r"/"RM" - { - ND_INS_PMOVSXBD, ND_CAT_SSE, ND_SET_SSE4, 601, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:989 Instruction:"PMOVSXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x22 /r"/"RM" - { - ND_INS_PMOVSXBQ, ND_CAT_SSE, ND_SET_SSE4, 602, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:990 Instruction:"PMOVSXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x20 /r"/"RM" - { - ND_INS_PMOVSXBW, ND_CAT_SSE, ND_SET_SSE4, 603, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:991 Instruction:"PMOVSXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x25 /r"/"RM" - { - ND_INS_PMOVSXDQ, ND_CAT_SSE, ND_SET_SSE4, 604, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:992 Instruction:"PMOVSXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x23 /r"/"RM" - { - ND_INS_PMOVSXWD, ND_CAT_SSE, ND_SET_SSE4, 605, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:993 Instruction:"PMOVSXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x24 /r"/"RM" - { - ND_INS_PMOVSXWQ, ND_CAT_SSE, ND_SET_SSE4, 606, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:994 Instruction:"PMOVZXBD Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x31 /r"/"RM" - { - ND_INS_PMOVZXBD, ND_CAT_SSE, ND_SET_SSE4, 607, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:995 Instruction:"PMOVZXBQ Vdq,Ww" Encoding:"0x66 0x0F 0x38 0x32 /r"/"RM" - { - ND_INS_PMOVZXBQ, ND_CAT_SSE, ND_SET_SSE4, 608, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:996 Instruction:"PMOVZXBW Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x30 /r"/"RM" - { - ND_INS_PMOVZXBW, ND_CAT_SSE, ND_SET_SSE4, 609, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:997 Instruction:"PMOVZXDQ Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x35 /r"/"RM" - { - ND_INS_PMOVZXDQ, ND_CAT_SSE, ND_SET_SSE4, 610, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:998 Instruction:"PMOVZXWD Vdq,Wq" Encoding:"0x66 0x0F 0x38 0x33 /r"/"RM" - { - ND_INS_PMOVZXWD, ND_CAT_SSE, ND_SET_SSE4, 611, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:999 Instruction:"PMOVZXWQ Vdq,Wd" Encoding:"0x66 0x0F 0x38 0x34 /r"/"RM" - { - ND_INS_PMOVZXWQ, ND_CAT_SSE, ND_SET_SSE4, 612, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1000 Instruction:"PMULDQ Vx,Wx" Encoding:"0x66 0x0F 0x38 0x28 /r"/"RM" - { - ND_INS_PMULDQ, ND_CAT_SSE, ND_SET_SSE4, 613, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1001 Instruction:"PMULHRSW Pq,Qq" Encoding:"NP 0x0F 0x38 0x0B /r"/"RM" - { - ND_INS_PMULHRSW, ND_CAT_MMX, ND_SET_SSSE3, 614, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1002 Instruction:"PMULHRSW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0B /r"/"RM" - { - ND_INS_PMULHRSW, ND_CAT_SSE, ND_SET_SSSE3, 614, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1003 Instruction:"PMULHRW Pq,Qq" Encoding:"0x0F 0x0F /r 0xB7"/"RM" - { - ND_INS_PMULHRW, ND_CAT_3DNOW, ND_SET_3DNOW, 615, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1004 Instruction:"PMULHUW Pq,Qq" Encoding:"NP 0x0F 0xE4 /r"/"RM" - { - ND_INS_PMULHUW, ND_CAT_MMX, ND_SET_MMX, 616, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1005 Instruction:"PMULHUW Vx,Wx" Encoding:"0x66 0x0F 0xE4 /r"/"RM" - { - ND_INS_PMULHUW, ND_CAT_SSE, ND_SET_SSE2, 616, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1006 Instruction:"PMULHW Pq,Qq" Encoding:"NP 0x0F 0xE5 /r"/"RM" - { - ND_INS_PMULHW, ND_CAT_MMX, ND_SET_MMX, 617, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1007 Instruction:"PMULHW Vx,Wx" Encoding:"0x66 0x0F 0xE5 /r"/"RM" - { - ND_INS_PMULHW, ND_CAT_SSE, ND_SET_SSE2, 617, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1008 Instruction:"PMULLD Vx,Wx" Encoding:"0x66 0x0F 0x38 0x40 /r"/"RM" - { - ND_INS_PMULLD, ND_CAT_SSE, ND_SET_SSE4, 618, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1009 Instruction:"PMULLW Pq,Qq" Encoding:"NP 0x0F 0xD5 /r"/"RM" - { - ND_INS_PMULLW, ND_CAT_MMX, ND_SET_MMX, 619, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1010 Instruction:"PMULLW Vx,Wx" Encoding:"0x66 0x0F 0xD5 /r"/"RM" - { - ND_INS_PMULLW, ND_CAT_SSE, ND_SET_SSE2, 619, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1011 Instruction:"PMULUDQ Pq,Qq" Encoding:"NP 0x0F 0xF4 /r"/"RM" - { - ND_INS_PMULUDQ, ND_CAT_MMX, ND_SET_SSE2, 620, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1012 Instruction:"PMULUDQ Vx,Wx" Encoding:"0x66 0x0F 0xF4 /r"/"RM" - { - ND_INS_PMULUDQ, ND_CAT_SSE, ND_SET_SSE2, 620, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1013 Instruction:"POP FS" Encoding:"0x0F 0xA1"/"" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_FS, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1014 Instruction:"POP GS" Encoding:"0x0F 0xA9"/"" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_GS, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1015 Instruction:"POP ES" Encoding:"0x07"/"" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_ES, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1016 Instruction:"POP SS" Encoding:"0x17"/"" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_SS, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1017 Instruction:"POP DS" Encoding:"0x1F"/"" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_DS, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1018 Instruction:"POP Zv" Encoding:"0x58"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1019 Instruction:"POP Zv" Encoding:"0x59"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1020 Instruction:"POP Zv" Encoding:"0x5A"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1021 Instruction:"POP Zv" Encoding:"0x5B"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1022 Instruction:"POP Zv" Encoding:"0x5C"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1023 Instruction:"POP Zv" Encoding:"0x5D"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1024 Instruction:"POP Zv" Encoding:"0x5E"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1025 Instruction:"POP Zv" Encoding:"0x5F"/"O" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1026 Instruction:"POP Ev" Encoding:"0x8F /0"/"M" - { - ND_INS_POP, ND_CAT_POP, ND_SET_I86, 621, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1027 Instruction:"POPA" Encoding:"ds16 0x61"/"" - { - ND_INS_POPA, ND_CAT_POP, ND_SET_I386, 622, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1028 Instruction:"POPAD" Encoding:"ds32 0x61"/"" - { - ND_INS_POPAD, ND_CAT_POP, ND_SET_I386, 623, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1029 Instruction:"POPCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xB8 /r"/"RM" - { - ND_INS_POPCNT, ND_CAT_SSE, ND_SET_POPCNT, 624, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_POPCNT, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1030 Instruction:"POPFD Fv" Encoding:"ds32 0x9D"/"" - { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 625, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1031 Instruction:"POPFQ Fv" Encoding:"dds64 0x9D"/"" - { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 626, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1032 Instruction:"POPFW Fv" Encoding:"ds16 0x9D"/"" - { - ND_INS_POPF, ND_CAT_POP, ND_SET_I86, 627, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1033 Instruction:"POR Pq,Qq" Encoding:"NP 0x0F 0xEB /r"/"RM" - { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_MMX, 628, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1034 Instruction:"POR Vx,Wx" Encoding:"0x66 0x0F 0xEB /r"/"RM" - { - ND_INS_POR, ND_CAT_LOGICAL, ND_SET_SSE2, 628, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1035 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M" - { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1036 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M" - { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1037 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M" - { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1038 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M" - { - ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 629, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1039 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M" - { - ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 630, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1040 Instruction:"PREFETCHIT0 Mb" Encoding:"piti riprel 0x0F 0x18 /7:mem"/"M" - { - ND_INS_PREFETCHIT0, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 631, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:1041 Instruction:"PREFETCHIT1 Mb" Encoding:"piti riprel 0x0F 0x18 /6:mem"/"M" - { - ND_INS_PREFETCHIT1, ND_CAT_PREFETCH, ND_SET_PREFETCHITI, 632, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_PREFETCHITI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_N, 0, 0), - }, - }, - - // Pos:1042 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M" - { - ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 633, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1043 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M" - { - ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1044 Instruction:"PREFETCHNTA Mb" Encoding:"piti 0x0F 0x18 /0:mem"/"M" - { - ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 634, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1045 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M" - { - ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1046 Instruction:"PREFETCHT0 Mb" Encoding:"piti 0x0F 0x18 /1:mem"/"M" - { - ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 635, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1047 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M" - { - ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1048 Instruction:"PREFETCHT1 Mb" Encoding:"piti 0x0F 0x18 /2:mem"/"M" - { - ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 636, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1049 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M" - { - ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1050 Instruction:"PREFETCHT2 Mb" Encoding:"piti 0x0F 0x18 /3:mem"/"M" - { - ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 637, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1051 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M" - { - ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 638, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1052 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M" - { - ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 639, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_P, 0, 0), - }, - }, - - // Pos:1053 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM" - { - ND_INS_PSADBW, ND_CAT_MMX, ND_SET_MMX, 640, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1054 Instruction:"PSADBW Vx,Wx" Encoding:"0x66 0x0F 0xF6 /r"/"RM" - { - ND_INS_PSADBW, ND_CAT_SSE, ND_SET_SSE2, 640, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1055 Instruction:"PSHUFB Pq,Qq" Encoding:"NP 0x0F 0x38 0x00 /r"/"RM" - { - ND_INS_PSHUFB, ND_CAT_MMX, ND_SET_SSSE3, 641, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1056 Instruction:"PSHUFB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x00 /r"/"RM" - { - ND_INS_PSHUFB, ND_CAT_SSE, ND_SET_SSSE3, 641, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1057 Instruction:"PSHUFD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x70 /r ib"/"RMI" - { - ND_INS_PSHUFD, ND_CAT_SSE, ND_SET_SSE2, 642, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1058 Instruction:"PSHUFHW Vx,Wx,Ib" Encoding:"0xF3 0x0F 0x70 /r ib"/"RMI" - { - ND_INS_PSHUFHW, ND_CAT_SSE, ND_SET_SSE2, 643, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1059 Instruction:"PSHUFLW Vx,Wx,Ib" Encoding:"0xF2 0x0F 0x70 /r ib"/"RMI" - { - ND_INS_PSHUFLW, ND_CAT_SSE, ND_SET_SSE2, 644, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1060 Instruction:"PSHUFW Pq,Qq,Ib" Encoding:"NP 0x0F 0x70 /r ib"/"RMI" - { - ND_INS_PSHUFW, ND_CAT_MMX, ND_SET_MMX, 645, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1061 Instruction:"PSIGNB Pq,Qq" Encoding:"NP 0x0F 0x38 0x08 /r"/"RM" - { - ND_INS_PSIGNB, ND_CAT_MMX, ND_SET_SSSE3, 646, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1062 Instruction:"PSIGNB Vx,Wx" Encoding:"0x66 0x0F 0x38 0x08 /r"/"RM" - { - ND_INS_PSIGNB, ND_CAT_SSE, ND_SET_SSSE3, 646, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1063 Instruction:"PSIGND Pq,Qq" Encoding:"NP 0x0F 0x38 0x0A /r"/"RM" - { - ND_INS_PSIGND, ND_CAT_MMX, ND_SET_SSSE3, 647, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1064 Instruction:"PSIGND Vx,Wx" Encoding:"0x66 0x0F 0x38 0x0A /r"/"RM" - { - ND_INS_PSIGND, ND_CAT_SSE, ND_SET_SSSE3, 647, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1065 Instruction:"PSIGNW Pq,Qq" Encoding:"NP 0x0F 0x38 0x09 /r"/"RM" - { - ND_INS_PSIGNW, ND_CAT_MMX, ND_SET_SSSE3, 648, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1066 Instruction:"PSIGNW Vx,Wx" Encoding:"0x66 0x0F 0x38 0x09 /r"/"RM" - { - ND_INS_PSIGNW, ND_CAT_SSE, ND_SET_SSSE3, 648, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSSE3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1067 Instruction:"PSLLD Nq,Ib" Encoding:"NP 0x0F 0x72 /6:reg ib"/"MI" - { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1068 Instruction:"PSLLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /6:reg ib"/"MI" - { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1069 Instruction:"PSLLD Pq,Qq" Encoding:"NP 0x0F 0xF2 /r"/"RM" - { - ND_INS_PSLLD, ND_CAT_MMX, ND_SET_MMX, 649, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1070 Instruction:"PSLLD Vx,Wx" Encoding:"0x66 0x0F 0xF2 /r"/"RM" - { - ND_INS_PSLLD, ND_CAT_SSE, ND_SET_SSE2, 649, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1071 Instruction:"PSLLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /7:reg ib"/"MI" - { - ND_INS_PSLLDQ, ND_CAT_SSE, ND_SET_SSE2, 650, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1072 Instruction:"PSLLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /6:reg ib"/"MI" - { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1073 Instruction:"PSLLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /6:reg ib"/"MI" - { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1074 Instruction:"PSLLQ Pq,Qq" Encoding:"NP 0x0F 0xF3 /r"/"RM" - { - ND_INS_PSLLQ, ND_CAT_MMX, ND_SET_MMX, 651, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1075 Instruction:"PSLLQ Vx,Wx" Encoding:"0x66 0x0F 0xF3 /r"/"RM" - { - ND_INS_PSLLQ, ND_CAT_SSE, ND_SET_SSE2, 651, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1076 Instruction:"PSLLW Nq,Ib" Encoding:"NP 0x0F 0x71 /6:reg ib"/"MI" - { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1077 Instruction:"PSLLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /6:reg ib"/"MI" - { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1078 Instruction:"PSLLW Pq,Qq" Encoding:"NP 0x0F 0xF1 /r"/"RM" - { - ND_INS_PSLLW, ND_CAT_MMX, ND_SET_MMX, 652, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1079 Instruction:"PSLLW Vx,Wx" Encoding:"0x66 0x0F 0xF1 /r"/"RM" - { - ND_INS_PSLLW, ND_CAT_SSE, ND_SET_SSE2, 652, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1080 Instruction:"PSMASH" Encoding:"0xF3 0x0F 0x01 /0xFF"/"" - { - ND_INS_PSMASH, ND_CAT_SYSTEM, ND_SET_SNP, 653, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1081 Instruction:"PSRAD Nq,Ib" Encoding:"NP 0x0F 0x72 /4:reg ib"/"MI" - { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1082 Instruction:"PSRAD Ux,Ib" Encoding:"0x66 0x0F 0x72 /4:reg ib"/"MI" - { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1083 Instruction:"PSRAD Pq,Qq" Encoding:"NP 0x0F 0xE2 /r"/"RM" - { - ND_INS_PSRAD, ND_CAT_MMX, ND_SET_MMX, 654, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1084 Instruction:"PSRAD Vx,Wx" Encoding:"0x66 0x0F 0xE2 /r"/"RM" - { - ND_INS_PSRAD, ND_CAT_SSE, ND_SET_SSE2, 654, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1085 Instruction:"PSRAW Nq,Ib" Encoding:"NP 0x0F 0x71 /4:reg ib"/"MI" - { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1086 Instruction:"PSRAW Ux,Ib" Encoding:"0x66 0x0F 0x71 /4:reg ib"/"MI" - { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1087 Instruction:"PSRAW Pq,Qq" Encoding:"NP 0x0F 0xE1 /r"/"RM" - { - ND_INS_PSRAW, ND_CAT_MMX, ND_SET_MMX, 655, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1088 Instruction:"PSRAW Vx,Wx" Encoding:"0x66 0x0F 0xE1 /r"/"RM" - { - ND_INS_PSRAW, ND_CAT_SSE, ND_SET_SSE2, 655, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1089 Instruction:"PSRLD Nq,Ib" Encoding:"NP 0x0F 0x72 /2:reg ib"/"MI" - { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1090 Instruction:"PSRLD Ux,Ib" Encoding:"0x66 0x0F 0x72 /2:reg ib"/"MI" - { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1091 Instruction:"PSRLD Pq,Qq" Encoding:"NP 0x0F 0xD2 /r"/"RM" - { - ND_INS_PSRLD, ND_CAT_MMX, ND_SET_MMX, 656, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1092 Instruction:"PSRLD Vx,Wx" Encoding:"0x66 0x0F 0xD2 /r"/"RM" - { - ND_INS_PSRLD, ND_CAT_SSE, ND_SET_SSE2, 656, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1093 Instruction:"PSRLDQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /3:reg ib"/"MI" - { - ND_INS_PSRLDQ, ND_CAT_SSE, ND_SET_SSE2, 657, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1094 Instruction:"PSRLQ Nq,Ib" Encoding:"NP 0x0F 0x73 /2:reg ib"/"MI" - { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1095 Instruction:"PSRLQ Ux,Ib" Encoding:"0x66 0x0F 0x73 /2:reg ib"/"MI" - { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1096 Instruction:"PSRLQ Pq,Qq" Encoding:"NP 0x0F 0xD3 /r"/"RM" - { - ND_INS_PSRLQ, ND_CAT_MMX, ND_SET_MMX, 658, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1097 Instruction:"PSRLQ Vx,Wx" Encoding:"0x66 0x0F 0xD3 /r"/"RM" - { - ND_INS_PSRLQ, ND_CAT_SSE, ND_SET_SSE2, 658, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1098 Instruction:"PSRLW Nq,Ib" Encoding:"NP 0x0F 0x71 /2:reg ib"/"MI" - { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_N, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1099 Instruction:"PSRLW Ux,Ib" Encoding:"0x66 0x0F 0x71 /2:reg ib"/"MI" - { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1100 Instruction:"PSRLW Pq,Qq" Encoding:"NP 0x0F 0xD1 /r"/"RM" - { - ND_INS_PSRLW, ND_CAT_MMX, ND_SET_MMX, 659, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1101 Instruction:"PSRLW Vx,Wx" Encoding:"0x66 0x0F 0xD1 /r"/"RM" - { - ND_INS_PSRLW, ND_CAT_SSE, ND_SET_SSE2, 659, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1102 Instruction:"PSUBB Pq,Qq" Encoding:"NP 0x0F 0xF8 /r"/"RM" - { - ND_INS_PSUBB, ND_CAT_MMX, ND_SET_MMX, 660, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1103 Instruction:"PSUBB Vx,Wx" Encoding:"0x66 0x0F 0xF8 /r"/"RM" - { - ND_INS_PSUBB, ND_CAT_SSE, ND_SET_SSE2, 660, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1104 Instruction:"PSUBD Pq,Qq" Encoding:"NP 0x0F 0xFA /r"/"RM" - { - ND_INS_PSUBD, ND_CAT_MMX, ND_SET_MMX, 661, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1105 Instruction:"PSUBD Vx,Wx" Encoding:"0x66 0x0F 0xFA /r"/"RM" - { - ND_INS_PSUBD, ND_CAT_SSE, ND_SET_SSE2, 661, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1106 Instruction:"PSUBQ Pq,Qq" Encoding:"NP 0x0F 0xFB /r"/"RM" - { - ND_INS_PSUBQ, ND_CAT_MMX, ND_SET_MMX, 662, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1107 Instruction:"PSUBQ Vx,Wx" Encoding:"0x66 0x0F 0xFB /r"/"RM" - { - ND_INS_PSUBQ, ND_CAT_SSE, ND_SET_SSE2, 662, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1108 Instruction:"PSUBSB Pq,Qq" Encoding:"NP 0x0F 0xE8 /r"/"RM" - { - ND_INS_PSUBSB, ND_CAT_MMX, ND_SET_MMX, 663, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1109 Instruction:"PSUBSB Vx,Wx" Encoding:"0x66 0x0F 0xE8 /r"/"RM" - { - ND_INS_PSUBSB, ND_CAT_SSE, ND_SET_SSE2, 663, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1110 Instruction:"PSUBSW Pq,Qq" Encoding:"NP 0x0F 0xE9 /r"/"RM" - { - ND_INS_PSUBSW, ND_CAT_MMX, ND_SET_MMX, 664, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1111 Instruction:"PSUBSW Vx,Wx" Encoding:"0x66 0x0F 0xE9 /r"/"RM" - { - ND_INS_PSUBSW, ND_CAT_SSE, ND_SET_SSE2, 664, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1112 Instruction:"PSUBUSB Pq,Qq" Encoding:"NP 0x0F 0xD8 /r"/"RM" - { - ND_INS_PSUBUSB, ND_CAT_MMX, ND_SET_MMX, 665, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1113 Instruction:"PSUBUSB Vx,Wx" Encoding:"0x66 0x0F 0xD8 /r"/"RM" - { - ND_INS_PSUBUSB, ND_CAT_SSE, ND_SET_SSE2, 665, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1114 Instruction:"PSUBUSW Pq,Qq" Encoding:"NP 0x0F 0xD9 /r"/"RM" - { - ND_INS_PSUBUSW, ND_CAT_MMX, ND_SET_MMX, 666, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1115 Instruction:"PSUBUSW Vx,Wx" Encoding:"0x66 0x0F 0xD9 /r"/"RM" - { - ND_INS_PSUBUSW, ND_CAT_SSE, ND_SET_SSE2, 666, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1116 Instruction:"PSUBW Pq,Qq" Encoding:"NP 0x0F 0xF9 /r"/"RM" - { - ND_INS_PSUBW, ND_CAT_MMX, ND_SET_MMX, 667, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1117 Instruction:"PSUBW Vx,Wx" Encoding:"0x66 0x0F 0xF9 /r"/"RM" - { - ND_INS_PSUBW, ND_CAT_SSE, ND_SET_SSE2, 667, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1118 Instruction:"PSWAPD Pq,Qq" Encoding:"0x0F 0x0F /r 0xBB"/"RM" - { - ND_INS_PSWAPD, ND_CAT_3DNOW, ND_SET_3DNOW, 668, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_3DNOW|ND_FLAG_MODRM, ND_CFF_3DNOW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1119 Instruction:"PTEST Vdq,Wdq" Encoding:"0x66 0x0F 0x38 0x17 /r"/"RM" - { - ND_INS_PTEST, ND_CAT_SSE, ND_SET_SSE4, 669, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1120 Instruction:"PTWRITE Ey" Encoding:"0xF3 0x0F 0xAE /4"/"M" - { - ND_INS_PTWRITE, ND_CAT_PTWRITE, ND_SET_PTWRITE, 670, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_NO66|ND_FLAG_MODRM, ND_CFF_PTWRITE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1121 Instruction:"PUNPCKHBW Pq,Qq" Encoding:"NP 0x0F 0x68 /r"/"RM" - { - ND_INS_PUNPCKHBW, ND_CAT_MMX, ND_SET_MMX, 671, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1122 Instruction:"PUNPCKHBW Vx,Wx" Encoding:"0x66 0x0F 0x68 /r"/"RM" - { - ND_INS_PUNPCKHBW, ND_CAT_SSE, ND_SET_SSE2, 671, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1123 Instruction:"PUNPCKHDQ Pq,Qq" Encoding:"NP 0x0F 0x6A /r"/"RM" - { - ND_INS_PUNPCKHDQ, ND_CAT_MMX, ND_SET_MMX, 672, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1124 Instruction:"PUNPCKHDQ Vx,Wx" Encoding:"0x66 0x0F 0x6A /r"/"RM" - { - ND_INS_PUNPCKHDQ, ND_CAT_SSE, ND_SET_SSE2, 672, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1125 Instruction:"PUNPCKHQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6D /r"/"RM" - { - ND_INS_PUNPCKHQDQ, ND_CAT_SSE, ND_SET_SSE2, 673, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1126 Instruction:"PUNPCKHWD Pq,Qq" Encoding:"NP 0x0F 0x69 /r"/"RM" - { - ND_INS_PUNPCKHWD, ND_CAT_MMX, ND_SET_MMX, 674, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1127 Instruction:"PUNPCKHWD Vx,Wx" Encoding:"0x66 0x0F 0x69 /r"/"RM" - { - ND_INS_PUNPCKHWD, ND_CAT_SSE, ND_SET_SSE2, 674, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1128 Instruction:"PUNPCKLBW Pq,Qd" Encoding:"NP 0x0F 0x60 /r"/"RM" - { - ND_INS_PUNPCKLBW, ND_CAT_MMX, ND_SET_MMX, 675, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1129 Instruction:"PUNPCKLBW Vx,Wx" Encoding:"0x66 0x0F 0x60 /r"/"RM" - { - ND_INS_PUNPCKLBW, ND_CAT_SSE, ND_SET_SSE2, 675, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1130 Instruction:"PUNPCKLDQ Pq,Qd" Encoding:"NP 0x0F 0x62 /r"/"RM" - { - ND_INS_PUNPCKLDQ, ND_CAT_MMX, ND_SET_MMX, 676, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1131 Instruction:"PUNPCKLDQ Vx,Wx" Encoding:"0x66 0x0F 0x62 /r"/"RM" - { - ND_INS_PUNPCKLDQ, ND_CAT_SSE, ND_SET_SSE2, 676, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1132 Instruction:"PUNPCKLQDQ Vx,Wx" Encoding:"0x66 0x0F 0x6C /r"/"RM" - { - ND_INS_PUNPCKLQDQ, ND_CAT_SSE, ND_SET_SSE2, 677, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1133 Instruction:"PUNPCKLWD Pq,Qd" Encoding:"NP 0x0F 0x61 /r"/"RM" - { - ND_INS_PUNPCKLWD, ND_CAT_MMX, ND_SET_MMX, 678, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1134 Instruction:"PUNPCKLWD Vx,Wx" Encoding:"0x66 0x0F 0x61 /r"/"RM" - { - ND_INS_PUNPCKLWD, ND_CAT_SSE, ND_SET_SSE2, 678, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1135 Instruction:"PUSH FS" Encoding:"0x0F 0xA0"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_FS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1136 Instruction:"PUSH GS" Encoding:"0x0F 0xA8"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_GS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1137 Instruction:"PUSH ES" Encoding:"0x06"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_ES, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1138 Instruction:"PUSH CS" Encoding:"0x0E"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1139 Instruction:"PUSH SS" Encoding:"0x16"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_SS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1140 Instruction:"PUSH DS" Encoding:"0x1E"/"" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_DS, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1141 Instruction:"PUSH Zv" Encoding:"0x50"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1142 Instruction:"PUSH Zv" Encoding:"0x51"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1143 Instruction:"PUSH Zv" Encoding:"0x52"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1144 Instruction:"PUSH Zv" Encoding:"0x53"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1145 Instruction:"PUSH Zv" Encoding:"0x54"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1146 Instruction:"PUSH Zv" Encoding:"0x55"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1147 Instruction:"PUSH Zv" Encoding:"0x56"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1148 Instruction:"PUSH Zv" Encoding:"0x57"/"O" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1149 Instruction:"PUSH Iz" Encoding:"0x68 iz"/"I" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_DWS, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1150 Instruction:"PUSH Ib" Encoding:"0x6A ib"/"I" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_DWS, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1151 Instruction:"PUSH Ev" Encoding:"0xFF /6"/"M" - { - ND_INS_PUSH, ND_CAT_PUSH, ND_SET_I86, 679, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64|ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1152 Instruction:"PUSHA" Encoding:"ds16 0x60"/"" - { - ND_INS_PUSHA, ND_CAT_PUSH, ND_SET_I386, 680, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1153 Instruction:"PUSHAD" Encoding:"ds32 0x60"/"" - { - ND_INS_PUSHAD, ND_CAT_PUSH, ND_SET_I386, 681, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_I64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v8, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1154 Instruction:"PUSHFD Fv" Encoding:"ds32 0x9C"/"" - { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 682, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1155 Instruction:"PUSHFQ Fv" Encoding:"dds64 0x9C"/"" - { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 683, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1156 Instruction:"PUSHFW Fv" Encoding:"ds16 0x9C"/"" - { - ND_INS_PUSHF, ND_CAT_PUSH, ND_SET_I86, 684, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_D64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_F, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1157 Instruction:"PVALIDATE" Encoding:"0xF2 0x0F 0x01 /0xFF"/"" - { - ND_INS_PVALIDATE, ND_CAT_SYSTEM, ND_SET_SNP, 685, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SNP, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF|NDR_RFLAG_CF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1158 Instruction:"PXOR Pq,Qq" Encoding:"NP 0x0F 0xEF /r"/"RM" - { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_MMX, 686, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_MMX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_P, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_Q, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1159 Instruction:"PXOR Vx,Wx" Encoding:"0x66 0x0F 0xEF /r"/"RM" - { - ND_INS_PXOR, ND_CAT_LOGICAL, ND_SET_SSE2, 686, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1160 Instruction:"RCL Eb,Ib" Encoding:"0xC0 /2 ib"/"MI" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1161 Instruction:"RCL Ev,Ib" Encoding:"0xC1 /2 ib"/"MI" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1162 Instruction:"RCL Eb,1" Encoding:"0xD0 /2"/"M1" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1163 Instruction:"RCL Ev,1" Encoding:"0xD1 /2"/"M1" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1164 Instruction:"RCL Eb,CL" Encoding:"0xD2 /2"/"MC" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1165 Instruction:"RCL Ev,CL" Encoding:"0xD3 /2"/"MC" - { - ND_INS_RCL, ND_CAT_ROTATE, ND_SET_I86, 687, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1166 Instruction:"RCPPS Vps,Wps" Encoding:"NP 0x0F 0x53 /r"/"RM" - { - ND_INS_RCPPS, ND_CAT_SSE, ND_SET_SSE, 688, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1167 Instruction:"RCPSS Vss,Wss" Encoding:"0xF3 0x0F 0x53 /r"/"RM" - { - ND_INS_RCPSS, ND_CAT_SSE, ND_SET_SSE, 689, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1168 Instruction:"RCR Eb,Ib" Encoding:"0xC0 /3 ib"/"MI" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1169 Instruction:"RCR Ev,Ib" Encoding:"0xC1 /3 ib"/"MI" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1170 Instruction:"RCR Eb,1" Encoding:"0xD0 /3"/"M1" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1171 Instruction:"RCR Ev,1" Encoding:"0xD1 /3"/"M1" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1172 Instruction:"RCR Eb,CL" Encoding:"0xD2 /3"/"MC" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1173 Instruction:"RCR Ev,CL" Encoding:"0xD3 /3"/"MC" - { - ND_INS_RCR, ND_CAT_ROTATE, ND_SET_I86, 690, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1174 Instruction:"RDFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /0:reg"/"M" - { - ND_INS_RDFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 691, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1175 Instruction:"RDGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /1:reg"/"M" - { - ND_INS_RDGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 692, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1176 Instruction:"RDMSR" Encoding:"0x0F 0x32"/"" - { - ND_INS_RDMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 693, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, ND_CFF_MSR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1177 Instruction:"RDMSRLIST" Encoding:"0xF2 0x0F 0x01 /0xC6"/"" - { - ND_INS_RDMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 694, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1178 Instruction:"RDPID Ryf" Encoding:"0xF3 0x0F 0xC7 /7:reg"/"M" - { - ND_INS_RDPID, ND_CAT_RDPID, ND_SET_RDPID, 695, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPID, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_yf, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1179 Instruction:"RDPKRU" Encoding:"NP 0x0F 0x01 /0xEE"/"" - { - ND_INS_RDPKRU, ND_CAT_MISC, ND_SET_PKU, 696, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1180 Instruction:"RDPMC" Encoding:"0x0F 0x33"/"" - { - ND_INS_RDPMC, ND_CAT_SYSTEM, ND_SET_RDPMC, 697, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1181 Instruction:"RDPRU" Encoding:"0x0F 0x01 /0xFD"/"" - { - ND_INS_RDPRU, ND_CAT_MISC, ND_SET_RDPRU, 698, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDPRU, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1182 Instruction:"RDRAND Rv" Encoding:"0x0F 0xC7 /6:reg"/"M" - { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDRAND, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1183 Instruction:"RDRAND Rv" Encoding:"0x66 0x0F 0xC7 /6:reg"/"M" - { - ND_INS_RDRAND, ND_CAT_RDRAND, ND_SET_RDRAND, 699, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDRAND, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1184 Instruction:"RDSEED Rv" Encoding:"0x0F 0xC7 /7:reg"/"M" - { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDSEED, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1185 Instruction:"RDSEED Rv" Encoding:"0x66 0x0F 0xC7 /7:reg"/"M" - { - ND_INS_RDSEED, ND_CAT_RDSEED, ND_SET_RDSEED, 700, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_S66|ND_FLAG_MODRM, ND_CFF_RDSEED, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1186 Instruction:"RDSHR Ed" Encoding:"cyrix 0x0F 0x36 /r"/"M" - { - ND_INS_RDSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 701, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1187 Instruction:"RDSSPD Rd" Encoding:"cet a0xF3 0x0F 0x1E /1:reg"/"M" - { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 702, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1188 Instruction:"RDSSPQ Rq" Encoding:"cet a0xF3 rexw 0x0F 0x1E /1:reg"/"M" - { - ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 703, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1189 Instruction:"RDTSC" Encoding:"0x0F 0x31"/"" - { - ND_INS_RDTSC, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 704, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1190 Instruction:"RDTSCP" Encoding:"0x0F 0x01 /0xF9"/"" - { - ND_INS_RDTSCP, ND_CAT_SYSTEM, ND_SET_RDTSCP, 705, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RDTSCP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MSR_TSC, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_TSCAUX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1191 Instruction:"RETF Iw" Encoding:"0xCA iw"/"I" - { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1192 Instruction:"RETF" Encoding:"0xCB"/"" - { - ND_INS_RETF, ND_CAT_RET, ND_SET_I86, 706, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v2, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1193 Instruction:"RETN Iw" Encoding:"0xC2 iw"/"I" - { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, - ND_PREF_BND, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1194 Instruction:"RETN" Encoding:"0xC3"/"" - { - ND_INS_RETN, ND_CAT_RET, ND_SET_I86, 707, - ND_PREF_BND, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1195 Instruction:"RMPADJUST" Encoding:"0xF3 0x0F 0x01 /0xFE"/"" - { - ND_INS_RMPADJUST, ND_CAT_SYSTEM, ND_SET_SNP, 708, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, - 0, - 0, - { - OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1196 Instruction:"RMPQUERY" Encoding:"0xF3 0x0F 0x01 /0xFD"/"" - { - ND_INS_RMPQUERY, ND_CAT_SYSTEM, ND_SET_SNP, 709, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RMPQUERY, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, - 0, - 0, - { - OP(ND_OPT_MEM_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1197 Instruction:"RMPUPDATE" Encoding:"0xF2 0x0F 0x01 /0xFE"/"" - { - ND_INS_RMPUPDATE, ND_CAT_SYSTEM, ND_SET_SNP, 710, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_I67|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_SNP, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_ZF|NDR_RFLAG_AF|NDR_RFLAG_PF|NDR_RFLAG_SF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MEM_rCX, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1198 Instruction:"ROL Eb,Ib" Encoding:"0xC0 /0 ib"/"MI" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1199 Instruction:"ROL Ev,Ib" Encoding:"0xC1 /0 ib"/"MI" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1200 Instruction:"ROL Eb,1" Encoding:"0xD0 /0"/"M1" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1201 Instruction:"ROL Ev,1" Encoding:"0xD1 /0"/"M1" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1202 Instruction:"ROL Eb,CL" Encoding:"0xD2 /0"/"MC" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1203 Instruction:"ROL Ev,CL" Encoding:"0xD3 /0"/"MC" - { - ND_INS_ROL, ND_CAT_ROTATE, ND_SET_I86, 711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1204 Instruction:"ROR Eb,Ib" Encoding:"0xC0 /1 ib"/"MI" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1205 Instruction:"ROR Ev,Ib" Encoding:"0xC1 /1 ib"/"MI" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1206 Instruction:"ROR Eb,1" Encoding:"0xD0 /1"/"M1" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1207 Instruction:"ROR Ev,1" Encoding:"0xD1 /1"/"M1" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1208 Instruction:"ROR Eb,CL" Encoding:"0xD2 /1"/"MC" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1209 Instruction:"ROR Ev,CL" Encoding:"0xD3 /1"/"MC" - { - ND_INS_ROR, ND_CAT_ROTATE, ND_SET_I86, 712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1210 Instruction:"RORX Gy,Ey,Ib" Encoding:"vex m:3 p:3 l:0 w:x 0xF0 /r ib"/"RMI" - { - ND_INS_RORX, ND_CAT_BMI2, ND_SET_BMI2, 713, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1211 Instruction:"ROUNDPD Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x09 /r ib"/"RMI" - { - ND_INS_ROUNDPD, ND_CAT_SSE, ND_SET_SSE4, 714, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1212 Instruction:"ROUNDPS Vx,Wx,Ib" Encoding:"0x66 0x0F 0x3A 0x08 /r ib"/"RMI" - { - ND_INS_ROUNDPS, ND_CAT_SSE, ND_SET_SSE4, 715, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1213 Instruction:"ROUNDSD Vsd,Wsd,Ib" Encoding:"0x66 0x0F 0x3A 0x0B /r ib"/"RMI" - { - ND_INS_ROUNDSD, ND_CAT_SSE, ND_SET_SSE4, 716, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1214 Instruction:"ROUNDSS Vss,Wss,Ib" Encoding:"0x66 0x0F 0x3A 0x0A /r ib"/"RMI" - { - ND_INS_ROUNDSS, ND_CAT_SSE, ND_SET_SSE4, 717, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1215 Instruction:"RSDC Sw,Ms" Encoding:"cyrix 0x0F 0x79 /r:mem"/"RM" - { - ND_INS_RSDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 718, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1216 Instruction:"RSLDT Ms" Encoding:"cyrix 0x0F 0x7B /r:mem"/"M" - { - ND_INS_RSLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 719, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1217 Instruction:"RSM" Encoding:"0x0F 0xAA"/"" - { - ND_INS_RSM, ND_CAT_SYSRET, ND_SET_I486, 720, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1218 Instruction:"RSQRTPS Vps,Wps" Encoding:"NP 0x0F 0x52 /r"/"RM" - { - ND_INS_RSQRTPS, ND_CAT_SSE, ND_SET_SSE, 721, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1219 Instruction:"RSQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x52 /r"/"RM" - { - ND_INS_RSQRTSS, ND_CAT_SSE, ND_SET_SSE, 722, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1220 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M" - { - ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 723, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_OF|NDR_RFLAG_SF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1221 Instruction:"RSTS Ms" Encoding:"cyrix 0x0F 0x7D /r:mem"/"M" - { - ND_INS_RSTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 724, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1222 Instruction:"SAHF" Encoding:"0x9E"/"" - { - ND_INS_SAHF, ND_CAT_FLAGOP, ND_SET_I86, 725, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0, - 0, - { - OP(ND_OPT_GPR_AH, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1223 Instruction:"SAL Eb,Ib" Encoding:"0xC0 /6 ib"/"MI" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1224 Instruction:"SAL Ev,Ib" Encoding:"0xC1 /6 ib"/"MI" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1225 Instruction:"SAL Eb,1" Encoding:"0xD0 /6"/"M1" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1226 Instruction:"SAL Ev,1" Encoding:"0xD1 /6"/"M1" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1227 Instruction:"SAL Eb,CL" Encoding:"0xD2 /6"/"MC" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1228 Instruction:"SAL Ev,CL" Encoding:"0xD3 /6"/"MC" - { - ND_INS_SAL, ND_CAT_SHIFT, ND_SET_I86, 726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1229 Instruction:"SALC" Encoding:"0xD6"/"" - { - ND_INS_SALC, ND_CAT_FLAGOP, ND_SET_I86, 727, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1230 Instruction:"SAR Eb,Ib" Encoding:"0xC0 /7 ib"/"MI" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1231 Instruction:"SAR Ev,Ib" Encoding:"0xC1 /7 ib"/"MI" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1232 Instruction:"SAR Eb,1" Encoding:"0xD0 /7"/"M1" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1233 Instruction:"SAR Ev,1" Encoding:"0xD1 /7"/"M1" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1234 Instruction:"SAR Eb,CL" Encoding:"0xD2 /7"/"MC" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1235 Instruction:"SAR Ev,CL" Encoding:"0xD3 /7"/"MC" - { - ND_INS_SAR, ND_CAT_SHIFT, ND_SET_I86, 728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1236 Instruction:"SARX Gy,Ey,By" Encoding:"vex m:2 p:2 l:0 w:x 0xF7 /r"/"RMV" - { - ND_INS_SARX, ND_CAT_BMI2, ND_SET_BMI2, 729, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1237 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/"" - { - ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 730, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_SHS, ND_OPS_12, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1238 Instruction:"SBB Eb,Gb" Encoding:"0x18 /r"/"MR" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1239 Instruction:"SBB Ev,Gv" Encoding:"0x19 /r"/"MR" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1240 Instruction:"SBB Gb,Eb" Encoding:"0x1A /r"/"RM" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1241 Instruction:"SBB Gv,Ev" Encoding:"0x1B /r"/"RM" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1242 Instruction:"SBB AL,Ib" Encoding:"0x1C ib"/"I" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1243 Instruction:"SBB rAX,Iz" Encoding:"0x1D iz"/"I" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1244 Instruction:"SBB Eb,Ib" Encoding:"0x80 /3 ib"/"MI" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1245 Instruction:"SBB Ev,Iz" Encoding:"0x81 /3 iz"/"MI" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1246 Instruction:"SBB Eb,Ib" Encoding:"0x82 /3 iz"/"MI" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1247 Instruction:"SBB Ev,Ib" Encoding:"0x83 /3 ib"/"MI" - { - ND_INS_SBB, ND_CAT_ARITH, ND_SET_I86, 731, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1248 Instruction:"SCASB AL,Yb" Encoding:"0xAE"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1249 Instruction:"SCASB AL,Yb" Encoding:"rep 0xAE"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 732, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1250 Instruction:"SCASD EAX,Yv" Encoding:"ds32 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1251 Instruction:"SCASD EAX,Yv" Encoding:"rep ds32 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 733, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1252 Instruction:"SCASQ RAX,Yv" Encoding:"ds64 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1253 Instruction:"SCASQ RAX,Yv" Encoding:"rep ds64 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 734, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1254 Instruction:"SCASW AX,Yv" Encoding:"ds16 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1255 Instruction:"SCASW AX,Yv" Encoding:"rep ds16 0xAF"/"" - { - ND_INS_SCAS, ND_CAT_STRINGOP, ND_SET_I86, 735, - ND_PREF_REPC, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_DF, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CR, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1256 Instruction:"SEAMCALL" Encoding:"0x66 0x0F 0x01 /0xCF"/"" - { - ND_INS_SEAMCALL, ND_CAT_TDX, ND_SET_TDX, 736, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1257 Instruction:"SEAMOPS" Encoding:"0x66 0x0F 0x01 /0xCE"/"" - { - ND_INS_SEAMOPS, ND_CAT_TDX, ND_SET_TDX, 737, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rR8, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rR9, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1258 Instruction:"SEAMRET" Encoding:"0x66 0x0F 0x01 /0xCD"/"" - { - ND_INS_SEAMRET, ND_CAT_TDX, ND_SET_TDX, 738, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - 0 - }, - }, - - // Pos:1259 Instruction:"SENDUIPI Rq" Encoding:"0xF3 0x0F 0xC7 /6:reg"/"M" - { - ND_INS_SENDUIPI, ND_CAT_UINTR, ND_SET_UINTR, 739, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1260 Instruction:"SERIALIZE" Encoding:"NP 0x0F 0x01 /0xE8"/"" - { - ND_INS_SERIALIZE, ND_CAT_MISC, ND_SET_SERIALIZE, 740, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL|ND_FLAG_MODRM, ND_CFF_SERIALIZE, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1261 Instruction:"SETBE Eb" Encoding:"0x0F 0x96 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 741, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1262 Instruction:"SETC Eb" Encoding:"0x0F 0x92 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 742, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1263 Instruction:"SETL Eb" Encoding:"0x0F 0x9C /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 743, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1264 Instruction:"SETLE Eb" Encoding:"0x0F 0x9E /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 744, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1265 Instruction:"SETNBE Eb" Encoding:"0x0F 0x97 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 745, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1266 Instruction:"SETNC Eb" Encoding:"0x0F 0x93 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 746, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_CF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1267 Instruction:"SETNL Eb" Encoding:"0x0F 0x9D /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 747, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1268 Instruction:"SETNLE Eb" Encoding:"0x0F 0x9F /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 748, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF|NDR_RFLAG_ZF|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1269 Instruction:"SETNO Eb" Encoding:"0x0F 0x91 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 749, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1270 Instruction:"SETNP Eb" Encoding:"0x0F 0x9B /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 750, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1271 Instruction:"SETNS Eb" Encoding:"0x0F 0x99 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 751, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1272 Instruction:"SETNZ Eb" Encoding:"0x0F 0x95 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 752, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1273 Instruction:"SETO Eb" Encoding:"0x0F 0x90 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 753, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_OF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1274 Instruction:"SETP Eb" Encoding:"0x0F 0x9A /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 754, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_PF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1275 Instruction:"SETS Eb" Encoding:"0x0F 0x98 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 755, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_SF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1276 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/"" - { - ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 756, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_SHS0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1277 Instruction:"SETZ Eb" Encoding:"0x0F 0x94 /r"/"M" - { - ND_INS_SETcc, ND_CAT_BITBYTE, ND_SET_I386, 757, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_COND|ND_FLAG_MODRM, 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1278 Instruction:"SFENCE" Encoding:"NP 0x0F 0xAE /7:reg"/"" - { - ND_INS_SFENCE, ND_CAT_MISC, ND_SET_SSE2, 758, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1279 Instruction:"SGDT Ms" Encoding:"0x0F 0x01 /0:mem"/"M" - { - ND_INS_SGDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 759, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_GDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1280 Instruction:"SHA1MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC9 /r"/"RM" - { - ND_INS_SHA1MSG1, ND_CAT_SHA, ND_SET_SHA, 760, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1281 Instruction:"SHA1MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCA /r"/"RM" - { - ND_INS_SHA1MSG2, ND_CAT_SHA, ND_SET_SHA, 761, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1282 Instruction:"SHA1NEXTE Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xC8 /r"/"RM" - { - ND_INS_SHA1NEXTE, ND_CAT_SHA, ND_SET_SHA, 762, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1283 Instruction:"SHA1RNDS4 Vdq,Wdq,Ib" Encoding:"NP 0x0F 0x3A 0xCC /r ib"/"RMI" - { - ND_INS_SHA1RNDS4, ND_CAT_SHA, ND_SET_SHA, 763, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1284 Instruction:"SHA256MSG1 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCC /r"/"RM" - { - ND_INS_SHA256MSG1, ND_CAT_SHA, ND_SET_SHA, 764, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1285 Instruction:"SHA256MSG2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCD /r"/"RM" - { - ND_INS_SHA256MSG2, ND_CAT_SHA, ND_SET_SHA, 765, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1286 Instruction:"SHA256RNDS2 Vdq,Wdq" Encoding:"NP 0x0F 0x38 0xCB /r"/"RM" - { - ND_INS_SHA256RNDS2, ND_CAT_SHA, ND_SET_SHA, 766, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1287 Instruction:"SHL Eb,Ib" Encoding:"0xC0 /4 ib"/"MI" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1288 Instruction:"SHL Ev,Ib" Encoding:"0xC1 /4 ib"/"MI" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1289 Instruction:"SHL Eb,1" Encoding:"0xD0 /4"/"M1" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1290 Instruction:"SHL Ev,1" Encoding:"0xD1 /4"/"M1" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1291 Instruction:"SHL Eb,CL" Encoding:"0xD2 /4"/"MC" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1292 Instruction:"SHL Ev,CL" Encoding:"0xD3 /4"/"MC" - { - ND_INS_SHL, ND_CAT_SHIFT, ND_SET_I86, 767, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1293 Instruction:"SHLD Ev,Gv,Ib" Encoding:"0x0F 0xA4 /r ib"/"MRI" - { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1294 Instruction:"SHLD Ev,Gv,CL" Encoding:"0x0F 0xA5 /r"/"MRC" - { - ND_INS_SHLD, ND_CAT_SHIFT, ND_SET_I386, 768, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1295 Instruction:"SHLX Gy,Ey,By" Encoding:"vex m:2 p:1 l:0 w:x 0xF7 /r"/"RMV" - { - ND_INS_SHLX, ND_CAT_BMI2, ND_SET_BMI2, 769, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1296 Instruction:"SHR Eb,Ib" Encoding:"0xC0 /5 ib"/"MI" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1297 Instruction:"SHR Ev,Ib" Encoding:"0xC1 /5 ib"/"MI" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1298 Instruction:"SHR Eb,1" Encoding:"0xD0 /5"/"M1" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1299 Instruction:"SHR Ev,1" Encoding:"0xD1 /5"/"M1" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_CONST_1, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1300 Instruction:"SHR Eb,CL" Encoding:"0xD2 /5"/"MC" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1301 Instruction:"SHR Ev,CL" Encoding:"0xD3 /5"/"MC" - { - ND_INS_SHR, ND_CAT_SHIFT, ND_SET_I86, 770, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1302 Instruction:"SHRD Ev,Gv,Ib" Encoding:"0x0F 0xAC /r ib"/"MRI" - { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1303 Instruction:"SHRD Ev,Gv,CL" Encoding:"0x0F 0xAD /r"/"MRC" - { - ND_INS_SHRD, ND_CAT_SHIFT, ND_SET_I386, 771, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - 0|NDR_RFLAG_CF|NDR_RFLAG_AF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RCW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1304 Instruction:"SHRX Gy,Ey,By" Encoding:"vex m:2 p:3 l:0 w:x 0xF7 /r"/"RMV" - { - ND_INS_SHRX, ND_CAT_BMI2, ND_SET_BMI2, 772, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_13, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1305 Instruction:"SHUFPD Vpd,Wpd,Ib" Encoding:"0x66 0x0F 0xC6 /r ib"/"RMI" - { - ND_INS_SHUFPD, ND_CAT_SSE, ND_SET_SSE2, 773, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1306 Instruction:"SHUFPS Vps,Wps,Ib" Encoding:"NP 0x0F 0xC6 /r ib"/"RMI" - { - ND_INS_SHUFPS, ND_CAT_SSE, ND_SET_SSE, 774, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1307 Instruction:"SIDT Ms" Encoding:"0x0F 0x01 /1:mem"/"M" - { - ND_INS_SIDT, ND_CAT_SYSTEM, ND_SET_I286REAL, 775, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_IDTR, ND_OPS_s, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1308 Instruction:"SKINIT" Encoding:"0x0F 0x01 /0xDE"/"" - { - ND_INS_SKINIT, ND_CAT_SYSTEM, ND_SET_SVM, 776, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1309 Instruction:"SLDT Mw" Encoding:"0x0F 0x00 /0:mem"/"M" - { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1310 Instruction:"SLDT Rv" Encoding:"0x0F 0x00 /0:reg"/"M" - { - ND_INS_SLDT, ND_CAT_SYSTEM, ND_SET_I286PROT, 777, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_LDTR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1311 Instruction:"SLWPCB Ry" Encoding:"xop m:9 0x12 /1:reg"/"M" - { - ND_INS_SLWPCB, ND_CAT_LWP, ND_SET_LWP, 778, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_LWP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1312 Instruction:"SMINT" Encoding:"cyrix 0x0F 0x7E"/"" - { - ND_INS_SMINT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 779, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1313 Instruction:"SMSW Mw" Encoding:"0x0F 0x01 /4:mem"/"M" - { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1314 Instruction:"SMSW Rv" Encoding:"0x0F 0x01 /4:reg"/"M" - { - ND_INS_SMSW, ND_CAT_SYSTEM, ND_SET_I286REAL, 780, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1315 Instruction:"SPFLT Ry" Encoding:"vex m:1 p:3 0xAE /6:reg"/"M" - { - ND_INS_SPFLT, ND_CAT_UNKNOWN, ND_SET_UNKNOWN, 781, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1316 Instruction:"SQRTPD Vpd,Wpd" Encoding:"0x66 0x0F 0x51 /r"/"RM" - { - ND_INS_SQRTPD, ND_CAT_SSE, ND_SET_SSE2, 782, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1317 Instruction:"SQRTPS Vps,Wps" Encoding:"NP 0x0F 0x51 /r"/"RM" - { - ND_INS_SQRTPS, ND_CAT_SSE, ND_SET_SSE, 783, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1318 Instruction:"SQRTSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x51 /r"/"RM" - { - ND_INS_SQRTSD, ND_CAT_SSE, ND_SET_SSE2, 784, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1319 Instruction:"SQRTSS Vss,Wss" Encoding:"0xF3 0x0F 0x51 /r"/"RM" - { - ND_INS_SQRTSS, ND_CAT_SSE, ND_SET_SSE, 785, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1320 Instruction:"STAC" Encoding:"NP 0x0F 0x01 /0xCB"/"" - { - ND_INS_STAC, ND_CAT_SMAP, ND_SET_SMAP, 786, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SMAP, - 0, - 0, - 0|NDR_RFLAG_AC, - 0, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1321 Instruction:"STC" Encoding:"0xF9"/"" - { - ND_INS_STC, ND_CAT_FLAGOP, ND_SET_I86, 787, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0|NDR_RFLAG_CF, - 0, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1322 Instruction:"STD" Encoding:"0xFD"/"" - { - ND_INS_STD, ND_CAT_FLAGOP, ND_SET_I86, 788, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0|NDR_RFLAG_DF, - 0, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1323 Instruction:"STGI" Encoding:"0x0F 0x01 /0xDC"/"" - { - ND_INS_STGI, ND_CAT_SYSTEM, ND_SET_SVM, 789, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1324 Instruction:"STI" Encoding:"0xFB"/"" - { - ND_INS_STI, ND_CAT_FLAGOP, ND_SET_I86, 790, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0|NDR_RFLAG_IF, - 0, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1325 Instruction:"STMXCSR Md" Encoding:"NP 0x0F 0xAE /3:mem"/"M" - { - ND_INS_STMXCSR, ND_CAT_SSE, ND_SET_SSE, 791, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1326 Instruction:"STOSB Yb,AL" Encoding:"0xAA"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1327 Instruction:"STOSB Yb,AL" Encoding:"rep 0xAA"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 792, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1328 Instruction:"STOSD Yv,EAX" Encoding:"ds32 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1329 Instruction:"STOSD Yv,EAX" Encoding:"rep ds32 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 793, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1330 Instruction:"STOSQ Yv,RAX" Encoding:"ds64 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1331 Instruction:"STOSQ Yv,RAX" Encoding:"rep ds64 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 794, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1332 Instruction:"STOSW Yv,AX" Encoding:"ds16 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1333 Instruction:"STOSW Yv,AX" Encoding:"rep ds16 0xAB"/"" - { - ND_INS_STOS, ND_CAT_STRINGOP, ND_SET_I86, 795, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 3), 0, 0, 0, 0, 0, 0, 0, 0, - 0|NDR_RFLAG_DF, - 0, - 0, - 0, - { - OP(ND_OPT_Y, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rDI, ND_OPS_asz, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1334 Instruction:"STR Mw" Encoding:"0x0F 0x00 /1:mem"/"M" - { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1335 Instruction:"STR Rv" Encoding:"0x0F 0x00 /1:reg"/"M" - { - ND_INS_STR, ND_CAT_SYSTEM, ND_SET_I286PROT, 796, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_SYS_TR, ND_OPS_w, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1336 Instruction:"STTILECFG Moq" Encoding:"vex m:2 p:1 l:0 w:0 0x49 /0:mem"/"M" - { - ND_INS_STTILECFG, ND_CAT_AMX, ND_SET_AMXTILE, 797, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E2, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_oq, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1337 Instruction:"STUI" Encoding:"0xF3 0x0F 0x01 /0xEF"/"" - { - ND_INS_STUI, ND_CAT_UINTR, ND_SET_UINTR, 798, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1338 Instruction:"SUB Eb,Gb" Encoding:"0x28 /r"/"MR" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1339 Instruction:"SUB Ev,Gv" Encoding:"0x29 /r"/"MR" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1340 Instruction:"SUB Gb,Eb" Encoding:"0x2A /r"/"RM" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1341 Instruction:"SUB Gv,Ev" Encoding:"0x2B /r"/"RM" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1342 Instruction:"SUB AL,Ib" Encoding:"0x2C ib"/"I" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1343 Instruction:"SUB rAX,Iz" Encoding:"0x2D iz"/"I" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1344 Instruction:"SUB Eb,Ib" Encoding:"0x80 /5 ib"/"MI" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1345 Instruction:"SUB Ev,Iz" Encoding:"0x81 /5 iz"/"MI" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1346 Instruction:"SUB Eb,Ib" Encoding:"0x82 /5 iz"/"MI" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1347 Instruction:"SUB Ev,Ib" Encoding:"0x83 /5 ib"/"MI" - { - ND_INS_SUB, ND_CAT_ARITH, ND_SET_I86, 799, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1348 Instruction:"SUBPD Vpd,Wpd" Encoding:"0x66 0x0F 0x5C /r"/"RM" - { - ND_INS_SUBPD, ND_CAT_SSE, ND_SET_SSE2, 800, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1349 Instruction:"SUBPS Vps,Wps" Encoding:"NP 0x0F 0x5C /r"/"RM" - { - ND_INS_SUBPS, ND_CAT_SSE, ND_SET_SSE, 801, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1350 Instruction:"SUBSD Vsd,Wsd" Encoding:"0xF2 0x0F 0x5C /r"/"RM" - { - ND_INS_SUBSD, ND_CAT_SSE, ND_SET_SSE2, 802, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1351 Instruction:"SUBSS Vss,Wss" Encoding:"0xF3 0x0F 0x5C /r"/"RM" - { - ND_INS_SUBSS, ND_CAT_SSE, ND_SET_SSE, 803, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1352 Instruction:"SVDC Ms,Sw" Encoding:"cyrix 0x0F 0x78 /r:mem"/"MR" - { - ND_INS_SVDC, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 804, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_S, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1353 Instruction:"SVLDT Ms" Encoding:"cyrix 0x0F 0x7A /r:mem"/"M" - { - ND_INS_SVLDT, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 805, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1354 Instruction:"SVTS Ms" Encoding:"cyrix 0x0F 0x7C /r:mem"/"M" - { - ND_INS_SVTS, ND_CAT_SEGOP, ND_SET_CYRIX_SMM, 806, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_s, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1355 Instruction:"SWAPGS" Encoding:"0x0F 0x01 /0xF8"/"" - { - ND_INS_SWAPGS, ND_CAT_SYSTEM, ND_SET_LONGMODE, 807, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_MSR_KGSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1356 Instruction:"SYSCALL" Encoding:"0x0F 0x05"/"" - { - ND_INS_SYSCALL, ND_CAT_SYSCALL, ND_SET_AMD, 808, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 10), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_CETT, ND_CFF_FSC, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_LSTAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_FMASK, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1357 Instruction:"SYSENTER" Encoding:"0x0F 0x34"/"" - { - ND_INS_SYSENTER, ND_CAT_SYSCALL, ND_SET_PPRO, 809, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 9), 0, 0, 0, 0, 0, 0, ND_FLAG_CETT, ND_CFF_SEP, - 0, - 0, - 0, - 0|NDR_RFLAG_IF, - { - OP(ND_OPT_MSR_SCS, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_SESP, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_SEIP, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1358 Instruction:"SYSEXIT" Encoding:"0x0F 0x35"/"" - { - ND_INS_SYSEXIT, ND_CAT_SYSRET, ND_SET_PPRO, 810, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 5), 0, 0, 0, 0, 0, 0, ND_FLAG_F64, ND_CFF_SEP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1359 Instruction:"SYSRET" Encoding:"0x0F 0x07"/"" - { - ND_INS_SYSRET, ND_CAT_SYSRET, ND_SET_AMD, 811, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 8), 0, 0, 0, 0, 0, 0, 0, ND_CFF_FSC, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MSR_STAR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_SS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rR11, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SEG_CS, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_SSP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1360 Instruction:"T1MSKC By,Ey" Encoding:"xop m:9 0x01 /7"/"VM" - { - ND_INS_T1MSKC, ND_CAT_BITBYTE, ND_SET_TBM, 812, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1361 Instruction:"TCMMIMFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x6C /r:reg"/"" - { - ND_INS_TCMMIMFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 813, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1362 Instruction:"TCMMRLFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x6C /r:reg"/"" - { - ND_INS_TCMMRLFP16PS, ND_CAT_AMX, ND_SET_AMXCOMPLEX, 814, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXCOMPLEX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1363 Instruction:"TDCALL" Encoding:"0x66 0x0F 0x01 /0xCC"/"" - { - ND_INS_TDCALL, ND_CAT_TDX, ND_SET_TDX, 815, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXN|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1364 Instruction:"TDPBF16PS rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5C /r:reg"/"" - { - ND_INS_TDPBF16PS, ND_CAT_AMX, ND_SET_AMXBF16, 816, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXBF16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1365 Instruction:"TDPBSSD rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5E /r:reg"/"" - { - ND_INS_TDPBSSD, ND_CAT_AMX, ND_SET_AMXINT8, 817, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1366 Instruction:"TDPBSUD rTt,mTt,vTt" Encoding:"vex m:2 p:2 l:0 w:0 0x5E /r:reg"/"" - { - ND_INS_TDPBSUD, ND_CAT_AMX, ND_SET_AMXINT8, 818, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1367 Instruction:"TDPBUSD rTt,mTt,vTt" Encoding:"vex m:2 p:1 l:0 w:0 0x5E /r:reg"/"" - { - ND_INS_TDPBUSD, ND_CAT_AMX, ND_SET_AMXINT8, 819, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1368 Instruction:"TDPBUUD rTt,mTt,vTt" Encoding:"vex m:2 p:0 l:0 w:0 0x5E /r:reg"/"" - { - ND_INS_TDPBUUD, ND_CAT_AMX, ND_SET_AMXINT8, 820, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1369 Instruction:"TDPFP16PS rTt,mTt,vTt" Encoding:"vex m:2 p:3 l:0 w:0 0x5C /r:reg"/"" - { - ND_INS_TDPFP16PS, ND_CAT_AMX, ND_SET_AMXFP16, 821, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_AMX_E4, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXFP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_mT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_vT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1370 Instruction:"TEST Eb,Gb" Encoding:"0x84 /r"/"MR" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1371 Instruction:"TEST Ev,Gv" Encoding:"0x85 /r"/"MR" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1372 Instruction:"TEST AL,Ib" Encoding:"0xA8 ib"/"I" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1373 Instruction:"TEST rAX,Iz" Encoding:"0xA9 iz"/"I" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1374 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /0 ib"/"MI" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1375 Instruction:"TEST Eb,Ib" Encoding:"0xF6 /1 ib"/"MI" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1376 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /0 iz"/"MI" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1377 Instruction:"TEST Ev,Iz" Encoding:"0xF7 /1 iz"/"MI" - { - ND_INS_TEST, ND_CAT_LOGIC, ND_SET_I86, 822, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1378 Instruction:"TESTUI" Encoding:"0xF3 0x0F 0x01 /0xED"/"" - { - ND_INS_TESTUI, ND_CAT_UINTR, ND_SET_UINTR, 823, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1379 Instruction:"TILELOADD rTt,Mt" Encoding:"vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem"/"M" - { - ND_INS_TILELOADD, ND_CAT_AMX, ND_SET_AMXTILE, 824, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1380 Instruction:"TILELOADDT1 rTt,Mt" Encoding:"vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem"/"M" - { - ND_INS_TILELOADDT1, ND_CAT_AMX, ND_SET_AMXTILE, 825, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1381 Instruction:"TILERELEASE" Encoding:"vex m:2 p:0 l:0 w:0 0x49 /0xC0"/"" - { - ND_INS_TILERELEASE, ND_CAT_AMX, ND_SET_AMXTILE, 826, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, ND_EXT_AMX_E6, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1382 Instruction:"TILESTORED Mt,rTt" Encoding:"vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem"/"M" - { - ND_INS_TILESTORED, ND_CAT_AMX, ND_SET_AMXTILE, 827, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_AMX_E3, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_SIBMEM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_t, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1383 Instruction:"TILEZERO rTt" Encoding:"vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0"/"" - { - ND_INS_TILEZERO, ND_CAT_AMX, ND_SET_AMXTILE, 828, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 0), 0, ND_EXT_AMX_E5, ND_EXC_AMX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_AMXTILE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rT, ND_OPS_t, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1384 Instruction:"TLBSYNC" Encoding:"0x0F 0x01 /0xFF"/"" - { - ND_INS_TLBSYNC, ND_CAT_SYSTEM, ND_SET_INVLPGB, 829, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_INVLPGB, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1385 Instruction:"TPAUSE Ry" Encoding:"0x66 0x0F 0xAE /6:reg"/"M" - { - ND_INS_TPAUSE, ND_CAT_WAITPKG, ND_SET_WAITPKG, 830, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1386 Instruction:"TZCNT Gv,Ev" Encoding:"a0xF3 0x0F 0xBC /r"/"RM" - { - ND_INS_TZCNT, ND_CAT_BMI1, ND_SET_BMI1, 831, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_BMI1, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1387 Instruction:"TZMSK By,Ey" Encoding:"xop m:9 0x01 /4"/"VM" - { - ND_INS_TZMSK, ND_CAT_BITBYTE, ND_SET_TBM, 832, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TBM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_B, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1388 Instruction:"UCOMISD Vsd,Wsd" Encoding:"0x66 0x0F 0x2E /r"/"RM" - { - ND_INS_UCOMISD, ND_CAT_SSE2, ND_SET_SSE2, 833, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1389 Instruction:"UCOMISS Vss,Wss" Encoding:"NP 0x0F 0x2E /r"/"RM" - { - ND_INS_UCOMISS, ND_CAT_SSE, ND_SET_SSE, 834, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1390 Instruction:"UD0 Gd,Ed" Encoding:"0x0F 0xFF /r"/"RM" - { - ND_INS_UD0, ND_CAT_UD, ND_SET_UD, 835, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1391 Instruction:"UD1 Gd,Ed" Encoding:"0x0F 0xB9 /r"/"RM" - { - ND_INS_UD1, ND_CAT_UD, ND_SET_UD, 836, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1392 Instruction:"UD2" Encoding:"0x0F 0x0B"/"" - { - ND_INS_UD2, ND_CAT_MISC, ND_SET_PPRO, 837, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1393 Instruction:"UIRET" Encoding:"0xF3 0x0F 0x01 /0xEC"/"" - { - ND_INS_UIRET, ND_CAT_RET, ND_SET_UINTR, 838, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 6), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_UINTR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_RIP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rSP, ND_OPS_ssz, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_UIF, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_K, ND_OPS_v3, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_SHSP, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1394 Instruction:"UMONITOR mMb" Encoding:"0xF3 0x0F 0xAE /6:reg"/"M" - { - ND_INS_UMONITOR, ND_CAT_WAITPKG, ND_SET_WAITPKG, 839, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, - 0, - 0|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_mM, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1395 Instruction:"UMWAIT Ry" Encoding:"0xF2 0x0F 0xAE /6:reg"/"M" - { - ND_INS_UMWAIT, ND_CAT_WAITPKG, ND_SET_WAITPKG, 840, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WAITPKG, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1396 Instruction:"UNPCKHPD Vx,Wx" Encoding:"0x66 0x0F 0x15 /r"/"RM" - { - ND_INS_UNPCKHPD, ND_CAT_SSE, ND_SET_SSE2, 841, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1397 Instruction:"UNPCKHPS Vx,Wx" Encoding:"NP 0x0F 0x15 /r"/"RM" - { - ND_INS_UNPCKHPS, ND_CAT_SSE, ND_SET_SSE, 842, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1398 Instruction:"UNPCKLPD Vx,Wx" Encoding:"0x66 0x0F 0x14 /r"/"RM" - { - ND_INS_UNPCKLPD, ND_CAT_SSE, ND_SET_SSE2, 843, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1399 Instruction:"UNPCKLPS Vx,Wx" Encoding:"NP 0x0F 0x14 /r"/"RM" - { - ND_INS_UNPCKLPS, ND_CAT_SSE, ND_SET_SSE, 844, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1400 Instruction:"V4FMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x9A /r:mem"/"RAVM" - { - ND_INS_V4FMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 845, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1401 Instruction:"V4FMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0x9B /r:mem"/"RAVM" - { - ND_INS_V4FMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 846, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1402 Instruction:"V4FNMADDPS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0xAA /r:mem"/"RAVM" - { - ND_INS_V4FNMADDPS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 847, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1403 Instruction:"V4FNMADDSS Vdq{K}{z},aKq,Hdq+3,Mdq" Encoding:"evex m:2 p:3 l:i w:0 0xAB /r:mem"/"RAVM" - { - ND_INS_V4FNMADDSS, ND_CAT_VFMAPS, ND_SET_AVX5124FMAPS, 848, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124FMAPS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1404 Instruction:"VADDPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x58 /r"/"RAVM" - { - ND_INS_VADDPD, ND_CAT_AVX512, ND_SET_AVX512F, 849, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1405 Instruction:"VADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x58 /r"/"RVM" - { - ND_INS_VADDPD, ND_CAT_AVX, ND_SET_AVX, 849, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1406 Instruction:"VADDPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x58 /r"/"RAVM" - { - ND_INS_VADDPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 850, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1407 Instruction:"VADDPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x58 /r"/"RAVM" - { - ND_INS_VADDPS, ND_CAT_AVX512, ND_SET_AVX512F, 851, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1408 Instruction:"VADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x58 /r"/"RVM" - { - ND_INS_VADDPS, ND_CAT_AVX, ND_SET_AVX, 851, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1409 Instruction:"VADDSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x58 /r"/"RAVM" - { - ND_INS_VADDSD, ND_CAT_AVX512, ND_SET_AVX512F, 852, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1410 Instruction:"VADDSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x58 /r"/"RVM" - { - ND_INS_VADDSD, ND_CAT_AVX, ND_SET_AVX, 852, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1411 Instruction:"VADDSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x58 /r"/"RAVM" - { - ND_INS_VADDSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 853, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1412 Instruction:"VADDSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x58 /r"/"RAVM" - { - ND_INS_VADDSS, ND_CAT_AVX512, ND_SET_AVX512F, 854, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1413 Instruction:"VADDSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x58 /r"/"RVM" - { - ND_INS_VADDSS, ND_CAT_AVX, ND_SET_AVX, 854, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1414 Instruction:"VADDSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0xD0 /r"/"RVM" - { - ND_INS_VADDSUBPD, ND_CAT_AVX, ND_SET_AVX, 855, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1415 Instruction:"VADDSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0xD0 /r"/"RVM" - { - ND_INS_VADDSUBPS, ND_CAT_AVX, ND_SET_AVX, 856, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1416 Instruction:"VAESDEC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDE /r"/"RVM" - { - ND_INS_VAESDEC, ND_CAT_VAES, ND_SET_VAES, 857, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1417 Instruction:"VAESDEC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDE /r"/"RVM" - { - ND_INS_VAESDEC, ND_CAT_AES, ND_SET_AES, 857, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1418 Instruction:"VAESDECLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDF /r"/"RVM" - { - ND_INS_VAESDECLAST, ND_CAT_VAES, ND_SET_VAES, 858, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1419 Instruction:"VAESDECLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDF /r"/"RVM" - { - ND_INS_VAESDECLAST, ND_CAT_AES, ND_SET_AES, 858, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1420 Instruction:"VAESENC Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDC /r"/"RVM" - { - ND_INS_VAESENC, ND_CAT_VAES, ND_SET_VAES, 859, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1421 Instruction:"VAESENC Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDC /r"/"RVM" - { - ND_INS_VAESENC, ND_CAT_AES, ND_SET_AES, 859, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1422 Instruction:"VAESENCLAST Vfv,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0xDD /r"/"RVM" - { - ND_INS_VAESENCLAST, ND_CAT_VAES, ND_SET_VAES, 860, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VAES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1423 Instruction:"VAESENCLAST Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0xDD /r"/"RVM" - { - ND_INS_VAESENCLAST, ND_CAT_AES, ND_SET_AES, 860, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1424 Instruction:"VAESIMC Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0xDB /r"/"RM" - { - ND_INS_VAESIMC, ND_CAT_AES, ND_SET_AES, 861, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1425 Instruction:"VAESKEYGENASSIST Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0xDF /r ib"/"RMI" - { - ND_INS_VAESKEYGENASSIST, ND_CAT_AES, ND_SET_AES, 862, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1426 Instruction:"VALIGND Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x03 /r ib"/"RAVMI" - { - ND_INS_VALIGND, ND_CAT_AVX512, ND_SET_AVX512F, 863, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1427 Instruction:"VALIGNQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x03 /r ib"/"RAVMI" - { - ND_INS_VALIGNQ, ND_CAT_AVX512, ND_SET_AVX512F, 864, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1428 Instruction:"VANDNPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x55 /r"/"RAVM" - { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 865, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:1429 Instruction:"VANDNPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x55 /r"/"RVM" - { - ND_INS_VANDNPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 865, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1430 Instruction:"VANDNPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x55 /r"/"RAVM" - { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 866, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1431 Instruction:"VANDNPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x55 /r"/"RVM" - { - ND_INS_VANDNPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 866, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1432 Instruction:"VANDPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x54 /r"/"RAVM" - { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 867, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:1433 Instruction:"VANDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x54 /r"/"RVM" - { - ND_INS_VANDPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 867, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1434 Instruction:"VANDPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x54 /r"/"RAVM" - { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 868, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1435 Instruction:"VANDPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x54 /r"/"RVM" - { - ND_INS_VANDPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 868, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1436 Instruction:"VBCSTNEBF162PS Vx,Mw" Encoding:"vex m:2 p:2 l:x w:0 0xB1 /r:mem"/"RM" - { - ND_INS_VBCSTNEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 869, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1437 Instruction:"VBCSTNESH2PS Vx,Mw" Encoding:"vex m:2 p:1 l:x w:0 0xB1 /r:mem"/"RM" - { - ND_INS_VBCSTNESH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 870, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1438 Instruction:"VBLENDMPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x65 /r"/"RAVM" - { - ND_INS_VBLENDMPD, ND_CAT_BLEND, ND_SET_AVX512F, 871, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:1439 Instruction:"VBLENDMPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x65 /r"/"RAVM" - { - ND_INS_VBLENDMPS, ND_CAT_BLEND, ND_SET_AVX512F, 872, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1440 Instruction:"VBLENDPD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0D /r ib"/"RVMI" - { - ND_INS_VBLENDPD, ND_CAT_AVX, ND_SET_AVX, 873, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1441 Instruction:"VBLENDPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0C /r ib"/"RVMI" - { - ND_INS_VBLENDPS, ND_CAT_AVX, ND_SET_AVX, 874, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1442 Instruction:"VBLENDVPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4B /r is4"/"RVML" - { - ND_INS_VBLENDVPD, ND_CAT_AVX, ND_SET_AVX, 875, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1443 Instruction:"VBLENDVPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4A /r is4"/"RVML" - { - ND_INS_VBLENDVPS, ND_CAT_AVX, ND_SET_AVX, 876, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1444 Instruction:"VBROADCASTF128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x1A /r:mem"/"RM" - { - ND_INS_VBROADCASTF128, ND_CAT_BROADCAST, ND_SET_AVX, 877, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1445 Instruction:"VBROADCASTF32X2 Vuv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x19 /r"/"RAM" - { - ND_INS_VBROADCASTF32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 878, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1446 Instruction:"VBROADCASTF32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x1A /r:mem"/"RAM" - { - ND_INS_VBROADCASTF32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 879, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1447 Instruction:"VBROADCASTF32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x1B /r:mem"/"RAM" - { - ND_INS_VBROADCASTF32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 880, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1448 Instruction:"VBROADCASTF64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x1A /r:mem"/"RAM" - { - ND_INS_VBROADCASTF64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 881, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1449 Instruction:"VBROADCASTF64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x1B /r:mem"/"RAM" - { - ND_INS_VBROADCASTF64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 882, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1450 Instruction:"VBROADCASTI128 Vqq,Mdq" Encoding:"vex m:2 p:1 l:1 w:0 0x5A /r:mem"/"RM" - { - ND_INS_VBROADCASTI128, ND_CAT_BROADCAST, ND_SET_AVX2, 883, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1451 Instruction:"VBROADCASTI32X2 Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:0 0x59 /r"/"RAM" - { - ND_INS_VBROADCASTI32X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 884, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1452 Instruction:"VBROADCASTI32X4 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:0 0x5A /r:mem"/"RAM" - { - ND_INS_VBROADCASTI32X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 885, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1453 Instruction:"VBROADCASTI32X8 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:0 0x5B /r:mem"/"RAM" - { - ND_INS_VBROADCASTI32X8, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 886, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1454 Instruction:"VBROADCASTI64X2 Vuv{K}{z},aKq,Mdq" Encoding:"evex m:2 p:1 l:x w:1 0x5A /r:mem"/"RAM" - { - ND_INS_VBROADCASTI64X2, ND_CAT_BROADCAST, ND_SET_AVX512DQ, 887, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1455 Instruction:"VBROADCASTI64X4 Voq{K}{z},aKq,Mqq" Encoding:"evex m:2 p:1 l:2 w:1 0x5B /r:mem"/"RAM" - { - ND_INS_VBROADCASTI64X4, ND_CAT_BROADCAST, ND_SET_AVX512F, 888, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T4, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1456 Instruction:"VBROADCASTSD Vuv{K}{z},aKq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x19 /r"/"RAM" - { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX512F, 889, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1457 Instruction:"VBROADCASTSD Vqq,Wsd" Encoding:"vex m:2 p:1 l:x w:0 0x19 /r"/"RM" - { - ND_INS_VBROADCASTSD, ND_CAT_BROADCAST, ND_SET_AVX, 889, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1458 Instruction:"VBROADCASTSS Vfv{K}{z},aKq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x18 /r"/"RAM" - { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX512F, 890, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1459 Instruction:"VBROADCASTSS Vx,Wss" Encoding:"vex m:2 p:1 l:x w:0 0x18 /r"/"RM" - { - ND_INS_VBROADCASTSS, ND_CAT_BROADCAST, ND_SET_AVX, 890, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1460 Instruction:"VCMPPD rKq{K},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPPD, ND_CAT_AVX512, ND_SET_AVX512F, 891, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1461 Instruction:"VCMPPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC2 /r ib"/"RVMI" - { - ND_INS_VCMPPD, ND_CAT_AVX, ND_SET_AVX, 891, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1462 Instruction:"VCMPPH rK{K},aKq,Hfv,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 892, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1463 Instruction:"VCMPPS rKq{K},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPPS, ND_CAT_AVX512, ND_SET_AVX512F, 893, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1464 Instruction:"VCMPPS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:0 l:i w:i 0xC2 /r ib"/"RVMI" - { - ND_INS_VCMPPS, ND_CAT_AVX, ND_SET_AVX, 893, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1465 Instruction:"VCMPSD rKq{K},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:1 p:3 l:x w:1 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPSD, ND_CAT_AVX512, ND_SET_AVX512F, 894, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1466 Instruction:"VCMPSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:1 p:3 l:i w:i 0xC2 /r ib"/"RVMI" - { - ND_INS_VCMPSD, ND_CAT_AVX, ND_SET_AVX, 894, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1467 Instruction:"VCMPSH rK{K},aKq,Hfv,Wsh{sae},Ib" Encoding:"evex m:3 p:2 l:i w:0 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 895, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1468 Instruction:"VCMPSS rKq{K},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:1 p:2 l:x w:0 0xC2 /r ib"/"RAVMI" - { - ND_INS_VCMPSS, ND_CAT_AVX512, ND_SET_AVX512F, 896, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1469 Instruction:"VCMPSS Vss,Hss,Wss,Ib" Encoding:"vex m:1 p:2 l:i w:i 0xC2 /r ib"/"RVMI" - { - ND_INS_VCMPSS, ND_CAT_AVX, ND_SET_AVX, 896, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1470 Instruction:"VCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2F /r"/"RM" - { - ND_INS_VCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 897, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1471 Instruction:"VCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2F /r"/"RM" - { - ND_INS_VCOMISD, ND_CAT_AVX, ND_SET_AVX, 897, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1472 Instruction:"VCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2F /r"/"RM" - { - ND_INS_VCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 898, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1473 Instruction:"VCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2F /r"/"RM" - { - ND_INS_VCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 899, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1474 Instruction:"VCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2F /r"/"RM" - { - ND_INS_VCOMISS, ND_CAT_AVX, ND_SET_AVX, 899, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1475 Instruction:"VCOMPRESSPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8A /r"/"MAR" - { - ND_INS_VCOMPRESSPD, ND_CAT_COMPRESS, ND_SET_AVX512F, 900, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1476 Instruction:"VCOMPRESSPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8A /r"/"MAR" - { - ND_INS_VCOMPRESSPS, ND_CAT_COMPRESS, ND_SET_AVX512F, 901, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1477 Instruction:"VCVTDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0xE6 /r"/"RAM" - { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 902, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1478 Instruction:"VCVTDQ2PD Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0xE6 /r"/"RM" - { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1479 Instruction:"VCVTDQ2PD Vqq,Wdq" Encoding:"vex m:1 p:2 l:1 w:i 0xE6 /r"/"RM" - { - ND_INS_VCVTDQ2PD, ND_CAT_CONVERT, ND_SET_AVX, 902, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1480 Instruction:"VCVTDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 903, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1481 Instruction:"VCVTDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 904, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1482 Instruction:"VCVTDQ2PS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5B /r"/"RM" - { - ND_INS_VCVTDQ2PS, ND_CAT_CONVERT, ND_SET_AVX, 904, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1483 Instruction:"VCVTNE2PS2BF16 Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x72 /r"/"RAVM" - { - ND_INS_VCVTNE2PS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 905, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1484 Instruction:"VCVTNEEBF162PS Vx,Mx" Encoding:"vex m:2 p:2 l:x w:0 0xB0 /r:mem"/"RM" - { - ND_INS_VCVTNEEBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 906, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1485 Instruction:"VCVTNEEPH2PS Vx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0xB0 /r:mem"/"RM" - { - ND_INS_VCVTNEEPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 907, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1486 Instruction:"VCVTNEOBF162PS Vx,Mx" Encoding:"vex m:2 p:3 l:x w:0 0xB0 /r:mem"/"RM" - { - ND_INS_VCVTNEOBF162PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 908, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1487 Instruction:"VCVTNEOPH2PS Vx,Mx" Encoding:"vex m:2 p:0 l:x w:0 0xB0 /r:mem"/"RM" - { - ND_INS_VCVTNEOPH2PS, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 909, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1488 Instruction:"VCVTNEPS2BF16 Vhv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x72 /r"/"RAM" - { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 910, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1489 Instruction:"VCVTNEPS2BF16 Vx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x72 /r"/"RM" - { - ND_INS_VCVTNEPS2BF16, ND_CAT_AVXNECONVERT, ND_SET_AVXNECONVERT, 910, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXNECONVERT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1490 Instruction:"VCVTPD2DQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0xE6 /r"/"RAM" - { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 911, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1491 Instruction:"VCVTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:3 l:x w:i 0xE6 /r"/"RM" - { - ND_INS_VCVTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 911, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1492 Instruction:"VCVTPD2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:1 l:x w:1 0x5A /r"/"RAM" - { - ND_INS_VCVTPD2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 912, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1493 Instruction:"VCVTPD2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5A /r"/"RAM" - { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 913, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1494 Instruction:"VCVTPD2PS Vdq,Wdq" Encoding:"vex m:1 p:1 l:0 w:i 0x5A /r"/"RM" - { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1495 Instruction:"VCVTPD2PS Vdq,Wqq" Encoding:"vex m:1 p:1 l:1 w:i 0x5A /r"/"RM" - { - ND_INS_VCVTPD2PS, ND_CAT_CONVERT, ND_SET_AVX, 913, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1496 Instruction:"VCVTPD2QQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x7B /r"/"RAM" - { - ND_INS_VCVTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 914, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1497 Instruction:"VCVTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x79 /r"/"RAM" - { - ND_INS_VCVTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 915, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1498 Instruction:"VCVTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x79 /r"/"RAM" - { - ND_INS_VCVTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 916, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1499 Instruction:"VCVTPH2DQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 917, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1500 Instruction:"VCVTPH2PD Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5A /r"/"RAM" - { - ND_INS_VCVTPH2PD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 918, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1501 Instruction:"VCVTPH2PS Vfv{K}{z},aKq,Whv{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x13 /r"/"RAM" - { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 919, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1502 Instruction:"VCVTPH2PS Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:0 0x13 /r"/"RM" - { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1503 Instruction:"VCVTPH2PS Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:0 0x13 /r"/"RM" - { - ND_INS_VCVTPH2PS, ND_CAT_CONVERT, ND_SET_F16C, 919, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1504 Instruction:"VCVTPH2PSX Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x13 /r"/"RAM" - { - ND_INS_VCVTPH2PSX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 920, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1505 Instruction:"VCVTPH2QQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7B /r"/"RAM" - { - ND_INS_VCVTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 921, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1506 Instruction:"VCVTPH2UDQ Vfv{K}{z},aKq,Whv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x79 /r"/"RAM" - { - ND_INS_VCVTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 922, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1507 Instruction:"VCVTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x79 /r"/"RAM" - { - ND_INS_VCVTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 923, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1508 Instruction:"VCVTPH2UW Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x7D /r"/"RAM" - { - ND_INS_VCVTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 924, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1509 Instruction:"VCVTPH2W Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:1 l:x w:0 0x7D /r"/"RAM" - { - ND_INS_VCVTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 925, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1510 Instruction:"VCVTPS2DQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 926, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1511 Instruction:"VCVTPS2DQ Vps,Wps" Encoding:"vex m:1 p:1 l:x w:i 0x5B /r"/"RM" - { - ND_INS_VCVTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 926, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1512 Instruction:"VCVTPS2PD Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5A /r"/"RAM" - { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 927, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1513 Instruction:"VCVTPS2PD Vpd,Wq" Encoding:"vex m:1 p:0 l:0 w:i 0x5A /r"/"RM" - { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1514 Instruction:"VCVTPS2PD Vqq,Wdq" Encoding:"vex m:1 p:0 l:1 w:i 0x5A /r"/"RM" - { - ND_INS_VCVTPS2PD, ND_CAT_CONVERT, ND_SET_AVX, 927, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1515 Instruction:"VCVTPS2PH Whv{K}{z},aKq,Vfv{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1D /r ib"/"MARI" - { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_AVX512F, 928, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_HVM, ND_EXT_E11, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1516 Instruction:"VCVTPS2PH Wq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x1D /r ib"/"MRI" - { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1517 Instruction:"VCVTPS2PH Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x1D /r ib"/"MRI" - { - ND_INS_VCVTPS2PH, ND_CAT_CONVERT, ND_SET_F16C, 928, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_11, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_F16C, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1518 Instruction:"VCVTPS2PHX Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:1 l:x w:0 0x1D /r"/"RAM" - { - ND_INS_VCVTPS2PHX, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 929, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1519 Instruction:"VCVTPS2QQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x7B /r"/"RAM" - { - ND_INS_VCVTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 930, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1520 Instruction:"VCVTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x79 /r"/"RAM" - { - ND_INS_VCVTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 931, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1521 Instruction:"VCVTPS2UQQ Vfv{K}{z},aKq,Whv|B32{er}" Encoding:"evex m:1 p:1 l:x w:0 0x79 /r"/"RAM" - { - ND_INS_VCVTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 932, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1522 Instruction:"VCVTQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0xE6 /r"/"RAM" - { - ND_INS_VCVTQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 933, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1523 Instruction:"VCVTQQ2PH Vdq{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:0 l:x w:1 0x5B /r"/"RAM" - { - ND_INS_VCVTQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 934, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1524 Instruction:"VCVTQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:0 l:x w:1 0x5B /r"/"RAM" - { - ND_INS_VCVTQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 935, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1525 Instruction:"VCVTSD2SH Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:5 p:3 l:i w:1 0x5A /r"/"RAVM" - { - ND_INS_VCVTSD2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 936, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1526 Instruction:"VCVTSD2SI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x2D /r"/"RM" - { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 937, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1527 Instruction:"VCVTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2D /r"/"RM" - { - ND_INS_VCVTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 937, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1528 Instruction:"VCVTSD2SS Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5A /r"/"RAVM" - { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 938, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1529 Instruction:"VCVTSD2SS Vss,Hx,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5A /r"/"RVM" - { - ND_INS_VCVTSD2SS, ND_CAT_CONVERT, ND_SET_AVX, 938, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1530 Instruction:"VCVTSD2USI Gy,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:x 0x79 /r"/"RM" - { - ND_INS_VCVTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 939, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1531 Instruction:"VCVTSH2SD Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5A /r"/"RAVM" - { - ND_INS_VCVTSH2SD, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 940, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1532 Instruction:"VCVTSH2SI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x2D /r"/"RM" - { - ND_INS_VCVTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 941, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1533 Instruction:"VCVTSH2SS Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:0 l:i w:0 0x13 /r"/"RAVM" - { - ND_INS_VCVTSH2SS, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 942, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1534 Instruction:"VCVTSH2USI Gy,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:x 0x79 /r"/"RM" - { - ND_INS_VCVTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 943, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1535 Instruction:"VCVTSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1536 Instruction:"VCVTSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 944, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1537 Instruction:"VCVTSI2SD Vsd,Hsd,Ey" Encoding:"vex m:1 p:3 l:i w:x 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SD, ND_CAT_CONVERT, ND_SET_AVX, 944, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1538 Instruction:"VCVTSI2SH Vdq,Hdq,Ey" Encoding:"evex m:5 p:2 l:i w:x 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 945, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1539 Instruction:"VCVTSI2SS Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 946, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1540 Instruction:"VCVTSI2SS Vss,Hss,Ey" Encoding:"vex m:1 p:2 l:i w:x 0x2A /r"/"RVM" - { - ND_INS_VCVTSI2SS, ND_CAT_CONVERT, ND_SET_AVX, 946, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1541 Instruction:"VCVTSS2SD Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5A /r"/"RAVM" - { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 947, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1542 Instruction:"VCVTSS2SD Vsd,Hx,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5A /r"/"RVM" - { - ND_INS_VCVTSS2SD, ND_CAT_CONVERT, ND_SET_AVX, 947, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1543 Instruction:"VCVTSS2SH Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:5 p:0 l:i w:0 0x1D /r"/"RAVM" - { - ND_INS_VCVTSS2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 948, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1544 Instruction:"VCVTSS2SI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x2D /r"/"RM" - { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 949, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1545 Instruction:"VCVTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2D /r"/"RM" - { - ND_INS_VCVTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 949, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1546 Instruction:"VCVTSS2USI Gy,Wss{er}" Encoding:"evex m:1 p:2 l:i w:x 0x79 /r"/"RM" - { - ND_INS_VCVTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 950, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1547 Instruction:"VCVTTPD2DQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0xE6 /r"/"RAM" - { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 951, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1548 Instruction:"VCVTTPD2DQ Vdq,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE6 /r"/"RM" - { - ND_INS_VCVTTPD2DQ, ND_CAT_CONVERT, ND_SET_AVX, 951, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1549 Instruction:"VCVTTPD2QQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x7A /r"/"RAM" - { - ND_INS_VCVTTPD2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 952, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1550 Instruction:"VCVTTPD2UDQ Vhv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:0 l:x w:1 0x78 /r"/"RAM" - { - ND_INS_VCVTTPD2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 953, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1551 Instruction:"VCVTTPD2UQQ Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x78 /r"/"RAM" - { - ND_INS_VCVTTPD2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 954, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1552 Instruction:"VCVTTPH2DQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:2 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTTPH2DQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 955, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1553 Instruction:"VCVTTPH2QQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7A /r"/"RAM" - { - ND_INS_VCVTTPH2QQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 956, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1554 Instruction:"VCVTTPH2UDQ Vfv{K}{z},aKq,Whv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x78 /r"/"RAM" - { - ND_INS_VCVTTPH2UDQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 957, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1555 Instruction:"VCVTTPH2UQQ Vfv{K}{z},aKq,Wqv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x78 /r"/"RAM" - { - ND_INS_VCVTTPH2UQQ, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 958, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_QV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1556 Instruction:"VCVTTPH2UW Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x7C /r"/"RAM" - { - ND_INS_VCVTTPH2UW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 959, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1557 Instruction:"VCVTTPH2W Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:5 p:1 l:x w:0 0x7C /r"/"RAM" - { - ND_INS_VCVTTPH2W, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 960, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1558 Instruction:"VCVTTPS2DQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:2 l:x w:0 0x5B /r"/"RAM" - { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX512F, 961, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1559 Instruction:"VCVTTPS2DQ Vps,Wps" Encoding:"vex m:1 p:2 l:x w:i 0x5B /r"/"RM" - { - ND_INS_VCVTTPS2DQ, ND_CAT_CONVERT, ND_SET_AVX, 961, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1560 Instruction:"VCVTTPS2QQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x7A /r"/"RAM" - { - ND_INS_VCVTTPS2QQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 962, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1561 Instruction:"VCVTTPS2UDQ Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x78 /r"/"RAM" - { - ND_INS_VCVTTPS2UDQ, ND_CAT_CONVERT, ND_SET_AVX512F, 963, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1562 Instruction:"VCVTTPS2UQQ Vfv{K}{z},aKq,Whv|B32{sae}" Encoding:"evex m:1 p:1 l:x w:0 0x78 /r"/"RAM" - { - ND_INS_VCVTTPS2UQQ, ND_CAT_CONVERT, ND_SET_AVX512DQ, 964, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1563 Instruction:"VCVTTSD2SI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x2C /r"/"RM" - { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 965, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1564 Instruction:"VCVTTSD2SI Gy,Wsd" Encoding:"vex m:1 p:3 l:i w:x 0x2C /r"/"RM" - { - ND_INS_VCVTTSD2SI, ND_CAT_CONVERT, ND_SET_AVX, 965, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1565 Instruction:"VCVTTSD2USI Gy,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:x 0x78 /r"/"RM" - { - ND_INS_VCVTTSD2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 966, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1566 Instruction:"VCVTTSH2SI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:x 0x2C /r"/"RM" - { - ND_INS_VCVTTSH2SI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 967, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1567 Instruction:"VCVTTSH2USI Gy,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x78 /r"/"RM" - { - ND_INS_VCVTTSH2USI, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 968, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1568 Instruction:"VCVTTSS2SI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x2C /r"/"RM" - { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX512F, 969, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1569 Instruction:"VCVTTSS2SI Gy,Wss" Encoding:"vex m:1 p:2 l:i w:x 0x2C /r"/"RM" - { - ND_INS_VCVTTSS2SI, ND_CAT_CONVERT, ND_SET_AVX, 969, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1570 Instruction:"VCVTTSS2USI Gy,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:x 0x78 /r"/"RM" - { - ND_INS_VCVTTSS2USI, ND_CAT_CONVERT, ND_SET_AVX512F, 970, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 0), ND_TUPLE_T1F, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1571 Instruction:"VCVTUDQ2PD Vfv{K}{z},aKq,Whv|B32" Encoding:"evex m:1 p:2 l:x w:0 0x7A /r"/"RAM" - { - ND_INS_VCVTUDQ2PD, ND_CAT_CONVERT, ND_SET_AVX512F, 971, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_HV, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1572 Instruction:"VCVTUDQ2PH Vhv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7A /r"/"RAM" - { - ND_INS_VCVTUDQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 972, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1573 Instruction:"VCVTUDQ2PS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:3 l:x w:0 0x7A /r"/"RAM" - { - ND_INS_VCVTUDQ2PS, ND_CAT_CONVERT, ND_SET_AVX512F, 973, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1574 Instruction:"VCVTUQQ2PD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:2 l:x w:1 0x7A /r"/"RAM" - { - ND_INS_VCVTUQQ2PD, ND_CAT_CONVERT, ND_SET_AVX512DQ, 974, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1575 Instruction:"VCVTUQQ2PH Vqv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:5 p:3 l:x w:1 0x7A /r"/"RAM" - { - ND_INS_VCVTUQQ2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 975, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1576 Instruction:"VCVTUQQ2PS Vhv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:3 l:x w:1 0x7A /r"/"RAM" - { - ND_INS_VCVTUQQ2PS, ND_CAT_CONVERT, ND_SET_AVX512DQ, 976, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1577 Instruction:"VCVTUSI2SD Vdq,Hdq,Ey" Encoding:"evex m:1 p:3 l:i w:0 0x7B /r"/"RVM" - { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IER|ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1578 Instruction:"VCVTUSI2SD Vdq,Hdq{er},Ey" Encoding:"evex m:1 p:3 l:i w:1 0x7B /r"/"RVM" - { - ND_INS_VCVTUSI2SD, ND_CAT_CONVERT, ND_SET_AVX512F, 977, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, ND_OPD_ER, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1579 Instruction:"VCVTUSI2SH Vdq,Hdq,Ey{er}" Encoding:"evex m:5 p:2 l:i w:x 0x7B /r"/"RVM" - { - ND_INS_VCVTUSI2SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 978, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1580 Instruction:"VCVTUSI2SS Vss,Hss{er},Ey" Encoding:"evex m:1 p:2 l:i w:x 0x7B /r"/"RVM" - { - ND_INS_VCVTUSI2SS, ND_CAT_CONVERT, ND_SET_AVX512F, 979, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_ER, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1581 Instruction:"VCVTUW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:3 l:x w:0 0x7D /r"/"RAM" - { - ND_INS_VCVTUW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 980, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1582 Instruction:"VCVTW2PH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:2 l:x w:0 0x7D /r"/"RAM" - { - ND_INS_VCVTW2PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 981, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1583 Instruction:"VDBPSADBW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x42 /r ib"/"RAVMI" - { - ND_INS_VDBPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 982, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1584 Instruction:"VDIVPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5E /r"/"RAVM" - { - ND_INS_VDIVPD, ND_CAT_AVX512, ND_SET_AVX512F, 983, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1585 Instruction:"VDIVPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5E /r"/"RVM" - { - ND_INS_VDIVPD, ND_CAT_AVX, ND_SET_AVX, 983, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1586 Instruction:"VDIVPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x5E /r"/"RAVM" - { - ND_INS_VDIVPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 984, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1587 Instruction:"VDIVPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5E /r"/"RAVM" - { - ND_INS_VDIVPS, ND_CAT_AVX512, ND_SET_AVX512F, 985, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1588 Instruction:"VDIVPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5E /r"/"RVM" - { - ND_INS_VDIVPS, ND_CAT_AVX, ND_SET_AVX, 985, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1589 Instruction:"VDIVSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5E /r"/"RAVM" - { - ND_INS_VDIVSD, ND_CAT_AVX512, ND_SET_AVX512F, 986, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1590 Instruction:"VDIVSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5E /r"/"RVM" - { - ND_INS_VDIVSD, ND_CAT_AVX, ND_SET_AVX, 986, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1591 Instruction:"VDIVSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x5E /r"/"RAVM" - { - ND_INS_VDIVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 987, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1592 Instruction:"VDIVSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5E /r"/"RAVM" - { - ND_INS_VDIVSS, ND_CAT_AVX512, ND_SET_AVX512F, 988, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1593 Instruction:"VDIVSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5E /r"/"RVM" - { - ND_INS_VDIVSS, ND_CAT_AVX, ND_SET_AVX, 988, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1594 Instruction:"VDPBF16PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x52 /r"/"RAVM" - { - ND_INS_VDPBF16PS, ND_CAT_AVX512BF16, ND_SET_AVX512BF16, 989, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BF16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:1595 Instruction:"VDPPD Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x41 /r ib"/"RVMI" - { - ND_INS_VDPPD, ND_CAT_AVX, ND_SET_AVX, 990, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1596 Instruction:"VDPPS Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x40 /r ib"/"RVMI" - { - ND_INS_VDPPS, ND_CAT_AVX, ND_SET_AVX, 991, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1597 Instruction:"VERR Ew" Encoding:"0x0F 0x00 /4"/"M" - { - ND_INS_VERR, ND_CAT_SYSTEM, ND_SET_I286PROT, 992, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1598 Instruction:"VERW Ew" Encoding:"0x0F 0x00 /5"/"M" - { - ND_INS_VERW, ND_CAT_SYSTEM, ND_SET_I286PROT, 993, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1599 Instruction:"VEXP2PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xC8 /r"/"RAM" - { - ND_INS_VEXP2PD, ND_CAT_KNL, ND_SET_AVX512ER, 994, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1600 Instruction:"VEXP2PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xC8 /r"/"RAM" - { - ND_INS_VEXP2PS, ND_CAT_KNL, ND_SET_AVX512ER, 995, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1601 Instruction:"VEXPANDPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x88 /r"/"RAM" - { - ND_INS_VEXPANDPD, ND_CAT_EXPAND, ND_SET_AVX512F, 996, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1602 Instruction:"VEXPANDPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x88 /r"/"RAM" - { - ND_INS_VEXPANDPS, ND_CAT_EXPAND, ND_SET_AVX512F, 997, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1603 Instruction:"VEXTRACTF128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x19 /r ib"/"MRI" - { - ND_INS_VEXTRACTF128, ND_CAT_AVX, ND_SET_AVX, 998, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1604 Instruction:"VEXTRACTF32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x19 /r ib"/"MARI" - { - ND_INS_VEXTRACTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 999, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1605 Instruction:"VEXTRACTF32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1B /r ib"/"MARI" - { - ND_INS_VEXTRACTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1000, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1606 Instruction:"VEXTRACTF64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x19 /r ib"/"MARI" - { - ND_INS_VEXTRACTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1001, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1607 Instruction:"VEXTRACTF64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1B /r ib"/"MARI" - { - ND_INS_VEXTRACTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1002, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1608 Instruction:"VEXTRACTI128 Wdq,Vqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x39 /r ib"/"MRI" - { - ND_INS_VEXTRACTI128, ND_CAT_AVX2, ND_SET_AVX2, 1003, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1609 Instruction:"VEXTRACTI32X4 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x39 /r ib"/"MARI" - { - ND_INS_VEXTRACTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1004, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1610 Instruction:"VEXTRACTI32X8 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3B /r ib"/"MARI" - { - ND_INS_VEXTRACTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1005, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1611 Instruction:"VEXTRACTI64X2 Wdq{K}{z},aKq,Vuv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x39 /r ib"/"MARI" - { - ND_INS_VEXTRACTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1006, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1612 Instruction:"VEXTRACTI64X4 Wqq{K}{z},aKq,Voq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3B /r ib"/"MARI" - { - ND_INS_VEXTRACTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1007, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1613 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" - { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1614 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" - { - ND_INS_VEXTRACTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1008, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1615 Instruction:"VEXTRACTPS Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:mem ib"/"MRI" - { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1616 Instruction:"VEXTRACTPS Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x17 /r:reg ib"/"MRI" - { - ND_INS_VEXTRACTPS, ND_CAT_AVX, ND_SET_AVX, 1008, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1617 Instruction:"VFCMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0x56 /r"/"RAVM" - { - ND_INS_VFCMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1009, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1618 Instruction:"VFCMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0x57 /r"/"RAVM" - { - ND_INS_VFCMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1010, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1619 Instruction:"VFCMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:3 l:x w:0 0xD6 /r"/"RAVM" - { - ND_INS_VFCMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1011, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1620 Instruction:"VFCMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:3 l:i w:0 0xD7 /r"/"RAVM" - { - ND_INS_VFCMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1012, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1621 Instruction:"VFIXUPIMMPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x54 /r ib"/"RAVMI" - { - ND_INS_VFIXUPIMMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1013, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1622 Instruction:"VFIXUPIMMPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x54 /r ib"/"RAVMI" - { - ND_INS_VFIXUPIMMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1014, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1623 Instruction:"VFIXUPIMMSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x55 /r ib"/"RAVMI" - { - ND_INS_VFIXUPIMMSD, ND_CAT_AVX512, ND_SET_AVX512F, 1015, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1624 Instruction:"VFIXUPIMMSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x55 /r ib"/"RAVMI" - { - ND_INS_VFIXUPIMMSS, ND_CAT_AVX512, ND_SET_AVX512F, 1016, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1625 Instruction:"VFMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x98 /r"/"RAVM" - { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1017, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1626 Instruction:"VFMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x98 /r"/"RVM" - { - ND_INS_VFMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1017, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1627 Instruction:"VFMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x98 /r"/"RAVM" - { - ND_INS_VFMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1018, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1628 Instruction:"VFMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x98 /r"/"RAVM" - { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1019, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1629 Instruction:"VFMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x98 /r"/"RVM" - { - ND_INS_VFMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1019, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1630 Instruction:"VFMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x99 /r"/"RAVM" - { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1020, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1631 Instruction:"VFMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x99 /r"/"RVM" - { - ND_INS_VFMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1020, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1632 Instruction:"VFMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x99 /r"/"RAVM" - { - ND_INS_VFMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1021, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1633 Instruction:"VFMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x99 /r"/"RAVM" - { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1022, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1634 Instruction:"VFMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x99 /r"/"RVM" - { - ND_INS_VFMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1022, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1635 Instruction:"VFMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA8 /r"/"RAVM" - { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1023, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1636 Instruction:"VFMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA8 /r"/"RVM" - { - ND_INS_VFMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1023, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1637 Instruction:"VFMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA8 /r"/"RAVM" - { - ND_INS_VFMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1024, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1638 Instruction:"VFMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA8 /r"/"RAVM" - { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1025, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1639 Instruction:"VFMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA8 /r"/"RVM" - { - ND_INS_VFMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1025, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1640 Instruction:"VFMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xA9 /r"/"RAVM" - { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1026, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1641 Instruction:"VFMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xA9 /r"/"RVM" - { - ND_INS_VFMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1026, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1642 Instruction:"VFMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xA9 /r"/"RAVM" - { - ND_INS_VFMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1027, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1643 Instruction:"VFMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xA9 /r"/"RAVM" - { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1028, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1644 Instruction:"VFMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xA9 /r"/"RVM" - { - ND_INS_VFMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1028, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1645 Instruction:"VFMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB8 /r"/"RAVM" - { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1029, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1646 Instruction:"VFMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB8 /r"/"RVM" - { - ND_INS_VFMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1029, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1647 Instruction:"VFMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB8 /r"/"RAVM" - { - ND_INS_VFMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1030, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1648 Instruction:"VFMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB8 /r"/"RAVM" - { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1031, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1649 Instruction:"VFMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB8 /r"/"RVM" - { - ND_INS_VFMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1031, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1650 Instruction:"VFMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xB9 /r"/"RAVM" - { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1032, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1651 Instruction:"VFMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xB9 /r"/"RVM" - { - ND_INS_VFMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1032, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1652 Instruction:"VFMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xB9 /r"/"RAVM" - { - ND_INS_VFMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1033, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1653 Instruction:"VFMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xB9 /r"/"RAVM" - { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1034, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1654 Instruction:"VFMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xB9 /r"/"RVM" - { - ND_INS_VFMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1034, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1655 Instruction:"VFMADDCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0x56 /r"/"RAVM" - { - ND_INS_VFMADDCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1035, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1656 Instruction:"VFMADDCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0x57 /r"/"RAVM" - { - ND_INS_VFMADDCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1036, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1657 Instruction:"VFMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x69 /r is4"/"RVML" - { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1658 Instruction:"VFMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x69 /r is4"/"RVLM" - { - ND_INS_VFMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1037, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1659 Instruction:"VFMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x68 /r is4"/"RVML" - { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1660 Instruction:"VFMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x68 /r is4"/"RVLM" - { - ND_INS_VFMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1038, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1661 Instruction:"VFMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6B /r is4"/"RVML" - { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1662 Instruction:"VFMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6B /r is4"/"RVLM" - { - ND_INS_VFMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1039, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1663 Instruction:"VFMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6A /r is4"/"RVML" - { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1664 Instruction:"VFMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6A /r is4"/"RVLM" - { - ND_INS_VFMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1040, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1665 Instruction:"VFMADDSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x96 /r"/"RAVM" - { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1041, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1666 Instruction:"VFMADDSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x96 /r"/"RVM" - { - ND_INS_VFMADDSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1041, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1667 Instruction:"VFMADDSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x96 /r"/"RAVM" - { - ND_INS_VFMADDSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1042, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1668 Instruction:"VFMADDSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x96 /r"/"RAVM" - { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1043, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1669 Instruction:"VFMADDSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x96 /r"/"RVM" - { - ND_INS_VFMADDSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1043, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1670 Instruction:"VFMADDSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA6 /r"/"RAVM" - { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1044, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1671 Instruction:"VFMADDSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA6 /r"/"RVM" - { - ND_INS_VFMADDSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1044, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1672 Instruction:"VFMADDSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA6 /r"/"RAVM" - { - ND_INS_VFMADDSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1045, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1673 Instruction:"VFMADDSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA6 /r"/"RAVM" - { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1046, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1674 Instruction:"VFMADDSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA6 /r"/"RVM" - { - ND_INS_VFMADDSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1046, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1675 Instruction:"VFMADDSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB6 /r"/"RAVM" - { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1047, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1676 Instruction:"VFMADDSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB6 /r"/"RVM" - { - ND_INS_VFMADDSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1047, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1677 Instruction:"VFMADDSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB6 /r"/"RAVM" - { - ND_INS_VFMADDSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1048, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1678 Instruction:"VFMADDSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB6 /r"/"RAVM" - { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1049, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1679 Instruction:"VFMADDSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB6 /r"/"RVM" - { - ND_INS_VFMADDSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1049, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1680 Instruction:"VFMADDSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5D /r is4"/"RVML" - { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1681 Instruction:"VFMADDSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5D /r is4"/"RVLM" - { - ND_INS_VFMADDSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1050, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1682 Instruction:"VFMADDSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5C /r is4"/"RVML" - { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1683 Instruction:"VFMADDSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5C /r is4"/"RVLM" - { - ND_INS_VFMADDSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1051, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1684 Instruction:"VFMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9A /r"/"RAVM" - { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1052, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1685 Instruction:"VFMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9A /r"/"RVM" - { - ND_INS_VFMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1052, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1686 Instruction:"VFMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9A /r"/"RAVM" - { - ND_INS_VFMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1053, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1687 Instruction:"VFMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9A /r"/"RAVM" - { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1054, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1688 Instruction:"VFMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9A /r"/"RVM" - { - ND_INS_VFMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1054, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1689 Instruction:"VFMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9B /r"/"RAVM" - { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1055, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1690 Instruction:"VFMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9B /r"/"RVM" - { - ND_INS_VFMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1055, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1691 Instruction:"VFMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9B /r"/"RAVM" - { - ND_INS_VFMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1056, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1692 Instruction:"VFMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9B /r"/"RAVM" - { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1057, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1693 Instruction:"VFMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9B /r"/"RVM" - { - ND_INS_VFMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1057, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1694 Instruction:"VFMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAA /r"/"RAVM" - { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1058, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1695 Instruction:"VFMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAA /r"/"RVM" - { - ND_INS_VFMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1058, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1696 Instruction:"VFMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAA /r"/"RAVM" - { - ND_INS_VFMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1059, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1697 Instruction:"VFMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAA /r"/"RAVM" - { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1060, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1698 Instruction:"VFMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAA /r"/"RVM" - { - ND_INS_VFMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1060, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1699 Instruction:"VFMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAB /r"/"RAVM" - { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1061, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1700 Instruction:"VFMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAB /r"/"RVM" - { - ND_INS_VFMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1061, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1701 Instruction:"VFMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAB /r"/"RAVM" - { - ND_INS_VFMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1062, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1702 Instruction:"VFMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAB /r"/"RAVM" - { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1063, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1703 Instruction:"VFMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAB /r"/"RVM" - { - ND_INS_VFMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1063, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1704 Instruction:"VFMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBA /r"/"RAVM" - { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1064, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1705 Instruction:"VFMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBA /r"/"RVM" - { - ND_INS_VFMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1064, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1706 Instruction:"VFMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBA /r"/"RAVM" - { - ND_INS_VFMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1065, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1707 Instruction:"VFMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBA /r"/"RAVM" - { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1066, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1708 Instruction:"VFMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBA /r"/"RVM" - { - ND_INS_VFMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1066, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1709 Instruction:"VFMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBB /r"/"RAVM" - { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1067, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1710 Instruction:"VFMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBB /r"/"RVM" - { - ND_INS_VFMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1067, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1711 Instruction:"VFMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBB /r"/"RAVM" - { - ND_INS_VFMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1068, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1712 Instruction:"VFMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBB /r"/"RAVM" - { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1069, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1713 Instruction:"VFMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBB /r"/"RVM" - { - ND_INS_VFMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1069, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1714 Instruction:"VFMSUBADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x97 /r"/"RAVM" - { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1070, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1715 Instruction:"VFMSUBADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x97 /r"/"RVM" - { - ND_INS_VFMSUBADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1070, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1716 Instruction:"VFMSUBADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x97 /r"/"RAVM" - { - ND_INS_VFMSUBADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1071, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1717 Instruction:"VFMSUBADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x97 /r"/"RAVM" - { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1072, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1718 Instruction:"VFMSUBADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x97 /r"/"RVM" - { - ND_INS_VFMSUBADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1072, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1719 Instruction:"VFMSUBADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xA7 /r"/"RAVM" - { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1073, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1720 Instruction:"VFMSUBADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xA7 /r"/"RVM" - { - ND_INS_VFMSUBADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1073, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1721 Instruction:"VFMSUBADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xA7 /r"/"RAVM" - { - ND_INS_VFMSUBADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1074, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1722 Instruction:"VFMSUBADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xA7 /r"/"RAVM" - { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1075, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1723 Instruction:"VFMSUBADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xA7 /r"/"RVM" - { - ND_INS_VFMSUBADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1075, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1724 Instruction:"VFMSUBADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xB7 /r"/"RAVM" - { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1076, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1725 Instruction:"VFMSUBADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB7 /r"/"RVM" - { - ND_INS_VFMSUBADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1076, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1726 Instruction:"VFMSUBADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xB7 /r"/"RAVM" - { - ND_INS_VFMSUBADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1077, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1727 Instruction:"VFMSUBADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xB7 /r"/"RAVM" - { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1078, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1728 Instruction:"VFMSUBADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xB7 /r"/"RVM" - { - ND_INS_VFMSUBADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1078, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1729 Instruction:"VFMSUBADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5F /r is4"/"RVML" - { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1730 Instruction:"VFMSUBADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5F /r is4"/"RVLM" - { - ND_INS_VFMSUBADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1079, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1731 Instruction:"VFMSUBADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x5E /r is4"/"RVML" - { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1732 Instruction:"VFMSUBADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x5E /r is4"/"RVLM" - { - ND_INS_VFMSUBADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1080, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1733 Instruction:"VFMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6D /r is4"/"RVML" - { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1734 Instruction:"VFMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6D /r is4"/"RVLM" - { - ND_INS_VFMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1081, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1735 Instruction:"VFMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x6C /r is4"/"RVML" - { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1736 Instruction:"VFMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x6C /r is4"/"RVLM" - { - ND_INS_VFMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1082, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1737 Instruction:"VFMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6F /r is4"/"RVML" - { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1738 Instruction:"VFMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x6F /r is4"/"RVLM" - { - ND_INS_VFMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1083, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1739 Instruction:"VFMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x6E /r is4"/"RVML" - { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1740 Instruction:"VFMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x6E /r is4"/"RVLM" - { - ND_INS_VFMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1084, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1741 Instruction:"VFMULCPH Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:6 p:2 l:x w:0 0xD6 /r"/"RAVM" - { - ND_INS_VFMULCPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1085, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1742 Instruction:"VFMULCSH Vdq{K}{z},aKq,Hdq,Wd{er}" Encoding:"evex m:6 p:2 l:i w:0 0xD7 /r"/"RAVM" - { - ND_INS_VFMULCSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1086, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10S, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1743 Instruction:"VFNMADD132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9C /r"/"RAVM" - { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1087, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1744 Instruction:"VFNMADD132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9C /r"/"RVM" - { - ND_INS_VFNMADD132PD, ND_CAT_VFMA, ND_SET_FMA, 1087, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1745 Instruction:"VFNMADD132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9C /r"/"RAVM" - { - ND_INS_VFNMADD132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1088, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1746 Instruction:"VFNMADD132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9C /r"/"RAVM" - { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1089, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1747 Instruction:"VFNMADD132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9C /r"/"RVM" - { - ND_INS_VFNMADD132PS, ND_CAT_VFMA, ND_SET_FMA, 1089, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1748 Instruction:"VFNMADD132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9D /r"/"RAVM" - { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1090, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1749 Instruction:"VFNMADD132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9D /r"/"RVM" - { - ND_INS_VFNMADD132SD, ND_CAT_VFMA, ND_SET_FMA, 1090, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1750 Instruction:"VFNMADD132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9D /r"/"RAVM" - { - ND_INS_VFNMADD132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1091, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1751 Instruction:"VFNMADD132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9D /r"/"RAVM" - { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1092, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1752 Instruction:"VFNMADD132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9D /r"/"RVM" - { - ND_INS_VFNMADD132SS, ND_CAT_VFMA, ND_SET_FMA, 1092, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1753 Instruction:"VFNMADD213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAC /r"/"RAVM" - { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1093, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1754 Instruction:"VFNMADD213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAC /r"/"RVM" - { - ND_INS_VFNMADD213PD, ND_CAT_VFMA, ND_SET_FMA, 1093, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1755 Instruction:"VFNMADD213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAC /r"/"RAVM" - { - ND_INS_VFNMADD213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1094, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1756 Instruction:"VFNMADD213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAC /r"/"RAVM" - { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1095, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1757 Instruction:"VFNMADD213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAC /r"/"RVM" - { - ND_INS_VFNMADD213PS, ND_CAT_VFMA, ND_SET_FMA, 1095, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1758 Instruction:"VFNMADD213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAD /r"/"RAVM" - { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1096, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1759 Instruction:"VFNMADD213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAD /r"/"RVM" - { - ND_INS_VFNMADD213SD, ND_CAT_VFMA, ND_SET_FMA, 1096, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1760 Instruction:"VFNMADD213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAD /r"/"RAVM" - { - ND_INS_VFNMADD213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1097, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1761 Instruction:"VFNMADD213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAD /r"/"RAVM" - { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1098, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1762 Instruction:"VFNMADD213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAD /r"/"RVM" - { - ND_INS_VFNMADD213SS, ND_CAT_VFMA, ND_SET_FMA, 1098, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1763 Instruction:"VFNMADD231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBC /r"/"RAVM" - { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1099, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1764 Instruction:"VFNMADD231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBC /r"/"RVM" - { - ND_INS_VFNMADD231PD, ND_CAT_VFMA, ND_SET_FMA, 1099, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1765 Instruction:"VFNMADD231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBC /r"/"RAVM" - { - ND_INS_VFNMADD231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1100, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1766 Instruction:"VFNMADD231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBC /r"/"RAVM" - { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1101, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1767 Instruction:"VFNMADD231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBC /r"/"RVM" - { - ND_INS_VFNMADD231PS, ND_CAT_VFMA, ND_SET_FMA, 1101, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1768 Instruction:"VFNMADD231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBD /r"/"RAVM" - { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1102, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1769 Instruction:"VFNMADD231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBD /r"/"RVM" - { - ND_INS_VFNMADD231SD, ND_CAT_VFMA, ND_SET_FMA, 1102, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1770 Instruction:"VFNMADD231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBD /r"/"RAVM" - { - ND_INS_VFNMADD231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1103, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1771 Instruction:"VFNMADD231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBD /r"/"RAVM" - { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1104, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1772 Instruction:"VFNMADD231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBD /r"/"RVM" - { - ND_INS_VFNMADD231SS, ND_CAT_VFMA, ND_SET_FMA, 1104, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1773 Instruction:"VFNMADDPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x79 /r is4"/"RVML" - { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1774 Instruction:"VFNMADDPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x79 /r is4"/"RVLM" - { - ND_INS_VFNMADDPD, ND_CAT_FMA4, ND_SET_FMA4, 1105, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1775 Instruction:"VFNMADDPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x78 /r is4"/"RVML" - { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1776 Instruction:"VFNMADDPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x78 /r is4"/"RVLM" - { - ND_INS_VFNMADDPS, ND_CAT_FMA4, ND_SET_FMA4, 1106, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1777 Instruction:"VFNMADDSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7B /r is4"/"RVML" - { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1778 Instruction:"VFNMADDSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7B /r is4"/"RVLM" - { - ND_INS_VFNMADDSD, ND_CAT_FMA4, ND_SET_FMA4, 1107, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1779 Instruction:"VFNMADDSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7A /r is4"/"RVML" - { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1780 Instruction:"VFNMADDSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7A /r is4"/"RVLM" - { - ND_INS_VFNMADDSS, ND_CAT_FMA4, ND_SET_FMA4, 1108, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1781 Instruction:"VFNMSUB132PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x9E /r"/"RAVM" - { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_AVX512F, 1109, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1782 Instruction:"VFNMSUB132PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x9E /r"/"RVM" - { - ND_INS_VFNMSUB132PD, ND_CAT_VFMA, ND_SET_FMA, 1109, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1783 Instruction:"VFNMSUB132PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x9E /r"/"RAVM" - { - ND_INS_VFNMSUB132PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1110, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1784 Instruction:"VFNMSUB132PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x9E /r"/"RAVM" - { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_AVX512F, 1111, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1785 Instruction:"VFNMSUB132PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x9E /r"/"RVM" - { - ND_INS_VFNMSUB132PS, ND_CAT_VFMA, ND_SET_FMA, 1111, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1786 Instruction:"VFNMSUB132SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x9F /r"/"RAVM" - { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_AVX512F, 1112, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1787 Instruction:"VFNMSUB132SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0x9F /r"/"RVM" - { - ND_INS_VFNMSUB132SD, ND_CAT_VFMA, ND_SET_FMA, 1112, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1788 Instruction:"VFNMSUB132SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x9F /r"/"RAVM" - { - ND_INS_VFNMSUB132SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1113, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1789 Instruction:"VFNMSUB132SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x9F /r"/"RAVM" - { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_AVX512F, 1114, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1790 Instruction:"VFNMSUB132SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0x9F /r"/"RVM" - { - ND_INS_VFNMSUB132SS, ND_CAT_VFMA, ND_SET_FMA, 1114, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1791 Instruction:"VFNMSUB213PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xAE /r"/"RAVM" - { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_AVX512F, 1115, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1792 Instruction:"VFNMSUB213PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xAE /r"/"RVM" - { - ND_INS_VFNMSUB213PD, ND_CAT_VFMA, ND_SET_FMA, 1115, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1793 Instruction:"VFNMSUB213PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xAE /r"/"RAVM" - { - ND_INS_VFNMSUB213PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1116, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1794 Instruction:"VFNMSUB213PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xAE /r"/"RAVM" - { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_AVX512F, 1117, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1795 Instruction:"VFNMSUB213PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xAE /r"/"RVM" - { - ND_INS_VFNMSUB213PS, ND_CAT_VFMA, ND_SET_FMA, 1117, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1796 Instruction:"VFNMSUB213SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xAF /r"/"RAVM" - { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_AVX512F, 1118, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1797 Instruction:"VFNMSUB213SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xAF /r"/"RVM" - { - ND_INS_VFNMSUB213SD, ND_CAT_VFMA, ND_SET_FMA, 1118, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1798 Instruction:"VFNMSUB213SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xAF /r"/"RAVM" - { - ND_INS_VFNMSUB213SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1119, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1799 Instruction:"VFNMSUB213SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xAF /r"/"RAVM" - { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_AVX512F, 1120, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1800 Instruction:"VFNMSUB213SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xAF /r"/"RVM" - { - ND_INS_VFNMSUB213SS, ND_CAT_VFMA, ND_SET_FMA, 1120, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1801 Instruction:"VFNMSUB231PD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0xBE /r"/"RAVM" - { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_AVX512F, 1121, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:1802 Instruction:"VFNMSUB231PD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xBE /r"/"RVM" - { - ND_INS_VFNMSUB231PD, ND_CAT_VFMA, ND_SET_FMA, 1121, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1803 Instruction:"VFNMSUB231PH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0xBE /r"/"RAVM" - { - ND_INS_VFNMSUB231PH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1122, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:1804 Instruction:"VFNMSUB231PS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0xBE /r"/"RAVM" - { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_AVX512F, 1123, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:1805 Instruction:"VFNMSUB231PS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xBE /r"/"RVM" - { - ND_INS_VFNMSUB231PS, ND_CAT_VFMA, ND_SET_FMA, 1123, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1806 Instruction:"VFNMSUB231SD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0xBF /r"/"RAVM" - { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_AVX512F, 1124, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1807 Instruction:"VFNMSUB231SD Vdq,Hdq,Wsd" Encoding:"vex m:2 p:1 l:i w:1 0xBF /r"/"RVM" - { - ND_INS_VFNMSUB231SD, ND_CAT_VFMA, ND_SET_FMA, 1124, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1808 Instruction:"VFNMSUB231SH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0xBF /r"/"RAVM" - { - ND_INS_VFNMSUB231SH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1125, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1809 Instruction:"VFNMSUB231SS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0xBF /r"/"RAVM" - { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_AVX512F, 1126, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:1810 Instruction:"VFNMSUB231SS Vdq,Hdq,Wss" Encoding:"vex m:2 p:1 l:i w:0 0xBF /r"/"RVM" - { - ND_INS_VFNMSUB231SS, ND_CAT_VFMA, ND_SET_FMA, 1126, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1811 Instruction:"VFNMSUBPD Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7D /r is4"/"RVML" - { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1812 Instruction:"VFNMSUBPD Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7D /r is4"/"RVLM" - { - ND_INS_VFNMSUBPD, ND_CAT_FMA4, ND_SET_FMA4, 1127, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1813 Instruction:"VFNMSUBPS Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x7C /r is4"/"RVML" - { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1814 Instruction:"VFNMSUBPS Vx,Hx,Lx,Wx" Encoding:"vex m:3 p:1 l:x w:1 0x7C /r is4"/"RVLM" - { - ND_INS_VFNMSUBPS, ND_CAT_FMA4, ND_SET_FMA4, 1128, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1815 Instruction:"VFNMSUBSD Vdq,Hdq,Wsd,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7F /r is4"/"RVML" - { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1816 Instruction:"VFNMSUBSD Vdq,Hdq,Ldq,Wsd" Encoding:"vex m:3 p:1 l:x w:1 0x7F /r is4"/"RVLM" - { - ND_INS_VFNMSUBSD, ND_CAT_FMA4, ND_SET_FMA4, 1129, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1817 Instruction:"VFNMSUBSS Vdq,Hdq,Wss,Ldq" Encoding:"vex m:3 p:1 l:x w:0 0x7E /r is4"/"RVML" - { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1818 Instruction:"VFNMSUBSS Vdq,Hdq,Ldq,Wss" Encoding:"vex m:3 p:1 l:x w:1 0x7E /r is4"/"RVLM" - { - ND_INS_VFNMSUBSS, ND_CAT_FMA4, ND_SET_FMA4, 1130, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_FMA4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1819 Instruction:"VFPCLASSPD rKq{K},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x66 /r ib"/"RAMI" - { - ND_INS_VFPCLASSPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1131, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1820 Instruction:"VFPCLASSPH rKq{K},aKq,Wfv|B16,Ib" Encoding:"evex m:3 p:0 l:x w:0 0x66 /r ib"/"RAMI" - { - ND_INS_VFPCLASSPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1132, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1821 Instruction:"VFPCLASSPS rKq{K},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x66 /r ib"/"RAMI" - { - ND_INS_VFPCLASSPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1133, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1822 Instruction:"VFPCLASSSD rKq{K},aKq,Wsd,Ib" Encoding:"evex m:3 p:1 l:i w:1 0x67 /r ib"/"RAMI" - { - ND_INS_VFPCLASSSD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1134, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1823 Instruction:"VFPCLASSSH rKq{K},aKq,Wsh,Ib" Encoding:"evex m:3 p:0 l:i w:0 0x67 /r ib"/"RAMI" - { - ND_INS_VFPCLASSSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1135, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1824 Instruction:"VFPCLASSSS rKq{K},aKq,Wss,Ib" Encoding:"evex m:3 p:1 l:i w:0 0x67 /r ib"/"RAMI" - { - ND_INS_VFPCLASSSS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1136, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1825 Instruction:"VFRCZPD Vx,Wx" Encoding:"xop m:9 0x81 /r"/"RM" - { - ND_INS_VFRCZPD, ND_CAT_XOP, ND_SET_XOP, 1137, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1826 Instruction:"VFRCZPS Vx,Wx" Encoding:"xop m:9 0x80 /r"/"RM" - { - ND_INS_VFRCZPS, ND_CAT_XOP, ND_SET_XOP, 1138, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1827 Instruction:"VFRCZSD Vdq,Wsd" Encoding:"xop m:9 0x83 /r"/"RM" - { - ND_INS_VFRCZSD, ND_CAT_XOP, ND_SET_XOP, 1139, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1828 Instruction:"VFRCZSS Vdq,Wss" Encoding:"xop m:9 0x82 /r"/"RM" - { - ND_INS_VFRCZSS, ND_CAT_XOP, ND_SET_XOP, 1140, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1829 Instruction:"VGATHERDPD Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RAM" - { - ND_INS_VGATHERDPD, ND_CAT_GATHER, ND_SET_AVX512F, 1141, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1830 Instruction:"VGATHERDPD Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x92 /r:mem vsib"/"RMV" - { - ND_INS_VGATHERDPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1141, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1831 Instruction:"VGATHERDPS Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RAM" - { - ND_INS_VGATHERDPS, ND_CAT_GATHER, ND_SET_AVX512F, 1142, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1832 Instruction:"VGATHERDPS Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x92 /r:mem vsib"/"RMV" - { - ND_INS_VGATHERDPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1142, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1833 Instruction:"VGATHERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib"/"MA" - { - ND_INS_VGATHERPF0DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1143, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1834 Instruction:"VGATHERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib"/"MA" - { - ND_INS_VGATHERPF0DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1144, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1835 Instruction:"VGATHERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib"/"MA" - { - ND_INS_VGATHERPF0QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1145, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1836 Instruction:"VGATHERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib"/"MA" - { - ND_INS_VGATHERPF0QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1146, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1837 Instruction:"VGATHERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib"/"MA" - { - ND_INS_VGATHERPF1DPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1147, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1838 Instruction:"VGATHERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib"/"MA" - { - ND_INS_VGATHERPF1DPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1148, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1839 Instruction:"VGATHERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib"/"MA" - { - ND_INS_VGATHERPF1QPD, ND_CAT_GATHER, ND_SET_AVX512PF, 1149, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1840 Instruction:"VGATHERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib"/"MA" - { - ND_INS_VGATHERPF1QPS, ND_CAT_GATHER, ND_SET_AVX512PF, 1150, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1841 Instruction:"VGATHERQPD Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RAM" - { - ND_INS_VGATHERQPD, ND_CAT_GATHER, ND_SET_AVX512F, 1151, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1842 Instruction:"VGATHERQPD Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x93 /r:mem vsib"/"RMV" - { - ND_INS_VGATHERQPD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1151, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1843 Instruction:"VGATHERQPS Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RAM" - { - ND_INS_VGATHERQPS, ND_CAT_GATHER, ND_SET_AVX512F, 1152, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1844 Instruction:"VGATHERQPS Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x93 /r:mem vsib"/"RMV" - { - ND_INS_VGATHERQPS, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1152, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:1845 Instruction:"VGETEXPPD Vfv{K}{z},aKq,Wfv|B64{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x42 /r"/"RAM" - { - ND_INS_VGETEXPPD, ND_CAT_AVX512, ND_SET_AVX512F, 1153, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1846 Instruction:"VGETEXPPH Vfv{K}{z},aKq,Wfv|B16{sae}" Encoding:"evex m:6 p:1 l:x w:0 0x42 /r"/"RAM" - { - ND_INS_VGETEXPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1154, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1847 Instruction:"VGETEXPPS Vfv{K}{z},aKq,Wfv|B32{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x42 /r"/"RAM" - { - ND_INS_VGETEXPPS, ND_CAT_AVX512, ND_SET_AVX512F, 1155, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1848 Instruction:"VGETEXPSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:x w:1 0x43 /r"/"RAVM" - { - ND_INS_VGETEXPSD, ND_CAT_AVX512, ND_SET_AVX512F, 1156, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1849 Instruction:"VGETEXPSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:6 p:1 l:i w:0 0x43 /r"/"RAVM" - { - ND_INS_VGETEXPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1157, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1850 Instruction:"VGETEXPSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:x w:0 0x43 /r"/"RAVM" - { - ND_INS_VGETEXPSS, ND_CAT_AVX512, ND_SET_AVX512F, 1158, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1851 Instruction:"VGETMANTPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x26 /r ib"/"RAMI" - { - ND_INS_VGETMANTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1159, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1852 Instruction:"VGETMANTPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x26 /r ib"/"RAMI" - { - ND_INS_VGETMANTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1160, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1853 Instruction:"VGETMANTPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x26 /r ib"/"RAMI" - { - ND_INS_VGETMANTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1161, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1854 Instruction:"VGETMANTSD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x27 /r ib"/"RAVMI" - { - ND_INS_VGETMANTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1162, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1855 Instruction:"VGETMANTSH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x27 /r ib"/"RAVMI" - { - ND_INS_VGETMANTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1163, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1856 Instruction:"VGETMANTSS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x27 /r ib"/"RAVMI" - { - ND_INS_VGETMANTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1164, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1857 Instruction:"VGF2P8AFFINEINVQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCF /r ib"/"RAVMI" - { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1858 Instruction:"VGF2P8AFFINEINVQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCF /r ib"/"RVMI" - { - ND_INS_VGF2P8AFFINEINVQB, ND_CAT_GFNI, ND_SET_GFNI, 1165, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1859 Instruction:"VGF2P8AFFINEQB Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0xCE /r ib"/"RAVMI" - { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1860 Instruction:"VGF2P8AFFINEQB Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:1 0xCE /r ib"/"RVMI" - { - ND_INS_VGF2P8AFFINEQB, ND_CAT_GFNI, ND_SET_GFNI, 1166, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1861 Instruction:"VGF2P8MULB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0xCF /r"/"RAVM" - { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1862 Instruction:"VGF2P8MULB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xCF /r"/"RVM" - { - ND_INS_VGF2P8MULB, ND_CAT_GFNI, ND_SET_GFNI, 1167, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_GFNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1863 Instruction:"VHADDPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7C /r"/"RVM" - { - ND_INS_VHADDPD, ND_CAT_AVX, ND_SET_AVX, 1168, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1864 Instruction:"VHADDPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7C /r"/"RVM" - { - ND_INS_VHADDPS, ND_CAT_AVX, ND_SET_AVX, 1169, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1865 Instruction:"VHSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x7D /r"/"RVM" - { - ND_INS_VHSUBPD, ND_CAT_AVX, ND_SET_AVX, 1170, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1866 Instruction:"VHSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:3 l:x w:i 0x7D /r"/"RVM" - { - ND_INS_VHSUBPS, ND_CAT_AVX, ND_SET_AVX, 1171, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1867 Instruction:"VINSERTF128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x18 /r ib"/"RVMI" - { - ND_INS_VINSERTF128, ND_CAT_AVX, ND_SET_AVX, 1172, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1868 Instruction:"VINSERTF32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x18 /r ib"/"RAVMI" - { - ND_INS_VINSERTF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1173, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1869 Instruction:"VINSERTF32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x1A /r ib"/"RAVMI" - { - ND_INS_VINSERTF32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1174, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1870 Instruction:"VINSERTF64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x18 /r ib"/"RAVMI" - { - ND_INS_VINSERTF64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1175, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1871 Instruction:"VINSERTF64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x1A /r ib"/"RAVMI" - { - ND_INS_VINSERTF64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1176, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1872 Instruction:"VINSERTI128 Vqq,Hqq,Wdq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x38 /r ib"/"RVMI" - { - ND_INS_VINSERTI128, ND_CAT_AVX2, ND_SET_AVX2, 1177, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1873 Instruction:"VINSERTI32X4 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x38 /r ib"/"RAVMI" - { - ND_INS_VINSERTI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1178, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1874 Instruction:"VINSERTI32X8 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:0 0x3A /r ib"/"RAVMI" - { - ND_INS_VINSERTI32X8, ND_CAT_AVX512, ND_SET_AVX512DQ, 1179, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T8, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1875 Instruction:"VINSERTI64X2 Vuv{K}{z},aKq,Huv,Wdq,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x38 /r ib"/"RAVMI" - { - ND_INS_VINSERTI64X2, ND_CAT_AVX512, ND_SET_AVX512DQ, 1180, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T2, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1876 Instruction:"VINSERTI64X4 Voq{K}{z},aKq,Hoq,Wqq,Ib" Encoding:"evex m:3 p:1 l:2 w:1 0x3A /r ib"/"RAVMI" - { - ND_INS_VINSERTI64X4, ND_CAT_AVX512, ND_SET_AVX512F, 1181, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_T4, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1877 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" - { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1878 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" - { - ND_INS_VINSERTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1182, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1879 Instruction:"VINSERTPS Vdq,Hdq,Md,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:mem ib"/"RVMI" - { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1880 Instruction:"VINSERTPS Vdq,Hdq,Udq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x21 /r:reg ib"/"RVMI" - { - ND_INS_VINSERTPS, ND_CAT_AVX, ND_SET_AVX, 1182, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1881 Instruction:"VLDDQU Vx,Mx" Encoding:"vex m:1 p:3 l:x w:i 0xF0 /r:mem"/"RM" - { - ND_INS_VLDDQU, ND_CAT_AVX, ND_SET_AVX, 1183, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1882 Instruction:"VLDMXCSR Md" Encoding:"vex m:1 p:0 0xAE /2:mem"/"M" - { - ND_INS_VLDMXCSR, ND_CAT_AVX, ND_SET_AVX, 1184, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1883 Instruction:"VMASKMOVDQU Vdq,Udq" Encoding:"vex m:1 p:1 l:0 w:i 0xF7 /r:reg"/"RM" - { - ND_INS_VMASKMOVDQU, ND_CAT_AVX, ND_SET_AVX, 1185, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_rDI, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1884 Instruction:"VMASKMOVPD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2D /r:mem"/"RVM" - { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1885 Instruction:"VMASKMOVPD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2F /r:mem"/"MVR" - { - ND_INS_VMASKMOVPD, ND_CAT_AVX, ND_SET_AVX, 1186, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1886 Instruction:"VMASKMOVPS Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x2C /r:mem"/"RVM" - { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1887 Instruction:"VMASKMOVPS Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x2E /r:mem"/"MVR" - { - ND_INS_VMASKMOVPS, ND_CAT_AVX, ND_SET_AVX, 1187, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1888 Instruction:"VMAXPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5F /r"/"RAVM" - { - ND_INS_VMAXPD, ND_CAT_AVX512, ND_SET_AVX512F, 1188, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1889 Instruction:"VMAXPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5F /r"/"RVM" - { - ND_INS_VMAXPD, ND_CAT_AVX, ND_SET_AVX, 1188, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1890 Instruction:"VMAXPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5F /r"/"RAVM" - { - ND_INS_VMAXPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1189, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1891 Instruction:"VMAXPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5F /r"/"RAVM" - { - ND_INS_VMAXPS, ND_CAT_AVX512, ND_SET_AVX512F, 1190, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1892 Instruction:"VMAXPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5F /r"/"RVM" - { - ND_INS_VMAXPS, ND_CAT_AVX, ND_SET_AVX, 1190, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1893 Instruction:"VMAXSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5F /r"/"RAVM" - { - ND_INS_VMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1191, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1894 Instruction:"VMAXSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5F /r"/"RVM" - { - ND_INS_VMAXSD, ND_CAT_AVX, ND_SET_AVX, 1191, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1895 Instruction:"VMAXSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5F /r"/"RAVM" - { - ND_INS_VMAXSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1192, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1896 Instruction:"VMAXSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5F /r"/"RAVM" - { - ND_INS_VMAXSS, ND_CAT_AVX512, ND_SET_AVX512F, 1193, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1897 Instruction:"VMAXSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5F /r"/"RVM" - { - ND_INS_VMAXSS, ND_CAT_AVX, ND_SET_AVX, 1193, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1898 Instruction:"VMCALL" Encoding:"NP 0x0F 0x01 /0xC1"/"" - { - ND_INS_VMCALL, ND_CAT_VTX, ND_SET_VTX, 1194, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1899 Instruction:"VMCLEAR Mq" Encoding:"0x66 0x0F 0xC7 /6:mem"/"M" - { - ND_INS_VMCLEAR, ND_CAT_VTX, ND_SET_VTX, 1195, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1900 Instruction:"VMFUNC" Encoding:"NP 0x0F 0x01 /0xD4"/"" - { - ND_INS_VMFUNC, ND_CAT_VTX, ND_SET_VTX, 1196, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1901 Instruction:"VMGEXIT" Encoding:"0xF3 0x0F 0x01 /0xD9"/"" - { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1902 Instruction:"VMGEXIT" Encoding:"0xF2 0x0F 0x01 /0xD9"/"" - { - ND_INS_VMGEXIT, ND_CAT_SYSTEM, ND_SET_SVM, 1197, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1903 Instruction:"VMINPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae}" Encoding:"evex m:1 p:1 l:x w:1 0x5D /r"/"RAVM" - { - ND_INS_VMINPD, ND_CAT_AVX512, ND_SET_AVX512F, 1198, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:1904 Instruction:"VMINPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5D /r"/"RVM" - { - ND_INS_VMINPD, ND_CAT_AVX, ND_SET_AVX, 1198, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1905 Instruction:"VMINPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5D /r"/"RAVM" - { - ND_INS_VMINPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1199, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:1906 Instruction:"VMINPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae}" Encoding:"evex m:1 p:0 l:x w:0 0x5D /r"/"RAVM" - { - ND_INS_VMINPS, ND_CAT_AVX512, ND_SET_AVX512F, 1200, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:1907 Instruction:"VMINPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5D /r"/"RVM" - { - ND_INS_VMINPS, ND_CAT_AVX, ND_SET_AVX, 1200, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1908 Instruction:"VMINSD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:1 p:3 l:i w:1 0x5D /r"/"RAVM" - { - ND_INS_VMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1201, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1909 Instruction:"VMINSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5D /r"/"RVM" - { - ND_INS_VMINSD, ND_CAT_AVX, ND_SET_AVX, 1201, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1910 Instruction:"VMINSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5D /r"/"RAVM" - { - ND_INS_VMINSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1202, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1911 Instruction:"VMINSS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:1 p:2 l:i w:0 0x5D /r"/"RAVM" - { - ND_INS_VMINSS, ND_CAT_AVX512, ND_SET_AVX512F, 1203, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:1912 Instruction:"VMINSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5D /r"/"RVM" - { - ND_INS_VMINSS, ND_CAT_AVX, ND_SET_AVX, 1203, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1913 Instruction:"VMLAUNCH" Encoding:"NP 0x0F 0x01 /0xC2"/"" - { - ND_INS_VMLAUNCH, ND_CAT_VTX, ND_SET_VTX, 1204, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:1914 Instruction:"VMLOAD" Encoding:"0x0F 0x01 /0xDA"/"" - { - ND_INS_VMLOAD, ND_CAT_SYSTEM, ND_SET_SVM, 1205, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1915 Instruction:"VMMCALL" Encoding:"0x0F 0x01 /0xD9"/"" - { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1916 Instruction:"VMMCALL" Encoding:"0x66 0x0F 0x01 /0xD9"/"" - { - ND_INS_VMMCALL, ND_CAT_SYSTEM, ND_SET_SVM, 1206, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:1917 Instruction:"VMOVAPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x28 /r"/"RAM" - { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1918 Instruction:"VMOVAPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x29 /r"/"MAR" - { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1207, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1919 Instruction:"VMOVAPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x28 /r"/"RM" - { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1920 Instruction:"VMOVAPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x29 /r"/"MR" - { - ND_INS_VMOVAPD, ND_CAT_DATAXFER, ND_SET_AVX, 1207, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1921 Instruction:"VMOVAPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x28 /r"/"RAM" - { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1922 Instruction:"VMOVAPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x29 /r"/"MAR" - { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1208, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1923 Instruction:"VMOVAPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x28 /r"/"RM" - { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1924 Instruction:"VMOVAPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x29 /r"/"MR" - { - ND_INS_VMOVAPS, ND_CAT_DATAXFER, ND_SET_AVX, 1208, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1925 Instruction:"VMOVD Vdq,Ed" Encoding:"evex m:1 p:1 l:0 w:0 0x6E /r"/"RM" - { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1926 Instruction:"VMOVD Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:0 0x7E /r"/"MR" - { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1209, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1927 Instruction:"VMOVD Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:0 0x6E /r"/"RM" - { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1928 Instruction:"VMOVD Ey,Vd" Encoding:"vex m:1 p:1 l:0 w:0 0x7E /r"/"MR" - { - ND_INS_VMOVD, ND_CAT_DATAXFER, ND_SET_AVX, 1209, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1929 Instruction:"VMOVDDUP Vdq{K}{z},aKq,Wq" Encoding:"evex m:1 p:3 l:0 w:1 0x12 /r"/"RAM" - { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1930 Instruction:"VMOVDDUP Vqq{K}{z},aKq,Wqq" Encoding:"evex m:1 p:3 l:1 w:1 0x12 /r"/"RAM" - { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1931 Instruction:"VMOVDDUP Voq{K}{z},aKq,Woq" Encoding:"evex m:1 p:3 l:2 w:1 0x12 /r"/"RAM" - { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1210, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_DUP, ND_EXT_E5NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1932 Instruction:"VMOVDDUP Vdq,Wq" Encoding:"vex m:1 p:3 l:0 w:i 0x12 /r"/"RM" - { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1933 Instruction:"VMOVDDUP Vqq,Wqq" Encoding:"vex m:1 p:3 l:1 w:i 0x12 /r"/"RM" - { - ND_INS_VMOVDDUP, ND_CAT_DATAXFER, ND_SET_AVX, 1210, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1934 Instruction:"VMOVDQA Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6F /r"/"RM" - { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1935 Instruction:"VMOVDQA Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x7F /r"/"MR" - { - ND_INS_VMOVDQA, ND_CAT_DATAXFER, ND_SET_AVX, 1211, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1936 Instruction:"VMOVDQA32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:0 0x6F /r"/"RAM" - { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1937 Instruction:"VMOVDQA32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0x7F /r"/"MAR" - { - ND_INS_VMOVDQA32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1212, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1938 Instruction:"VMOVDQA64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x6F /r"/"RAM" - { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1939 Instruction:"VMOVDQA64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x7F /r"/"MAR" - { - ND_INS_VMOVDQA64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1213, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E1, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1940 Instruction:"VMOVDQU Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x6F /r"/"RM" - { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1941 Instruction:"VMOVDQU Wx,Vx" Encoding:"vex m:1 p:2 l:x w:i 0x7F /r"/"MR" - { - ND_INS_VMOVDQU, ND_CAT_DATAXFER, ND_SET_AVX, 1214, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1942 Instruction:"VMOVDQU16 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:1 0x6F /r"/"RAM" - { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1943 Instruction:"VMOVDQU16 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:1 0x7F /r"/"MAR" - { - ND_INS_VMOVDQU16, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1215, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1944 Instruction:"VMOVDQU32 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x6F /r"/"RAM" - { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1945 Instruction:"VMOVDQU32 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:0 0x7F /r"/"MAR" - { - ND_INS_VMOVDQU32, ND_CAT_DATAXFER, ND_SET_AVX512F, 1216, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1946 Instruction:"VMOVDQU64 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:1 0x6F /r"/"RAM" - { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1947 Instruction:"VMOVDQU64 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:2 l:x w:1 0x7F /r"/"MAR" - { - ND_INS_VMOVDQU64, ND_CAT_DATAXFER, ND_SET_AVX512F, 1217, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1948 Instruction:"VMOVDQU8 Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:3 l:x w:0 0x6F /r"/"RAM" - { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1949 Instruction:"VMOVDQU8 Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:3 l:x w:0 0x7F /r"/"MAR" - { - ND_INS_VMOVDQU8, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1218, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1950 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:reg"/"RVM" - { - ND_INS_VMOVHLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1219, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1951 Instruction:"VMOVHLPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:reg"/"RVM" - { - ND_INS_VMOVHLPS, ND_CAT_AVX, ND_SET_AVX, 1219, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1952 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x16 /r:mem"/"RVM" - { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1953 Instruction:"VMOVHPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x17 /r:mem"/"MR" - { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1220, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1954 Instruction:"VMOVHPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x16 /r:mem"/"RVM" - { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1955 Instruction:"VMOVHPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x17 /r:mem"/"MR" - { - ND_INS_VMOVHPD, ND_CAT_DATAXFER, ND_SET_AVX, 1220, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1956 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:mem"/"RVM" - { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1957 Instruction:"VMOVHPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x17 /r:mem"/"MR" - { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1221, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1958 Instruction:"VMOVHPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:mem"/"RVM" - { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1959 Instruction:"VMOVHPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x17 /r:mem"/"MR" - { - ND_INS_VMOVHPS, ND_CAT_DATAXFER, ND_SET_AVX, 1221, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1960 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"evex m:1 p:0 l:0 w:0 0x16 /r:reg"/"RVM" - { - ND_INS_VMOVLHPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1222, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1961 Instruction:"VMOVLHPS Vdq,Hdq,Udq" Encoding:"vex m:1 p:0 l:0 w:i 0x16 /r:reg"/"RVM" - { - ND_INS_VMOVLHPS, ND_CAT_AVX, ND_SET_AVX, 1222, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1962 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"evex m:1 p:1 l:0 w:1 0x12 /r:mem"/"RVM" - { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1963 Instruction:"VMOVLPD Mq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x13 /r:mem"/"MR" - { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1223, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1964 Instruction:"VMOVLPD Vdq,Hdq,Mq" Encoding:"vex m:1 p:1 l:0 w:i 0x12 /r:mem"/"RVM" - { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1965 Instruction:"VMOVLPD Mq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0x13 /r:mem"/"MR" - { - ND_INS_VMOVLPD, ND_CAT_DATAXFER, ND_SET_AVX, 1223, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1966 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"evex m:1 p:0 l:0 w:0 0x12 /r:mem"/"RVM" - { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1967 Instruction:"VMOVLPS Mq,Vdq" Encoding:"evex m:1 p:0 l:0 w:0 0x13 /r:mem"/"MR" - { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1224, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T2, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1968 Instruction:"VMOVLPS Vdq,Hdq,Mq" Encoding:"vex m:1 p:0 l:0 w:i 0x12 /r:mem"/"RVM" - { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1969 Instruction:"VMOVLPS Mq,Vdq" Encoding:"vex m:1 p:0 l:0 w:i 0x13 /r:mem"/"MR" - { - ND_INS_VMOVLPS, ND_CAT_DATAXFER, ND_SET_AVX, 1224, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1970 Instruction:"VMOVMSKPD Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0x50 /r:reg"/"RM" - { - ND_INS_VMOVMSKPD, ND_CAT_DATAXFER, ND_SET_AVX, 1225, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1971 Instruction:"VMOVMSKPS Gy,Ux" Encoding:"vex m:1 p:0 l:x w:i 0x50 /r:reg"/"RM" - { - ND_INS_VMOVMSKPS, ND_CAT_DATAXFER, ND_SET_AVX, 1226, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1972 Instruction:"VMOVNTDQ Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:0 0xE7 /r:mem"/"MR" - { - ND_INS_VMOVNTDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1227, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1973 Instruction:"VMOVNTDQ Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0xE7 /r:mem"/"MR" - { - ND_INS_VMOVNTDQ, ND_CAT_AVX, ND_SET_AVX, 1227, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1974 Instruction:"VMOVNTDQA Vfv,Mfv" Encoding:"evex m:2 p:1 l:x w:0 0x2A /r:mem"/"RM" - { - ND_INS_VMOVNTDQA, ND_CAT_DATAXFER, ND_SET_AVX512F, 1228, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1975 Instruction:"VMOVNTDQA Vx,Mx" Encoding:"vex m:2 p:1 l:x w:i 0x2A /r:mem"/"RM" - { - ND_INS_VMOVNTDQA, ND_CAT_AVX, ND_SET_AVX, 1228, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1976 Instruction:"VMOVNTPD Mfv,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x2B /r:mem"/"MR" - { - ND_INS_VMOVNTPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1229, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1977 Instruction:"VMOVNTPD Mx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x2B /r:mem"/"MR" - { - ND_INS_VMOVNTPD, ND_CAT_AVX, ND_SET_AVX, 1229, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1978 Instruction:"VMOVNTPS Mfv,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x2B /r:mem"/"MR" - { - ND_INS_VMOVNTPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1230, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_FVM, ND_EXT_E1NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1979 Instruction:"VMOVNTPS Mx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x2B /r:mem"/"MR" - { - ND_INS_VMOVNTPS, ND_CAT_AVX, ND_SET_AVX, 1230, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_1, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1980 Instruction:"VMOVQ Vdq,Eq" Encoding:"evex m:1 p:1 l:0 w:1 0x6E /r"/"RM" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1981 Instruction:"VMOVQ Ey,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0x7E /r"/"MR" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1982 Instruction:"VMOVQ Vdq,Wq" Encoding:"evex m:1 p:2 l:0 w:1 0x7E /r"/"RM" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1983 Instruction:"VMOVQ Wq,Vdq" Encoding:"evex m:1 p:1 l:0 w:1 0xD6 /r"/"MR" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1984 Instruction:"VMOVQ Vdq,Ey" Encoding:"vex m:1 p:1 l:0 w:1 0x6E /r"/"RM" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1985 Instruction:"VMOVQ Ey,Vq" Encoding:"vex m:1 p:1 l:0 w:1 0x7E /r"/"MR" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1986 Instruction:"VMOVQ Vdq,Wq" Encoding:"vex m:1 p:2 l:0 w:i 0x7E /r"/"RM" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1987 Instruction:"VMOVQ Wq,Vdq" Encoding:"vex m:1 p:1 l:0 w:i 0xD6 /r"/"MR" - { - ND_INS_VMOVQ, ND_CAT_DATAXFER, ND_SET_AVX, 1231, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1988 Instruction:"VMOVSD Vdq{K}{z},aKq,Msd" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:mem"/"RAM" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1989 Instruction:"VMOVSD Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:3 l:i w:1 0x10 /r:reg"/"RAVM" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1990 Instruction:"VMOVSD Msd{K},aKq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:mem"/"MAR" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1991 Instruction:"VMOVSD Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:3 l:i w:1 0x11 /r:reg"/"MAVR" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1992 Instruction:"VMOVSD Vdq,Hdq,Usd" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:reg"/"RVM" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1993 Instruction:"VMOVSD Vdq,Mq" Encoding:"vex m:1 p:3 l:i w:i 0x10 /r:mem"/"RM" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1994 Instruction:"VMOVSD Usd,Hsd,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:reg"/"MVR" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1995 Instruction:"VMOVSD Mq,Vsd" Encoding:"vex m:1 p:3 l:i w:i 0x11 /r:mem"/"MR" - { - ND_INS_VMOVSD, ND_CAT_DATAXFER, ND_SET_AVX, 1232, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1996 Instruction:"VMOVSH Vdq{K}{z},aKq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:mem"/"RAM" - { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1997 Instruction:"VMOVSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:5 p:2 l:i w:0 0x10 /r:reg"/"RAVM" - { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1998 Instruction:"VMOVSH Wsh{K},aKq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:mem"/"MAR" - { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:1999 Instruction:"VMOVSH Wsh{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:5 p:2 l:i w:0 0x11 /r:reg"/"MAVR" - { - ND_INS_VMOVSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1233, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), 0, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2000 Instruction:"VMOVSHDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x16 /r"/"RAM" - { - ND_INS_VMOVSHDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1234, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2001 Instruction:"VMOVSHDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x16 /r"/"RM" - { - ND_INS_VMOVSHDUP, ND_CAT_AVX, ND_SET_AVX, 1234, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2002 Instruction:"VMOVSLDUP Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:2 l:x w:0 0x12 /r"/"RAM" - { - ND_INS_VMOVSLDUP, ND_CAT_DATAXFER, ND_SET_AVX512F, 1235, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2003 Instruction:"VMOVSLDUP Vx,Wx" Encoding:"vex m:1 p:2 l:x w:i 0x12 /r"/"RM" - { - ND_INS_VMOVSLDUP, ND_CAT_AVX, ND_SET_AVX, 1235, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2004 Instruction:"VMOVSS Vdq{K}{z},aKq,Mss" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:mem"/"RAM" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2005 Instruction:"VMOVSS Vdq{K}{z},aKq,Hdq,Udq" Encoding:"evex m:1 p:2 l:i w:0 0x10 /r:reg"/"RAVM" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2006 Instruction:"VMOVSS Mss{K},aKq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:mem"/"MAR" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2007 Instruction:"VMOVSS Udq{K}{z},aKq,Hdq,Vdq" Encoding:"evex m:1 p:2 l:i w:0 0x11 /r:reg"/"MAVR" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2008 Instruction:"VMOVSS Vdq,Hdq,Uss" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:reg"/"RVM" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2009 Instruction:"VMOVSS Vdq,Md" Encoding:"vex m:1 p:2 l:i w:i 0x10 /r:mem"/"RM" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2010 Instruction:"VMOVSS Uss,Hss,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:reg"/"MVR" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_U, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2011 Instruction:"VMOVSS Md,Vss" Encoding:"vex m:1 p:2 l:i w:i 0x11 /r:mem"/"MR" - { - ND_INS_VMOVSS, ND_CAT_DATAXFER, ND_SET_AVX, 1236, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2012 Instruction:"VMOVUPD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:1 l:x w:1 0x10 /r"/"RAM" - { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2013 Instruction:"VMOVUPD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:1 l:x w:1 0x11 /r"/"MAR" - { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1237, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2014 Instruction:"VMOVUPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x10 /r"/"RM" - { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2015 Instruction:"VMOVUPD Wx,Vx" Encoding:"vex m:1 p:1 l:x w:i 0x11 /r"/"MR" - { - ND_INS_VMOVUPD, ND_CAT_DATAXFER, ND_SET_AVX, 1237, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2016 Instruction:"VMOVUPS Vfv{K}{z},aKq,Wfv" Encoding:"evex m:1 p:0 l:x w:0 0x10 /r"/"RAM" - { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2017 Instruction:"VMOVUPS Wfv{K}{z},aKq,Vfv" Encoding:"evex m:1 p:0 l:x w:0 0x11 /r"/"MAR" - { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX512F, 1238, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2018 Instruction:"VMOVUPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x10 /r"/"RM" - { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2019 Instruction:"VMOVUPS Wx,Vx" Encoding:"vex m:1 p:0 l:x w:i 0x11 /r"/"MR" - { - ND_INS_VMOVUPS, ND_CAT_DATAXFER, ND_SET_AVX, 1238, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2020 Instruction:"VMOVW Vdq,Mw" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:mem"/"RM" - { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2021 Instruction:"VMOVW Vdq,Rd" Encoding:"evex m:5 p:1 l:0 w:i 0x6E /r:reg"/"RM" - { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2022 Instruction:"VMOVW Mw,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:mem"/"MR" - { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2023 Instruction:"VMOVW Rd,Vdq" Encoding:"evex m:5 p:1 l:0 w:i 0x7E /r:reg"/"MR" - { - ND_INS_VMOVW, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1239, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2024 Instruction:"VMPSADBW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x42 /r ib"/"RVMI" - { - ND_INS_VMPSADBW, ND_CAT_AVX, ND_SET_AVX, 1240, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2025 Instruction:"VMPTRLD Mq" Encoding:"NP 0x0F 0xC7 /6:mem"/"M" - { - ND_INS_VMPTRLD, ND_CAT_VTX, ND_SET_VTX, 1241, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2026 Instruction:"VMPTRST Mq" Encoding:"NP 0x0F 0xC7 /7:mem"/"M" - { - ND_INS_VMPTRST, ND_CAT_VTX, ND_SET_VTX, 1242, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2027 Instruction:"VMREAD Ey,Gy" Encoding:"NP 0x0F 0x78 /r"/"MR" - { - ND_INS_VMREAD, ND_CAT_VTX, ND_SET_VTX, 1243, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2028 Instruction:"VMRESUME" Encoding:"NP 0x0F 0x01 /0xC3"/"" - { - ND_INS_VMRESUME, ND_CAT_VTX, ND_SET_VTX, 1244, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2029 Instruction:"VMRUN" Encoding:"0x0F 0x01 /0xD8"/"" - { - ND_INS_VMRUN, ND_CAT_SYSTEM, ND_SET_SVM, 1245, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2030 Instruction:"VMSAVE" Encoding:"0x0F 0x01 /0xDB"/"" - { - ND_INS_VMSAVE, ND_CAT_SYSTEM, ND_SET_SVM, 1246, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_SVM, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2031 Instruction:"VMULPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x59 /r"/"RAVM" - { - ND_INS_VMULPD, ND_CAT_AVX512, ND_SET_AVX512F, 1247, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:2032 Instruction:"VMULPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x59 /r"/"RVM" - { - ND_INS_VMULPD, ND_CAT_AVX, ND_SET_AVX, 1247, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2033 Instruction:"VMULPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x59 /r"/"RAVM" - { - ND_INS_VMULPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1248, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:2034 Instruction:"VMULPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x59 /r"/"RAVM" - { - ND_INS_VMULPS, ND_CAT_AVX512, ND_SET_AVX512F, 1249, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:2035 Instruction:"VMULPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x59 /r"/"RVM" - { - ND_INS_VMULPS, ND_CAT_AVX, ND_SET_AVX, 1249, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2036 Instruction:"VMULSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x59 /r"/"RAVM" - { - ND_INS_VMULSD, ND_CAT_AVX512, ND_SET_AVX512F, 1250, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2037 Instruction:"VMULSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x59 /r"/"RVM" - { - ND_INS_VMULSD, ND_CAT_AVX, ND_SET_AVX, 1250, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2038 Instruction:"VMULSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x59 /r"/"RAVM" - { - ND_INS_VMULSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1251, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2039 Instruction:"VMULSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x59 /r"/"RAVM" - { - ND_INS_VMULSS, ND_CAT_AVX512, ND_SET_AVX512F, 1252, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2040 Instruction:"VMULSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x59 /r"/"RVM" - { - ND_INS_VMULSS, ND_CAT_AVX, ND_SET_AVX, 1252, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2041 Instruction:"VMWRITE Gy,Ey" Encoding:"NP 0x0F 0x79 /r"/"RM" - { - ND_INS_VMWRITE, ND_CAT_VTX, ND_SET_VTX, 1253, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_F64|ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2042 Instruction:"VMXOFF" Encoding:"NP 0x0F 0x01 /0xC4"/"" - { - ND_INS_VMXOFF, ND_CAT_VTX, ND_SET_VTX, 1254, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2043 Instruction:"VMXON Mq" Encoding:"0xF3 0x0F 0xC7 /6:mem"/"M" - { - ND_INS_VMXON, ND_CAT_VTX, ND_SET_VTX, 1255, - 0, - ND_MOD_R0|ND_MOD_PROT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXR_SEAM|ND_MOD_SGX_OFF|ND_MOD_TSX_OFF|ND_MOD_SMM_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_VTX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2044 Instruction:"VORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x56 /r"/"RAVM" - { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1256, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2045 Instruction:"VORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x56 /r"/"RVM" - { - ND_INS_VORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1256, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2046 Instruction:"VORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x56 /r"/"RAVM" - { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1257, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2047 Instruction:"VORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x56 /r"/"RVM" - { - ND_INS_VORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1257, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2048 Instruction:"VP2INTERSECTD rKq+1,Hfv,Wfv|B32" Encoding:"evex m:2 p:3 l:x w:0 0x68 /r"/"RVM" - { - ND_INS_VP2INTERSECTD, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1258, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2049 Instruction:"VP2INTERSECTQ rKq+1,Hfv,Wfv|B64" Encoding:"evex m:2 p:3 l:x w:1 0x68 /r"/"RVM" - { - ND_INS_VP2INTERSECTQ, ND_CAT_AVX512VP2INTERSECT, ND_SET_AVX512VP2INTERSECT, 1259, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VP2INTERSECT, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 2), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2050 Instruction:"VP4DPWSSD Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x52 /r:mem"/"RAVM" - { - ND_INS_VP4DPWSSD, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1260, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2051 Instruction:"VP4DPWSSDS Voq{K}{z},aKq,Hoq+3,Mdq" Encoding:"evex m:2 p:3 l:2 w:0 0x53 /r:mem"/"RAVM" - { - ND_INS_VP4DPWSSDS, ND_CAT_VNNIW, ND_SET_AVX5124VNNIW, 1261, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1_4X, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX5124VNNIW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_oq, 0, ND_OPA_R, 0, 4), - OP(ND_OPT_M, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2052 Instruction:"VPABSB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1C /r"/"RAM" - { - ND_INS_VPABSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1262, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2053 Instruction:"VPABSB Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1C /r"/"RM" - { - ND_INS_VPABSB, ND_CAT_AVX, ND_SET_AVX, 1262, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2054 Instruction:"VPABSD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x1E /r"/"RAM" - { - ND_INS_VPABSD, ND_CAT_AVX512, ND_SET_AVX512F, 1263, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2055 Instruction:"VPABSD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1E /r"/"RM" - { - ND_INS_VPABSD, ND_CAT_AVX, ND_SET_AVX, 1263, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2056 Instruction:"VPABSQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x1F /r"/"RAM" - { - ND_INS_VPABSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1264, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2057 Instruction:"VPABSW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:x 0x1D /r"/"RAM" - { - ND_INS_VPABSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1265, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2058 Instruction:"VPABSW Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x1D /r"/"RM" - { - ND_INS_VPABSW, ND_CAT_AVX, ND_SET_AVX, 1265, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2059 Instruction:"VPACKSSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6B /r"/"RAVM" - { - ND_INS_VPACKSSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1266, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2060 Instruction:"VPACKSSDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6B /r"/"RVM" - { - ND_INS_VPACKSSDW, ND_CAT_AVX, ND_SET_AVX, 1266, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2061 Instruction:"VPACKSSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x63 /r"/"RAVM" - { - ND_INS_VPACKSSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1267, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2062 Instruction:"VPACKSSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x63 /r"/"RVM" - { - ND_INS_VPACKSSWB, ND_CAT_AVX, ND_SET_AVX, 1267, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2063 Instruction:"VPACKUSDW Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x2B /r"/"RAVM" - { - ND_INS_VPACKUSDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1268, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2064 Instruction:"VPACKUSDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x2B /r"/"RVM" - { - ND_INS_VPACKUSDW, ND_CAT_AVX, ND_SET_AVX, 1268, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2065 Instruction:"VPACKUSWB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x67 /r"/"RAVM" - { - ND_INS_VPACKUSWB, ND_CAT_AVX512, ND_SET_AVX512BW, 1269, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2066 Instruction:"VPACKUSWB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x67 /r"/"RVM" - { - ND_INS_VPACKUSWB, ND_CAT_AVX, ND_SET_AVX, 1269, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2067 Instruction:"VPADDB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFC /r"/"RAVM" - { - ND_INS_VPADDB, ND_CAT_AVX512, ND_SET_AVX512BW, 1270, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2068 Instruction:"VPADDB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFC /r"/"RVM" - { - ND_INS_VPADDB, ND_CAT_AVX, ND_SET_AVX, 1270, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2069 Instruction:"VPADDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFE /r"/"RAVM" - { - ND_INS_VPADDD, ND_CAT_AVX512, ND_SET_AVX512F, 1271, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2070 Instruction:"VPADDD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFE /r"/"RVM" - { - ND_INS_VPADDD, ND_CAT_AVX, ND_SET_AVX, 1271, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2071 Instruction:"VPADDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xD4 /r"/"RAVM" - { - ND_INS_VPADDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1272, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2072 Instruction:"VPADDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD4 /r"/"RVM" - { - ND_INS_VPADDQ, ND_CAT_AVX, ND_SET_AVX, 1272, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2073 Instruction:"VPADDSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEC /r"/"RAVM" - { - ND_INS_VPADDSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1273, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2074 Instruction:"VPADDSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEC /r"/"RVM" - { - ND_INS_VPADDSB, ND_CAT_AVX, ND_SET_AVX, 1273, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2075 Instruction:"VPADDSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xED /r"/"RAVM" - { - ND_INS_VPADDSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1274, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2076 Instruction:"VPADDSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xED /r"/"RVM" - { - ND_INS_VPADDSW, ND_CAT_AVX, ND_SET_AVX, 1274, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2077 Instruction:"VPADDUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDC /r"/"RAVM" - { - ND_INS_VPADDUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1275, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2078 Instruction:"VPADDUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDC /r"/"RVM" - { - ND_INS_VPADDUSB, ND_CAT_AVX, ND_SET_AVX, 1275, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2079 Instruction:"VPADDUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDD /r"/"RAVM" - { - ND_INS_VPADDUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1276, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2080 Instruction:"VPADDUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDD /r"/"RVM" - { - ND_INS_VPADDUSW, ND_CAT_AVX, ND_SET_AVX, 1276, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2081 Instruction:"VPADDW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xFD /r"/"RAVM" - { - ND_INS_VPADDW, ND_CAT_AVX512, ND_SET_AVX512BW, 1277, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2082 Instruction:"VPADDW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFD /r"/"RVM" - { - ND_INS_VPADDW, ND_CAT_AVX, ND_SET_AVX, 1277, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2083 Instruction:"VPALIGNR Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x0F /r ib"/"RAVMI" - { - ND_INS_VPALIGNR, ND_CAT_AVX512, ND_SET_AVX512BW, 1278, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2084 Instruction:"VPALIGNR Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0F /r ib"/"RVMI" - { - ND_INS_VPALIGNR, ND_CAT_AVX, ND_SET_AVX, 1278, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2085 Instruction:"VPAND Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDB /r"/"RVM" - { - ND_INS_VPAND, ND_CAT_LOGICAL, ND_SET_AVX, 1279, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2086 Instruction:"VPANDD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDB /r"/"RAVM" - { - ND_INS_VPANDD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1280, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2087 Instruction:"VPANDN Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDF /r"/"RVM" - { - ND_INS_VPANDN, ND_CAT_LOGICAL, ND_SET_AVX, 1281, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2088 Instruction:"VPANDND Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xDF /r"/"RAVM" - { - ND_INS_VPANDND, ND_CAT_LOGICAL, ND_SET_AVX512F, 1282, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2089 Instruction:"VPANDNQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDF /r"/"RAVM" - { - ND_INS_VPANDNQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1283, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2090 Instruction:"VPANDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xDB /r"/"RAVM" - { - ND_INS_VPANDQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1284, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2091 Instruction:"VPAVGB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE0 /r"/"RAVM" - { - ND_INS_VPAVGB, ND_CAT_AVX512, ND_SET_AVX512BW, 1285, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2092 Instruction:"VPAVGB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE0 /r"/"RVM" - { - ND_INS_VPAVGB, ND_CAT_AVX, ND_SET_AVX, 1285, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2093 Instruction:"VPAVGW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE3 /r"/"RAVM" - { - ND_INS_VPAVGW, ND_CAT_AVX512, ND_SET_AVX512BW, 1286, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2094 Instruction:"VPAVGW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE3 /r"/"RVM" - { - ND_INS_VPAVGW, ND_CAT_AVX, ND_SET_AVX, 1286, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2095 Instruction:"VPBLENDD Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x02 /r ib"/"RVMI" - { - ND_INS_VPBLENDD, ND_CAT_AVX2, ND_SET_AVX2, 1287, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2096 Instruction:"VPBLENDMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x66 /r"/"RAVM" - { - ND_INS_VPBLENDMB, ND_CAT_BLEND, ND_SET_AVX512BW, 1288, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2097 Instruction:"VPBLENDMD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x64 /r"/"RAVM" - { - ND_INS_VPBLENDMD, ND_CAT_BLEND, ND_SET_AVX512F, 1289, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2098 Instruction:"VPBLENDMQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x64 /r"/"RAVM" - { - ND_INS_VPBLENDMQ, ND_CAT_BLEND, ND_SET_AVX512F, 1290, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2099 Instruction:"VPBLENDMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x66 /r"/"RAVM" - { - ND_INS_VPBLENDMW, ND_CAT_BLEND, ND_SET_AVX512BW, 1291, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2100 Instruction:"VPBLENDVB Vx,Hx,Wx,Lx" Encoding:"vex m:3 p:1 l:x w:0 0x4C /r is4"/"RVML" - { - ND_INS_VPBLENDVB, ND_CAT_AVX, ND_SET_AVX, 1292, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2101 Instruction:"VPBLENDW Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x0E /r ib"/"RVMI" - { - ND_INS_VPBLENDW, ND_CAT_AVX, ND_SET_AVX, 1293, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2102 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Wb" Encoding:"evex m:2 p:1 l:x w:0 0x78 /r"/"RAM" - { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2103 Instruction:"VPBROADCASTB Vfv{K}{z},aKq,Rb" Encoding:"evex m:2 p:1 l:x w:0 0x7A /r:reg"/"RAM" - { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1294, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2104 Instruction:"VPBROADCASTB Vx,Wb" Encoding:"vex m:2 p:1 l:x w:0 0x78 /r"/"RM" - { - ND_INS_VPBROADCASTB, ND_CAT_BROADCAST, ND_SET_AVX2, 1294, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2105 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Wd" Encoding:"evex m:2 p:1 l:x w:0 0x58 /r"/"RAM" - { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2106 Instruction:"VPBROADCASTD Vfv{K}{z},aKq,Rd" Encoding:"evex m:2 p:1 l:x w:0 0x7C /r:reg"/"RAM" - { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX512F, 1295, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2107 Instruction:"VPBROADCASTD Vx,Wd" Encoding:"vex m:2 p:1 l:x w:0 0x58 /r"/"RM" - { - ND_INS_VPBROADCASTD, ND_CAT_BROADCAST, ND_SET_AVX2, 1295, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2108 Instruction:"VPBROADCASTMB2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x2A /r:reg"/"RM" - { - ND_INS_VPBROADCASTMB2Q, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1296, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2109 Instruction:"VPBROADCASTMW2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x3A /r:reg"/"RM" - { - ND_INS_VPBROADCASTMW2D, ND_CAT_BROADCAST, ND_SET_AVX512CD, 1297, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E6NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2110 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Wq" Encoding:"evex m:2 p:1 l:x w:1 0x59 /r"/"RAM" - { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2111 Instruction:"VPBROADCASTQ Vfv{K}{z},aKq,Rq" Encoding:"evex m:2 p:1 l:x w:1 0x7C /r:reg"/"RAM" - { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX512F, 1298, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2112 Instruction:"VPBROADCASTQ Vx,Wq" Encoding:"vex m:2 p:1 l:x w:0 0x59 /r"/"RM" - { - ND_INS_VPBROADCASTQ, ND_CAT_BROADCAST, ND_SET_AVX2, 1298, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2113 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Ww" Encoding:"evex m:2 p:1 l:x w:0 0x79 /r"/"RAM" - { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2114 Instruction:"VPBROADCASTW Vfv{K}{z},aKq,Rw" Encoding:"evex m:2 p:1 l:x w:0 0x7B /r:reg"/"RAM" - { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX512BW, 1299, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2115 Instruction:"VPBROADCASTW Vx,Ww" Encoding:"vex m:2 p:1 l:x w:0 0x79 /r"/"RM" - { - ND_INS_VPBROADCASTW, ND_CAT_BROADCAST, ND_SET_AVX2, 1299, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2116 Instruction:"VPCLMULQDQ Vfv,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" - { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2117 Instruction:"VPCLMULQDQ Vx,Hx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x44 /r ib"/"RVMI" - { - ND_INS_VPCLMULQDQ, ND_CAT_VPCLMULQDQ, ND_SET_VPCLMULQDQ, 1300, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_VPCLMULQDQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2118 Instruction:"VPCMOV Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA2 /r is4"/"RVML" - { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2119 Instruction:"VPCMOV Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA2 /r is4"/"RVLM" - { - ND_INS_VPCMOV, ND_CAT_XOP, ND_SET_XOP, 1301, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2120 Instruction:"VPCMPB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3F /r ib"/"RAVMI" - { - ND_INS_VPCMPB, ND_CAT_AVX512, ND_SET_AVX512BW, 1302, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2121 Instruction:"VPCMPD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1F /r ib"/"RAVMI" - { - ND_INS_VPCMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1303, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2122 Instruction:"VPCMPEQB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x74 /r"/"RAVM" - { - ND_INS_VPCMPEQB, ND_CAT_AVX512, ND_SET_AVX512BW, 1304, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2123 Instruction:"VPCMPEQB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x74 /r"/"RVM" - { - ND_INS_VPCMPEQB, ND_CAT_AVX, ND_SET_AVX, 1304, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2124 Instruction:"VPCMPEQD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:i 0x76 /r"/"RAVM" - { - ND_INS_VPCMPEQD, ND_CAT_AVX512, ND_SET_AVX512F, 1305, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2125 Instruction:"VPCMPEQD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x76 /r"/"RVM" - { - ND_INS_VPCMPEQD, ND_CAT_AVX, ND_SET_AVX, 1305, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2126 Instruction:"VPCMPEQQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x29 /r"/"RAVM" - { - ND_INS_VPCMPEQQ, ND_CAT_AVX512, ND_SET_AVX512F, 1306, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2127 Instruction:"VPCMPEQQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x29 /r"/"RVM" - { - ND_INS_VPCMPEQQ, ND_CAT_AVX, ND_SET_AVX, 1306, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2128 Instruction:"VPCMPEQW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x75 /r"/"RAVM" - { - ND_INS_VPCMPEQW, ND_CAT_AVX512, ND_SET_AVX512BW, 1307, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2129 Instruction:"VPCMPEQW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x75 /r"/"RVM" - { - ND_INS_VPCMPEQW, ND_CAT_AVX, ND_SET_AVX, 1307, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2130 Instruction:"VPCMPESTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x61 /r ib"/"RMI" - { - ND_INS_VPCMPESTRI, ND_CAT_STTNI, ND_SET_AVX, 1308, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2131 Instruction:"VPCMPESTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x60 /r ib"/"RMI" - { - ND_INS_VPCMPESTRM, ND_CAT_STTNI, ND_SET_AVX, 1309, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 4), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2132 Instruction:"VPCMPGTB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x64 /r"/"RAVM" - { - ND_INS_VPCMPGTB, ND_CAT_AVX512, ND_SET_AVX512BW, 1310, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2133 Instruction:"VPCMPGTB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x64 /r"/"RVM" - { - ND_INS_VPCMPGTB, ND_CAT_AVX, ND_SET_AVX, 1310, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2134 Instruction:"VPCMPGTD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x66 /r"/"RAVM" - { - ND_INS_VPCMPGTD, ND_CAT_AVX512, ND_SET_AVX512F, 1311, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2135 Instruction:"VPCMPGTD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x66 /r"/"RVM" - { - ND_INS_VPCMPGTD, ND_CAT_AVX, ND_SET_AVX, 1311, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2136 Instruction:"VPCMPGTQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x37 /r"/"RAVM" - { - ND_INS_VPCMPGTQ, ND_CAT_AVX512, ND_SET_AVX512F, 1312, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2137 Instruction:"VPCMPGTQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x37 /r"/"RVM" - { - ND_INS_VPCMPGTQ, ND_CAT_AVX, ND_SET_AVX, 1312, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2138 Instruction:"VPCMPGTW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x65 /r"/"RAVM" - { - ND_INS_VPCMPGTW, ND_CAT_AVX512, ND_SET_AVX512BW, 1313, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2139 Instruction:"VPCMPGTW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x65 /r"/"RVM" - { - ND_INS_VPCMPGTW, ND_CAT_AVX, ND_SET_AVX, 1313, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2140 Instruction:"VPCMPISTRI Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x63 /r ib"/"RMI" - { - ND_INS_VPCMPISTRI, ND_CAT_STTNI, ND_SET_AVX, 1314, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_y, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2141 Instruction:"VPCMPISTRM Vdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x62 /r ib"/"RMI" - { - ND_INS_VPCMPISTRM, ND_CAT_STTNI, ND_SET_AVX, 1315, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 2), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_SSE_XMM0, ND_OPS_dq, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2142 Instruction:"VPCMPQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1F /r ib"/"RAVMI" - { - ND_INS_VPCMPQ, ND_CAT_AVX512, ND_SET_AVX512F, 1316, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2143 Instruction:"VPCMPUB rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x3E /r ib"/"RAVMI" - { - ND_INS_VPCMPUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1317, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2144 Instruction:"VPCMPUD rKq{K},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x1E /r ib"/"RAVMI" - { - ND_INS_VPCMPUD, ND_CAT_AVX512, ND_SET_AVX512F, 1318, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2145 Instruction:"VPCMPUQ rKq{K},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x1E /r ib"/"RAVMI" - { - ND_INS_VPCMPUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1319, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2146 Instruction:"VPCMPUW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3E /r ib"/"RAVMI" - { - ND_INS_VPCMPUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1320, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2147 Instruction:"VPCMPW rKq{K},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x3F /r ib"/"RAVMI" - { - ND_INS_VPCMPW, ND_CAT_AVX512, ND_SET_AVX512BW, 1321, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2148 Instruction:"VPCOMB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCC /r ib"/"RVMI" - { - ND_INS_VPCOMB, ND_CAT_XOP, ND_SET_XOP, 1322, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2149 Instruction:"VPCOMD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCE /r ib"/"RVMI" - { - ND_INS_VPCOMD, ND_CAT_XOP, ND_SET_XOP, 1323, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2150 Instruction:"VPCOMPRESSB Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x63 /r"/"MAR" - { - ND_INS_VPCOMPRESSB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1324, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2151 Instruction:"VPCOMPRESSD Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0x8B /r"/"MAR" - { - ND_INS_VPCOMPRESSD, ND_CAT_COMPRESS, ND_SET_AVX512F, 1325, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2152 Instruction:"VPCOMPRESSQ Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x8B /r"/"MAR" - { - ND_INS_VPCOMPRESSQ, ND_CAT_COMPRESS, ND_SET_AVX512F, 1326, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2153 Instruction:"VPCOMPRESSW Wfv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0x63 /r"/"MAR" - { - ND_INS_VPCOMPRESSW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1327, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2154 Instruction:"VPCOMQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCF /r ib"/"RVMI" - { - ND_INS_VPCOMQ, ND_CAT_XOP, ND_SET_XOP, 1328, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2155 Instruction:"VPCOMUB Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEC /r ib"/"RVMI" - { - ND_INS_VPCOMUB, ND_CAT_XOP, ND_SET_XOP, 1329, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2156 Instruction:"VPCOMUD Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEE /r ib"/"RVMI" - { - ND_INS_VPCOMUD, ND_CAT_XOP, ND_SET_XOP, 1330, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2157 Instruction:"VPCOMUQ Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xEF /r ib"/"RVMI" - { - ND_INS_VPCOMUQ, ND_CAT_XOP, ND_SET_XOP, 1331, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2158 Instruction:"VPCOMUW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xED /r ib"/"RVMI" - { - ND_INS_VPCOMUW, ND_CAT_XOP, ND_SET_XOP, 1332, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2159 Instruction:"VPCOMW Vdq,Hdq,Wdq,Ib" Encoding:"xop m:8 0xCD /r ib"/"RVMI" - { - ND_INS_VPCOMW, ND_CAT_XOP, ND_SET_XOP, 1333, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2160 Instruction:"VPCONFLICTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0xC4 /r"/"RAM" - { - ND_INS_VPCONFLICTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1334, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2161 Instruction:"VPCONFLICTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xC4 /r"/"RAM" - { - ND_INS_VPCONFLICTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1335, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2162 Instruction:"VPDPBSSD Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x50 /r"/"RVM" - { - ND_INS_VPDPBSSD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1336, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2163 Instruction:"VPDPBSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0x51 /r"/"RVM" - { - ND_INS_VPDPBSSDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1337, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2164 Instruction:"VPDPBSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x50 /r"/"RVM" - { - ND_INS_VPDPBSUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1338, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2165 Instruction:"VPDPBSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0x51 /r"/"RVM" - { - ND_INS_VPDPBSUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1339, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2166 Instruction:"VPDPBUSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x50 /r"/"RAVM" - { - ND_INS_VPDPBUSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1340, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2167 Instruction:"VPDPBUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x50 /r"/"RVM" - { - ND_INS_VPDPBUSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1340, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2168 Instruction:"VPDPBUSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x51 /r"/"RAVM" - { - ND_INS_VPDPBUSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1341, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2169 Instruction:"VPDPBUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x51 /r"/"RVM" - { - ND_INS_VPDPBUSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1341, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2170 Instruction:"VPDPBUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x50 /r"/"RVM" - { - ND_INS_VPDPBUUD, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1342, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2171 Instruction:"VPDPBUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0x51 /r"/"RVM" - { - ND_INS_VPDPBUUDS, ND_CAT_AVXVNNIINT8, ND_SET_AVXVNNIINT8, 1343, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT8, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2172 Instruction:"VPDPWSSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x52 /r"/"RAVM" - { - ND_INS_VPDPWSSD, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1344, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2173 Instruction:"VPDPWSSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x52 /r"/"RVM" - { - ND_INS_VPDPWSSD, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1344, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2174 Instruction:"VPDPWSSDS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x53 /r"/"RAVM" - { - ND_INS_VPDPWSSDS, ND_CAT_VNNI, ND_SET_AVX512VNNI, 1345, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2175 Instruction:"VPDPWSSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x53 /r"/"RVM" - { - ND_INS_VPDPWSSDS, ND_CAT_AVXVNNI, ND_SET_AVXVNNI, 1345, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2176 Instruction:"VPDPWSUD Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD2 /r"/"RVM" - { - ND_INS_VPDPWSUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1346, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2177 Instruction:"VPDPWSUDS Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xD3 /r"/"RVM" - { - ND_INS_VPDPWSUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1347, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2178 Instruction:"VPDPWUSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD2 /r"/"RVM" - { - ND_INS_VPDPWUSD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1348, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2179 Instruction:"VPDPWUSDS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0xD3 /r"/"RVM" - { - ND_INS_VPDPWUSDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1349, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2180 Instruction:"VPDPWUUD Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD2 /r"/"RVM" - { - ND_INS_VPDPWUUD, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1350, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2181 Instruction:"VPDPWUUDS Vx,Hx,Wx" Encoding:"vex m:2 p:0 l:x w:0 0xD3 /r"/"RVM" - { - ND_INS_VPDPWUUDS, ND_CAT_AVXVNNIINT16, ND_SET_AVXVNNIINT16, 1351, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXVNNIINT16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2182 Instruction:"VPERM2F128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x06 /r ib"/"RVMI" - { - ND_INS_VPERM2F128, ND_CAT_AVX, ND_SET_AVX, 1352, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2183 Instruction:"VPERM2I128 Vqq,Hqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:0 0x46 /r ib"/"RVMI" - { - ND_INS_VPERM2I128, ND_CAT_AVX2, ND_SET_AVX2, 1353, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2184 Instruction:"VPERMB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8D /r"/"RAVM" - { - ND_INS_VPERMB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1354, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2185 Instruction:"VPERMD Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x36 /r"/"RAVM" - { - ND_INS_VPERMD, ND_CAT_AVX512, ND_SET_AVX512F, 1355, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2186 Instruction:"VPERMD Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x36 /r"/"RVM" - { - ND_INS_VPERMD, ND_CAT_AVX2, ND_SET_AVX2, 1355, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2187 Instruction:"VPERMI2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x75 /r"/"RAVM" - { - ND_INS_VPERMI2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1356, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2188 Instruction:"VPERMI2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x76 /r"/"RAVM" - { - ND_INS_VPERMI2D, ND_CAT_AVX512, ND_SET_AVX512F, 1357, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2189 Instruction:"VPERMI2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x77 /r"/"RAVM" - { - ND_INS_VPERMI2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1358, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2190 Instruction:"VPERMI2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x77 /r"/"RAVM" - { - ND_INS_VPERMI2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1359, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2191 Instruction:"VPERMI2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x76 /r"/"RAVM" - { - ND_INS_VPERMI2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1360, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2192 Instruction:"VPERMI2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x75 /r"/"RAVM" - { - ND_INS_VPERMI2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1361, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2193 Instruction:"VPERMIL2PD Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x49 /r is4"/"RVML" - { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2194 Instruction:"VPERMIL2PD Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x49 /r is4"/"RVLM" - { - ND_INS_VPERMIL2PD, ND_CAT_XOP, ND_SET_XOP, 1362, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2195 Instruction:"VPERMIL2PS Vx,Hx,Wx,Lx,m2zIb" Encoding:"vex m:3 p:1 l:x w:0 0x48 /r is4"/"RVML" - { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2196 Instruction:"VPERMIL2PS Vx,Hx,Lx,Wx,m2zIb" Encoding:"vex m:3 p:1 l:x w:1 0x48 /r is4"/"RVLM" - { - ND_INS_VPERMIL2PS, ND_CAT_XOP, ND_SET_XOP, 1363, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(5, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_Im2z, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2197 Instruction:"VPERMILPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x0D /r"/"RAVM" - { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2198 Instruction:"VPERMILPD Vfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x05 /r ib"/"RAMI" - { - ND_INS_VPERMILPD, ND_CAT_AVX512, ND_SET_AVX512F, 1364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2199 Instruction:"VPERMILPD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0D /r"/"RVM" - { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2200 Instruction:"VPERMILPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x05 /r ib"/"RMI" - { - ND_INS_VPERMILPD, ND_CAT_AVX, ND_SET_AVX, 1364, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2201 Instruction:"VPERMILPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x0C /r"/"RAVM" - { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2202 Instruction:"VPERMILPS Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x04 /r ib"/"RAMI" - { - ND_INS_VPERMILPS, ND_CAT_AVX512, ND_SET_AVX512F, 1365, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2203 Instruction:"VPERMILPS Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0C /r"/"RVM" - { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2204 Instruction:"VPERMILPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:0 0x04 /r ib"/"RMI" - { - ND_INS_VPERMILPS, ND_CAT_AVX, ND_SET_AVX, 1365, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2205 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:1 w:1 0x16 /r"/"RAVM" - { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2206 Instruction:"VPERMPD Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:2 w:1 0x16 /r"/"RAVM" - { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2207 Instruction:"VPERMPD Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x01 /r ib"/"RAMI" - { - ND_INS_VPERMPD, ND_CAT_AVX512, ND_SET_AVX512F, 1366, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2208 Instruction:"VPERMPD Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x01 /r ib"/"RMI" - { - ND_INS_VPERMPD, ND_CAT_AVX2, ND_SET_AVX2, 1366, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2209 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:1 w:0 0x16 /r"/"RAVM" - { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2210 Instruction:"VPERMPS Vuv{K}{z},aKq,Huv,Wuv|B32" Encoding:"evex m:2 p:1 l:2 w:0 0x16 /r"/"RAVM" - { - ND_INS_VPERMPS, ND_CAT_AVX512, ND_SET_AVX512F, 1367, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2211 Instruction:"VPERMPS Vqq,Hqq,Wqq" Encoding:"vex m:2 p:1 l:1 w:0 0x16 /r"/"RVM" - { - ND_INS_VPERMPS, ND_CAT_AVX2, ND_SET_AVX2, 1367, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2212 Instruction:"VPERMQ Vuv{K}{z},aKq,Huv,Wuv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x36 /r"/"RAVM" - { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2213 Instruction:"VPERMQ Vuv{K}{z},aKq,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x00 /r ib"/"RAMI" - { - ND_INS_VPERMQ, ND_CAT_AVX512, ND_SET_AVX512F, 1368, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2214 Instruction:"VPERMQ Vqq,Wqq,Ib" Encoding:"vex m:3 p:1 l:1 w:1 0x00 /r ib"/"RMI" - { - ND_INS_VPERMQ, ND_CAT_AVX2, ND_SET_AVX2, 1368, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2215 Instruction:"VPERMT2B Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x7D /r"/"RAVM" - { - ND_INS_VPERMT2B, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1369, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2216 Instruction:"VPERMT2D Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7E /r"/"RAVM" - { - ND_INS_VPERMT2D, ND_CAT_AVX512, ND_SET_AVX512F, 1370, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2217 Instruction:"VPERMT2PD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7F /r"/"RAVM" - { - ND_INS_VPERMT2PD, ND_CAT_AVX512, ND_SET_AVX512F, 1371, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2218 Instruction:"VPERMT2PS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x7F /r"/"RAVM" - { - ND_INS_VPERMT2PS, ND_CAT_AVX512, ND_SET_AVX512F, 1372, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2219 Instruction:"VPERMT2Q Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x7E /r"/"RAVM" - { - ND_INS_VPERMT2Q, ND_CAT_AVX512, ND_SET_AVX512F, 1373, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2220 Instruction:"VPERMT2W Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x7D /r"/"RAVM" - { - ND_INS_VPERMT2W, ND_CAT_AVX512, ND_SET_AVX512BW, 1374, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2221 Instruction:"VPERMW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x8D /r"/"RAVM" - { - ND_INS_VPERMW, ND_CAT_AVX512, ND_SET_AVX512BW, 1375, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOMZ|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2222 Instruction:"VPEXPANDB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x62 /r"/"RAM" - { - ND_INS_VPEXPANDB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1376, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2223 Instruction:"VPEXPANDD Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x89 /r"/"RAM" - { - ND_INS_VPEXPANDD, ND_CAT_EXPAND, ND_SET_AVX512F, 1377, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2224 Instruction:"VPEXPANDQ Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x89 /r"/"RAM" - { - ND_INS_VPEXPANDQ, ND_CAT_EXPAND, ND_SET_AVX512F, 1378, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2225 Instruction:"VPEXPANDW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x62 /r"/"RAM" - { - ND_INS_VPEXPANDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1379, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2226 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2227 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1380, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2228 Instruction:"VPEXTRB Mb,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2229 Instruction:"VPEXTRB Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x14 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRB, ND_CAT_AVX, ND_SET_AVX, 1380, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2230 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2231 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1381, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2232 Instruction:"VPEXTRD Md,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2233 Instruction:"VPEXTRD Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x16 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRD, ND_CAT_AVX, ND_SET_AVX, 1381, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_D64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2234 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2235 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1382, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2236 Instruction:"VPEXTRQ Mq,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2237 Instruction:"VPEXTRQ Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x16 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRQ, ND_CAT_AVX, ND_SET_AVX, 1382, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2238 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" - { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2239 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2240 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2241 Instruction:"VPEXTRW Gy,Udq,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib"/"RMI" - { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2242 Instruction:"VPEXTRW Mw,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:mem ib"/"MRI" - { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2243 Instruction:"VPEXTRW Ry,Vdq,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x15 /r:reg ib"/"MRI" - { - ND_INS_VPEXTRW, ND_CAT_AVX, ND_SET_AVX, 1383, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2244 Instruction:"VPGATHERDD Vfv{K},aKq,Mvm32n" Encoding:"evex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RAM" - { - ND_INS_VPGATHERDD, ND_CAT_GATHER, ND_SET_AVX512F, 1384, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2245 Instruction:"VPGATHERDD Vx,Mvm32n,Hx" Encoding:"vex m:2 p:1 l:x w:0 0x90 /r:mem vsib"/"RMV" - { - ND_INS_VPGATHERDD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1384, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2246 Instruction:"VPGATHERDQ Vfv{K},aKq,Mvm32h" Encoding:"evex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RAM" - { - ND_INS_VPGATHERDQ, ND_CAT_GATHER, ND_SET_AVX512F, 1385, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2247 Instruction:"VPGATHERDQ Vx,Mvm32h,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x90 /r:mem vsib"/"RMV" - { - ND_INS_VPGATHERDQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1385, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2248 Instruction:"VPGATHERQD Vhv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RAM" - { - ND_INS_VPGATHERQD, ND_CAT_GATHER, ND_SET_AVX512F, 1386, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2249 Instruction:"VPGATHERQD Vdq,Mvm64n,Hdq" Encoding:"vex m:2 p:1 l:x w:0 0x91 /r:mem vsib"/"RMV" - { - ND_INS_VPGATHERQD, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1386, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2250 Instruction:"VPGATHERQQ Vfv{K},aKq,Mvm64n" Encoding:"evex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RAM" - { - ND_INS_VPGATHERQQ, ND_CAT_GATHER, ND_SET_AVX512F, 1387, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2251 Instruction:"VPGATHERQQ Vx,Mvm64n,Hx" Encoding:"vex m:2 p:1 l:x w:1 0x91 /r:mem vsib"/"RMV" - { - ND_INS_VPGATHERQQ, ND_CAT_AVX2GATHER, ND_SET_AVX2GATHER, 1387, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_12, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_CRW, 0, 0), - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2252 Instruction:"VPHADDBD Vdq,Wdq" Encoding:"xop m:9 0xC2 /r"/"RM" - { - ND_INS_VPHADDBD, ND_CAT_XOP, ND_SET_XOP, 1388, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2253 Instruction:"VPHADDBQ Vdq,Wdq" Encoding:"xop m:9 0xC3 /r"/"RM" - { - ND_INS_VPHADDBQ, ND_CAT_XOP, ND_SET_XOP, 1389, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2254 Instruction:"VPHADDBW Vdq,Wdq" Encoding:"xop m:9 0xC1 /r"/"RM" - { - ND_INS_VPHADDBW, ND_CAT_XOP, ND_SET_XOP, 1390, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2255 Instruction:"VPHADDD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x02 /r"/"RVM" - { - ND_INS_VPHADDD, ND_CAT_AVX, ND_SET_AVX, 1391, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2256 Instruction:"VPHADDDQ Vdq,Wdq" Encoding:"xop m:9 0xCB /r"/"RM" - { - ND_INS_VPHADDDQ, ND_CAT_XOP, ND_SET_XOP, 1392, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2257 Instruction:"VPHADDSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x03 /r"/"RVM" - { - ND_INS_VPHADDSW, ND_CAT_AVX, ND_SET_AVX, 1393, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2258 Instruction:"VPHADDUBD Vdq,Wdq" Encoding:"xop m:9 0xD2 /r"/"RM" - { - ND_INS_VPHADDUBD, ND_CAT_XOP, ND_SET_XOP, 1394, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2259 Instruction:"VPHADDUBQ Vdq,Wdq" Encoding:"xop m:9 0xD3 /r"/"RM" - { - ND_INS_VPHADDUBQ, ND_CAT_XOP, ND_SET_XOP, 1395, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2260 Instruction:"VPHADDUBW Vdq,Wdq" Encoding:"xop m:9 0xD1 /r"/"RM" - { - ND_INS_VPHADDUBW, ND_CAT_XOP, ND_SET_XOP, 1396, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2261 Instruction:"VPHADDUDQ Vdq,Wdq" Encoding:"xop m:9 0xDB /r"/"RM" - { - ND_INS_VPHADDUDQ, ND_CAT_XOP, ND_SET_XOP, 1397, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2262 Instruction:"VPHADDUWD Vdq,Wdq" Encoding:"xop m:9 0xD6 /r"/"RM" - { - ND_INS_VPHADDUWD, ND_CAT_XOP, ND_SET_XOP, 1398, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2263 Instruction:"VPHADDUWQ Vdq,Wdq" Encoding:"xop m:9 0xD7 /r"/"RM" - { - ND_INS_VPHADDUWQ, ND_CAT_XOP, ND_SET_XOP, 1399, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2264 Instruction:"VPHADDW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x01 /r"/"RVM" - { - ND_INS_VPHADDW, ND_CAT_AVX, ND_SET_AVX, 1400, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2265 Instruction:"VPHADDWD Vdq,Wdq" Encoding:"xop m:9 0xC6 /r"/"RM" - { - ND_INS_VPHADDWD, ND_CAT_XOP, ND_SET_XOP, 1401, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2266 Instruction:"VPHADDWQ Vdq,Wdq" Encoding:"xop m:9 0xC7 /r"/"RM" - { - ND_INS_VPHADDWQ, ND_CAT_XOP, ND_SET_XOP, 1402, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2267 Instruction:"VPHMINPOSUW Vdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:i 0x41 /r"/"RM" - { - ND_INS_VPHMINPOSUW, ND_CAT_AVX, ND_SET_AVX, 1403, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2268 Instruction:"VPHSUBBW Vdq,Wdq" Encoding:"xop m:9 0xE1 /r"/"RM" - { - ND_INS_VPHSUBBW, ND_CAT_XOP, ND_SET_XOP, 1404, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2269 Instruction:"VPHSUBD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x06 /r"/"RVM" - { - ND_INS_VPHSUBD, ND_CAT_AVX, ND_SET_AVX, 1405, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2270 Instruction:"VPHSUBDQ Vdq,Wdq" Encoding:"xop m:9 0xE3 /r"/"RM" - { - ND_INS_VPHSUBDQ, ND_CAT_XOP, ND_SET_XOP, 1406, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2271 Instruction:"VPHSUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x07 /r"/"RVM" - { - ND_INS_VPHSUBSW, ND_CAT_AVX, ND_SET_AVX, 1407, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2272 Instruction:"VPHSUBW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x05 /r"/"RVM" - { - ND_INS_VPHSUBW, ND_CAT_AVX, ND_SET_AVX, 1408, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2273 Instruction:"VPHSUBWD Vdq,Wdq" Encoding:"xop m:9 0xE2 /r"/"RM" - { - ND_INS_VPHSUBWD, ND_CAT_XOP, ND_SET_XOP, 1409, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2274 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" - { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2275 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"evex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" - { - ND_INS_VPINSRB, ND_CAT_AVX512, ND_SET_AVX512BW, 1410, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S8, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2276 Instruction:"VPINSRB Vdq,Hdq,Mb,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:mem ib"/"RVMI" - { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2277 Instruction:"VPINSRB Vdq,Hdq,Rd,Ib" Encoding:"vex m:3 p:1 l:0 w:i 0x20 /r:reg ib"/"RVMI" - { - ND_INS_VPINSRB, ND_CAT_AVX, ND_SET_AVX, 1410, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2278 Instruction:"VPINSRD Vdq,Hdq,Ed,Ib" Encoding:"evex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" - { - ND_INS_VPINSRD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1411, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2279 Instruction:"VPINSRD Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0x22 /r ib"/"RVMI" - { - ND_INS_VPINSRD, ND_CAT_AVX, ND_SET_AVX, 1411, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2280 Instruction:"VPINSRQ Vdq,Hdq,Eq,Ib" Encoding:"evex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" - { - ND_INS_VPINSRQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1412, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2281 Instruction:"VPINSRQ Vdq,Hdq,Ey,Ib" Encoding:"vex m:3 p:1 l:0 w:1 0x22 /r ib"/"RVMI" - { - ND_INS_VPINSRQ, ND_CAT_AVX, ND_SET_AVX, 1412, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_IWO64|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_E, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2282 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" - { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2283 Instruction:"VPINSRW Vdq,Hdq,Rv,Ib" Encoding:"evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" - { - ND_INS_VPINSRW, ND_CAT_AVX512, ND_SET_AVX512BW, 1413, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E9NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2284 Instruction:"VPINSRW Vdq,Hdq,Mw,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib"/"RVMI" - { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_w, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2285 Instruction:"VPINSRW Vdq,Hdq,Rd,Ib" Encoding:"vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib"/"RVMI" - { - ND_INS_VPINSRW, ND_CAT_AVX, ND_SET_AVX, 1413, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_R, ND_OPS_d, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2286 Instruction:"VPLZCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x44 /r"/"RAM" - { - ND_INS_VPLZCNTD, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1414, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2287 Instruction:"VPLZCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x44 /r"/"RAM" - { - ND_INS_VPLZCNTQ, ND_CAT_CONFLICT, ND_SET_AVX512CD, 1415, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512CD, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2288 Instruction:"VPMACSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9E /r is4"/"RVML" - { - ND_INS_VPMACSDD, ND_CAT_XOP, ND_SET_XOP, 1416, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2289 Instruction:"VPMACSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x9F /r is4"/"RVML" - { - ND_INS_VPMACSDQH, ND_CAT_XOP, ND_SET_XOP, 1417, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2290 Instruction:"VPMACSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x97 /r is4"/"RVML" - { - ND_INS_VPMACSDQL, ND_CAT_XOP, ND_SET_XOP, 1418, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2291 Instruction:"VPMACSSDD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8E /r is4"/"RVML" - { - ND_INS_VPMACSSDD, ND_CAT_XOP, ND_SET_XOP, 1419, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2292 Instruction:"VPMACSSDQH Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x8F /r is4"/"RVML" - { - ND_INS_VPMACSSDQH, ND_CAT_XOP, ND_SET_XOP, 1420, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2293 Instruction:"VPMACSSDQL Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x87 /r is4"/"RVML" - { - ND_INS_VPMACSSDQL, ND_CAT_XOP, ND_SET_XOP, 1421, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2294 Instruction:"VPMACSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x86 /r is4"/"RVML" - { - ND_INS_VPMACSSWD, ND_CAT_XOP, ND_SET_XOP, 1422, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2295 Instruction:"VPMACSSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x85 /r is4"/"RVML" - { - ND_INS_VPMACSSWW, ND_CAT_XOP, ND_SET_XOP, 1423, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2296 Instruction:"VPMACSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x96 /r is4"/"RVML" - { - ND_INS_VPMACSWD, ND_CAT_XOP, ND_SET_XOP, 1424, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2297 Instruction:"VPMACSWW Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0x95 /r is4"/"RVML" - { - ND_INS_VPMACSWW, ND_CAT_XOP, ND_SET_XOP, 1425, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2298 Instruction:"VPMADCSSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xA6 /r is4"/"RVML" - { - ND_INS_VPMADCSSWD, ND_CAT_XOP, ND_SET_XOP, 1426, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2299 Instruction:"VPMADCSWD Vdq,Hdq,Wdq,Ldq" Encoding:"xop m:8 0xB6 /r is4"/"RVML" - { - ND_INS_VPMADCSWD, ND_CAT_XOP, ND_SET_XOP, 1427, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2300 Instruction:"VPMADD52HUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB5 /r"/"RAVM" - { - ND_INS_VPMADD52HUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1428, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2301 Instruction:"VPMADD52HUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB5 /r"/"RVM" - { - ND_INS_VPMADD52HUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1428, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2302 Instruction:"VPMADD52LUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0xB4 /r"/"RAVM" - { - ND_INS_VPMADD52LUQ, ND_CAT_IFMA, ND_SET_AVX512IFMA, 1429, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512IFMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2303 Instruction:"VPMADD52LUQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0xB4 /r"/"RVM" - { - ND_INS_VPMADD52LUQ, ND_CAT_AVXIFMA, ND_SET_AVXIFMA, 1429, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVXIFMA, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2304 Instruction:"VPMADDUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x04 /r"/"RAVM" - { - ND_INS_VPMADDUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1430, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2305 Instruction:"VPMADDUBSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x04 /r"/"RVM" - { - ND_INS_VPMADDUBSW, ND_CAT_AVX, ND_SET_AVX, 1430, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2306 Instruction:"VPMADDWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF5 /r"/"RAVM" - { - ND_INS_VPMADDWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1431, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2307 Instruction:"VPMADDWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF5 /r"/"RVM" - { - ND_INS_VPMADDWD, ND_CAT_AVX, ND_SET_AVX, 1431, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2308 Instruction:"VPMASKMOVD Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:0 0x8C /r:mem"/"RVM" - { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2309 Instruction:"VPMASKMOVD Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:0 0x8E /r:mem"/"MVR" - { - ND_INS_VPMASKMOVD, ND_CAT_AVX2, ND_SET_AVX2, 1432, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2310 Instruction:"VPMASKMOVQ Vx,Hx,Mx" Encoding:"vex m:2 p:1 l:x w:1 0x8C /r:mem"/"RVM" - { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2311 Instruction:"VPMASKMOVQ Mx,Hx,Vx" Encoding:"vex m:2 p:1 l:x w:1 0x8E /r:mem"/"MVR" - { - ND_INS_VPMASKMOVQ, ND_CAT_AVX2, ND_SET_AVX2, 1433, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2312 Instruction:"VPMAXSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3C /r"/"RAVM" - { - ND_INS_VPMAXSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1434, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2313 Instruction:"VPMAXSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3C /r"/"RVM" - { - ND_INS_VPMAXSB, ND_CAT_AVX, ND_SET_AVX, 1434, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2314 Instruction:"VPMAXSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3D /r"/"RAVM" - { - ND_INS_VPMAXSD, ND_CAT_AVX512, ND_SET_AVX512F, 1435, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2315 Instruction:"VPMAXSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3D /r"/"RVM" - { - ND_INS_VPMAXSD, ND_CAT_AVX, ND_SET_AVX, 1435, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2316 Instruction:"VPMAXSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3D /r"/"RAVM" - { - ND_INS_VPMAXSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1436, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2317 Instruction:"VPMAXSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEE /r"/"RAVM" - { - ND_INS_VPMAXSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1437, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2318 Instruction:"VPMAXSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEE /r"/"RVM" - { - ND_INS_VPMAXSW, ND_CAT_AVX, ND_SET_AVX, 1437, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2319 Instruction:"VPMAXUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDE /r"/"RAVM" - { - ND_INS_VPMAXUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1438, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2320 Instruction:"VPMAXUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDE /r"/"RVM" - { - ND_INS_VPMAXUB, ND_CAT_AVX, ND_SET_AVX, 1438, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2321 Instruction:"VPMAXUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3F /r"/"RAVM" - { - ND_INS_VPMAXUD, ND_CAT_AVX512, ND_SET_AVX512F, 1439, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2322 Instruction:"VPMAXUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3F /r"/"RVM" - { - ND_INS_VPMAXUD, ND_CAT_AVX, ND_SET_AVX, 1439, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2323 Instruction:"VPMAXUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3F /r"/"RAVM" - { - ND_INS_VPMAXUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1440, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2324 Instruction:"VPMAXUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3E /r"/"RAVM" - { - ND_INS_VPMAXUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1441, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2325 Instruction:"VPMAXUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3E /r"/"RVM" - { - ND_INS_VPMAXUW, ND_CAT_AVX, ND_SET_AVX, 1441, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2326 Instruction:"VPMINSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x38 /r"/"RAVM" - { - ND_INS_VPMINSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1442, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2327 Instruction:"VPMINSB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x38 /r"/"RVM" - { - ND_INS_VPMINSB, ND_CAT_AVX, ND_SET_AVX, 1442, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2328 Instruction:"VPMINSD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x39 /r"/"RAVM" - { - ND_INS_VPMINSD, ND_CAT_AVX512, ND_SET_AVX512F, 1443, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2329 Instruction:"VPMINSD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x39 /r"/"RVM" - { - ND_INS_VPMINSD, ND_CAT_AVX, ND_SET_AVX, 1443, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2330 Instruction:"VPMINSQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x39 /r"/"RAVM" - { - ND_INS_VPMINSQ, ND_CAT_AVX512, ND_SET_AVX512F, 1444, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2331 Instruction:"VPMINSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xEA /r"/"RAVM" - { - ND_INS_VPMINSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1445, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2332 Instruction:"VPMINSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEA /r"/"RVM" - { - ND_INS_VPMINSW, ND_CAT_AVX, ND_SET_AVX, 1445, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2333 Instruction:"VPMINUB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xDA /r"/"RAVM" - { - ND_INS_VPMINUB, ND_CAT_AVX512, ND_SET_AVX512BW, 1446, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2334 Instruction:"VPMINUB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xDA /r"/"RVM" - { - ND_INS_VPMINUB, ND_CAT_AVX, ND_SET_AVX, 1446, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2335 Instruction:"VPMINUD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x3B /r"/"RAVM" - { - ND_INS_VPMINUD, ND_CAT_AVX512, ND_SET_AVX512F, 1447, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2336 Instruction:"VPMINUD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3B /r"/"RVM" - { - ND_INS_VPMINUD, ND_CAT_AVX, ND_SET_AVX, 1447, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2337 Instruction:"VPMINUQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x3B /r"/"RAVM" - { - ND_INS_VPMINUQ, ND_CAT_AVX512, ND_SET_AVX512F, 1448, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2338 Instruction:"VPMINUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x3A /r"/"RAVM" - { - ND_INS_VPMINUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1449, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2339 Instruction:"VPMINUW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x3A /r"/"RVM" - { - ND_INS_VPMINUW, ND_CAT_AVX, ND_SET_AVX, 1449, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2340 Instruction:"VPMOVB2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x29 /r:reg"/"RM" - { - ND_INS_VPMOVB2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1450, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2341 Instruction:"VPMOVD2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:0 0x39 /r:reg"/"RM" - { - ND_INS_VPMOVD2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1451, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2342 Instruction:"VPMOVDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x31 /r"/"MAR" - { - ND_INS_VPMOVDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1452, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2343 Instruction:"VPMOVDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x33 /r"/"MAR" - { - ND_INS_VPMOVDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1453, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2344 Instruction:"VPMOVM2B Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x28 /r:reg"/"RM" - { - ND_INS_VPMOVM2B, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1454, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2345 Instruction:"VPMOVM2D Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:0 0x38 /r:reg"/"RM" - { - ND_INS_VPMOVM2D, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1455, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2346 Instruction:"VPMOVM2Q Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x38 /r:reg"/"RM" - { - ND_INS_VPMOVM2Q, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1456, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2347 Instruction:"VPMOVM2W Vfv,mKq" Encoding:"evex m:2 p:2 l:x w:1 0x28 /r:reg"/"RM" - { - ND_INS_VPMOVM2W, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1457, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_mK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2348 Instruction:"VPMOVMSKB Gy,Ux" Encoding:"vex m:1 p:1 l:x w:i 0xD7 /r:reg"/"RM" - { - ND_INS_VPMOVMSKB, ND_CAT_DATAXFER, ND_SET_AVX, 1458, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_D64|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2349 Instruction:"VPMOVQ2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x39 /r:reg"/"RM" - { - ND_INS_VPMOVQ2M, ND_CAT_DATAXFER, ND_SET_AVX512DQ, 1459, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2350 Instruction:"VPMOVQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x32 /r"/"MAR" - { - ND_INS_VPMOVQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1460, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2351 Instruction:"VPMOVQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x35 /r"/"MAR" - { - ND_INS_VPMOVQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1461, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2352 Instruction:"VPMOVQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x34 /r"/"MAR" - { - ND_INS_VPMOVQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1462, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2353 Instruction:"VPMOVSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x21 /r"/"MAR" - { - ND_INS_VPMOVSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1463, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2354 Instruction:"VPMOVSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x23 /r"/"MAR" - { - ND_INS_VPMOVSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1464, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2355 Instruction:"VPMOVSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x22 /r"/"MAR" - { - ND_INS_VPMOVSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1465, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2356 Instruction:"VPMOVSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x25 /r"/"MAR" - { - ND_INS_VPMOVSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1466, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2357 Instruction:"VPMOVSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x24 /r"/"MAR" - { - ND_INS_VPMOVSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1467, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2358 Instruction:"VPMOVSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x20 /r"/"MAR" - { - ND_INS_VPMOVSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1468, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2359 Instruction:"VPMOVSXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x21 /r"/"RAM" - { - ND_INS_VPMOVSXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1469, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2360 Instruction:"VPMOVSXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x21 /r"/"RM" - { - ND_INS_VPMOVSXBD, ND_CAT_AVX, ND_SET_AVX, 1469, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2361 Instruction:"VPMOVSXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x21 /r"/"RM" - { - ND_INS_VPMOVSXBD, ND_CAT_AVX2, ND_SET_AVX2, 1469, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2362 Instruction:"VPMOVSXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x22 /r"/"RAM" - { - ND_INS_VPMOVSXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1470, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2363 Instruction:"VPMOVSXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x22 /r"/"RM" - { - ND_INS_VPMOVSXBQ, ND_CAT_AVX, ND_SET_AVX, 1470, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2364 Instruction:"VPMOVSXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x22 /r"/"RM" - { - ND_INS_VPMOVSXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1470, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2365 Instruction:"VPMOVSXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x20 /r"/"RAM" - { - ND_INS_VPMOVSXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1471, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2366 Instruction:"VPMOVSXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x20 /r"/"RM" - { - ND_INS_VPMOVSXBW, ND_CAT_AVX, ND_SET_AVX, 1471, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2367 Instruction:"VPMOVSXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x20 /r"/"RM" - { - ND_INS_VPMOVSXBW, ND_CAT_AVX2, ND_SET_AVX2, 1471, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2368 Instruction:"VPMOVSXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x25 /r"/"RAM" - { - ND_INS_VPMOVSXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1472, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2369 Instruction:"VPMOVSXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x25 /r"/"RM" - { - ND_INS_VPMOVSXDQ, ND_CAT_AVX, ND_SET_AVX, 1472, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2370 Instruction:"VPMOVSXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x25 /r"/"RM" - { - ND_INS_VPMOVSXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1472, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2371 Instruction:"VPMOVSXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x23 /r"/"RAM" - { - ND_INS_VPMOVSXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1473, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2372 Instruction:"VPMOVSXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x23 /r"/"RM" - { - ND_INS_VPMOVSXWD, ND_CAT_AVX, ND_SET_AVX, 1473, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2373 Instruction:"VPMOVSXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x23 /r"/"RM" - { - ND_INS_VPMOVSXWD, ND_CAT_AVX2, ND_SET_AVX2, 1473, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2374 Instruction:"VPMOVSXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x24 /r"/"RAM" - { - ND_INS_VPMOVSXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1474, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2375 Instruction:"VPMOVSXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x24 /r"/"RM" - { - ND_INS_VPMOVSXWQ, ND_CAT_AVX, ND_SET_AVX, 1474, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2376 Instruction:"VPMOVSXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x24 /r"/"RM" - { - ND_INS_VPMOVSXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1474, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2377 Instruction:"VPMOVUSDB Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x11 /r"/"MAR" - { - ND_INS_VPMOVUSDB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1475, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2378 Instruction:"VPMOVUSDW Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x13 /r"/"MAR" - { - ND_INS_VPMOVUSDW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1476, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2379 Instruction:"VPMOVUSQB Wev{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x12 /r"/"MAR" - { - ND_INS_VPMOVUSQB, ND_CAT_DATAXFER, ND_SET_AVX512F, 1477, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2380 Instruction:"VPMOVUSQD Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x15 /r"/"MAR" - { - ND_INS_VPMOVUSQD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1478, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2381 Instruction:"VPMOVUSQW Wqv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x14 /r"/"MAR" - { - ND_INS_VPMOVUSQW, ND_CAT_DATAXFER, ND_SET_AVX512F, 1479, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2382 Instruction:"VPMOVUSWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x10 /r"/"MAR" - { - ND_INS_VPMOVUSWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1480, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2383 Instruction:"VPMOVW2M rKq,Ufv" Encoding:"evex m:2 p:2 l:x w:1 0x29 /r:reg"/"RM" - { - ND_INS_VPMOVW2M, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1481, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_E7NM, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2384 Instruction:"VPMOVWB Whv{K}{z},aKq,Vfv" Encoding:"evex m:2 p:2 l:x w:0 0x30 /r"/"MAR" - { - ND_INS_VPMOVWB, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1482, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E6, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2385 Instruction:"VPMOVZXBD Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x31 /r"/"RAM" - { - ND_INS_VPMOVZXBD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1483, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2386 Instruction:"VPMOVZXBD Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x31 /r"/"RM" - { - ND_INS_VPMOVZXBD, ND_CAT_AVX, ND_SET_AVX, 1483, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2387 Instruction:"VPMOVZXBD Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x31 /r"/"RM" - { - ND_INS_VPMOVZXBD, ND_CAT_AVX2, ND_SET_AVX2, 1483, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2388 Instruction:"VPMOVZXBQ Vfv{K}{z},aKq,Wev" Encoding:"evex m:2 p:1 l:x w:i 0x32 /r"/"RAM" - { - ND_INS_VPMOVZXBQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1484, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_OVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ev, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2389 Instruction:"VPMOVZXBQ Vdq,Ww" Encoding:"vex m:2 p:1 l:0 w:i 0x32 /r"/"RM" - { - ND_INS_VPMOVZXBQ, ND_CAT_AVX, ND_SET_AVX, 1484, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_w, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2390 Instruction:"VPMOVZXBQ Vqq,Wd" Encoding:"vex m:2 p:1 l:1 w:i 0x32 /r"/"RM" - { - ND_INS_VPMOVZXBQ, ND_CAT_AVX2, ND_SET_AVX2, 1484, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2391 Instruction:"VPMOVZXBW Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x30 /r"/"RAM" - { - ND_INS_VPMOVZXBW, ND_CAT_DATAXFER, ND_SET_AVX512BW, 1485, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2392 Instruction:"VPMOVZXBW Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x30 /r"/"RM" - { - ND_INS_VPMOVZXBW, ND_CAT_AVX, ND_SET_AVX, 1485, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2393 Instruction:"VPMOVZXBW Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x30 /r"/"RM" - { - ND_INS_VPMOVZXBW, ND_CAT_AVX2, ND_SET_AVX2, 1485, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2394 Instruction:"VPMOVZXDQ Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:0 0x35 /r"/"RAM" - { - ND_INS_VPMOVZXDQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1486, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2395 Instruction:"VPMOVZXDQ Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x35 /r"/"RM" - { - ND_INS_VPMOVZXDQ, ND_CAT_AVX, ND_SET_AVX, 1486, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2396 Instruction:"VPMOVZXDQ Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x35 /r"/"RM" - { - ND_INS_VPMOVZXDQ, ND_CAT_AVX2, ND_SET_AVX2, 1486, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2397 Instruction:"VPMOVZXWD Vfv{K}{z},aKq,Whv" Encoding:"evex m:2 p:1 l:x w:i 0x33 /r"/"RAM" - { - ND_INS_VPMOVZXWD, ND_CAT_DATAXFER, ND_SET_AVX512F, 1487, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_HVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_hv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2398 Instruction:"VPMOVZXWD Vdq,Wq" Encoding:"vex m:2 p:1 l:0 w:i 0x33 /r"/"RM" - { - ND_INS_VPMOVZXWD, ND_CAT_AVX, ND_SET_AVX, 1487, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2399 Instruction:"VPMOVZXWD Vqq,Wdq" Encoding:"vex m:2 p:1 l:1 w:i 0x33 /r"/"RM" - { - ND_INS_VPMOVZXWD, ND_CAT_AVX2, ND_SET_AVX2, 1487, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2400 Instruction:"VPMOVZXWQ Vfv{K}{z},aKq,Wqv" Encoding:"evex m:2 p:1 l:x w:i 0x34 /r"/"RAM" - { - ND_INS_VPMOVZXWQ, ND_CAT_DATAXFER, ND_SET_AVX512F, 1488, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_QVM, ND_EXT_E5, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_qv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2401 Instruction:"VPMOVZXWQ Vdq,Wd" Encoding:"vex m:2 p:1 l:0 w:i 0x34 /r"/"RM" - { - ND_INS_VPMOVZXWQ, ND_CAT_AVX, ND_SET_AVX, 1488, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_d, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2402 Instruction:"VPMOVZXWQ Vqq,Wq" Encoding:"vex m:2 p:1 l:1 w:i 0x34 /r"/"RM" - { - ND_INS_VPMOVZXWQ, ND_CAT_AVX2, ND_SET_AVX2, 1488, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2403 Instruction:"VPMULDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x28 /r"/"RAVM" - { - ND_INS_VPMULDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1489, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2404 Instruction:"VPMULDQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x28 /r"/"RVM" - { - ND_INS_VPMULDQ, ND_CAT_AVX, ND_SET_AVX, 1489, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2405 Instruction:"VPMULHRSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x0B /r"/"RAVM" - { - ND_INS_VPMULHRSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1490, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2406 Instruction:"VPMULHRSW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0B /r"/"RVM" - { - ND_INS_VPMULHRSW, ND_CAT_AVX, ND_SET_AVX, 1490, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2407 Instruction:"VPMULHUW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE4 /r"/"RAVM" - { - ND_INS_VPMULHUW, ND_CAT_AVX512, ND_SET_AVX512BW, 1491, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2408 Instruction:"VPMULHUW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE4 /r"/"RVM" - { - ND_INS_VPMULHUW, ND_CAT_AVX, ND_SET_AVX, 1491, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2409 Instruction:"VPMULHW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE5 /r"/"RAVM" - { - ND_INS_VPMULHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1492, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2410 Instruction:"VPMULHW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE5 /r"/"RVM" - { - ND_INS_VPMULHW, ND_CAT_AVX, ND_SET_AVX, 1492, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2411 Instruction:"VPMULLD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x40 /r"/"RAVM" - { - ND_INS_VPMULLD, ND_CAT_AVX512, ND_SET_AVX512F, 1493, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2412 Instruction:"VPMULLD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x40 /r"/"RVM" - { - ND_INS_VPMULLD, ND_CAT_AVX, ND_SET_AVX, 1493, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2413 Instruction:"VPMULLQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x40 /r"/"RAVM" - { - ND_INS_VPMULLQ, ND_CAT_AVX512, ND_SET_AVX512DQ, 1494, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2414 Instruction:"VPMULLW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD5 /r"/"RAVM" - { - ND_INS_VPMULLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1495, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2415 Instruction:"VPMULLW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD5 /r"/"RVM" - { - ND_INS_VPMULLW, ND_CAT_AVX, ND_SET_AVX, 1495, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2416 Instruction:"VPMULTISHIFTQB Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x83 /r"/"RAVM" - { - ND_INS_VPMULTISHIFTQB, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI, 1496, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2417 Instruction:"VPMULUDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xF4 /r"/"RAVM" - { - ND_INS_VPMULUDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1497, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2418 Instruction:"VPMULUDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF4 /r"/"RVM" - { - ND_INS_VPMULUDQ, ND_CAT_AVX, ND_SET_AVX, 1497, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2419 Instruction:"VPOPCNTB Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x54 /r"/"RAM" - { - ND_INS_VPOPCNTB, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1498, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2420 Instruction:"VPOPCNTD Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x55 /r"/"RAM" - { - ND_INS_VPOPCNTD, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1499, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2421 Instruction:"VPOPCNTQ Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x55 /r"/"RAM" - { - ND_INS_VPOPCNTQ, ND_CAT_VPOPCNT, ND_SET_AVX512VPOPCNTDQ, 1500, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VPOPCNTDQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2422 Instruction:"VPOPCNTW Vfv{K}{z},aKq,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x54 /r"/"RAM" - { - ND_INS_VPOPCNTW, ND_CAT_VPOPCNT, ND_SET_AVX512BITALG, 1501, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2423 Instruction:"VPOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEB /r"/"RVM" - { - ND_INS_VPOR, ND_CAT_LOGICAL, ND_SET_AVX, 1502, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2424 Instruction:"VPORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEB /r"/"RAVM" - { - ND_INS_VPORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1503, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2425 Instruction:"VPORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEB /r"/"RAVM" - { - ND_INS_VPORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1504, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2426 Instruction:"VPPERM Vx,Hx,Wx,Lx" Encoding:"xop m:8 w:0 0xA3 /r is4"/"RVML" - { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2427 Instruction:"VPPERM Vx,Hx,Lx,Wx" Encoding:"xop m:8 w:1 0xA3 /r is4"/"RVLM" - { - ND_INS_VPPERM, ND_CAT_XOP, ND_SET_XOP, 1505, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_L, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2428 Instruction:"VPROLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /1 ib"/"VAMI" - { - ND_INS_VPROLD, ND_CAT_AVX512, ND_SET_AVX512F, 1506, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2429 Instruction:"VPROLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /1 ib"/"VAMI" - { - ND_INS_VPROLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1507, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2430 Instruction:"VPROLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x15 /r"/"RAVM" - { - ND_INS_VPROLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1508, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2431 Instruction:"VPROLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x15 /r"/"RAVM" - { - ND_INS_VPROLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1509, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2432 Instruction:"VPRORD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /0 ib"/"VAMI" - { - ND_INS_VPRORD, ND_CAT_AVX512, ND_SET_AVX512F, 1510, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2433 Instruction:"VPRORQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /0 ib"/"VAMI" - { - ND_INS_VPRORQ, ND_CAT_AVX512, ND_SET_AVX512F, 1511, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2434 Instruction:"VPRORVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x14 /r"/"RAVM" - { - ND_INS_VPRORVD, ND_CAT_AVX512, ND_SET_AVX512F, 1512, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2435 Instruction:"VPRORVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x14 /r"/"RAVM" - { - ND_INS_VPRORVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1513, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2436 Instruction:"VPROTB Vdq,Wdq,Ib" Encoding:"xop m:8 0xC0 /r ib"/"RMI" - { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2437 Instruction:"VPROTB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x90 /r"/"RMV" - { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2438 Instruction:"VPROTB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x90 /r"/"RVM" - { - ND_INS_VPROTB, ND_CAT_XOP, ND_SET_XOP, 1514, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2439 Instruction:"VPROTD Vdq,Wdq,Ib" Encoding:"xop m:8 0xC2 /r ib"/"RMI" - { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2440 Instruction:"VPROTD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x92 /r"/"RMV" - { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2441 Instruction:"VPROTD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x92 /r"/"RVM" - { - ND_INS_VPROTD, ND_CAT_XOP, ND_SET_XOP, 1515, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2442 Instruction:"VPROTQ Vdq,Wdq,Ib" Encoding:"xop m:8 0xC3 /r ib"/"RMI" - { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2443 Instruction:"VPROTQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x93 /r"/"RMV" - { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2444 Instruction:"VPROTQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x93 /r"/"RVM" - { - ND_INS_VPROTQ, ND_CAT_XOP, ND_SET_XOP, 1516, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2445 Instruction:"VPROTW Vdq,Wdq,Ib" Encoding:"xop m:8 0xC1 /r ib"/"RMI" - { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2446 Instruction:"VPROTW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x91 /r"/"RMV" - { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2447 Instruction:"VPROTW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x91 /r"/"RVM" - { - ND_INS_VPROTW, ND_CAT_XOP, ND_SET_XOP, 1517, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2448 Instruction:"VPSADBW Vfv,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" - { - ND_INS_VPSADBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1518, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2449 Instruction:"VPSADBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF6 /r"/"RVM" - { - ND_INS_VPSADBW, ND_CAT_AVX, ND_SET_AVX, 1518, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2450 Instruction:"VPSCATTERDD Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib"/"MAR" - { - ND_INS_VPSCATTERDD, ND_CAT_SCATTER, ND_SET_AVX512F, 1519, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2451 Instruction:"VPSCATTERDQ Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib"/"MAR" - { - ND_INS_VPSCATTERDQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1520, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2452 Instruction:"VPSCATTERQD Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib"/"MAR" - { - ND_INS_VPSCATTERQD, ND_CAT_SCATTER, ND_SET_AVX512F, 1521, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2453 Instruction:"VPSCATTERQQ Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib"/"MAR" - { - ND_INS_VPSCATTERQQ, ND_CAT_SCATTER, ND_SET_AVX512F, 1522, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2454 Instruction:"VPSHAB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x98 /r"/"RMV" - { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2455 Instruction:"VPSHAB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x98 /r"/"RVM" - { - ND_INS_VPSHAB, ND_CAT_XOP, ND_SET_XOP, 1523, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2456 Instruction:"VPSHAD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9A /r"/"RMV" - { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2457 Instruction:"VPSHAD Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9A /r"/"RVM" - { - ND_INS_VPSHAD, ND_CAT_XOP, ND_SET_XOP, 1524, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2458 Instruction:"VPSHAQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x9B /r"/"RMV" - { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2459 Instruction:"VPSHAQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x9B /r"/"RVM" - { - ND_INS_VPSHAQ, ND_CAT_XOP, ND_SET_XOP, 1525, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2460 Instruction:"VPSHAW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x99 /r"/"RMV" - { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2461 Instruction:"VPSHAW Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x99 /r"/"RVM" - { - ND_INS_VPSHAW, ND_CAT_XOP, ND_SET_XOP, 1526, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2462 Instruction:"VPSHLB Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x94 /r"/"RMV" - { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2463 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x94 /r"/"RVM" - { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2464 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x95 /r"/"RVM" - { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2465 Instruction:"VPSHLB Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x96 /r"/"RVM" - { - ND_INS_VPSHLB, ND_CAT_XOP, ND_SET_XOP, 1527, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2466 Instruction:"VPSHLD Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x96 /r"/"RMV" - { - ND_INS_VPSHLD, ND_CAT_XOP, ND_SET_XOP, 1528, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2467 Instruction:"VPSHLDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x71 /r ib"/"RAVMI" - { - ND_INS_VPSHLDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1529, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2468 Instruction:"VPSHLDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x71 /r ib"/"RAVMI" - { - ND_INS_VPSHLDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1530, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2469 Instruction:"VPSHLDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x71 /r"/"RAVM" - { - ND_INS_VPSHLDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1531, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2470 Instruction:"VPSHLDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x71 /r"/"RAVM" - { - ND_INS_VPSHLDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1532, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2471 Instruction:"VPSHLDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x70 /r"/"RAVM" - { - ND_INS_VPSHLDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1533, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2472 Instruction:"VPSHLDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x70 /r ib"/"RAVMI" - { - ND_INS_VPSHLDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1534, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2473 Instruction:"VPSHLQ Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x97 /r"/"RMV" - { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2474 Instruction:"VPSHLQ Vdq,Hdq,Wdq" Encoding:"xop m:9 w:1 0x97 /r"/"RVM" - { - ND_INS_VPSHLQ, ND_CAT_XOP, ND_SET_XOP, 1535, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2475 Instruction:"VPSHLW Vdq,Wdq,Hdq" Encoding:"xop m:9 w:0 0x95 /r"/"RMV" - { - ND_INS_VPSHLW, ND_CAT_XOP, ND_SET_XOP, 1536, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_XOP, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2476 Instruction:"VPSHRDD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x73 /r ib"/"RAVMI" - { - ND_INS_VPSHRDD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1537, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2477 Instruction:"VPSHRDQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x73 /r ib"/"RAVMI" - { - ND_INS_VPSHRDQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1538, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2478 Instruction:"VPSHRDVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x73 /r"/"RAVM" - { - ND_INS_VPSHRDVD, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1539, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2479 Instruction:"VPSHRDVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x73 /r"/"RAVM" - { - ND_INS_VPSHRDVQ, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1540, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2480 Instruction:"VPSHRDVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x72 /r"/"RAVM" - { - ND_INS_VPSHRDVW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1541, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2481 Instruction:"VPSHRDW Vfv{K}{z},aKq,Hfv,Wfv,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x72 /r ib"/"RAVMI" - { - ND_INS_VPSHRDW, ND_CAT_AVX512VBMI, ND_SET_AVX512VBMI2, 1542, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(5, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512VBMI2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2482 Instruction:"VPSHUFB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:i 0x00 /r"/"RAVM" - { - ND_INS_VPSHUFB, ND_CAT_AVX512, ND_SET_AVX512BW, 1543, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2483 Instruction:"VPSHUFB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x00 /r"/"RVM" - { - ND_INS_VPSHUFB, ND_CAT_AVX, ND_SET_AVX, 1543, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2484 Instruction:"VPSHUFBITQMB rK{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x8F /r"/"RAVM" - { - ND_INS_VPSHUFBITQMB, ND_CAT_AVX512VBMI, ND_SET_AVX512BITALG, 1544, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BITALG, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2485 Instruction:"VPSHUFD Vfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x70 /r ib"/"RAMI" - { - ND_INS_VPSHUFD, ND_CAT_AVX512, ND_SET_AVX512F, 1545, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2486 Instruction:"VPSHUFD Vx,Wx,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x70 /r ib"/"RMI" - { - ND_INS_VPSHUFD, ND_CAT_AVX, ND_SET_AVX, 1545, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2487 Instruction:"VPSHUFHW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:2 l:x w:i 0x70 /r ib"/"RAMI" - { - ND_INS_VPSHUFHW, ND_CAT_AVX512, ND_SET_AVX512BW, 1546, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2488 Instruction:"VPSHUFHW Vx,Wx,Ib" Encoding:"vex m:1 p:2 l:x w:i 0x70 /r ib"/"RMI" - { - ND_INS_VPSHUFHW, ND_CAT_AVX, ND_SET_AVX, 1546, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2489 Instruction:"VPSHUFLW Vfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:3 l:x w:i 0x70 /r ib"/"RAMI" - { - ND_INS_VPSHUFLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1547, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2490 Instruction:"VPSHUFLW Vx,Wx,Ib" Encoding:"vex m:1 p:3 l:x w:i 0x70 /r ib"/"RMI" - { - ND_INS_VPSHUFLW, ND_CAT_AVX, ND_SET_AVX, 1547, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2491 Instruction:"VPSIGNB Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x08 /r"/"RVM" - { - ND_INS_VPSIGNB, ND_CAT_AVX, ND_SET_AVX, 1548, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2492 Instruction:"VPSIGND Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x0A /r"/"RVM" - { - ND_INS_VPSIGND, ND_CAT_AVX, ND_SET_AVX, 1549, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2493 Instruction:"VPSIGNW Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x09 /r"/"RVM" - { - ND_INS_VPSIGNW, ND_CAT_AVX, ND_SET_AVX, 1550, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2494 Instruction:"VPSLLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /6 ib"/"VAMI" - { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2495 Instruction:"VPSLLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xF2 /r"/"RAVM" - { - ND_INS_VPSLLD, ND_CAT_AVX512, ND_SET_AVX512F, 1551, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2496 Instruction:"VPSLLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /6:reg ib"/"VMI" - { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2497 Instruction:"VPSLLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF2 /r"/"RVM" - { - ND_INS_VPSLLD, ND_CAT_AVX, ND_SET_AVX, 1551, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2498 Instruction:"VPSLLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /7 ib"/"VMI" - { - ND_INS_VPSLLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1552, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2499 Instruction:"VPSLLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /7:reg ib"/"VMI" - { - ND_INS_VPSLLDQ, ND_CAT_AVX, ND_SET_AVX, 1552, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2500 Instruction:"VPSLLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /6 ib"/"VAMI" - { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2501 Instruction:"VPSLLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xF3 /r"/"RAVM" - { - ND_INS_VPSLLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1553, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2502 Instruction:"VPSLLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /6:reg ib"/"VMI" - { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2503 Instruction:"VPSLLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF3 /r"/"RVM" - { - ND_INS_VPSLLQ, ND_CAT_AVX, ND_SET_AVX, 1553, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2504 Instruction:"VPSLLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x47 /r"/"RAVM" - { - ND_INS_VPSLLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1554, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2505 Instruction:"VPSLLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x47 /r"/"RVM" - { - ND_INS_VPSLLVD, ND_CAT_AVX2, ND_SET_AVX2, 1554, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2506 Instruction:"VPSLLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x47 /r"/"RAVM" - { - ND_INS_VPSLLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1555, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2507 Instruction:"VPSLLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x47 /r"/"RVM" - { - ND_INS_VPSLLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1555, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2508 Instruction:"VPSLLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x12 /r"/"RAVM" - { - ND_INS_VPSLLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1556, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2509 Instruction:"VPSLLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /6 ib"/"VAMI" - { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2510 Instruction:"VPSLLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xF1 /r"/"RAVM" - { - ND_INS_VPSLLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1557, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2511 Instruction:"VPSLLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /6:reg ib"/"VMI" - { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2512 Instruction:"VPSLLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xF1 /r"/"RVM" - { - ND_INS_VPSLLW, ND_CAT_AVX, ND_SET_AVX, 1557, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2513 Instruction:"VPSRAD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /4 ib"/"VAMI" - { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2514 Instruction:"VPSRAD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xE2 /r"/"RAVM" - { - ND_INS_VPSRAD, ND_CAT_AVX512, ND_SET_AVX512F, 1558, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2515 Instruction:"VPSRAD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /4:reg ib"/"VMI" - { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2516 Instruction:"VPSRAD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE2 /r"/"RVM" - { - ND_INS_VPSRAD, ND_CAT_AVX, ND_SET_AVX, 1558, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2517 Instruction:"VPSRAQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x72 /4 ib"/"VAMI" - { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2518 Instruction:"VPSRAQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xE2 /r"/"RAVM" - { - ND_INS_VPSRAQ, ND_CAT_AVX512, ND_SET_AVX512F, 1559, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2519 Instruction:"VPSRAVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x46 /r"/"RAVM" - { - ND_INS_VPSRAVD, ND_CAT_AVX512, ND_SET_AVX512F, 1560, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2520 Instruction:"VPSRAVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x46 /r"/"RVM" - { - ND_INS_VPSRAVD, ND_CAT_AVX2, ND_SET_AVX2, 1560, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2521 Instruction:"VPSRAVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x46 /r"/"RAVM" - { - ND_INS_VPSRAVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1561, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2522 Instruction:"VPSRAVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x11 /r"/"RAVM" - { - ND_INS_VPSRAVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1562, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2523 Instruction:"VPSRAW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /4 ib"/"VAMI" - { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2524 Instruction:"VPSRAW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xE1 /r"/"RAVM" - { - ND_INS_VPSRAW, ND_CAT_AVX512, ND_SET_AVX512BW, 1563, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2525 Instruction:"VPSRAW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /4:reg ib"/"VMI" - { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2526 Instruction:"VPSRAW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xE1 /r"/"RVM" - { - ND_INS_VPSRAW, ND_CAT_AVX, ND_SET_AVX, 1563, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2527 Instruction:"VPSRLD Hfv{K}{z},aKq,Wfv|B32,Ib" Encoding:"evex m:1 p:1 l:x w:0 0x72 /2 ib"/"VAMI" - { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2528 Instruction:"VPSRLD Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:0 0xD2 /r"/"RAVM" - { - ND_INS_VPSRLD, ND_CAT_AVX512, ND_SET_AVX512F, 1564, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2529 Instruction:"VPSRLD Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x72 /2:reg ib"/"VMI" - { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2530 Instruction:"VPSRLD Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD2 /r"/"RVM" - { - ND_INS_VPSRLD, ND_CAT_AVX, ND_SET_AVX, 1564, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2531 Instruction:"VPSRLDQ Hfv,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x73 /3 ib"/"VMI" - { - ND_INS_VPSRLDQ, ND_CAT_AVX512, ND_SET_AVX512BW, 1565, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2532 Instruction:"VPSRLDQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /3:reg ib"/"VMI" - { - ND_INS_VPSRLDQ, ND_CAT_AVX, ND_SET_AVX, 1565, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2533 Instruction:"VPSRLQ Hfv{K}{z},aKq,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0x73 /2 ib"/"VAMI" - { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2534 Instruction:"VPSRLQ Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:1 0xD3 /r"/"RAVM" - { - ND_INS_VPSRLQ, ND_CAT_AVX512, ND_SET_AVX512F, 1566, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2535 Instruction:"VPSRLQ Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x73 /2:reg ib"/"VMI" - { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2536 Instruction:"VPSRLQ Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD3 /r"/"RVM" - { - ND_INS_VPSRLQ, ND_CAT_AVX, ND_SET_AVX, 1566, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2537 Instruction:"VPSRLVD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x45 /r"/"RAVM" - { - ND_INS_VPSRLVD, ND_CAT_AVX512, ND_SET_AVX512F, 1567, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2538 Instruction:"VPSRLVD Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x45 /r"/"RVM" - { - ND_INS_VPSRLVD, ND_CAT_AVX2, ND_SET_AVX2, 1567, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2539 Instruction:"VPSRLVQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x45 /r"/"RAVM" - { - ND_INS_VPSRLVQ, ND_CAT_AVX512, ND_SET_AVX512F, 1568, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2540 Instruction:"VPSRLVQ Vx,Hx,Wx" Encoding:"vex m:2 p:1 l:x w:1 0x45 /r"/"RVM" - { - ND_INS_VPSRLVQ, ND_CAT_AVX2, ND_SET_AVX2, 1568, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2541 Instruction:"VPSRLVW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x10 /r"/"RAVM" - { - ND_INS_VPSRLVW, ND_CAT_AVX512, ND_SET_AVX512BW, 1569, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2542 Instruction:"VPSRLW Hfv{K}{z},aKq,Wfv,Ib" Encoding:"evex m:1 p:1 l:x w:i 0x71 /2 ib"/"VAMI" - { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2543 Instruction:"VPSRLW Vfv{K}{z},aKq,Hfv,Wdq" Encoding:"evex m:1 p:1 l:x w:i 0xD1 /r"/"RAVM" - { - ND_INS_VPSRLW, ND_CAT_AVX512, ND_SET_AVX512BW, 1570, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_M128, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2544 Instruction:"VPSRLW Hx,Ux,Ib" Encoding:"vex m:1 p:1 l:x w:i 0x71 /2:reg ib"/"VMI" - { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_7, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_U, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2545 Instruction:"VPSRLW Vx,Hx,Wdq" Encoding:"vex m:1 p:1 l:x w:i 0xD1 /r"/"RVM" - { - ND_INS_VPSRLW, ND_CAT_AVX, ND_SET_AVX, 1570, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2546 Instruction:"VPSUBB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF8 /r"/"RAVM" - { - ND_INS_VPSUBB, ND_CAT_AVX512, ND_SET_AVX512BW, 1571, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2547 Instruction:"VPSUBB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF8 /r"/"RVM" - { - ND_INS_VPSUBB, ND_CAT_AVX, ND_SET_AVX, 1571, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2548 Instruction:"VPSUBD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xFA /r"/"RAVM" - { - ND_INS_VPSUBD, ND_CAT_AVX512, ND_SET_AVX512F, 1572, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2549 Instruction:"VPSUBD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFA /r"/"RVM" - { - ND_INS_VPSUBD, ND_CAT_AVX, ND_SET_AVX, 1572, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2550 Instruction:"VPSUBQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xFB /r"/"RAVM" - { - ND_INS_VPSUBQ, ND_CAT_AVX512, ND_SET_AVX512F, 1573, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2551 Instruction:"VPSUBQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xFB /r"/"RVM" - { - ND_INS_VPSUBQ, ND_CAT_AVX, ND_SET_AVX, 1573, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2552 Instruction:"VPSUBSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE8 /r"/"RAVM" - { - ND_INS_VPSUBSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1574, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2553 Instruction:"VPSUBSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE8 /r"/"RVM" - { - ND_INS_VPSUBSB, ND_CAT_AVX, ND_SET_AVX, 1574, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2554 Instruction:"VPSUBSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xE9 /r"/"RAVM" - { - ND_INS_VPSUBSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1575, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2555 Instruction:"VPSUBSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xE9 /r"/"RVM" - { - ND_INS_VPSUBSW, ND_CAT_AVX, ND_SET_AVX, 1575, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2556 Instruction:"VPSUBUSB Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD8 /r"/"RAVM" - { - ND_INS_VPSUBUSB, ND_CAT_AVX512, ND_SET_AVX512BW, 1576, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2557 Instruction:"VPSUBUSB Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD8 /r"/"RVM" - { - ND_INS_VPSUBUSB, ND_CAT_AVX, ND_SET_AVX, 1576, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2558 Instruction:"VPSUBUSW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xD9 /r"/"RAVM" - { - ND_INS_VPSUBUSW, ND_CAT_AVX512, ND_SET_AVX512BW, 1577, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2559 Instruction:"VPSUBUSW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xD9 /r"/"RVM" - { - ND_INS_VPSUBUSW, ND_CAT_AVX, ND_SET_AVX, 1577, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2560 Instruction:"VPSUBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0xF9 /r"/"RAVM" - { - ND_INS_VPSUBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1578, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2561 Instruction:"VPSUBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xF9 /r"/"RVM" - { - ND_INS_VPSUBW, ND_CAT_AVX, ND_SET_AVX, 1578, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2562 Instruction:"VPTERNLOGD Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x25 /r ib"/"RAVMI" - { - ND_INS_VPTERNLOGD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1579, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2563 Instruction:"VPTERNLOGQ Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x25 /r ib"/"RAVMI" - { - ND_INS_VPTERNLOGQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1580, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2564 Instruction:"VPTEST Vx,Wx" Encoding:"vex m:2 p:1 l:x w:i 0x17 /r"/"RM" - { - ND_INS_VPTEST, ND_CAT_LOGICAL, ND_SET_AVX, 1581, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2565 Instruction:"VPTESTMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:0 0x26 /r"/"RAVM" - { - ND_INS_VPTESTMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1582, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2566 Instruction:"VPTESTMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x27 /r"/"RAVM" - { - ND_INS_VPTESTMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1583, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2567 Instruction:"VPTESTMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x27 /r"/"RAVM" - { - ND_INS_VPTESTMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1584, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2568 Instruction:"VPTESTMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:1 l:x w:1 0x26 /r"/"RAVM" - { - ND_INS_VPTESTMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1585, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2569 Instruction:"VPTESTNMB rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:0 0x26 /r"/"RAVM" - { - ND_INS_VPTESTNMB, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1586, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2570 Instruction:"VPTESTNMD rKq{K},aKq,Hfv,Wfv|B32" Encoding:"evex m:2 p:2 l:x w:0 0x27 /r"/"RAVM" - { - ND_INS_VPTESTNMD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1587, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2571 Instruction:"VPTESTNMQ rKq{K},aKq,Hfv,Wfv|B64" Encoding:"evex m:2 p:2 l:x w:1 0x27 /r"/"RAVM" - { - ND_INS_VPTESTNMQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1588, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2572 Instruction:"VPTESTNMW rKq{K},aKq,Hfv,Wfv" Encoding:"evex m:2 p:2 l:x w:1 0x26 /r"/"RAVM" - { - ND_INS_VPTESTNMW, ND_CAT_LOGICAL, ND_SET_AVX512BW, 1589, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4nb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_rK, ND_OPS_q, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2573 Instruction:"VPUNPCKHBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x68 /r"/"RAVM" - { - ND_INS_VPUNPCKHBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1590, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2574 Instruction:"VPUNPCKHBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x68 /r"/"RVM" - { - ND_INS_VPUNPCKHBW, ND_CAT_AVX, ND_SET_AVX, 1590, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2575 Instruction:"VPUNPCKHDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x6A /r"/"RAVM" - { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1591, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2576 Instruction:"VPUNPCKHDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6A /r"/"RVM" - { - ND_INS_VPUNPCKHDQ, ND_CAT_AVX, ND_SET_AVX, 1591, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2577 Instruction:"VPUNPCKHQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6D /r"/"RAVM" - { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1592, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2578 Instruction:"VPUNPCKHQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6D /r"/"RVM" - { - ND_INS_VPUNPCKHQDQ, ND_CAT_AVX, ND_SET_AVX, 1592, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2579 Instruction:"VPUNPCKHWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:i 0x69 /r"/"RAVM" - { - ND_INS_VPUNPCKHWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1593, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2580 Instruction:"VPUNPCKHWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x69 /r"/"RVM" - { - ND_INS_VPUNPCKHWD, ND_CAT_AVX, ND_SET_AVX, 1593, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2581 Instruction:"VPUNPCKLBW Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x60 /r"/"RAVM" - { - ND_INS_VPUNPCKLBW, ND_CAT_AVX512, ND_SET_AVX512BW, 1594, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2582 Instruction:"VPUNPCKLBW Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x60 /r"/"RVM" - { - ND_INS_VPUNPCKLBW, ND_CAT_AVX, ND_SET_AVX, 1594, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2583 Instruction:"VPUNPCKLDQ Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0x62 /r"/"RAVM" - { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1595, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2584 Instruction:"VPUNPCKLDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x62 /r"/"RVM" - { - ND_INS_VPUNPCKLDQ, ND_CAT_AVX, ND_SET_AVX, 1595, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2585 Instruction:"VPUNPCKLQDQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x6C /r"/"RAVM" - { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX512, ND_SET_AVX512F, 1596, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2586 Instruction:"VPUNPCKLQDQ Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x6C /r"/"RVM" - { - ND_INS_VPUNPCKLQDQ, ND_CAT_AVX, ND_SET_AVX, 1596, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2587 Instruction:"VPUNPCKLWD Vfv{K}{z},aKq,Hfv,Wfv" Encoding:"evex m:1 p:1 l:x w:x 0x61 /r"/"RAVM" - { - ND_INS_VPUNPCKLWD, ND_CAT_AVX512, ND_SET_AVX512BW, 1597, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_FVM, ND_EXT_E4NFnb, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512BW, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2588 Instruction:"VPUNPCKLWD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x61 /r"/"RVM" - { - ND_INS_VPUNPCKLWD, ND_CAT_AVX, ND_SET_AVX, 1597, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2589 Instruction:"VPXOR Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0xEF /r"/"RVM" - { - ND_INS_VPXOR, ND_CAT_LOGICAL, ND_SET_AVX, 1598, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2590 Instruction:"VPXORD Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:1 l:x w:0 0xEF /r"/"RAVM" - { - ND_INS_VPXORD, ND_CAT_LOGICAL, ND_SET_AVX512F, 1599, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2591 Instruction:"VPXORQ Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0xEF /r"/"RAVM" - { - ND_INS_VPXORQ, ND_CAT_LOGICAL, ND_SET_AVX512F, 1600, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2592 Instruction:"VRANGEPD Vfv{K}{z},aKq,Hfv,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x50 /r ib"/"RAVMI" - { - ND_INS_VRANGEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1601, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2593 Instruction:"VRANGEPS Vfv{K}{z},aKq,Hfv,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x50 /r ib"/"RAVMI" - { - ND_INS_VRANGEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1602, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2594 Instruction:"VRANGESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x51 /r ib"/"RAVMI" - { - ND_INS_VRANGESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1603, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2595 Instruction:"VRANGESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x51 /r ib"/"RAVMI" - { - ND_INS_VRANGESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1604, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2596 Instruction:"VRCP14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4C /r"/"RAM" - { - ND_INS_VRCP14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1605, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2597 Instruction:"VRCP14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4C /r"/"RAM" - { - ND_INS_VRCP14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1606, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2598 Instruction:"VRCP14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4D /r"/"RAVM" - { - ND_INS_VRCP14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1607, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2599 Instruction:"VRCP14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4D /r"/"RAVM" - { - ND_INS_VRCP14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1608, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2600 Instruction:"VRCP28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCA /r"/"RAM" - { - ND_INS_VRCP28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1609, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:2601 Instruction:"VRCP28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCA /r"/"RAM" - { - ND_INS_VRCP28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1610, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:2602 Instruction:"VRCP28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCB /r"/"RAVM" - { - ND_INS_VRCP28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1611, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:2603 Instruction:"VRCP28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCB /r"/"RAVM" - { - ND_INS_VRCP28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1612, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:2604 Instruction:"VRCPPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4C /r"/"RAM" - { - ND_INS_VRCPPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1613, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), - }, - }, - - // Pos:2605 Instruction:"VRCPPS Vps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x53 /r"/"RM" - { - ND_INS_VRCPPS, ND_CAT_AVX, ND_SET_AVX, 1614, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2606 Instruction:"VRCPSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4D /r"/"RAVM" - { - ND_INS_VRCPSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1615, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2607 Instruction:"VRCPSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x53 /r"/"RVM" - { - ND_INS_VRCPSS, ND_CAT_AVX, ND_SET_AVX, 1616, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2608 Instruction:"VREDUCEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x56 /r ib"/"RAMI" - { - ND_INS_VREDUCEPD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1617, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2609 Instruction:"VREDUCEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x56 /r ib"/"RAMI" - { - ND_INS_VREDUCEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1618, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2610 Instruction:"VREDUCEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x56 /r ib"/"RAMI" - { - ND_INS_VREDUCEPS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1619, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2611 Instruction:"VREDUCESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x57 /r ib"/"RAVMI" - { - ND_INS_VREDUCESD, ND_CAT_AVX512, ND_SET_AVX512DQ, 1620, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2612 Instruction:"VREDUCESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x57 /r ib"/"RAVMI" - { - ND_INS_VREDUCESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1621, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2613 Instruction:"VREDUCESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x57 /r ib"/"RAVMI" - { - ND_INS_VREDUCESS, ND_CAT_AVX512, ND_SET_AVX512DQ, 1622, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2614 Instruction:"VRNDSCALEPD Vfv{K}{z},aKq,Wfv|B64{sae},Ib" Encoding:"evex m:3 p:1 l:x w:1 0x09 /r ib"/"RAMI" - { - ND_INS_VRNDSCALEPD, ND_CAT_AVX512, ND_SET_AVX512F, 1623, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2615 Instruction:"VRNDSCALEPH Vfv{K}{z},aKq,Wfv|B16{sae},Ib" Encoding:"evex m:3 p:0 l:x w:0 0x08 /r ib"/"RAMI" - { - ND_INS_VRNDSCALEPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1624, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2616 Instruction:"VRNDSCALEPS Vfv{K}{z},aKq,Wfv|B32{sae},Ib" Encoding:"evex m:3 p:1 l:x w:0 0x08 /r ib"/"RAMI" - { - ND_INS_VRNDSCALEPS, ND_CAT_AVX512, ND_SET_AVX512F, 1625, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2617 Instruction:"VRNDSCALESD Vdq{K}{z},aKq,Hdq,Wsd{sae},Ib" Encoding:"evex m:3 p:1 l:i w:1 0x0B /r ib"/"RAVMI" - { - ND_INS_VRNDSCALESD, ND_CAT_AVX512, ND_SET_AVX512F, 1626, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2618 Instruction:"VRNDSCALESH Vdq{K}{z},aKq,Hdq,Wsh{sae},Ib" Encoding:"evex m:3 p:0 l:i w:0 0x0A /r ib"/"RAVMI" - { - ND_INS_VRNDSCALESH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1627, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2619 Instruction:"VRNDSCALESS Vdq{K}{z},aKq,Hdq,Wss{sae},Ib" Encoding:"evex m:3 p:1 l:i w:0 0x0A /r ib"/"RAVMI" - { - ND_INS_VRNDSCALESS, ND_CAT_AVX512, ND_SET_AVX512F, 1628, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(5, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2620 Instruction:"VROUNDPD Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x09 /r ib"/"RMI" - { - ND_INS_VROUNDPD, ND_CAT_AVX, ND_SET_AVX, 1629, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2621 Instruction:"VROUNDPS Vx,Wx,Ib" Encoding:"vex m:3 p:1 l:x w:i 0x08 /r ib"/"RMI" - { - ND_INS_VROUNDPS, ND_CAT_AVX, ND_SET_AVX, 1630, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2622 Instruction:"VROUNDSD Vsd,Hsd,Wsd,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0B /r ib"/"RVMI" - { - ND_INS_VROUNDSD, ND_CAT_AVX, ND_SET_AVX, 1631, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2623 Instruction:"VROUNDSS Vss,Hss,Wss,Ib" Encoding:"vex m:3 p:1 l:i w:i 0x0A /r ib"/"RVMI" - { - ND_INS_VROUNDSS, ND_CAT_AVX, ND_SET_AVX, 1632, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2624 Instruction:"VRSQRT14PD Vfv{K}{z},aKq,Wfv|B64" Encoding:"evex m:2 p:1 l:x w:1 0x4E /r"/"RAM" - { - ND_INS_VRSQRT14PD, ND_CAT_AVX512, ND_SET_AVX512F, 1633, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2625 Instruction:"VRSQRT14PS Vfv{K}{z},aKq,Wfv|B32" Encoding:"evex m:2 p:1 l:x w:0 0x4E /r"/"RAM" - { - ND_INS_VRSQRT14PS, ND_CAT_AVX512, ND_SET_AVX512F, 1634, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2626 Instruction:"VRSQRT14SD Vdq{K}{z},aKq,Hdq,Wsd" Encoding:"evex m:2 p:1 l:x w:1 0x4F /r"/"RAVM" - { - ND_INS_VRSQRT14SD, ND_CAT_AVX512, ND_SET_AVX512F, 1635, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2627 Instruction:"VRSQRT14SS Vdq{K}{z},aKq,Hdq,Wss" Encoding:"evex m:2 p:1 l:x w:0 0x4F /r"/"RAVM" - { - ND_INS_VRSQRT14SS, ND_CAT_AVX512, ND_SET_AVX512F, 1636, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2628 Instruction:"VRSQRT28PD Voq{K}{z},aKq,Woq|B64{sae}" Encoding:"evex m:2 p:1 l:2 w:1 0xCC /r"/"RAM" - { - ND_INS_VRSQRT28PD, ND_CAT_KNL, ND_SET_AVX512ER, 1637, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B64, 0), - }, - }, - - // Pos:2629 Instruction:"VRSQRT28PS Voq{K}{z},aKq,Woq|B32{sae}" Encoding:"evex m:2 p:1 l:2 w:0 0xCC /r"/"RAM" - { - ND_INS_VRSQRT28PS, ND_CAT_KNL, ND_SET_AVX512ER, 1638, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_oq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_oq, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B32, 0), - }, - }, - - // Pos:2630 Instruction:"VRSQRT28SD Vdq{K}{z},aKq,Hdq,Wsd{sae}" Encoding:"evex m:2 p:1 l:i w:1 0xCD /r"/"RAVM" - { - ND_INS_VRSQRT28SD, ND_CAT_KNL, ND_SET_AVX512ER, 1639, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:2631 Instruction:"VRSQRT28SS Vdq{K}{z},aKq,Hdq,Wss{sae}" Encoding:"evex m:2 p:1 l:i w:0 0xCD /r"/"RAVM" - { - ND_INS_VRSQRT28SS, ND_CAT_KNL, ND_SET_AVX512ER, 1640, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512ER, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:2632 Instruction:"VRSQRTPH Vfv{K}{z},aKq,Wfv|B16" Encoding:"evex m:6 p:1 l:x w:0 0x4E /r"/"RAM" - { - ND_INS_VRSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1641, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B16, 0), - }, - }, - - // Pos:2633 Instruction:"VRSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x52 /r"/"RM" - { - ND_INS_VRSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1642, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2634 Instruction:"VRSQRTSH Vdq{K}{z},aKq,Hdq,Wsh" Encoding:"evex m:6 p:1 l:i w:0 0x4F /r"/"RAVM" - { - ND_INS_VRSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1643, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E10, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2635 Instruction:"VRSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x52 /r"/"RVM" - { - ND_INS_VRSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1644, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2636 Instruction:"VSCALEFPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:2 p:1 l:x w:1 0x2C /r"/"RAVM" - { - ND_INS_VSCALEFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1645, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:2637 Instruction:"VSCALEFPH Vfv{K}{z},aKq,Hfv,Wfv|B16{er}" Encoding:"evex m:6 p:1 l:x w:0 0x2C /r"/"RAVM" - { - ND_INS_VSCALEFPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1646, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:2638 Instruction:"VSCALEFPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:2 p:1 l:x w:0 0x2C /r"/"RAVM" - { - ND_INS_VSCALEFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1647, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:2639 Instruction:"VSCALEFSD Vsd{K}{z},aKq,Hsd,Wsd{er}" Encoding:"evex m:2 p:1 l:i w:1 0x2D /r"/"RAVM" - { - ND_INS_VSCALEFSD, ND_CAT_AVX512, ND_SET_AVX512F, 1648, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2640 Instruction:"VSCALEFSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:6 p:1 l:i w:0 0x2D /r"/"RAVM" - { - ND_INS_VSCALEFSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1649, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2641 Instruction:"VSCALEFSS Vss{K}{z},aKq,Hss,Wss{er}" Encoding:"evex m:2 p:1 l:i w:0 0x2D /r"/"RAVM" - { - ND_INS_VSCALEFSS, ND_CAT_AVX512, ND_SET_AVX512F, 1650, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2642 Instruction:"VSCATTERDPD Mvm32h{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib"/"MAR" - { - ND_INS_VSCATTERDPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1651, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2643 Instruction:"VSCATTERDPS Mvm32n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib"/"MAR" - { - ND_INS_VSCATTERDPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1652, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2644 Instruction:"VSCATTERPF0DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib"/"MA" - { - ND_INS_VSCATTERPF0DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1653, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2645 Instruction:"VSCATTERPF0DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib"/"MA" - { - ND_INS_VSCATTERPF0DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1654, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2646 Instruction:"VSCATTERPF0QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib"/"MA" - { - ND_INS_VSCATTERPF0QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1655, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2647 Instruction:"VSCATTERPF0QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib"/"MA" - { - ND_INS_VSCATTERPF0QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1656, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2648 Instruction:"VSCATTERPF1DPD Mvm32h{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib"/"MA" - { - ND_INS_VSCATTERPF1DPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1657, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32h, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2649 Instruction:"VSCATTERPF1DPS Mvm32n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib"/"MA" - { - ND_INS_VSCATTERPF1DPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1658, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm32n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2650 Instruction:"VSCATTERPF1QPD Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib"/"MA" - { - ND_INS_VSCATTERPF1QPD, ND_CAT_SCATTER, ND_SET_AVX512PF, 1659, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2651 Instruction:"VSCATTERPF1QPS Mvm64n{K},aKq" Encoding:"evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib"/"MA" - { - ND_INS_VSCATTERPF1QPS, ND_CAT_SCATTER, ND_SET_AVX512PF, 1660, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(2, 0), ND_TUPLE_T1S, ND_EXT_E12NP, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB, ND_CFF_AVX512PF, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_P, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2652 Instruction:"VSCATTERQPD Mvm64n{K},aKq,Vfv" Encoding:"evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib"/"MAR" - { - ND_INS_VSCATTERQPD, ND_CAT_SCATTER, ND_SET_AVX512F, 1661, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2653 Instruction:"VSCATTERQPS Mvm64n{K},aKq,Vhv" Encoding:"evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib"/"MAR" - { - ND_INS_VSCATTERQPS, ND_CAT_SCATTER, ND_SET_AVX512F, 1662, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK, ND_OPS_CNT(3, 0), ND_TUPLE_T1S, ND_EXT_E12, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MMASK|ND_FLAG_MODRM|ND_FLAG_VSIB|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_vm64n, 0, ND_OPA_W, ND_OPD_MASK, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_V, ND_OPS_hv, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2654 Instruction:"VSHA512MSG1 Vqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCC /r:reg"/"RM" - { - ND_INS_VSHA512MSG1, ND_CAT_SHA512, ND_SET_SHA512, 1663, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2655 Instruction:"VSHA512MSG2 Vqq,Uqq" Encoding:"vex m:2 p:3 l:1 w:0 0xCD /r:reg"/"RM" - { - ND_INS_VSHA512MSG2, ND_CAT_SHA512, ND_SET_SHA512, 1664, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_U, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2656 Instruction:"VSHA512RNDS2 Vqq,Hqq,Udq" Encoding:"vex m:2 p:3 l:1 w:0 0xCB /r:reg"/"RVM" - { - ND_INS_VSHA512RNDS2, ND_CAT_SHA512, ND_SET_SHA512, 1665, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SHA512, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_qq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_qq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_U, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2657 Instruction:"VSHUFF32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x23 /r ib"/"RAVMI" - { - ND_INS_VSHUFF32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1666, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2658 Instruction:"VSHUFF64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x23 /r ib"/"RAVMI" - { - ND_INS_VSHUFF64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1667, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2659 Instruction:"VSHUFI32X4 Vuv{K}{z},aKq,Huv,Wuv|B32,Ib" Encoding:"evex m:3 p:1 l:x w:0 0x43 /r ib"/"RAVMI" - { - ND_INS_VSHUFI32X4, ND_CAT_AVX512, ND_SET_AVX512F, 1668, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2660 Instruction:"VSHUFI64X2 Vuv{K}{z},aKq,Huv,Wuv|B64,Ib" Encoding:"evex m:3 p:1 l:x w:1 0x43 /r ib"/"RAVMI" - { - ND_INS_VSHUFI64X2, ND_CAT_AVX512, ND_SET_AVX512F, 1669, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_NOL0|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_uv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_uv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_uv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2661 Instruction:"VSHUFPD Vfv{K}{z},aKq,Hfv,Wfv|B64,Ib" Encoding:"evex m:1 p:1 l:x w:1 0xC6 /r ib"/"RAVMI" - { - ND_INS_VSHUFPD, ND_CAT_AVX512, ND_SET_AVX512F, 1670, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2662 Instruction:"VSHUFPD Vpd,Hpd,Wpd,Ib" Encoding:"vex m:1 p:1 l:x w:i 0xC6 /r ib"/"RVMI" - { - ND_INS_VSHUFPD, ND_CAT_AVX, ND_SET_AVX, 1670, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2663 Instruction:"VSHUFPS Vfv{K}{z},aKq,Hfv,Wfv|B32,Ib" Encoding:"evex m:1 p:0 l:x w:0 0xC6 /r ib"/"RAVMI" - { - ND_INS_VSHUFPS, ND_CAT_AVX512, ND_SET_AVX512F, 1671, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(5, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2664 Instruction:"VSHUFPS Vps,Hps,Wps,Ib" Encoding:"vex m:1 p:0 l:x w:i 0xC6 /r ib"/"RVMI" - { - ND_INS_VSHUFPS, ND_CAT_AVX, ND_SET_AVX, 1671, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2665 Instruction:"VSM3MSG1 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:0 l:0 w:0 0xDA /r"/"RVM" - { - ND_INS_VSM3MSG1, ND_CAT_SM3, ND_SET_SM3, 1672, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2666 Instruction:"VSM3MSG2 Vdq,Hdq,Wdq" Encoding:"vex m:2 p:1 l:0 w:0 0xDA /r"/"RVM" - { - ND_INS_VSM3MSG2, ND_CAT_SM3, ND_SET_SM3, 1673, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2667 Instruction:"VSM3RNDS2 Vdq,Hdq,Wdq,Ib" Encoding:"vex m:3 p:1 l:0 w:0 0xDE /r ib"/"RVMI" - { - ND_INS_VSM3RNDS2, ND_CAT_SM3, ND_SET_SM3, 1674, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(4, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM3, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2668 Instruction:"VSM4KEY4 Vx,Hx,Wx" Encoding:"vex m:2 p:2 l:x w:0 0xDA /r"/"RVM" - { - ND_INS_VSM4KEY4, ND_CAT_SM4, ND_SET_SM4, 1675, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2669 Instruction:"VSM4RNDS4 Vx,Hx,Wx" Encoding:"vex m:2 p:3 l:x w:0 0xDA /r"/"RVM" - { - ND_INS_VSM4RNDS4, ND_CAT_SM4, ND_SET_SM4, 1676, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_6, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SM4, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2670 Instruction:"VSQRTPD Vfv{K}{z},aKq,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x51 /r"/"RAM" - { - ND_INS_VSQRTPD, ND_CAT_AVX512, ND_SET_AVX512F, 1677, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:2671 Instruction:"VSQRTPD Vx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x51 /r"/"RM" - { - ND_INS_VSQRTPD, ND_CAT_AVX, ND_SET_AVX, 1677, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2672 Instruction:"VSQRTPH Vfv{K}{z},aKq,Wfv|B16{er}" Encoding:"evex m:5 p:0 l:x w:0 0x51 /r"/"RAM" - { - ND_INS_VSQRTPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1678, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B16, 0), - }, - }, - - // Pos:2673 Instruction:"VSQRTPS Vfv{K}{z},aKq,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x51 /r"/"RAM" - { - ND_INS_VSQRTPS, ND_CAT_AVX512, ND_SET_AVX512F, 1679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(3, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:2674 Instruction:"VSQRTPS Vx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x51 /r"/"RM" - { - ND_INS_VSQRTPS, ND_CAT_AVX, ND_SET_AVX, 1679, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2675 Instruction:"VSQRTSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x51 /r"/"RAVM" - { - ND_INS_VSQRTSD, ND_CAT_AVX512, ND_SET_AVX512F, 1680, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2676 Instruction:"VSQRTSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x51 /r"/"RVM" - { - ND_INS_VSQRTSD, ND_CAT_AVX, ND_SET_AVX, 1680, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2677 Instruction:"VSQRTSH Vdq{K}{z},aKq,Hdq,Wsh{er}" Encoding:"evex m:5 p:2 l:i w:0 0x51 /r"/"RAVM" - { - ND_INS_VSQRTSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1681, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2678 Instruction:"VSQRTSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x51 /r"/"RAVM" - { - ND_INS_VSQRTSS, ND_CAT_AVX512, ND_SET_AVX512F, 1682, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2679 Instruction:"VSQRTSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x51 /r"/"RVM" - { - ND_INS_VSQRTSS, ND_CAT_AVX, ND_SET_AVX, 1682, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2680 Instruction:"VSTMXCSR Md" Encoding:"vex m:1 p:0 0xAE /3:mem"/"M" - { - ND_INS_VSTMXCSR, ND_CAT_AVX, ND_SET_AVX, 1683, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(1, 1), 0, ND_EXT_5, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_d, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_MXCSR, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2681 Instruction:"VSUBPD Vfv{K}{z},aKq,Hfv,Wfv|B64{er}" Encoding:"evex m:1 p:1 l:x w:1 0x5C /r"/"RAVM" - { - ND_INS_VSUBPD, ND_CAT_AVX512, ND_SET_AVX512F, 1684, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B64, 0), - }, - }, - - // Pos:2682 Instruction:"VSUBPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x5C /r"/"RVM" - { - ND_INS_VSUBPD, ND_CAT_AVX, ND_SET_AVX, 1684, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2683 Instruction:"VSUBPH Vfv{K}{z},aKq,Hfv,Wfv|B16{sae}" Encoding:"evex m:5 p:0 l:x w:0 0x5C /r"/"RAVM" - { - ND_INS_VSUBPH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1685, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_SAE|ND_OPD_B16, 0), - }, - }, - - // Pos:2684 Instruction:"VSUBPS Vfv{K}{z},aKq,Hfv,Wfv|B32{er}" Encoding:"evex m:1 p:0 l:x w:0 0x5C /r"/"RAVM" - { - ND_INS_VSUBPS, ND_CAT_AVX512, ND_SET_AVX512F, 1686, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E2, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_ER|ND_OPD_B32, 0), - }, - }, - - // Pos:2685 Instruction:"VSUBPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x5C /r"/"RVM" - { - ND_INS_VSUBPS, ND_CAT_AVX, ND_SET_AVX, 1686, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2686 Instruction:"VSUBSD Vdq{K}{z},aKq,Hdq,Wsd{er}" Encoding:"evex m:1 p:3 l:i w:1 0x5C /r"/"RAVM" - { - ND_INS_VSUBSD, ND_CAT_AVX512, ND_SET_AVX512F, 1687, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2687 Instruction:"VSUBSD Vsd,Hsd,Wsd" Encoding:"vex m:1 p:3 l:i w:i 0x5C /r"/"RVM" - { - ND_INS_VSUBSD, ND_CAT_AVX, ND_SET_AVX, 1687, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2688 Instruction:"VSUBSH Vdq{K}{z},aKq,Hdq,Wsh{sae}" Encoding:"evex m:5 p:2 l:i w:0 0x5C /r"/"RAVM" - { - ND_INS_VSUBSH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1688, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_SAE, ND_OPS_CNT(4, 0), ND_TUPLE_T1S16, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - }, - }, - - // Pos:2689 Instruction:"VSUBSS Vdq{K}{z},aKq,Hdq,Wss{er}" Encoding:"evex m:1 p:2 l:i w:0 0x5C /r"/"RAVM" - { - ND_INS_VSUBSS, ND_CAT_AVX512, ND_SET_AVX512F, 1689, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_ER, ND_OPS_CNT(4, 0), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_ER, 0), - }, - }, - - // Pos:2690 Instruction:"VSUBSS Vss,Hss,Wss" Encoding:"vex m:1 p:2 l:i w:i 0x5C /r"/"RVM" - { - ND_INS_VSUBSS, ND_CAT_AVX, ND_SET_AVX, 1689, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_2, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2691 Instruction:"VTESTPD Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0F /r"/"RM" - { - ND_INS_VTESTPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1690, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2692 Instruction:"VTESTPS Vx,Wx" Encoding:"vex m:2 p:1 l:x w:0 0x0E /r"/"RM" - { - ND_INS_VTESTPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1691, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2693 Instruction:"VUCOMISD Vdq,Wsd{sae}" Encoding:"evex m:1 p:1 l:i w:1 0x2E /r"/"RM" - { - ND_INS_VUCOMISD, ND_CAT_AVX512, ND_SET_AVX512F, 1692, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2694 Instruction:"VUCOMISD Vsd,Wsd" Encoding:"vex m:1 p:1 l:i w:i 0x2E /r"/"RM" - { - ND_INS_VUCOMISD, ND_CAT_AVX, ND_SET_AVX, 1692, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2695 Instruction:"VUCOMISH Vdq,Wsh{sae}" Encoding:"evex m:5 p:0 l:i w:0 0x2E /r"/"RM" - { - ND_INS_VUCOMISH, ND_CAT_AVX512FP16, ND_SET_AVX512FP16, 1693, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S16, ND_EXT_E3NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512FP16, - 0, - 0|NDR_RFLAG_ZF|NDR_RFLAG_PF|NDR_RFLAG_CF, - 0, - 0|NDR_RFLAG_OF|NDR_RFLAG_SF|NDR_RFLAG_AF, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_sh, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2696 Instruction:"VUCOMISS Vdq,Wss{sae}" Encoding:"evex m:1 p:0 l:i w:0 0x2E /r"/"RM" - { - ND_INS_VUCOMISS, ND_CAT_AVX512, ND_SET_AVX512F, 1694, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_SAE, ND_OPS_CNT(2, 1), ND_TUPLE_T1S, ND_EXT_E3, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_dq, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, ND_OPD_SAE, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2697 Instruction:"VUCOMISS Vss,Wss" Encoding:"vex m:1 p:0 l:i w:i 0x2E /r"/"RM" - { - ND_INS_VUCOMISS, ND_CAT_AVX, ND_SET_AVX, 1694, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(2, 1), 0, ND_EXT_3, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_LIG|ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_ZF, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ss, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2698 Instruction:"VUNPCKHPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x15 /r"/"RAVM" - { - ND_INS_VUNPCKHPD, ND_CAT_AVX512, ND_SET_AVX512F, 1695, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2699 Instruction:"VUNPCKHPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x15 /r"/"RVM" - { - ND_INS_VUNPCKHPD, ND_CAT_AVX, ND_SET_AVX, 1695, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2700 Instruction:"VUNPCKHPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x15 /r"/"RAVM" - { - ND_INS_VUNPCKHPS, ND_CAT_AVX512, ND_SET_AVX512F, 1696, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2701 Instruction:"VUNPCKHPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x15 /r"/"RVM" - { - ND_INS_VUNPCKHPS, ND_CAT_AVX, ND_SET_AVX, 1696, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2702 Instruction:"VUNPCKLPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x14 /r"/"RAVM" - { - ND_INS_VUNPCKLPD, ND_CAT_AVX512, ND_SET_AVX512F, 1697, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2703 Instruction:"VUNPCKLPD Vx,Hx,Wx" Encoding:"vex m:1 p:1 l:x w:i 0x14 /r"/"RVM" - { - ND_INS_VUNPCKLPD, ND_CAT_AVX, ND_SET_AVX, 1697, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2704 Instruction:"VUNPCKLPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x14 /r"/"RAVM" - { - ND_INS_VUNPCKLPS, ND_CAT_AVX512, ND_SET_AVX512F, 1698, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4NF, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512F, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2705 Instruction:"VUNPCKLPS Vx,Hx,Wx" Encoding:"vex m:1 p:0 l:x w:i 0x14 /r"/"RVM" - { - ND_INS_VUNPCKLPS, ND_CAT_AVX, ND_SET_AVX, 1698, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_x, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_x, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_x, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2706 Instruction:"VXORPD Vfv{K}{z},aKq,Hfv,Wfv|B64" Encoding:"evex m:1 p:1 l:x w:1 0x57 /r"/"RAVM" - { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1699, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B64, 0), - }, - }, - - // Pos:2707 Instruction:"VXORPD Vpd,Hpd,Wpd" Encoding:"vex m:1 p:1 l:x w:i 0x57 /r"/"RVM" - { - ND_INS_VXORPD, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1699, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2708 Instruction:"VXORPS Vfv{K}{z},aKq,Hfv,Wfv|B32" Encoding:"evex m:1 p:0 l:x w:0 0x57 /r"/"RAVM" - { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX512DQ, 1700, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - ND_DECO_MASK|ND_DECO_ZERO|ND_DECO_BROADCAST, ND_OPS_CNT(4, 0), ND_TUPLE_FV, ND_EXT_E4, ND_EXC_EVEX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX512DQ, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_fv, 0, ND_OPA_W, ND_OPD_MASK|ND_OPD_Z, 0), - OP(ND_OPT_aK, ND_OPS_q, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_H, ND_OPS_fv, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_fv, 0, ND_OPA_R, ND_OPD_B32, 0), - }, - }, - - // Pos:2709 Instruction:"VXORPS Vps,Hps,Wps" Encoding:"vex m:1 p:0 l:x w:i 0x57 /r"/"RVM" - { - ND_INS_VXORPS, ND_CAT_LOGICAL_FP, ND_SET_AVX, 1700, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(3, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_WIG|ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_H, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2710 Instruction:"VZEROALL" Encoding:"vex m:1 p:0 l:1 0x77"/"" - { - ND_INS_VZEROALL, ND_CAT_AVX, ND_SET_AVX, 1701, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2711 Instruction:"VZEROUPPER" Encoding:"vex m:1 p:0 l:0 0x77"/"" - { - ND_INS_VZEROUPPER, ND_CAT_AVX, ND_SET_AVX, 1702, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF, - 0, ND_OPS_CNT(0, 1), 0, ND_EXT_8, ND_EXC_SSE_AVX, 0, 0, 0, 0, ND_CFF_AVX, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2712 Instruction:"WAIT" Encoding:"0x9B"/"" - { - ND_INS_WAIT, ND_CAT_X87_ALU, ND_SET_X87, 1703, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0xff, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2713 Instruction:"WBINVD" Encoding:"0x0F 0x09"/"" - { - ND_INS_WBINVD, ND_CAT_SYSTEM, ND_SET_I486REAL, 1704, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2714 Instruction:"WBNOINVD" Encoding:"a0xF3 0x0F 0x09"/"" - { - ND_INS_WBNOINVD, ND_CAT_WBNOINVD, ND_SET_WBNOINVD, 1705, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, 0, ND_CFF_WBNOINVD, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2715 Instruction:"WRFSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /2:reg"/"M" - { - ND_INS_WRFSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1706, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_FSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2716 Instruction:"WRGSBASE Ry" Encoding:"o64 0xF3 0x0F 0xAE /3:reg"/"M" - { - ND_INS_WRGSBASE, ND_CAT_RDWRFSGS, ND_SET_RDWRFSGS, 1707, - 0, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_RDWRFSGS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_R, ND_OPS_y, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR_GSBASE, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2717 Instruction:"WRMSR" Encoding:"0x0F 0x30"/"" - { - ND_INS_WRMSR, ND_CAT_SYSTEM, ND_SET_PENTIUMREAL, 1708, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_SERIAL, ND_CFF_MSR, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2718 Instruction:"WRMSRLIST" Encoding:"0xF3 0x0F 0x01 /0xC6"/"" - { - ND_INS_WRMSRLIST, ND_CAT_SYSTEM, ND_SET_MSRLIST, 1709, - 0, - ND_MOD_R0|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 3), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_O64, ND_CFF_MSRLIST, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_MEM_SMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MEM_DMSRT, ND_OPS_4096, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2719 Instruction:"WRMSRNS" Encoding:"NP 0x0F 0x01 /0xC6"/"" - { - ND_INS_WRMSRNS, ND_CAT_SYSTEM, ND_SET_WRMSRNS, 1710, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_WRMSRNS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_MSR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2720 Instruction:"WRPKRU" Encoding:"NP 0x0F 0x01 /0xEF"/"" - { - ND_INS_WRPKRU, ND_CAT_MISC, ND_SET_PKU, 1711, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_PKU, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_PKRU, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2721 Instruction:"WRSHR Ed" Encoding:"cyrix 0x0F 0x37 /r"/"M" - { - ND_INS_WRSHR, ND_CAT_SYSTEM, ND_SET_CYRIX, 1712, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_d, 0, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2722 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR" - { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1713, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2723 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR" - { - ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1714, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2724 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR" - { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1715, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2725 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR" - { - ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1716, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2726 Instruction:"XABORT Ib" Encoding:"0xC6 /0xF8 ib"/"I" - { - ND_INS_XABORT, ND_CAT_UNCOND_BR, ND_SET_TSX, 1717, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - }, - }, - - // Pos:2727 Instruction:"XADD Eb,Gb" Encoding:"0x0F 0xC0 /r"/"MR" - { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2728 Instruction:"XADD Ev,Gv" Encoding:"0x0F 0xC1 /r"/"MR" - { - ND_INS_XADD, ND_CAT_SEMAPHORE, ND_SET_I486REAL, 1718, - ND_PREF_LOCK|ND_PREF_HLE, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_ZF|NDR_RFLAG_SF|NDR_RFLAG_OF, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2729 Instruction:"XBEGIN Jz" Encoding:"0xC7 /0xF8 cz"/"D" - { - ND_INS_XBEGIN, ND_CAT_COND_BR, ND_SET_TSX, 1719, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_J, ND_OPS_z, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_RCW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - }, - }, - - // Pos:2730 Instruction:"XCHG Eb,Gb" Encoding:"0x86 /r"/"MR" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2731 Instruction:"XCHG Ev,Gv" Encoding:"0x87 /r"/"MR" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - ND_PREF_HLE|ND_PREF_LOCK|ND_PREF_HLE_WO_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2732 Instruction:"XCHG Zv,rAX" Encoding:"rexb 0x90"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2733 Instruction:"XCHG Zv,rAX" Encoding:"0x91"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2734 Instruction:"XCHG Zv,rAX" Encoding:"0x92"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2735 Instruction:"XCHG Zv,rAX" Encoding:"0x93"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2736 Instruction:"XCHG Zv,rAX" Encoding:"0x94"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2737 Instruction:"XCHG Zv,rAX" Encoding:"0x95"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2738 Instruction:"XCHG Zv,rAX" Encoding:"0x96"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2739 Instruction:"XCHG Zv,rAX" Encoding:"0x97"/"O" - { - ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1720, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_Z, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - }, - }, - - // Pos:2740 Instruction:"XCRYPTCBC" Encoding:"0xF3 0x0F 0xA7 /0xD0"/"" - { - ND_INS_XCRYPTCBC, ND_CAT_PADLOCK, ND_SET_CYRIX, 1721, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2741 Instruction:"XCRYPTCFB" Encoding:"0xF3 0x0F 0xA7 /0xE0"/"" - { - ND_INS_XCRYPTCFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1722, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2742 Instruction:"XCRYPTCTR" Encoding:"0xF3 0x0F 0xA7 /0xD8"/"" - { - ND_INS_XCRYPTCTR, ND_CAT_PADLOCK, ND_SET_CYRIX, 1723, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2743 Instruction:"XCRYPTECB" Encoding:"0xF3 0x0F 0xA7 /0xC8"/"" - { - ND_INS_XCRYPTECB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1724, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2744 Instruction:"XCRYPTOFB" Encoding:"0xF3 0x0F 0xA7 /0xE8"/"" - { - ND_INS_XCRYPTOFB, ND_CAT_PADLOCK, ND_SET_CYRIX, 1725, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2745 Instruction:"XEND" Encoding:"NP 0x0F 0x01 /0xD5"/"" - { - ND_INS_XEND, ND_CAT_COND_BR, ND_SET_TSX, 1726, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_RIP, ND_OPS_yf, ND_OPF_DEFAULT, ND_OPA_CW, 0, 0), - }, - }, - - // Pos:2746 Instruction:"XGETBV" Encoding:"NP 0x0F 0x01 /0xD0"/"" - { - ND_INS_XGETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1727, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2747 Instruction:"XLATB" Encoding:"0xD7"/"" - { - ND_INS_XLATB, ND_CAT_MISC, ND_SET_I86, 1728, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - OP(ND_OPT_MEM_rBX_AL, ND_OPS_b, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2748 Instruction:"XOR Eb,Gb" Encoding:"0x30 /r"/"MR" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2749 Instruction:"XOR Ev,Gv" Encoding:"0x31 /r"/"MR" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2750 Instruction:"XOR Gb,Eb" Encoding:"0x32 /r"/"RM" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2751 Instruction:"XOR Gv,Ev" Encoding:"0x33 /r"/"RM" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_G, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2752 Instruction:"XOR AL,Ib" Encoding:"0x34 ib"/"I" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2753 Instruction:"XOR rAX,Iz" Encoding:"0x35 iz"/"I" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, 0, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_GPR_rAX, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2754 Instruction:"XOR Eb,Ib" Encoding:"0x80 /6 ib"/"MI" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2755 Instruction:"XOR Ev,Iz" Encoding:"0x81 /6 iz"/"MI" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_z, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2756 Instruction:"XOR Eb,Ib" Encoding:"0x82 /6 iz"/"MI" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_R0|ND_MOD_R1|ND_MOD_R2|ND_MOD_R3|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_I64, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_b, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2757 Instruction:"XOR Ev,Ib" Encoding:"0x83 /6 ib"/"MI" - { - ND_INS_XOR, ND_CAT_LOGIC, ND_SET_I86, 1729, - ND_PREF_HLE|ND_PREF_LOCK, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0|NDR_RFLAG_PF|NDR_RFLAG_ZF|NDR_RFLAG_SF, - 0|NDR_RFLAG_AF, - 0|NDR_RFLAG_CF|NDR_RFLAG_OF|NDR_RFLAG_AF, - { - OP(ND_OPT_E, ND_OPS_v, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_I, ND_OPS_b, ND_OPF_SEX_OP1, ND_OPA_R, 0, 0), - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2758 Instruction:"XORPD Vpd,Wpd" Encoding:"0x66 0x0F 0x57 /r"/"RM" - { - ND_INS_XORPD, ND_CAT_LOGICAL_FP, ND_SET_SSE2, 1730, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE2, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_pd, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_pd, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2759 Instruction:"XORPS Vps,Wps" Encoding:"NP 0x0F 0x57 /r"/"RM" - { - ND_INS_XORPS, ND_CAT_LOGICAL_FP, ND_SET_SSE, 1731, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(2, 0), 0, ND_EXT_4, ND_EXC_SSE_AVX, 0, 0, 0, ND_FLAG_MODRM|ND_FLAG_VECTOR, ND_CFF_SSE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_V, ND_OPS_ps, 0, ND_OPA_RW, 0, 0), - OP(ND_OPT_W, ND_OPS_ps, 0, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2760 Instruction:"XRESLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE9"/"" - { - ND_INS_XRESLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1732, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2761 Instruction:"XRSTOR M?" Encoding:"NP 0x0F 0xAE /5:mem"/"M" - { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1733, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2762 Instruction:"XRSTOR64 M?" Encoding:"rexw NP 0x0F 0xAE /5:mem"/"M" - { - ND_INS_XRSTOR, ND_CAT_XSAVE, ND_SET_XSAVE, 1734, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2763 Instruction:"XRSTORS M?" Encoding:"NP 0x0F 0xC7 /3:mem"/"M" - { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1735, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2764 Instruction:"XRSTORS64 M?" Encoding:"rexw NP 0x0F 0xC7 /3:mem"/"M" - { - ND_INS_XRSTORS, ND_CAT_XSAVE, ND_SET_XSAVES, 1736, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2765 Instruction:"XSAVE M?" Encoding:"NP 0x0F 0xAE /4:mem"/"M" - { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1737, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2766 Instruction:"XSAVE64 M?" Encoding:"rexw NP 0x0F 0xAE /4:mem"/"M" - { - ND_INS_XSAVE, ND_CAT_XSAVE, ND_SET_XSAVE, 1738, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2767 Instruction:"XSAVEC M?" Encoding:"NP 0x0F 0xC7 /4:mem"/"M" - { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1739, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2768 Instruction:"XSAVEC64 M?" Encoding:"rexw NP 0x0F 0xC7 /4:mem"/"M" - { - ND_INS_XSAVEC, ND_CAT_XSAVE, ND_SET_XSAVEC, 1740, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVEC, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2769 Instruction:"XSAVEOPT M?" Encoding:"NP 0x0F 0xAE /6:mem"/"M" - { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1741, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2770 Instruction:"XSAVEOPT64 M?" Encoding:"rexw NP 0x0F 0xAE /6:mem"/"M" - { - ND_INS_XSAVEOPT, ND_CAT_XSAVE, ND_SET_XSAVE, 1742, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2771 Instruction:"XSAVES M?" Encoding:"NP 0x0F 0xC7 /5:mem"/"M" - { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1743, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2772 Instruction:"XSAVES64 M?" Encoding:"rexw NP 0x0F 0xC7 /5:mem"/"M" - { - ND_INS_XSAVES, ND_CAT_XSAVE, ND_SET_XSAVES, 1744, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(1, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVES, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_M, ND_OPS_unknown, 0, ND_OPA_W, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR_0, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_REG_BANK, ND_OPS_unknown, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - }, - }, - - // Pos:2773 Instruction:"XSETBV" Encoding:"NP 0x0F 0x01 /0xD1"/"" - { - ND_INS_XSETBV, ND_CAT_XSAVE, ND_SET_XSAVE, 1745, - 0, - ND_MOD_R0|ND_MOD_REAL|ND_MOD_V8086|ND_MOD_PROT|ND_MOD_COMPAT|ND_MOD_LONG|ND_MOD_VMXR|ND_MOD_VMXN|ND_MOD_VMXR_SEAM|ND_MOD_VMXN_SEAM|ND_MOD_VMX_OFF|ND_MOD_SMM|ND_MOD_SMM_OFF|ND_MOD_SGX_OFF|ND_MOD_TSX|ND_MOD_TSX_OFF, - 0, ND_OPS_CNT(0, 4), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_XSAVE, - 0, - 0, - 0, - 0, - { - OP(ND_OPT_GPR_rCX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rDX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_GPR_rAX, ND_OPS_d, ND_OPF_DEFAULT, ND_OPA_R, 0, 0), - OP(ND_OPT_XCR, ND_OPS_q, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - // Pos:2774 Instruction:"XSHA1" Encoding:"0xF3 0x0F 0xA6 /0xC8"/"" - { - ND_INS_XSHA1, ND_CAT_PADLOCK, ND_SET_CYRIX, 1746, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2775 Instruction:"XSHA256" Encoding:"0xF3 0x0F 0xA6 /0xD0"/"" - { - ND_INS_XSHA256, ND_CAT_PADLOCK, ND_SET_CYRIX, 1747, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2776 Instruction:"XSTORE" Encoding:"0x0F 0xA7 /0xC0"/"" - { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2777 Instruction:"XSTORE" Encoding:"0xF3 0x0F 0xA7 /0xC0"/"" - { - ND_INS_XSTORE, ND_CAT_PADLOCK, ND_SET_CYRIX, 1748, - ND_PREF_REP, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, 0, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2778 Instruction:"XSUSLDTRK" Encoding:"0xF2 0x0F 0x01 /0xE8"/"" - { - ND_INS_XSUSLDTRK, ND_CAT_MISC, ND_SET_TSXLDTRK, 1749, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_TSXLDTRK, - 0, - 0, - 0, - 0, - { - 0 - }, - }, - - // Pos:2779 Instruction:"XTEST" Encoding:"NP 0x0F 0x01 /0xD6"/"" - { - ND_INS_XTEST, ND_CAT_LOGIC, ND_SET_TSX, 1750, - 0, - ND_MOD_ANY, - 0, ND_OPS_CNT(0, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_RTM, - 0, - 0|NDR_RFLAG_ZF, - 0, - 0|NDR_RFLAG_CF|NDR_RFLAG_PF|NDR_RFLAG_AF|NDR_RFLAG_SF|NDR_RFLAG_OF, - { - OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT, ND_OPA_W, 0, 0), - }, - }, - - -}; - -#endif diff --git a/bddisasm/include/table_evex.h b/bddisasm/include/table_evex.h deleted file mode 100644 index e9ffc31..0000000 --- a/bddisasm/include/table_evex.h +++ /dev/null @@ -1,15250 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ - -// -// This file was auto-generated by generate_tables.py. DO NOT MODIFY! -// - -#ifndef TABLE_EVEX_H -#define TABLE_EVEX_H - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_03_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1400] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9a_03_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_9a_03_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_9a_03_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_9a_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_9a_03_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1684] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1687] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9a_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9a_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9a_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_9a_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_03_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1401] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9b_03_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_9b_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_9b_03_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1689] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1692] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9b_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9b_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_9b_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_03_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1402] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_aa_03_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_aa_03_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_aa_03_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_aa_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_aa_03_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1694] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_aa_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1697] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_aa_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_aa_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_aa_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_aa_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_aa_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_aa_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_03_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1403] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ab_03_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_ab_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_ab_03_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1699] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ab_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1702] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ab_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ab_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ab_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ab_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ab_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_ab_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_de_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1416] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_de_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_de_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_df_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1418] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_df_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_df_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_dc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1420] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_dc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_dc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_dd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1422] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_dd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_dd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1438] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_65_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1439] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_65_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_65_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_65_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_65_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_65_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1445] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_19_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1456] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_19_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_19_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_19_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_19_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_19_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1446] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1a_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1448] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_1a_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_1a_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_1a_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_1a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_1a_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1447] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1b_01_mem_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1449] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_1b_01_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_1b_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_1b_01_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_1b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_1b_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1451] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_59_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2110] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_59_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_59_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_59_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_59_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_59_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1452] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_5a_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1454] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_5a_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_5a_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_5a_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_5a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_5a_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_5a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_5a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1453] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_5b_01_mem_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1455] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_5b_01_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_5b_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_5b_01_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_5b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_5b_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_5b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_5b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_18_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1458] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_18_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_18_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_18_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_18_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1475] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1476] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_8a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_8a_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_8a_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_8a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_8a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1483] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_72_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_72_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1488] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_72_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_72_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_72_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2480] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_72_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_72_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_72_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_72_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_72_02_w, - /* 03 */ (const void *)&gEvexTable_root_02_72_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1501] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_13_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_13_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_13_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2378] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_13_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_13_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_13_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_13_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_13_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1594] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_52_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_52_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_03_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2050] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_52_03_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_52_03_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_52_03_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_52_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_52_03_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_52_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2172] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_52_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_52_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_52_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_52_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_52_02_w, - /* 03 */ (const void *)&gEvexTable_root_02_52_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1599] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c8_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1600] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c8_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c8_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c8_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c8_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c8_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_c8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c8_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1601] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_88_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1602] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_88_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_88_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_88_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_88_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_88_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1625] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_98_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1628] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_98_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_98_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_98_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_98_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_98_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1630] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_99_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1633] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_99_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_99_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_99_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_99_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_99_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1635] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1638] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a8_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a8_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1640] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1643] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a9_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a9_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1645] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1648] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_b8_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_b8_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1650] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1653] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_b9_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_b9_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1665] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_96_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1668] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_96_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_96_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_96_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_96_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_96_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1670] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1673] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a6_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a6_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1675] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1678] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_b6_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_b6_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1704] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ba_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1707] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ba_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ba_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ba_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ba_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ba_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1709] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bb_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1712] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_bb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_bb_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_bb_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_bb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_bb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1714] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_97_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1717] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_97_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_97_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_97_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_97_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_97_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1719] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1722] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a7_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a7_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1724] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1727] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_b7_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_b7_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1743] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1746] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9c_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1748] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1751] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1753] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ac_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1756] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ac_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ac_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ac_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ac_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ac_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1758] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ad_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1761] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ad_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ad_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ad_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ad_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ad_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1763] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bc_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1766] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_bc_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_bc_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_bc_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_bc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_bc_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1768] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bd_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1771] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_bd_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_bd_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_bd_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_bd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_bd_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1781] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1784] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9e_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1786] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_9f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1789] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_9f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_9f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_9f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_9f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_9f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1791] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ae_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1794] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ae_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ae_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ae_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ae_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ae_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1796] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_af_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1799] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_af_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_af_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_af_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_af_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_af_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1801] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_be_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1804] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_be_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_be_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_be_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_be_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_be_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1806] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_bf_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1809] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_bf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_bf_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_bf_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_bf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_bf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1829] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_92_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1831] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_92_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_92_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_92_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_92_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_92_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_92_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_92_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1833] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1834] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1837] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_02_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1838] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_02_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2644] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_05_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2645] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_05_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_05_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2648] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c6_01_mem_06_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2649] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c6_01_mem_06_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c6_01_mem_06_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gEvexTable_root_02_c6_01_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_mem_01_l, - /* 02 */ (const void *)&gEvexTable_root_02_c6_01_mem_02_l, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gEvexTable_root_02_c6_01_mem_05_l, - /* 06 */ (const void *)&gEvexTable_root_02_c6_01_mem_06_l, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_c6_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_c6_01_mem_modrmreg, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_c6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c6_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1835] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1836] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1839] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_02_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1840] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_02_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2646] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_05_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2647] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_05_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_05_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2650] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c7_01_mem_06_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2651] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c7_01_mem_06_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_c7_01_mem_06_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gEvexTable_root_02_c7_01_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_mem_01_l, - /* 02 */ (const void *)&gEvexTable_root_02_c7_01_mem_02_l, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gEvexTable_root_02_c7_01_mem_05_l, - /* 06 */ (const void *)&gEvexTable_root_02_c7_01_mem_06_l, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_c7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_c7_01_mem_modrmreg, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_c7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1841] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_93_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1843] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_93_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_93_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_93_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_93_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_93_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_93_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_93_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1845] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_42_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1847] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_42_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_42_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_42_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_42_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_42_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1848] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_43_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1850] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_43_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_43_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_43_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_43_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_43_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cf_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1861] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_cf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_cf_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_cf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_cf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1974] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_2a_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_2a_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2a_02_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2108] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_2a_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_2a_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2a_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_2a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2a_01_modrmmod, - /* 02 */ (const void *)&gEvexTable_root_02_2a_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2048] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_68_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2049] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_68_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_68_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_68_03_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_68_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_68_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_03_mem_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2051] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_53_03_mem_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_53_03_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_53_03_mem_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_53_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_53_03_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_53_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2174] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_53_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_53_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_53_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_53_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_02_53_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2052] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2054] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_1e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_1e_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2056] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_1f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_1d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2057] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_1d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_1d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2063] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_2b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_2b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_2b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2096] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_66_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2099] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_66_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_66_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_66_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_66_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_66_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2097] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_64_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2098] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_64_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_64_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_64_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_64_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_64_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_78_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2102] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_78_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_78_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_78_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_78_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7a_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2103] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7a_01_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_7a_01_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_7a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7a_01_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_58_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2105] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_58_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_58_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_58_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_58_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2106] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7c_01_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2111] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7c_01_reg_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_02_7c_01_reg_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_7c_01_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_7c_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7c_01_reg_wi, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7c_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2109] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_3a_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_3a_02_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_3a_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3a_02_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2338] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3a_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_3a_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_79_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2113] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_79_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_79_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_79_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_79_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7b_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2114] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7b_01_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_7b_01_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_7b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7b_01_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2126] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_29_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_29_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2340] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_29_02_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2383] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_29_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_29_02_reg_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_29_02_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_29_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_29_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_29_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_29_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_29_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_37_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2136] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_37_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_37_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_37_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_37_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2150] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_63_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2153] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_63_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_63_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_63_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_63_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_63_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2151] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2152] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_8b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_8b_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_8b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_8b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_8b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2160] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_c4_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2161] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_c4_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_c4_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_c4_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_c4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_c4_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_50_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2166] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_50_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_50_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_50_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_50_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_51_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2168] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_51_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_51_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_51_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2184] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2221] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_8d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_8d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_8d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_8d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_8d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2185] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_36_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2212] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_36_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_36_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_36_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_36_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_36_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2187] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_75_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2192] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_75_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_75_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_75_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_75_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_75_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2188] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_76_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2191] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_76_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_76_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_76_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_76_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_76_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2189] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_77_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2190] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_77_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_77_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_77_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_77_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_77_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_0d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2197] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_0d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_0d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_0d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_0d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_0c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2201] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_0c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_0c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_0c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_0c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2205] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2209] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_16_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_16_01_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_16_01_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2206] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_16_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2210] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_16_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_16_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_16_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_16_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_16_01_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_16_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_16_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2215] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2220] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_7d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_7d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2216] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2219] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_7e_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_7e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2217] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_7f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2218] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_7f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_7f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_7f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_7f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_7f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2222] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_62_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2225] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_62_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_62_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_62_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_62_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_62_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2223] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_89_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2224] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_89_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_89_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_89_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_89_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_89_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2244] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_90_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2246] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_90_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_90_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_90_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_90_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_90_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_90_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_90_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2248] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_91_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2250] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_91_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_91_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_91_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_91_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_91_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_91_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_91_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2286] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_44_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2287] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_44_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_44_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_44_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_44_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_44_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b5_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2300] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b5_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b5_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b5_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_b4_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2302] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_b4_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b4_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_b4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_b4_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2304] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_04_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_04_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2312] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2314] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2316] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_3d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_3d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_3d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2321] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2323] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_3f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_3f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_3f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2324] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3e_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2326] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2345] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_38_02_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2346] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_38_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_38_02_reg_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_38_02_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_38_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_38_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_38_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_38_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_38_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2328] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2330] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_39_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_39_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_39_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2341] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_39_02_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2349] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_39_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_39_02_reg_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_39_02_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_39_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_39_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_39_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_39_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_39_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2335] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_3b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2337] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_3b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_3b_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_3b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_3b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_3b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2342] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_31_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_31_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_31_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2385] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_31_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_31_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_31_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2343] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_33_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_33_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_33_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2397] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_33_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_33_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_33_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2344] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_02_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2347] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_28_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_28_02_reg_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_28_02_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_28_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_28_02_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_28_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2403] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_28_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_28_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_28_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_28_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_28_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2350] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_32_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_32_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_32_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2388] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_32_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_32_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_32_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2351] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_35_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_35_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_35_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2394] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_35_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_35_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_35_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_35_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_35_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2352] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_34_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_34_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_34_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2400] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_34_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_34_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_34_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2353] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_21_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_21_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_21_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2359] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_21_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_21_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_21_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2354] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_23_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_23_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_23_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2371] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_23_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_23_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_23_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2355] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_22_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_22_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_22_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2362] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_22_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_22_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_22_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2356] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_25_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_25_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_25_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2368] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_25_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_25_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_25_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_25_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_25_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2357] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_24_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_24_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_24_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2374] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_24_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_24_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_24_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2358] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_20_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_20_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_20_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2365] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_20_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_20_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_20_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2377] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_11_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_11_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_11_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2522] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_11_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_11_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_11_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_11_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_11_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2379] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_12_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_12_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_12_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2508] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_12_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_12_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_12_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_12_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_12_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2380] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_15_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_15_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2430] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_15_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2431] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_15_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_15_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_15_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_15_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_15_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_15_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2381] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_14_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_14_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2434] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_14_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2435] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_14_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_14_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_14_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_14_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_14_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_14_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2382] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_10_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_10_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_10_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2541] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_10_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_10_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_10_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_10_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_10_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2384] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_30_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_30_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_30_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2391] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_30_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_30_01_leaf, - /* 02 */ (const void *)&gEvexTable_root_02_30_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_0b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2405] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_0b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_0b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2411] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_40_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2413] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_40_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_40_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_40_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_40_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_40_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_83_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2416] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_83_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_83_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_83_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_83_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2419] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_54_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2422] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_54_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_54_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_54_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_54_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_54_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2420] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_55_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2421] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_55_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_55_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_55_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_55_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_55_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2450] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a0_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2451] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a0_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a0_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a0_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_a0_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_a0_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a0_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2452] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a1_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2453] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a1_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a1_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a1_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_a1_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_a1_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a1_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2469] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_71_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2470] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_71_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_71_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_71_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_71_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_71_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_70_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2471] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_70_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_70_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_70_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_70_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2478] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_73_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2479] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_73_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_73_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_73_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_73_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_73_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2482] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_00_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_00_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_8f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2484] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_8f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_8f_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_8f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_8f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2504] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_47_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2506] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_47_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_47_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_47_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_47_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_47_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2519] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_46_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2521] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_46_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_46_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_46_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_46_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_46_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2537] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_45_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2539] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_45_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_45_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_45_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_45_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_45_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2565] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2568] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_26_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_26_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_26_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2569] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_26_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2572] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_26_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_26_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_26_02_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_26_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_26_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_26_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2566] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2567] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_27_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_27_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_27_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2570] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_27_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2571] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_27_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_27_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_27_02_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_27_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_27_01_w, - /* 02 */ (const void *)&gEvexTable_root_02_27_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2596] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2597] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_4c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_4c_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_4c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_4c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_4c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2598] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2599] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_4d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_4d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_4d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_4d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_4d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2600] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_ca_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2601] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_ca_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_ca_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_ca_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_ca_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_ca_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_ca_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_ca_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2602] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cb_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2603] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_cb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_cb_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_cb_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_cb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_cb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2624] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2625] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_4e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_4e_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_4e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_4e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_4e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2626] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_4f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2627] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_4f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_4f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_4f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_4f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_4f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2628] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cc_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2629] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_cc_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_cc_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_cc_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_02_cc_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_02_cc_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_cc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_cc_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2630] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_cd_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2631] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_cd_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_cd_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_cd_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_cd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_cd_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2636] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2638] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_2c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_2c_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_2c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2639] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_2d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2641] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_2d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_2d_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_2d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_2d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2642] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a2_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2643] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a2_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a2_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a2_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_a2_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_a2_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a2_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2652] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_02_a3_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2653] -}; - -const ND_TABLE_VEX_W gEvexTable_root_02_a3_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_02_a3_01_mem_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_02_a3_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_02_a3_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_02_a3_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_02_a3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_02_a3_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gEvexTable_root_02_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gEvexTable_root_02_00_pp, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gEvexTable_root_02_04_pp, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ (const void *)&gEvexTable_root_02_0b_pp, - /* 0c */ (const void *)&gEvexTable_root_02_0c_pp, - /* 0d */ (const void *)&gEvexTable_root_02_0d_pp, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gEvexTable_root_02_10_pp, - /* 11 */ (const void *)&gEvexTable_root_02_11_pp, - /* 12 */ (const void *)&gEvexTable_root_02_12_pp, - /* 13 */ (const void *)&gEvexTable_root_02_13_pp, - /* 14 */ (const void *)&gEvexTable_root_02_14_pp, - /* 15 */ (const void *)&gEvexTable_root_02_15_pp, - /* 16 */ (const void *)&gEvexTable_root_02_16_pp, - /* 17 */ ND_NULL, - /* 18 */ (const void *)&gEvexTable_root_02_18_pp, - /* 19 */ (const void *)&gEvexTable_root_02_19_pp, - /* 1a */ (const void *)&gEvexTable_root_02_1a_pp, - /* 1b */ (const void *)&gEvexTable_root_02_1b_pp, - /* 1c */ (const void *)&gEvexTable_root_02_1c_pp, - /* 1d */ (const void *)&gEvexTable_root_02_1d_pp, - /* 1e */ (const void *)&gEvexTable_root_02_1e_pp, - /* 1f */ (const void *)&gEvexTable_root_02_1f_pp, - /* 20 */ (const void *)&gEvexTable_root_02_20_pp, - /* 21 */ (const void *)&gEvexTable_root_02_21_pp, - /* 22 */ (const void *)&gEvexTable_root_02_22_pp, - /* 23 */ (const void *)&gEvexTable_root_02_23_pp, - /* 24 */ (const void *)&gEvexTable_root_02_24_pp, - /* 25 */ (const void *)&gEvexTable_root_02_25_pp, - /* 26 */ (const void *)&gEvexTable_root_02_26_pp, - /* 27 */ (const void *)&gEvexTable_root_02_27_pp, - /* 28 */ (const void *)&gEvexTable_root_02_28_pp, - /* 29 */ (const void *)&gEvexTable_root_02_29_pp, - /* 2a */ (const void *)&gEvexTable_root_02_2a_pp, - /* 2b */ (const void *)&gEvexTable_root_02_2b_pp, - /* 2c */ (const void *)&gEvexTable_root_02_2c_pp, - /* 2d */ (const void *)&gEvexTable_root_02_2d_pp, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ (const void *)&gEvexTable_root_02_30_pp, - /* 31 */ (const void *)&gEvexTable_root_02_31_pp, - /* 32 */ (const void *)&gEvexTable_root_02_32_pp, - /* 33 */ (const void *)&gEvexTable_root_02_33_pp, - /* 34 */ (const void *)&gEvexTable_root_02_34_pp, - /* 35 */ (const void *)&gEvexTable_root_02_35_pp, - /* 36 */ (const void *)&gEvexTable_root_02_36_pp, - /* 37 */ (const void *)&gEvexTable_root_02_37_pp, - /* 38 */ (const void *)&gEvexTable_root_02_38_pp, - /* 39 */ (const void *)&gEvexTable_root_02_39_pp, - /* 3a */ (const void *)&gEvexTable_root_02_3a_pp, - /* 3b */ (const void *)&gEvexTable_root_02_3b_pp, - /* 3c */ (const void *)&gEvexTable_root_02_3c_pp, - /* 3d */ (const void *)&gEvexTable_root_02_3d_pp, - /* 3e */ (const void *)&gEvexTable_root_02_3e_pp, - /* 3f */ (const void *)&gEvexTable_root_02_3f_pp, - /* 40 */ (const void *)&gEvexTable_root_02_40_pp, - /* 41 */ ND_NULL, - /* 42 */ (const void *)&gEvexTable_root_02_42_pp, - /* 43 */ (const void *)&gEvexTable_root_02_43_pp, - /* 44 */ (const void *)&gEvexTable_root_02_44_pp, - /* 45 */ (const void *)&gEvexTable_root_02_45_pp, - /* 46 */ (const void *)&gEvexTable_root_02_46_pp, - /* 47 */ (const void *)&gEvexTable_root_02_47_pp, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ (const void *)&gEvexTable_root_02_4c_pp, - /* 4d */ (const void *)&gEvexTable_root_02_4d_pp, - /* 4e */ (const void *)&gEvexTable_root_02_4e_pp, - /* 4f */ (const void *)&gEvexTable_root_02_4f_pp, - /* 50 */ (const void *)&gEvexTable_root_02_50_pp, - /* 51 */ (const void *)&gEvexTable_root_02_51_pp, - /* 52 */ (const void *)&gEvexTable_root_02_52_pp, - /* 53 */ (const void *)&gEvexTable_root_02_53_pp, - /* 54 */ (const void *)&gEvexTable_root_02_54_pp, - /* 55 */ (const void *)&gEvexTable_root_02_55_pp, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ (const void *)&gEvexTable_root_02_58_pp, - /* 59 */ (const void *)&gEvexTable_root_02_59_pp, - /* 5a */ (const void *)&gEvexTable_root_02_5a_pp, - /* 5b */ (const void *)&gEvexTable_root_02_5b_pp, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ (const void *)&gEvexTable_root_02_62_pp, - /* 63 */ (const void *)&gEvexTable_root_02_63_pp, - /* 64 */ (const void *)&gEvexTable_root_02_64_pp, - /* 65 */ (const void *)&gEvexTable_root_02_65_pp, - /* 66 */ (const void *)&gEvexTable_root_02_66_pp, - /* 67 */ ND_NULL, - /* 68 */ (const void *)&gEvexTable_root_02_68_pp, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ (const void *)&gEvexTable_root_02_70_pp, - /* 71 */ (const void *)&gEvexTable_root_02_71_pp, - /* 72 */ (const void *)&gEvexTable_root_02_72_pp, - /* 73 */ (const void *)&gEvexTable_root_02_73_pp, - /* 74 */ ND_NULL, - /* 75 */ (const void *)&gEvexTable_root_02_75_pp, - /* 76 */ (const void *)&gEvexTable_root_02_76_pp, - /* 77 */ (const void *)&gEvexTable_root_02_77_pp, - /* 78 */ (const void *)&gEvexTable_root_02_78_pp, - /* 79 */ (const void *)&gEvexTable_root_02_79_pp, - /* 7a */ (const void *)&gEvexTable_root_02_7a_pp, - /* 7b */ (const void *)&gEvexTable_root_02_7b_pp, - /* 7c */ (const void *)&gEvexTable_root_02_7c_pp, - /* 7d */ (const void *)&gEvexTable_root_02_7d_pp, - /* 7e */ (const void *)&gEvexTable_root_02_7e_pp, - /* 7f */ (const void *)&gEvexTable_root_02_7f_pp, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ (const void *)&gEvexTable_root_02_83_pp, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ (const void *)&gEvexTable_root_02_88_pp, - /* 89 */ (const void *)&gEvexTable_root_02_89_pp, - /* 8a */ (const void *)&gEvexTable_root_02_8a_pp, - /* 8b */ (const void *)&gEvexTable_root_02_8b_pp, - /* 8c */ ND_NULL, - /* 8d */ (const void *)&gEvexTable_root_02_8d_pp, - /* 8e */ ND_NULL, - /* 8f */ (const void *)&gEvexTable_root_02_8f_pp, - /* 90 */ (const void *)&gEvexTable_root_02_90_pp, - /* 91 */ (const void *)&gEvexTable_root_02_91_pp, - /* 92 */ (const void *)&gEvexTable_root_02_92_pp, - /* 93 */ (const void *)&gEvexTable_root_02_93_pp, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ (const void *)&gEvexTable_root_02_96_pp, - /* 97 */ (const void *)&gEvexTable_root_02_97_pp, - /* 98 */ (const void *)&gEvexTable_root_02_98_pp, - /* 99 */ (const void *)&gEvexTable_root_02_99_pp, - /* 9a */ (const void *)&gEvexTable_root_02_9a_pp, - /* 9b */ (const void *)&gEvexTable_root_02_9b_pp, - /* 9c */ (const void *)&gEvexTable_root_02_9c_pp, - /* 9d */ (const void *)&gEvexTable_root_02_9d_pp, - /* 9e */ (const void *)&gEvexTable_root_02_9e_pp, - /* 9f */ (const void *)&gEvexTable_root_02_9f_pp, - /* a0 */ (const void *)&gEvexTable_root_02_a0_pp, - /* a1 */ (const void *)&gEvexTable_root_02_a1_pp, - /* a2 */ (const void *)&gEvexTable_root_02_a2_pp, - /* a3 */ (const void *)&gEvexTable_root_02_a3_pp, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ (const void *)&gEvexTable_root_02_a6_pp, - /* a7 */ (const void *)&gEvexTable_root_02_a7_pp, - /* a8 */ (const void *)&gEvexTable_root_02_a8_pp, - /* a9 */ (const void *)&gEvexTable_root_02_a9_pp, - /* aa */ (const void *)&gEvexTable_root_02_aa_pp, - /* ab */ (const void *)&gEvexTable_root_02_ab_pp, - /* ac */ (const void *)&gEvexTable_root_02_ac_pp, - /* ad */ (const void *)&gEvexTable_root_02_ad_pp, - /* ae */ (const void *)&gEvexTable_root_02_ae_pp, - /* af */ (const void *)&gEvexTable_root_02_af_pp, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ (const void *)&gEvexTable_root_02_b4_pp, - /* b5 */ (const void *)&gEvexTable_root_02_b5_pp, - /* b6 */ (const void *)&gEvexTable_root_02_b6_pp, - /* b7 */ (const void *)&gEvexTable_root_02_b7_pp, - /* b8 */ (const void *)&gEvexTable_root_02_b8_pp, - /* b9 */ (const void *)&gEvexTable_root_02_b9_pp, - /* ba */ (const void *)&gEvexTable_root_02_ba_pp, - /* bb */ (const void *)&gEvexTable_root_02_bb_pp, - /* bc */ (const void *)&gEvexTable_root_02_bc_pp, - /* bd */ (const void *)&gEvexTable_root_02_bd_pp, - /* be */ (const void *)&gEvexTable_root_02_be_pp, - /* bf */ (const void *)&gEvexTable_root_02_bf_pp, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ (const void *)&gEvexTable_root_02_c4_pp, - /* c5 */ ND_NULL, - /* c6 */ (const void *)&gEvexTable_root_02_c6_pp, - /* c7 */ (const void *)&gEvexTable_root_02_c7_pp, - /* c8 */ (const void *)&gEvexTable_root_02_c8_pp, - /* c9 */ ND_NULL, - /* ca */ (const void *)&gEvexTable_root_02_ca_pp, - /* cb */ (const void *)&gEvexTable_root_02_cb_pp, - /* cc */ (const void *)&gEvexTable_root_02_cc_pp, - /* cd */ (const void *)&gEvexTable_root_02_cd_pp, - /* ce */ ND_NULL, - /* cf */ (const void *)&gEvexTable_root_02_cf_pp, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ (const void *)&gEvexTable_root_02_dc_pp, - /* dd */ (const void *)&gEvexTable_root_02_dd_pp, - /* de */ (const void *)&gEvexTable_root_02_de_pp, - /* df */ (const void *)&gEvexTable_root_02_df_pp, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1404] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_58_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_58_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1407] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_58_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_58_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1409] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_58_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_58_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_58_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1412] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_58_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_58_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_58_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_58_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_58_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_58_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_58_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1428] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_55_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_55_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_55_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1430] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_55_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_55_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_55_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_55_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_55_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1432] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_54_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_54_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_54_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1434] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_54_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_54_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_54_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_54_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_54_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1460] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c2_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c2_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1463] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c2_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_c2_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1465] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c2_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c2_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c2_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1468] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c2_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_c2_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_c2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_c2_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_c2_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_c2_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_c2_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1470] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_2f_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2f_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1473] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2f_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_2f_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_2f_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_2f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1477] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1522] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_e6_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_e6_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_e6_02_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1490] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_e6_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e6_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1547] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_e6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e6_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e6_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_e6_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_e6_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1481] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1524] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5b_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5b_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_5b_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1510] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5b_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1558] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5b_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5b_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5b_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5b_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5b_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1493] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5a_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1512] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5a_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5a_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1528] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5a_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5a_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5a_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1541] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5a_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5a_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5a_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5a_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5a_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_5a_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1496] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1519] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7b_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7b_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1577] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1578] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7b_03_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_01_7b_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7b_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7b_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1580] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_7b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_7b_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_7b_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_7b_03_wi, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1497] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1520] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_79_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_79_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_79_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1498] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1521] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_79_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_79_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_79_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1530] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_79_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1546] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_79_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_79_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_79_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_79_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_79_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1526] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2d_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1544] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_01_2d_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_2d_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1535] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1536] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2a_03_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_01_2a_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_2a_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2a_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1539] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_01_2a_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_2a_03_wi, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1549] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1560] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7a_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7a_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1571] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1574] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7a_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7a_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7a_02_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1573] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7a_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1576] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7a_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7a_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7a_03_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_7a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_7a_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_7a_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_7a_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1550] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1561] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_78_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_78_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_78_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1551] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1562] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_78_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_78_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_78_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1565] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_78_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1570] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_78_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_78_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_78_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_78_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_78_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1563] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2c_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1568] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_01_2c_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_2c_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1584] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5e_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1587] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5e_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5e_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1589] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5e_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5e_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5e_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1592] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5e_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5e_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5e_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5e_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5e_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_5e_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1888] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5f_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1891] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5f_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5f_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1893] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5f_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5f_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5f_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1896] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5f_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5f_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5f_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5f_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5f_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_5f_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1903] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5d_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1906] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5d_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5d_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1908] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5d_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5d_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5d_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1911] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5d_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5d_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5d_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5d_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5d_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_5d_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1917] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_28_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_28_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_28_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1921] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_28_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_28_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_28_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_28_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_28_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1918] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_29_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_29_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_29_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1922] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_29_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_29_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_29_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_29_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_29_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1925] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6e_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1980] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6e_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_01_6e_01_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_6e_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_6e_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_6e_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6e_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1926] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1981] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7e_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_01_7e_01_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7e_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_7e_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_7e_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7e_02_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1982] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7e_02_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_7e_02_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_7e_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_7e_02_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_7e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_7e_01_l, - /* 02 */ (const void *)&gEvexTable_root_01_7e_02_l, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1929] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_03_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_12_03_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1930] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_03_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_03_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1931] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_03_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_12_03_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_12_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_03_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_12_03_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_12_03_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1950] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_12_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1966] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_12_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_mem_l, - /* 01 */ (const void *)&gEvexTable_root_01_12_00_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1962] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_12_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_12_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_12_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_12_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2002] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_12_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_12_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_12_00_modrmmod, - /* 01 */ (const void *)&gEvexTable_root_01_12_01_modrmmod, - /* 02 */ (const void *)&gEvexTable_root_01_12_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_12_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1936] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1938] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_6f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_6f_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1942] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1948] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6f_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_6f_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_6f_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1944] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6f_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1946] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6f_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_6f_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_6f_02_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6f_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_6f_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_6f_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1937] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1939] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7f_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1943] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1949] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7f_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7f_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7f_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1945] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_7f_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1947] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_7f_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_7f_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_7f_02_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_7f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_7f_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_7f_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_7f_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1952] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_16_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_16_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_16_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1956] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_16_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_16_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1960] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_16_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_16_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_16_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_mem_l, - /* 01 */ (const void *)&gEvexTable_root_01_16_00_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_16_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2000] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_16_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_16_00_modrmmod, - /* 01 */ (const void *)&gEvexTable_root_01_16_01_modrmmod, - /* 02 */ (const void *)&gEvexTable_root_01_16_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1953] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_17_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_17_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_17_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_17_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1957] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_17_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_17_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_17_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_00_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_17_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_17_00_modrmmod, - /* 01 */ (const void *)&gEvexTable_root_01_17_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1963] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_13_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_13_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_13_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_13_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1967] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_13_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_13_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_13_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_00_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_13_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_13_00_modrmmod, - /* 01 */ (const void *)&gEvexTable_root_01_13_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e7_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1972] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_e7_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_e7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_e7_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1976] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2b_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_2b_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_2b_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2b_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1978] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2b_00_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_2b_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_2b_00_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_2b_00_modrmmod, - /* 01 */ (const void *)&gEvexTable_root_01_2b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d6_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1983] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_d6_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d6_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_d6_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_d6_01_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d6_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1988] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_03_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_10_03_mem_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_03_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1989] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_03_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_10_03_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_03_mem_w, - /* 01 */ (const void *)&gEvexTable_root_01_10_03_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2004] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2005] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_02_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_10_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_02_mem_w, - /* 01 */ (const void *)&gEvexTable_root_01_10_02_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2012] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_10_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_10_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2016] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_10_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_10_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_10_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_10_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_10_02_modrmmod, - /* 03 */ (const void *)&gEvexTable_root_01_10_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1990] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_03_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_11_03_mem_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_03_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1991] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_03_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_11_03_reg_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_03_mem_w, - /* 01 */ (const void *)&gEvexTable_root_01_11_03_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2006] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2007] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_02_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_11_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_02_mem_w, - /* 01 */ (const void *)&gEvexTable_root_01_11_02_reg_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2013] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_11_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_11_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2017] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_11_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_11_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_11_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_11_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_11_02_modrmmod, - /* 03 */ (const void *)&gEvexTable_root_01_11_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2031] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_59_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_59_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2034] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_59_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_59_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2036] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_59_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_59_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_59_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2039] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_59_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_59_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_59_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_59_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_59_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_59_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_59_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2044] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_56_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_56_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_56_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2046] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_56_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_56_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_56_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_56_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_56_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2059] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_6b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_63_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2061] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_63_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_63_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_67_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2065] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_67_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_67_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_fc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2067] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_fc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_fe_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2069] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_fe_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_fe_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_fe_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fe_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d4_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2071] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_d4_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d4_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d4_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ec_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2073] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_ec_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_ec_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ed_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2075] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_ed_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_ed_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_dc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2077] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_dc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_dc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_dd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2079] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_dd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_dd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_fd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2081] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_fd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2086] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_db_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2090] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_db_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_db_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_db_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_db_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_db_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2088] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_df_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2089] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_df_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_df_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_df_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_df_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_df_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e0_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2091] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e0_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2093] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e3_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_74_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2122] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_74_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_74_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_76_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2124] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_76_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_76_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_75_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2128] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_75_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_75_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_64_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2132] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_64_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_64_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_66_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2134] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_66_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_66_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_66_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_66_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_65_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2138] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_65_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_65_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c5_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2238] -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_c5_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_c5_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_c5_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c5_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_c5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c5_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2282] -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_c4_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c4_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2283] -}; - -const ND_TABLE_VEX_L gEvexTable_root_01_c4_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_01_c4_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_01_c4_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_01_c4_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_01_c4_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_c4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c4_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2306] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ee_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2317] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_ee_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_ee_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_de_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2319] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_de_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_de_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ea_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2331] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_ea_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_ea_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_da_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2333] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_da_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_da_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e4_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2407] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e4_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2409] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2414] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f4_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2417] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_f4_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f4_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f4_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2424] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_eb_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2425] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_eb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_eb_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_eb_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_eb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_eb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2428] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2429] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_72_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_72_01_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2432] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2433] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_72_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_72_01_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_06_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2494] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_72_01_06_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_06_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2513] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2517] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_72_01_04_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_04_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_72_01_04_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_72_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2527] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_72_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gEvexTable_root_01_72_01_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gEvexTable_root_01_72_01_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_72_01_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_72_01_02_w, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gEvexTable_root_01_72_01_04_w, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gEvexTable_root_01_72_01_06_w, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_72_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_72_01_modrmreg, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f6_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2448] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f6_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2485] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_70_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_70_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2487] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_70_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2489] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_70_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_70_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_70_02_leaf, - /* 03 */ (const void *)&gEvexTable_root_01_70_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f2_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2495] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_f2_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_f2_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f2_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2498] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_06_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2500] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_73_01_06_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_73_01_06_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2531] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_73_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2533] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_73_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_73_01_02_01_leaf, - } -}; - -const ND_TABLE_MODRM_REG gEvexTable_root_01_73_01_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_01_73_01_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_73_01_03_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gEvexTable_root_01_73_01_06_w, - /* 07 */ (const void *)&gEvexTable_root_01_73_01_07_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_73_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_73_01_modrmreg, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f3_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2501] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_f3_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f3_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f3_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2509] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2523] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_71_01_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2542] -}; - -const ND_TABLE_MODRM_REG gEvexTable_root_01_71_01_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_01_71_01_02_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gEvexTable_root_01_71_01_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gEvexTable_root_01_71_01_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_71_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_71_01_modrmreg, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2510] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2514] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e2_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2518] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_e2_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_e2_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_e2_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e2_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2524] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d2_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2528] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_d2_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_d2_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d2_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d3_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2534] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_d3_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d3_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d3_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2543] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2546] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_fa_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2548] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_fa_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_fa_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_fa_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fa_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_fb_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2550] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_fb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fb_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_fb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_fb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2552] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_e9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2554] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_e9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_e9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2556] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_d9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2558] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_d9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_d9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_f9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2560] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_f9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_f9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_68_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2573] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_68_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_68_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2575] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_6a_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2577] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_69_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2579] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_69_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_69_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_60_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2581] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_60_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_60_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_62_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2583] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_62_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_62_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_62_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_62_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_6c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2585] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_6c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_6c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_6c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_61_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2587] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_61_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_61_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2590] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_ef_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2591] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_ef_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_ef_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_01_ef_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_ef_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_ef_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2661] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_c6_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_c6_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2663] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_c6_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_c6_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_c6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_c6_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_c6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2670] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_51_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_51_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2673] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_51_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_51_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2675] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_51_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_51_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_51_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2678] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_51_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_51_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_51_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_51_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_51_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_51_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2681] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5c_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2684] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5c_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5c_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2686] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5c_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_5c_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_5c_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2689] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_5c_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_5c_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_5c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_5c_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_5c_01_w, - /* 02 */ (const void *)&gEvexTable_root_01_5c_02_w, - /* 03 */ (const void *)&gEvexTable_root_01_5c_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2693] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_2e_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_2e_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2696] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_2e_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_2e_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_2e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_2e_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_2e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2698] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_15_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_15_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_15_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2700] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_15_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_15_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_15_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_15_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_15_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2702] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_14_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_14_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_14_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2704] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_14_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_14_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_14_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_14_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_14_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2706] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_57_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_57_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_01_57_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2708] -}; - -const ND_TABLE_VEX_W gEvexTable_root_01_57_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_01_57_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_01_57_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_01_57_00_w, - /* 01 */ (const void *)&gEvexTable_root_01_57_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gEvexTable_root_01_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gEvexTable_root_01_10_pp, - /* 11 */ (const void *)&gEvexTable_root_01_11_pp, - /* 12 */ (const void *)&gEvexTable_root_01_12_pp, - /* 13 */ (const void *)&gEvexTable_root_01_13_pp, - /* 14 */ (const void *)&gEvexTable_root_01_14_pp, - /* 15 */ (const void *)&gEvexTable_root_01_15_pp, - /* 16 */ (const void *)&gEvexTable_root_01_16_pp, - /* 17 */ (const void *)&gEvexTable_root_01_17_pp, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ (const void *)&gEvexTable_root_01_28_pp, - /* 29 */ (const void *)&gEvexTable_root_01_29_pp, - /* 2a */ (const void *)&gEvexTable_root_01_2a_pp, - /* 2b */ (const void *)&gEvexTable_root_01_2b_pp, - /* 2c */ (const void *)&gEvexTable_root_01_2c_pp, - /* 2d */ (const void *)&gEvexTable_root_01_2d_pp, - /* 2e */ (const void *)&gEvexTable_root_01_2e_pp, - /* 2f */ (const void *)&gEvexTable_root_01_2f_pp, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ (const void *)&gEvexTable_root_01_51_pp, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ (const void *)&gEvexTable_root_01_54_pp, - /* 55 */ (const void *)&gEvexTable_root_01_55_pp, - /* 56 */ (const void *)&gEvexTable_root_01_56_pp, - /* 57 */ (const void *)&gEvexTable_root_01_57_pp, - /* 58 */ (const void *)&gEvexTable_root_01_58_pp, - /* 59 */ (const void *)&gEvexTable_root_01_59_pp, - /* 5a */ (const void *)&gEvexTable_root_01_5a_pp, - /* 5b */ (const void *)&gEvexTable_root_01_5b_pp, - /* 5c */ (const void *)&gEvexTable_root_01_5c_pp, - /* 5d */ (const void *)&gEvexTable_root_01_5d_pp, - /* 5e */ (const void *)&gEvexTable_root_01_5e_pp, - /* 5f */ (const void *)&gEvexTable_root_01_5f_pp, - /* 60 */ (const void *)&gEvexTable_root_01_60_pp, - /* 61 */ (const void *)&gEvexTable_root_01_61_pp, - /* 62 */ (const void *)&gEvexTable_root_01_62_pp, - /* 63 */ (const void *)&gEvexTable_root_01_63_pp, - /* 64 */ (const void *)&gEvexTable_root_01_64_pp, - /* 65 */ (const void *)&gEvexTable_root_01_65_pp, - /* 66 */ (const void *)&gEvexTable_root_01_66_pp, - /* 67 */ (const void *)&gEvexTable_root_01_67_pp, - /* 68 */ (const void *)&gEvexTable_root_01_68_pp, - /* 69 */ (const void *)&gEvexTable_root_01_69_pp, - /* 6a */ (const void *)&gEvexTable_root_01_6a_pp, - /* 6b */ (const void *)&gEvexTable_root_01_6b_pp, - /* 6c */ (const void *)&gEvexTable_root_01_6c_pp, - /* 6d */ (const void *)&gEvexTable_root_01_6d_pp, - /* 6e */ (const void *)&gEvexTable_root_01_6e_pp, - /* 6f */ (const void *)&gEvexTable_root_01_6f_pp, - /* 70 */ (const void *)&gEvexTable_root_01_70_pp, - /* 71 */ (const void *)&gEvexTable_root_01_71_pp, - /* 72 */ (const void *)&gEvexTable_root_01_72_pp, - /* 73 */ (const void *)&gEvexTable_root_01_73_pp, - /* 74 */ (const void *)&gEvexTable_root_01_74_pp, - /* 75 */ (const void *)&gEvexTable_root_01_75_pp, - /* 76 */ (const void *)&gEvexTable_root_01_76_pp, - /* 77 */ ND_NULL, - /* 78 */ (const void *)&gEvexTable_root_01_78_pp, - /* 79 */ (const void *)&gEvexTable_root_01_79_pp, - /* 7a */ (const void *)&gEvexTable_root_01_7a_pp, - /* 7b */ (const void *)&gEvexTable_root_01_7b_pp, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ (const void *)&gEvexTable_root_01_7e_pp, - /* 7f */ (const void *)&gEvexTable_root_01_7f_pp, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ (const void *)&gEvexTable_root_01_c2_pp, - /* c3 */ ND_NULL, - /* c4 */ (const void *)&gEvexTable_root_01_c4_pp, - /* c5 */ (const void *)&gEvexTable_root_01_c5_pp, - /* c6 */ (const void *)&gEvexTable_root_01_c6_pp, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ (const void *)&gEvexTable_root_01_d1_pp, - /* d2 */ (const void *)&gEvexTable_root_01_d2_pp, - /* d3 */ (const void *)&gEvexTable_root_01_d3_pp, - /* d4 */ (const void *)&gEvexTable_root_01_d4_pp, - /* d5 */ (const void *)&gEvexTable_root_01_d5_pp, - /* d6 */ (const void *)&gEvexTable_root_01_d6_pp, - /* d7 */ ND_NULL, - /* d8 */ (const void *)&gEvexTable_root_01_d8_pp, - /* d9 */ (const void *)&gEvexTable_root_01_d9_pp, - /* da */ (const void *)&gEvexTable_root_01_da_pp, - /* db */ (const void *)&gEvexTable_root_01_db_pp, - /* dc */ (const void *)&gEvexTable_root_01_dc_pp, - /* dd */ (const void *)&gEvexTable_root_01_dd_pp, - /* de */ (const void *)&gEvexTable_root_01_de_pp, - /* df */ (const void *)&gEvexTable_root_01_df_pp, - /* e0 */ (const void *)&gEvexTable_root_01_e0_pp, - /* e1 */ (const void *)&gEvexTable_root_01_e1_pp, - /* e2 */ (const void *)&gEvexTable_root_01_e2_pp, - /* e3 */ (const void *)&gEvexTable_root_01_e3_pp, - /* e4 */ (const void *)&gEvexTable_root_01_e4_pp, - /* e5 */ (const void *)&gEvexTable_root_01_e5_pp, - /* e6 */ (const void *)&gEvexTable_root_01_e6_pp, - /* e7 */ (const void *)&gEvexTable_root_01_e7_pp, - /* e8 */ (const void *)&gEvexTable_root_01_e8_pp, - /* e9 */ (const void *)&gEvexTable_root_01_e9_pp, - /* ea */ (const void *)&gEvexTable_root_01_ea_pp, - /* eb */ (const void *)&gEvexTable_root_01_eb_pp, - /* ec */ (const void *)&gEvexTable_root_01_ec_pp, - /* ed */ (const void *)&gEvexTable_root_01_ed_pp, - /* ee */ (const void *)&gEvexTable_root_01_ee_pp, - /* ef */ (const void *)&gEvexTable_root_01_ef_pp, - /* f0 */ ND_NULL, - /* f1 */ (const void *)&gEvexTable_root_01_f1_pp, - /* f2 */ (const void *)&gEvexTable_root_01_f2_pp, - /* f3 */ (const void *)&gEvexTable_root_01_f3_pp, - /* f4 */ (const void *)&gEvexTable_root_01_f4_pp, - /* f5 */ (const void *)&gEvexTable_root_01_f5_pp, - /* f6 */ (const void *)&gEvexTable_root_01_f6_pp, - /* f7 */ ND_NULL, - /* f8 */ (const void *)&gEvexTable_root_01_f8_pp, - /* f9 */ (const void *)&gEvexTable_root_01_f9_pp, - /* fa */ (const void *)&gEvexTable_root_01_fa_pp, - /* fb */ (const void *)&gEvexTable_root_01_fb_pp, - /* fc */ (const void *)&gEvexTable_root_01_fc_pp, - /* fd */ (const void *)&gEvexTable_root_01_fd_pp, - /* fe */ (const void *)&gEvexTable_root_01_fe_pp, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1406] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_58_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_58_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_58_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1411] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_58_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_58_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_58_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_58_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_58_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_2f_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1472] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_2f_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_2f_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_2f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_2f_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1480] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1523] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5b_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5b_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_05_5b_00_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1499] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5b_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1552] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5b_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5b_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5b_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_5b_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_5b_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1492] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_5a_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1500] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5a_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5a_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1525] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5a_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_5a_03_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5a_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1531] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5a_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5a_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5a_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_5a_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_5a_02_w, - /* 03 */ (const void *)&gEvexTable_root_05_5a_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1505] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7b_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1579] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_7b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_7b_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_7b_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1506] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_79_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_79_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1507] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_79_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_79_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_79_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1534] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_79_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_79_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_79_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_79_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1508] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7d_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7d_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1509] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1581] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7d_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7d_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7d_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1582] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7d_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7d_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_7d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_7d_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_7d_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_7d_02_w, - /* 03 */ (const void *)&gEvexTable_root_05_7d_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1518] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_1d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_1d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_1d_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1543] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_1d_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_1d_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_1d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_1d_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_1d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_2d_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1532] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_2d_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_2a_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1538] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_2a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_2a_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1553] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7a_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1572] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7a_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1575] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7a_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7a_03_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_05_7a_03_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_7a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_7a_01_w, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_05_7a_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1554] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_78_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_78_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1555] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_78_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_78_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_78_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1567] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_78_02_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_05_78_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_78_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_78_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_78_01_w, - /* 02 */ (const void *)&gEvexTable_root_05_78_02_wi, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1556] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7c_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7c_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1557] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_7c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_7c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_7c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_7c_00_w, - /* 01 */ (const void *)&gEvexTable_root_05_7c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_2c_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1566] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_2c_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1586] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5e_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5e_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5e_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1591] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5e_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5e_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5e_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_5e_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1890] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5f_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5f_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5f_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1895] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5f_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5f_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5f_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_5f_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1905] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5d_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5d_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5d_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1910] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5d_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5d_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5d_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_5d_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1996] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_10_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_10_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_10_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1997] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_10_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_10_02_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_05_10_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_05_10_02_mem_w, - /* 01 */ (const void *)&gEvexTable_root_05_10_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_10_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_10_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1998] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_11_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_11_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_11_02_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1999] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_11_02_reg_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_11_02_reg_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_05_11_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_05_11_02_mem_w, - /* 01 */ (const void *)&gEvexTable_root_05_11_02_reg_w, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_11_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_11_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2020] -}; - -const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_05_6e_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_6e_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2021] -}; - -const ND_TABLE_VEX_L gEvexTable_root_05_6e_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_05_6e_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_05_6e_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_05_6e_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_05_6e_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_6e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_6e_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2022] -}; - -const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_05_7e_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_7e_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2023] -}; - -const ND_TABLE_VEX_L gEvexTable_root_05_7e_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_05_7e_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_05_7e_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_05_7e_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_05_7e_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_7e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_05_7e_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2033] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_59_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_59_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_59_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2038] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_59_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_59_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_59_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_59_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_59_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2672] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_51_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_51_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_51_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2677] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_51_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_51_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_51_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_51_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2683] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5c_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5c_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_5c_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2688] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_5c_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_5c_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_5c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_5c_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_05_5c_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_05_2e_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2695] -}; - -const ND_TABLE_VEX_W gEvexTable_root_05_2e_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_05_2e_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_05_2e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_05_2e_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gEvexTable_root_05_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gEvexTable_root_05_10_pp, - /* 11 */ (const void *)&gEvexTable_root_05_11_pp, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ (const void *)&gEvexTable_root_05_1d_pp, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ (const void *)&gEvexTable_root_05_2a_pp, - /* 2b */ ND_NULL, - /* 2c */ (const void *)&gEvexTable_root_05_2c_pp, - /* 2d */ (const void *)&gEvexTable_root_05_2d_pp, - /* 2e */ (const void *)&gEvexTable_root_05_2e_pp, - /* 2f */ (const void *)&gEvexTable_root_05_2f_pp, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ (const void *)&gEvexTable_root_05_51_pp, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ (const void *)&gEvexTable_root_05_58_pp, - /* 59 */ (const void *)&gEvexTable_root_05_59_pp, - /* 5a */ (const void *)&gEvexTable_root_05_5a_pp, - /* 5b */ (const void *)&gEvexTable_root_05_5b_pp, - /* 5c */ (const void *)&gEvexTable_root_05_5c_pp, - /* 5d */ (const void *)&gEvexTable_root_05_5d_pp, - /* 5e */ (const void *)&gEvexTable_root_05_5e_pp, - /* 5f */ (const void *)&gEvexTable_root_05_5f_pp, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ (const void *)&gEvexTable_root_05_6e_pp, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ (const void *)&gEvexTable_root_05_78_pp, - /* 79 */ (const void *)&gEvexTable_root_05_79_pp, - /* 7a */ (const void *)&gEvexTable_root_05_7a_pp, - /* 7b */ (const void *)&gEvexTable_root_05_7b_pp, - /* 7c */ (const void *)&gEvexTable_root_05_7c_pp, - /* 7d */ (const void *)&gEvexTable_root_05_7d_pp, - /* 7e */ (const void *)&gEvexTable_root_05_7e_pp, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1426] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_03_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1427] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_03_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_03_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_03_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_03_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_03_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1462] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_c2_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_c2_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_c2_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1467] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_c2_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_c2_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_c2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_c2_00_w, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_03_c2_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1515] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_1d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_1d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_1d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_1d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_42_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1583] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_42_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_42_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_42_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_42_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1604] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_19_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1606] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_19_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_19_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_19_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_19_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_19_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1605] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1b_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1607] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_1b_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_1b_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_1b_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_1b_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_03_1b_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_1b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_1b_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1609] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_39_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1611] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_39_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_39_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_39_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_39_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_39_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1610] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3b_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1612] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_3b_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_3b_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_3b_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_3b_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_03_3b_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_3b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_3b_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1613] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_17_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_17_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_17_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1614] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_17_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_17_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_17_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_17_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_17_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_17_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_17_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1621] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_54_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1622] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_54_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_54_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_54_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_54_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_54_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1623] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_55_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1624] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_55_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_55_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_55_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_55_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_55_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1819] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1821] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_66_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_66_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_66_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_66_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1820] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_66_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_66_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_66_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_66_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_66_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1822] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1824] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_67_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_67_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_67_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_67_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1823] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_67_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_67_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_67_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_67_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_67_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1851] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1853] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_26_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_26_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_26_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_26_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1852] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_26_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_26_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_26_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_26_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_26_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1854] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1856] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_27_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_27_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_27_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_27_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1855] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_27_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_27_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_27_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_27_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_27_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_cf_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1857] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_cf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_cf_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_cf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_cf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_ce_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1859] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_ce_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_ce_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_ce_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_ce_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1868] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_18_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1870] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_18_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_18_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_18_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_18_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_18_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1869] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1a_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1871] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_1a_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_1a_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_1a_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_1a_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_03_1a_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_1a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_1a_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1873] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_38_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1875] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_38_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_38_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_38_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_38_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_38_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1874] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3a_01_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1876] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_3a_01_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_3a_01_02_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_3a_01_02_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_3a_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_03_3a_01_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_3a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_3a_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1877] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_21_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_21_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_21_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1878] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_21_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_21_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_21_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_21_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_21_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_21_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_21_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_0f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2083] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_0f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_0f_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_44_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2116] -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_44_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_44_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2120] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2147] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_3f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_3f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_3f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_3f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_3f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2121] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2142] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_1f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_1f_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_1f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_1f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_1f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2143] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_3e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2146] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_3e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_3e_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_3e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_3e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_3e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2144] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_1e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2145] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_1e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_1e_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_1e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_1e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_1e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_05_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2198] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_05_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_05_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_05_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_05_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_04_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2202] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_04_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_04_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_04_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_04_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_01_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2207] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_01_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_01_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_00_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2213] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_00_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_00_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_00_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_00_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2226] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_14_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_14_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_14_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2227] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_14_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_14_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_14_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_14_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_14_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_14_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_14_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2230] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2234] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_16_01_mem_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_16_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2231] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_16_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2235] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_16_01_reg_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_reg_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_16_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_reg_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_16_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_16_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_16_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2239] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_15_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_15_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_15_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2240] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_15_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_15_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_15_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_15_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_15_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_15_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_15_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2274] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_20_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_20_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_20_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2275] -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_20_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_20_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gEvexTable_root_03_20_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gEvexTable_root_03_20_01_mem_l, - /* 01 */ (const void *)&gEvexTable_root_03_20_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_20_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_20_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2278] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_22_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2280] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_22_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gEvexTable_root_03_22_01_00_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_22_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gEvexTable_root_03_22_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gEvexTable_root_03_22_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_22_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_22_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2467] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_71_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2468] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_71_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_71_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_71_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_71_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_71_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_70_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2472] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_70_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_70_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_70_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_70_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2476] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_73_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2477] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_73_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_73_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_73_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_73_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_73_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_72_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2481] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_72_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_72_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_72_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_72_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2562] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_25_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2563] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_25_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_25_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_25_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_25_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_25_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2592] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_50_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2593] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_50_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_50_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_50_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_50_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_50_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2594] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_51_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2595] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_51_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_51_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_51_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_51_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2608] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2610] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_56_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_56_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_56_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_56_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2609] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_56_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_56_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_56_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_56_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_56_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2611] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2613] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_57_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_57_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_57_01_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_57_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2612] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_57_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_57_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_57_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_57_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_57_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_09_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2614] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_09_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_09_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_09_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_09_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2615] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_08_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_08_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_08_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2616] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_08_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_08_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_08_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_08_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_08_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_0b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2617] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_0b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_0b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_0b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_0b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2618] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_0a_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_0a_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_0a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2619] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_0a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_0a_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_0a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_03_0a_00_w, - /* 01 */ (const void *)&gEvexTable_root_03_0a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2657] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_23_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2658] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_23_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_23_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_23_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_23_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_23_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2659] -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_03_43_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2660] -}; - -const ND_TABLE_VEX_W gEvexTable_root_03_43_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_03_43_01_00_leaf, - /* 01 */ (const void *)&gEvexTable_root_03_43_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_03_43_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_03_43_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gEvexTable_root_03_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gEvexTable_root_03_00_pp, - /* 01 */ (const void *)&gEvexTable_root_03_01_pp, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gEvexTable_root_03_03_pp, - /* 04 */ (const void *)&gEvexTable_root_03_04_pp, - /* 05 */ (const void *)&gEvexTable_root_03_05_pp, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ (const void *)&gEvexTable_root_03_08_pp, - /* 09 */ (const void *)&gEvexTable_root_03_09_pp, - /* 0a */ (const void *)&gEvexTable_root_03_0a_pp, - /* 0b */ (const void *)&gEvexTable_root_03_0b_pp, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ (const void *)&gEvexTable_root_03_0f_pp, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ (const void *)&gEvexTable_root_03_14_pp, - /* 15 */ (const void *)&gEvexTable_root_03_15_pp, - /* 16 */ (const void *)&gEvexTable_root_03_16_pp, - /* 17 */ (const void *)&gEvexTable_root_03_17_pp, - /* 18 */ (const void *)&gEvexTable_root_03_18_pp, - /* 19 */ (const void *)&gEvexTable_root_03_19_pp, - /* 1a */ (const void *)&gEvexTable_root_03_1a_pp, - /* 1b */ (const void *)&gEvexTable_root_03_1b_pp, - /* 1c */ ND_NULL, - /* 1d */ (const void *)&gEvexTable_root_03_1d_pp, - /* 1e */ (const void *)&gEvexTable_root_03_1e_pp, - /* 1f */ (const void *)&gEvexTable_root_03_1f_pp, - /* 20 */ (const void *)&gEvexTable_root_03_20_pp, - /* 21 */ (const void *)&gEvexTable_root_03_21_pp, - /* 22 */ (const void *)&gEvexTable_root_03_22_pp, - /* 23 */ (const void *)&gEvexTable_root_03_23_pp, - /* 24 */ ND_NULL, - /* 25 */ (const void *)&gEvexTable_root_03_25_pp, - /* 26 */ (const void *)&gEvexTable_root_03_26_pp, - /* 27 */ (const void *)&gEvexTable_root_03_27_pp, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ (const void *)&gEvexTable_root_03_38_pp, - /* 39 */ (const void *)&gEvexTable_root_03_39_pp, - /* 3a */ (const void *)&gEvexTable_root_03_3a_pp, - /* 3b */ (const void *)&gEvexTable_root_03_3b_pp, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ (const void *)&gEvexTable_root_03_3e_pp, - /* 3f */ (const void *)&gEvexTable_root_03_3f_pp, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ (const void *)&gEvexTable_root_03_42_pp, - /* 43 */ (const void *)&gEvexTable_root_03_43_pp, - /* 44 */ (const void *)&gEvexTable_root_03_44_pp, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ (const void *)&gEvexTable_root_03_50_pp, - /* 51 */ (const void *)&gEvexTable_root_03_51_pp, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ (const void *)&gEvexTable_root_03_54_pp, - /* 55 */ (const void *)&gEvexTable_root_03_55_pp, - /* 56 */ (const void *)&gEvexTable_root_03_56_pp, - /* 57 */ (const void *)&gEvexTable_root_03_57_pp, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ (const void *)&gEvexTable_root_03_66_pp, - /* 67 */ (const void *)&gEvexTable_root_03_67_pp, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ (const void *)&gEvexTable_root_03_70_pp, - /* 71 */ (const void *)&gEvexTable_root_03_71_pp, - /* 72 */ (const void *)&gEvexTable_root_03_72_pp, - /* 73 */ (const void *)&gEvexTable_root_03_73_pp, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ (const void *)&gEvexTable_root_03_c2_pp, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ (const void *)&gEvexTable_root_03_ce_pp, - /* cf */ (const void *)&gEvexTable_root_03_cf_pp, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1504] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_13_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_13_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_13_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1533] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_13_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_13_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_13_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gEvexTable_root_06_13_00_w, - /* 01 */ (const void *)&gEvexTable_root_06_13_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1617] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_56_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_56_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_56_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1655] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_56_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_56_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_56_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_06_56_02_w, - /* 03 */ (const void *)&gEvexTable_root_06_56_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1618] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_57_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_57_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_57_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1656] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_57_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_57_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_57_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_06_57_02_w, - /* 03 */ (const void *)&gEvexTable_root_06_57_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1619] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_d6_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_d6_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_d6_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1741] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_d6_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_d6_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_d6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_06_d6_02_w, - /* 03 */ (const void *)&gEvexTable_root_06_d6_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1620] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_d7_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_d7_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_d7_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1742] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_d7_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_d7_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_d7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gEvexTable_root_06_d7_02_w, - /* 03 */ (const void *)&gEvexTable_root_06_d7_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_98_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1627] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_98_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_98_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_98_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_98_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_99_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1632] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_99_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_99_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_99_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_99_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_a8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1637] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_a8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_a8_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_a8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_a8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_a9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1642] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_a9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_a9_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_a9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_a9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_b8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1647] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_b8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_b8_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_b8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_b8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_b9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1652] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_b9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_b9_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_b9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_b9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_96_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1667] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_96_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_96_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_96_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_96_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_a6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1672] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_a6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_a6_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_a6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_a6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_b6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1677] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_b6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_b6_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_b6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_b6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1686] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9a_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1691] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_aa_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1696] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_aa_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_aa_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_aa_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_aa_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_ab_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1701] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_ab_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_ab_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_ab_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_ab_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_ba_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1706] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_ba_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_ba_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_ba_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_ba_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_bb_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1711] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_bb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_bb_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_bb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_bb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_97_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1716] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_97_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_97_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_97_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_97_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_a7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1721] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_a7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_a7_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_a7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_a7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_b7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1726] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_b7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_b7_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_b7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_b7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1745] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1750] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_ac_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1755] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_ac_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_ac_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_ac_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_ac_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_ad_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1760] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_ad_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_ad_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_ad_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_ad_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_bc_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1765] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_bc_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_bc_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_bc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_bc_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_bd_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1770] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_bd_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_bd_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_bd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_bd_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1783] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9e_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_9f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1788] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_9f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_9f_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_9f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_9f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_ae_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1793] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_ae_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_ae_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_ae_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_ae_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_af_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1798] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_af_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_af_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_af_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_af_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_be_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1803] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_be_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_be_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_be_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_be_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_bf_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1808] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_bf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_bf_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_bf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_bf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_42_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1846] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_42_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_42_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_42_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_42_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_43_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1849] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_43_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_43_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_43_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_43_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_4c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2604] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_4c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_4c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_4c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_4c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_4d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2606] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_4d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_4d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_4d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_4d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_4e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2632] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_4e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_4e_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_4e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_4e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_4f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2634] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_4f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_4f_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_4f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_4f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_2c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2637] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_2c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_2c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_2c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gEvexTable_root_06_2d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2640] -}; - -const ND_TABLE_VEX_W gEvexTable_root_06_2d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gEvexTable_root_06_2d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gEvexTable_root_06_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_06_2d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gEvexTable_root_06_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ (const void *)&gEvexTable_root_06_13_pp, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ (const void *)&gEvexTable_root_06_2c_pp, - /* 2d */ (const void *)&gEvexTable_root_06_2d_pp, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ (const void *)&gEvexTable_root_06_42_pp, - /* 43 */ (const void *)&gEvexTable_root_06_43_pp, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ (const void *)&gEvexTable_root_06_4c_pp, - /* 4d */ (const void *)&gEvexTable_root_06_4d_pp, - /* 4e */ (const void *)&gEvexTable_root_06_4e_pp, - /* 4f */ (const void *)&gEvexTable_root_06_4f_pp, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ (const void *)&gEvexTable_root_06_56_pp, - /* 57 */ (const void *)&gEvexTable_root_06_57_pp, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ (const void *)&gEvexTable_root_06_96_pp, - /* 97 */ (const void *)&gEvexTable_root_06_97_pp, - /* 98 */ (const void *)&gEvexTable_root_06_98_pp, - /* 99 */ (const void *)&gEvexTable_root_06_99_pp, - /* 9a */ (const void *)&gEvexTable_root_06_9a_pp, - /* 9b */ (const void *)&gEvexTable_root_06_9b_pp, - /* 9c */ (const void *)&gEvexTable_root_06_9c_pp, - /* 9d */ (const void *)&gEvexTable_root_06_9d_pp, - /* 9e */ (const void *)&gEvexTable_root_06_9e_pp, - /* 9f */ (const void *)&gEvexTable_root_06_9f_pp, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ (const void *)&gEvexTable_root_06_a6_pp, - /* a7 */ (const void *)&gEvexTable_root_06_a7_pp, - /* a8 */ (const void *)&gEvexTable_root_06_a8_pp, - /* a9 */ (const void *)&gEvexTable_root_06_a9_pp, - /* aa */ (const void *)&gEvexTable_root_06_aa_pp, - /* ab */ (const void *)&gEvexTable_root_06_ab_pp, - /* ac */ (const void *)&gEvexTable_root_06_ac_pp, - /* ad */ (const void *)&gEvexTable_root_06_ad_pp, - /* ae */ (const void *)&gEvexTable_root_06_ae_pp, - /* af */ (const void *)&gEvexTable_root_06_af_pp, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ (const void *)&gEvexTable_root_06_b6_pp, - /* b7 */ (const void *)&gEvexTable_root_06_b7_pp, - /* b8 */ (const void *)&gEvexTable_root_06_b8_pp, - /* b9 */ (const void *)&gEvexTable_root_06_b9_pp, - /* ba */ (const void *)&gEvexTable_root_06_ba_pp, - /* bb */ (const void *)&gEvexTable_root_06_bb_pp, - /* bc */ (const void *)&gEvexTable_root_06_bc_pp, - /* bd */ (const void *)&gEvexTable_root_06_bd_pp, - /* be */ (const void *)&gEvexTable_root_06_be_pp, - /* bf */ (const void *)&gEvexTable_root_06_bf_pp, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ (const void *)&gEvexTable_root_06_d6_pp, - /* d7 */ (const void *)&gEvexTable_root_06_d7_pp, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_VEX_MMMMM gEvexTable_root_mmmmm = -{ - ND_ILUT_VEX_MMMMM, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gEvexTable_root_01_opcode, - /* 02 */ (const void *)&gEvexTable_root_02_opcode, - /* 03 */ (const void *)&gEvexTable_root_03_opcode, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gEvexTable_root_05_opcode, - /* 06 */ (const void *)&gEvexTable_root_06_opcode, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - } -}; - -const PND_TABLE gEvexTable = (const PND_TABLE)&gEvexTable_root_mmmmm; - - -#endif - diff --git a/bddisasm/include/table_root.h b/bddisasm/include/table_root.h deleted file mode 100644 index 2043b28..0000000 --- a/bddisasm/include/table_root.h +++ /dev/null @@ -1,16694 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ - -// -// This file was auto-generated by generate_tables.py. DO NOT MODIFY! -// - -#ifndef TABLE_ROOT_H -#define TABLE_ROOT_H - -const ND_TABLE_INSTRUCTION gRootTable_root_37_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[0] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d5_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[4] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[64] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fc_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[66] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_fc_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_fc_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_fc_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_fc_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_38_fc_mem_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fc_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_fc_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[16] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[33] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2722] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2723] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_NP_auxiliary, - /* 01 */ (const void *)&gRootTable_root_0f_38_f6_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_f6_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[16] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[33] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f6_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_f6_reg_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_f6_reg_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f6_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f6_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_f6_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[34] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[42] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_de_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_de_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_de_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[34] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_de_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_de_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_de_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_de_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_de_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[35] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[43] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_dd_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_dd_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dd_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[43] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_dd_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_dd_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dd_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_dd_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_dd_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[36] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[37] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_df_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_df_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_df_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[37] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_df_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_df_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_df_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_df_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_df_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_01_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[38] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_03_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[39] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[44] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_d8_mem_02_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[45] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_d8_mem_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_38_d8_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_d8_mem_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_d8_mem_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_38_d8_mem_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_38_d8_mem_03_mprefix, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_d8_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_d8_mem_modrmreg, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[40] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[41] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_dc_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_dc_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[40] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_dc_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[604] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_dc_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_dc_reg_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_dc_reg_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_dc_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_dc_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_dc_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_db_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[46] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_db_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_db_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_15_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[76] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_15_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_15_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_14_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[77] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_14_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_14_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[198] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_F2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[199] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_F2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[678] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[679] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f0_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_38_f0_mem_F2_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[198] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f0_reg_F2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[199] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_F2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f0_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_38_f0_reg_F2_mprefix, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f0_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f0_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_f0_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[200] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_F2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[201] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_F2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[680] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[681] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f1_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_38_f1_mem_F2_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[200] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f1_reg_F2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[201] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_F2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f1_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_38_f1_reg_F2_mprefix, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f1_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f1_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_f1_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fa_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[252] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_fa_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_fa_reg_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fa_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_fa_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_fb_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[253] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_fb_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_fb_reg_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_fb_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_fb_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[256] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[257] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f8_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[687] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f8_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_f8_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_38_f8_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_38_f8_mem_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f8_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f8_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cf_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[419] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_cf_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_cf_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_80_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[464] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_80_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_80_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_80_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_80_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_82_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[468] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_82_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_82_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_82_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_82_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_81_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[469] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_81_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_81_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_81_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_81_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f9_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[688] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f9_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f9_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f9_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2a_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[706] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_2a_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_2a_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_2a_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_2a_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[846] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[847] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_1c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_1c_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_1c_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[848] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1e_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[849] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_1e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_1e_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_1e_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[850] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_1d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[851] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_1d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_1d_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_1d_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_2b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[856] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_2b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_2b_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_10_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[887] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_10_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_10_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_29_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[895] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_29_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_29_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_37_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[904] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_37_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_37_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[943] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_02_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[944] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_02_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_02_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[945] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_03_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[946] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_03_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_03_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[947] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_01_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[948] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_01_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_01_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_41_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[949] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_41_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_41_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[950] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[951] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_06_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[952] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_07_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[953] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_07_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_07_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[954] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_05_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[955] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_05_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_05_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[966] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_04_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[967] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_04_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_04_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[970] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3c_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[971] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3d_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[976] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3f_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3e_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[977] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3e_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_38_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[978] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_38_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_38_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_39_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[979] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_39_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_39_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[984] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3b_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_3a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[985] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_3a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_3a_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_21_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[988] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_21_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_21_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_22_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[989] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_22_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_22_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_20_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[990] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_20_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_20_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_25_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[991] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_25_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_25_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_23_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[992] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_23_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_23_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_24_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[993] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_24_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_24_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_31_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[994] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_31_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_31_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_32_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[995] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_32_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_32_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_30_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[996] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_30_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_30_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_35_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[997] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_35_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_35_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_33_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[998] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_33_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_33_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_34_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[999] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_34_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_34_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_28_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1000] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_28_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_28_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1001] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1002] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_0b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_0b_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_0b_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_40_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1008] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_40_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_40_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1055] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_00_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1056] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_00_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_00_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1061] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_08_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1062] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_08_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_08_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_08_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1063] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_0a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1064] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_0a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_0a_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_0a_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1065] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_09_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1066] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_09_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_09_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_38_09_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_17_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1119] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_17_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_17_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c9_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1280] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_c9_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_c9_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_ca_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1281] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_ca_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_ca_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_c8_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1282] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_c8_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_c8_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cc_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1284] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_cc_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_cc_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cd_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1285] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_cd_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_cd_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_cb_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1286] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_cb_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2724] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2725] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_38_f5_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_38_f5_mem_66_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_38_f5_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_f5_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gRootTable_root_0f_38_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gRootTable_root_0f_38_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_38_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_38_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_38_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_38_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_38_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_38_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_38_07_mprefix, - /* 08 */ (const void *)&gRootTable_root_0f_38_08_mprefix, - /* 09 */ (const void *)&gRootTable_root_0f_38_09_mprefix, - /* 0a */ (const void *)&gRootTable_root_0f_38_0a_mprefix, - /* 0b */ (const void *)&gRootTable_root_0f_38_0b_mprefix, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gRootTable_root_0f_38_10_mprefix, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ (const void *)&gRootTable_root_0f_38_14_mprefix, - /* 15 */ (const void *)&gRootTable_root_0f_38_15_mprefix, - /* 16 */ ND_NULL, - /* 17 */ (const void *)&gRootTable_root_0f_38_17_mprefix, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ (const void *)&gRootTable_root_0f_38_1c_mprefix, - /* 1d */ (const void *)&gRootTable_root_0f_38_1d_mprefix, - /* 1e */ (const void *)&gRootTable_root_0f_38_1e_mprefix, - /* 1f */ ND_NULL, - /* 20 */ (const void *)&gRootTable_root_0f_38_20_mprefix, - /* 21 */ (const void *)&gRootTable_root_0f_38_21_mprefix, - /* 22 */ (const void *)&gRootTable_root_0f_38_22_mprefix, - /* 23 */ (const void *)&gRootTable_root_0f_38_23_mprefix, - /* 24 */ (const void *)&gRootTable_root_0f_38_24_mprefix, - /* 25 */ (const void *)&gRootTable_root_0f_38_25_mprefix, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ (const void *)&gRootTable_root_0f_38_28_mprefix, - /* 29 */ (const void *)&gRootTable_root_0f_38_29_mprefix, - /* 2a */ (const void *)&gRootTable_root_0f_38_2a_modrmmod, - /* 2b */ (const void *)&gRootTable_root_0f_38_2b_mprefix, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ (const void *)&gRootTable_root_0f_38_30_mprefix, - /* 31 */ (const void *)&gRootTable_root_0f_38_31_mprefix, - /* 32 */ (const void *)&gRootTable_root_0f_38_32_mprefix, - /* 33 */ (const void *)&gRootTable_root_0f_38_33_mprefix, - /* 34 */ (const void *)&gRootTable_root_0f_38_34_mprefix, - /* 35 */ (const void *)&gRootTable_root_0f_38_35_mprefix, - /* 36 */ ND_NULL, - /* 37 */ (const void *)&gRootTable_root_0f_38_37_mprefix, - /* 38 */ (const void *)&gRootTable_root_0f_38_38_mprefix, - /* 39 */ (const void *)&gRootTable_root_0f_38_39_mprefix, - /* 3a */ (const void *)&gRootTable_root_0f_38_3a_mprefix, - /* 3b */ (const void *)&gRootTable_root_0f_38_3b_mprefix, - /* 3c */ (const void *)&gRootTable_root_0f_38_3c_mprefix, - /* 3d */ (const void *)&gRootTable_root_0f_38_3d_mprefix, - /* 3e */ (const void *)&gRootTable_root_0f_38_3e_mprefix, - /* 3f */ (const void *)&gRootTable_root_0f_38_3f_mprefix, - /* 40 */ (const void *)&gRootTable_root_0f_38_40_mprefix, - /* 41 */ (const void *)&gRootTable_root_0f_38_41_mprefix, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ (const void *)&gRootTable_root_0f_38_80_modrmmod, - /* 81 */ (const void *)&gRootTable_root_0f_38_81_modrmmod, - /* 82 */ (const void *)&gRootTable_root_0f_38_82_modrmmod, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ (const void *)&gRootTable_root_0f_38_c8_mprefix, - /* c9 */ (const void *)&gRootTable_root_0f_38_c9_mprefix, - /* ca */ (const void *)&gRootTable_root_0f_38_ca_mprefix, - /* cb */ (const void *)&gRootTable_root_0f_38_cb_mprefix, - /* cc */ (const void *)&gRootTable_root_0f_38_cc_mprefix, - /* cd */ (const void *)&gRootTable_root_0f_38_cd_mprefix, - /* ce */ ND_NULL, - /* cf */ (const void *)&gRootTable_root_0f_38_cf_mprefix, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ (const void *)&gRootTable_root_0f_38_d8_modrmmod, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ (const void *)&gRootTable_root_0f_38_db_mprefix, - /* dc */ (const void *)&gRootTable_root_0f_38_dc_modrmmod, - /* dd */ (const void *)&gRootTable_root_0f_38_dd_modrmmod, - /* de */ (const void *)&gRootTable_root_0f_38_de_modrmmod, - /* df */ (const void *)&gRootTable_root_0f_38_df_modrmmod, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ (const void *)&gRootTable_root_0f_38_f0_modrmmod, - /* f1 */ (const void *)&gRootTable_root_0f_38_f1_modrmmod, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ (const void *)&gRootTable_root_0f_38_f5_modrmmod, - /* f6 */ (const void *)&gRootTable_root_0f_38_f6_modrmmod, - /* f7 */ ND_NULL, - /* f8 */ (const void *)&gRootTable_root_0f_38_f8_modrmmod, - /* f9 */ (const void *)&gRootTable_root_0f_38_f9_modrmmod, - /* fa */ (const void *)&gRootTable_root_0f_38_fa_modrmmod, - /* fb */ (const void *)&gRootTable_root_0f_38_fb_modrmmod, - /* fc */ (const void *)&gRootTable_root_0f_38_fc_modrmmod, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[27] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[28] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[29] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_58_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[30] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_58_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_58_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_58_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_58_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_58_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[31] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d0_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[32] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d0_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_d0_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_d0_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_df_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[47] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_df_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_df_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[74] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0d_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[75] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0c_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_41_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[246] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_41_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_41_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_40_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[247] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_40_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_40_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_17_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[261] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_17_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_17_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cf_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[417] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cf_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_cf_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_ce_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[418] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_ce_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_ce_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[423] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_f0_reg_00_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_3a_f0_reg_00_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_3a_f0_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_f0_reg_00_modrmrm, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_f0_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_f0_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[453] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_21_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_21_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[454] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_21_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_21_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_21_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_3a_21_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_42_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[745] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_42_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_42_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[875] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[876] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_0f_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0f_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0e_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[888] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0e_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_44_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[890] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_44_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_44_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_61_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[898] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_61_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_61_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_60_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[899] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_60_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_60_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_63_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[907] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_63_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_63_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_62_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[908] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_62_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_62_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[912] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_14_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_14_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[913] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_14_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_14_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_14_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_14_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_3a_14_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[914] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_mem_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[916] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_mem_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_16_mem_66_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[915] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_16_reg_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[917] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_16_reg_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_16_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_16_reg_66_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_16_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_16_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_3a_16_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[920] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_15_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_15_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[921] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_15_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_15_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_15_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_15_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_3a_15_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[958] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_20_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_20_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[959] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_20_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_20_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_3a_20_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_20_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_3a_20_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[960] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_22_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[961] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_3a_22_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_22_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_3a_22_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_22_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_22_66_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_09_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1211] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_09_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_09_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_08_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1212] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_08_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_08_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1213] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0b_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_0a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1214] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_0a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_3a_0a_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3a_cc_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1283] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_3a_cc_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_3a_cc_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gRootTable_root_0f_3a_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ (const void *)&gRootTable_root_0f_3a_08_mprefix, - /* 09 */ (const void *)&gRootTable_root_0f_3a_09_mprefix, - /* 0a */ (const void *)&gRootTable_root_0f_3a_0a_mprefix, - /* 0b */ (const void *)&gRootTable_root_0f_3a_0b_mprefix, - /* 0c */ (const void *)&gRootTable_root_0f_3a_0c_mprefix, - /* 0d */ (const void *)&gRootTable_root_0f_3a_0d_mprefix, - /* 0e */ (const void *)&gRootTable_root_0f_3a_0e_mprefix, - /* 0f */ (const void *)&gRootTable_root_0f_3a_0f_mprefix, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ (const void *)&gRootTable_root_0f_3a_14_modrmmod, - /* 15 */ (const void *)&gRootTable_root_0f_3a_15_modrmmod, - /* 16 */ (const void *)&gRootTable_root_0f_3a_16_modrmmod, - /* 17 */ (const void *)&gRootTable_root_0f_3a_17_mprefix, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ (const void *)&gRootTable_root_0f_3a_20_modrmmod, - /* 21 */ (const void *)&gRootTable_root_0f_3a_21_modrmmod, - /* 22 */ (const void *)&gRootTable_root_0f_3a_22_mprefix, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ (const void *)&gRootTable_root_0f_3a_40_mprefix, - /* 41 */ (const void *)&gRootTable_root_0f_3a_41_mprefix, - /* 42 */ (const void *)&gRootTable_root_0f_3a_42_mprefix, - /* 43 */ ND_NULL, - /* 44 */ (const void *)&gRootTable_root_0f_3a_44_mprefix, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ (const void *)&gRootTable_root_0f_3a_60_mprefix, - /* 61 */ (const void *)&gRootTable_root_0f_3a_61_mprefix, - /* 62 */ (const void *)&gRootTable_root_0f_3a_62_mprefix, - /* 63 */ (const void *)&gRootTable_root_0f_3a_63_mprefix, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ (const void *)&gRootTable_root_0f_3a_cc_mprefix, - /* cd */ ND_NULL, - /* ce */ (const void *)&gRootTable_root_0f_3a_ce_mprefix, - /* cf */ (const void *)&gRootTable_root_0f_3a_cf_mprefix, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ (const void *)&gRootTable_root_0f_3a_df_mprefix, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ (const void *)&gRootTable_root_0f_3a_f0_modrmmod, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[48] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[60] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_55_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[61] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_55_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_55_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_55_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[62] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_54_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[63] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_54_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_54_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_54_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[83] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[85] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[86] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[88] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_1a_mpx_mem_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1a_mpx_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1a_mpx_mem_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[83] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[85] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[88] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_mpx_reg_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[790] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_1a_mpx_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_1a_mpx_reg_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_reg_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1a_mpx_reg_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1a_mpx_reg_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_1a_mpx_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_1a_mpx_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1a_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[784] -}; - -const ND_TABLE_FEATURE gRootTable_root_0f_1a_feature = -{ - ND_ILUT_FEATURE, - { - /* 00 */ (const void *)&gRootTable_root_0f_1a_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1a_mpx_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[84] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[87] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[89] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_mem_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[90] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_1b_mpx_mem_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1b_mpx_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1b_mpx_mem_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[84] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[89] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[791] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_mpx_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[792] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_1b_mpx_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_1b_mpx_reg_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_reg_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1b_mpx_reg_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1b_mpx_reg_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_1b_mpx_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_1b_mpx_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1b_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[785] -}; - -const ND_TABLE_FEATURE gRootTable_root_0f_1b_feature = -{ - ND_ILUT_FEATURE, - { - /* 00 */ (const void *)&gRootTable_root_0f_1b_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1b_mpx_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[92] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1386] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_bc_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_bc_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[93] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bd_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[622] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_bd_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_bd_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_bd_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[94] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[95] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ca_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[96] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_cb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[97] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_cc_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[98] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_cd_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[99] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ce_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[100] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_cf_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[101] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[102] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[103] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[104] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[107] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ba_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[109] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_ba_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_ba_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_ba_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_ba_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_ba_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[105] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[106] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ab_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[108] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[118] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[259] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_02_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[260] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_02_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_01_02_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[249] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_07_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1256] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_07_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_07_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[635] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_00_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_01_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[753] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_01_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1257] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_06_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_05_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1258] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_05_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_03_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1320] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_03_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1363] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_04_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_01_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_01_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_01_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_01_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_01_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_01_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_01_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_01_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[126] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[466] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1308] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1323] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1901] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1902] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1915] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1916] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_03_01_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_03_01_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_01_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1914] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2029] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2030] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_03_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_03_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_03_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_03_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_03_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_03_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_03_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[130] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1179] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_06_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_06_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_02_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1237] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1260] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1276] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2778] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_00_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1337] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2720] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_07_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_07_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1378] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_05_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1393] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_04_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2760] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_05_01_F2_leaf, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_05_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_05_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_05_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_05_02_mprefix, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_05_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_05_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_05_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_05_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[132] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[467] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1195] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1197] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_06_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[629] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[636] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_02_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_03_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[754] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_03_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1080] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1157] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1384] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_07_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_07_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1181] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_05_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1196] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_05_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_05_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1190] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1355] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_07_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_07_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_07_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_07_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_07_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_07_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_07_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[250] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_07_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1900] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_04_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2745] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_05_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2746] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2773] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_01_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2779] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_06_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_02_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_02_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_02_01_mprefix, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_02_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_02_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_02_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_02_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[251] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[889] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_07_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_05_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[909] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_05_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1177] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2718] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2719] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_06_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_06_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1898] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_01_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1913] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_02_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2028] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_03_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2042] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_04_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_00_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_00_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_00_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_00_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_00_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_00_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_00_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_00_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[603] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1314] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_01_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_reg_00_modrmrm, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_01_modrmrm, - /* 02 */ (const void *)&gRootTable_root_0f_01_reg_02_modrmrm, - /* 03 */ (const void *)&gRootTable_root_0f_01_reg_03_modrmrm, - /* 04 */ (const void *)&gRootTable_root_0f_01_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_reg_05_modrmrm, - /* 06 */ (const void *)&gRootTable_root_0f_01_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_01_reg_07_modrmrm, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[465] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[596] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[598] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[603] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_05_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1220] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_01_mem_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_01_mem_05_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1279] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1307] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1313] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_01_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_01_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_01_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_01_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_01_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_01_mem_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_01_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_01_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_01_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_01_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[121] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[793] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[794] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_00_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[795] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_1c_cldm_mem_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_00_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_00_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_00_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_00_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[797] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[798] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[799] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[800] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[801] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[802] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[803] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[796] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[797] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[798] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[799] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[800] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[801] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[802] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_cldm_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[803] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_1c_cldm_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_1c_cldm_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_1c_cldm_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_1c_cldm_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1c_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[786] -}; - -const ND_TABLE_FEATURE gRootTable_root_0f_1c_feature = -{ - ND_ILUT_FEATURE, - { - /* 00 */ (const void *)&gRootTable_root_0f_1c_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_1c_cldm_modrmmod, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[124] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_07_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[125] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_07_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_07_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[128] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[131] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2769] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2770] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_06_NP_auxiliary, - /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_06_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_06_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[409] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_01_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[410] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_01_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_01_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[411] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_00_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[412] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_00_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[588] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_02_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1120] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2765] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2766] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_04_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_04_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_03_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1325] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_03_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2761] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2762] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_05_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_ae_mem_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_ae_mem_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_ae_mem_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_ae_mem_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_ae_mem_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_ae_mem_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_ae_mem_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[447] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_F3_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[448] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_05_F3_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_05_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[594] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_05_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_05_F3_auxiliary, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[630] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1385] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1394] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1395] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_06_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_06_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_04_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1120] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_04_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_00_F3_64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1174] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_00_F3_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_00_F3_auxiliary, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_01_F3_64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1175] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_01_F3_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_01_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_01_F3_auxiliary, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1278] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_07_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2715] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_02_F3_auxiliary, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2716] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_03_F3_auxiliary, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_ae_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_reg_00_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_01_mprefix, - /* 02 */ (const void *)&gRootTable_root_0f_ae_reg_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_ae_reg_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_ae_reg_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_ae_reg_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_ae_reg_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_ae_reg_07_mprefix, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_ae_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_ae_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_ae_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[129] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_46_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[134] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_42_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[135] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[136] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[137] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_47_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[138] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_43_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[139] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[140] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[141] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_41_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[142] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[143] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_49_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[144] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_45_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[145] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_40_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[146] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_4a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[147] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_48_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[148] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_44_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[149] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[173] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[174] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[178] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c2_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[183] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c2_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c2_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_c2_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_c2_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[187] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[188] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[189] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_01_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[190] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_01_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_01_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1899] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2025] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2043] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_06_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_06_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2026] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_07_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2763] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2764] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_03_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2767] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2768] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_04_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2771] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2772] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_05_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_05_NP_auxiliary, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_c7_mem_01_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_c7_mem_03_mprefix, - /* 04 */ (const void *)&gRootTable_root_0f_c7_mem_04_mprefix, - /* 05 */ (const void *)&gRootTable_root_0f_c7_mem_05_mprefix, - /* 06 */ (const void *)&gRootTable_root_0f_c7_mem_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_c7_mem_07_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1178] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1184] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_07_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1185] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_07_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_07_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_07_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1182] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1183] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_reg_06_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1259] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c7_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_reg_06_None_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_06_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_c7_reg_06_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_c7_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_c7_reg_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_c7_reg_07_mprefix, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_c7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_c7_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_c7_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[192] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2f_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[193] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2f_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2f_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[194] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[195] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_3c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[196] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[202] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[204] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e6_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[218] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e6_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_e6_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_e6_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_e6_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[203] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[209] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5b_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[220] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5b_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5b_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5b_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[205] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[211] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[212] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2d_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[217] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2d_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2d_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_2d_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_2d_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[206] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[210] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[213] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5a_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[216] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5a_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5a_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5a_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_5a_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[207] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[208] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[214] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2a_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[215] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2a_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2a_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_2a_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_2a_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[219] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[221] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[222] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2c_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[223] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2c_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2c_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_2c_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_2c_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[241] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[242] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[243] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5e_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[244] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5e_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5e_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5e_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_5e_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_39_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[245] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_77_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[248] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_77_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_77_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[254] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_03_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[816] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_03_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[255] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_02_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[815] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_07_02_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[813] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[814] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[817] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[818] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[819] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_07_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[820] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_1e_cet_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_02_auxiliary, - /* 03 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_03_auxiliary, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[805] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[806] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[807] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1188] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_01_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1187] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_1e_cet_reg_01_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_rexw_auxiliary, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[808] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[809] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[810] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[811] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[812] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_1e_cet_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1e_cet_reg_01_auxiliary, - /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_1e_cet_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_1e_cet_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_1e_cet_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_1e_cet_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_1e_cet_reg_07_modrmrm, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_cet_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[804] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_1e_cet_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_cet_mem_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_1e_cet_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1e_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[788] -}; - -const ND_TABLE_FEATURE gRootTable_root_0f_1e_feature = -{ - ND_ILUT_FEATURE, - { - /* 00 */ (const void *)&gRootTable_root_0f_1e_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_1e_cet_modrmmod, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_66_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[262] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_78_None_66_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_78_None_66_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[455] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2027] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_78_None_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_78_None_66_modrmreg, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_78_None_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1352] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_78_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_78_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_78_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_78_None_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_78_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[263] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[456] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2041] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_79_None_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_79_None_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_79_None_reg_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2041] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_79_None_mem_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_None_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_79_None_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_79_None_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1215] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_79_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_79_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_79_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_79_None_modrmmod, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_79_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[306] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_None_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[416] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_37_None_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2721] -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_37_None_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_37_cyrix_leaf, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[420] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_None_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[421] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_7c_None_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_7c_None_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_7c_None_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7c_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1354] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_7c_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_7c_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_7c_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_7c_None_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_7c_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[424] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_None_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[425] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_7d_None_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_7d_None_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_7d_None_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7d_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1221] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_7d_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_7d_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_7d_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_7d_None_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_7d_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_af_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[428] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_08_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[463] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_86_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[473] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_82_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[475] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[479] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[481] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[486] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[599] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_00_mem_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_mem_06_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_00_mem_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[601] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[619] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1309] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1334] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1597] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1598] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_00_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_00_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_00_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_00_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_00_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_00_mem_06_mprefix, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[486] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_06_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[600] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_00_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_reg_06_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_00_reg_06_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[601] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[619] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1310] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1335] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1597] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1598] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_00_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_00_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_00_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_00_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_00_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_00_reg_06_mprefix, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_00_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[487] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b8_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1029] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_b8_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_b8_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_b8_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_87_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[490] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_83_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[492] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[494] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[496] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_81_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[498] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[500] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_89_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[502] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_85_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[504] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_80_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[506] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_8a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[508] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_88_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[511] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_84_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[513] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[585] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_02_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[586] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_02_mem_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_02_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f0_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[587] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f0_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_0f_f0_mem_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_f0_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_f0_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b4_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[595] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_b4_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_b4_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b5_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[597] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_b5_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_b5_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[616] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_03_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[617] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_03_mem_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_03_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b2_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[618] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_b2_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_b2_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[623] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f7_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[624] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f7_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f7_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_f7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_f7_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[625] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[626] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[627] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5f_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[628] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5f_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5f_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5f_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_5f_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[631] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[632] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[633] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5d_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[634] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5d_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5d_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5d_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_5d_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_00_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[637] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_00_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2774] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_01_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2775] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_02_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_02_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_a6_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_a6_reg_00_modrmrm, - /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_01_modrmrm, - /* 02 */ (const void *)&gRootTable_root_0f_a6_reg_02_modrmrm, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_a6_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_a6_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_20_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[638] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_21_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[639] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_22_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[640] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_23_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[641] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_24_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[642] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_26_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[643] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[674] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_28_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[676] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_28_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_28_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_28_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[675] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_29_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[677] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_29_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_29_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_29_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[682] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[713] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_6e_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[683] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6e_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[714] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_6e_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_6e_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_6e_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_6e_NP_auxiliary, - /* 01 */ (const void *)&gRootTable_root_0f_6e_66_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[684] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_NP_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[716] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_NP_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_7e_None_NP_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[685] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_66_rexw_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[717] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_7e_None_66_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_7e_None_66_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_7e_None_66_rexw_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_None_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[718] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_7e_None_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_7e_None_NP_auxiliary, - /* 01 */ (const void *)&gRootTable_root_0f_7e_None_66_auxiliary, - /* 02 */ (const void *)&gRootTable_root_0f_7e_None_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7e_cyrix_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1312] -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_7e_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ (const void *)&gRootTable_root_0f_7e_None_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_7e_cyrix_leaf, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[686] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[694] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[700] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[729] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_12_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_12_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_12_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_12_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_12_mem_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[686] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[694] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_12_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[729] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_12_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_12_reg_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_12_reg_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_12_reg_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_12_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_12_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_12_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[689] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[720] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[721] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d6_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_d6_reg_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_d6_reg_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_d6_reg_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d6_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[720] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d6_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_d6_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_d6_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_d6_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_d6_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[690] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[692] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6f_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[715] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_6f_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_6f_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_6f_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[691] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[693] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7f_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[719] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_7f_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_7f_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_7f_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_7f_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[695] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[697] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[728] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_16_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_16_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_16_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_16_mem_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[699] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_16_reg_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[728] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_16_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_16_reg_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_16_reg_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_16_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_16_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_16_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[696] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_17_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[698] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_17_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_17_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_17_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_17_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_17_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[701] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_13_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[702] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_13_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_13_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_13_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_13_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_13_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[703] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_50_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[704] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_50_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_50_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_50_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_50_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_50_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[705] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e7_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[710] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e7_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e7_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_e7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_e7_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c3_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[707] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c3_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_c3_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_c3_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[708] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[709] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[711] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2b_mem_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[712] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2b_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2b_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2b_mem_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_2b_mem_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_2b_mem_F2_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_2b_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_2b_mem_mprefix, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[724] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[732] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[739] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_10_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[741] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_10_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_10_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_10_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_10_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_10_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[725] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[733] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[740] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_11_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[742] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_11_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_11_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_11_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_11_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_11_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_be_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[736] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_bf_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[737] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[743] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[744] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[748] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[749] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[750] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_59_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[751] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_59_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_59_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_59_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_59_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_59_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[757] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[758] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[759] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[760] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[761] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[762] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[763] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[764] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_0d_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_0d_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_0d_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_0d_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_0d_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_0d_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_0d_reg_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1035] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1036] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1037] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1038] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1039] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1042] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1051] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0d_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1052] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_0d_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_0d_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_0d_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_0d_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_0d_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_0d_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_0d_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_0d_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_0d_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_0d_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_0d_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[765] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[766] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[767] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[768] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[769] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[770] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[771] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[772] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_None_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_None_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_None_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_None_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_None_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_None_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_None_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_None_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_18_None_reg_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[769] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[770] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[771] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[772] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1043] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1045] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1047] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_None_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1049] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_None_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_None_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_None_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_None_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_None_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_None_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_None_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_None_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_18_None_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_None_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_None_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_18_None_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[774] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[775] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[776] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[777] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[778] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[779] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[781] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[783] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_piti_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_piti_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_piti_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_piti_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_piti_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_piti_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_piti_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_piti_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_18_piti_reg_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[778] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[779] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[780] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_06_riprel_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1041] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_06_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_riprel_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[782] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_07_riprel_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1040] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_18_piti_mem_07_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_riprel_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1044] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1046] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1048] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_18_piti_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1050] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_18_piti_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_18_piti_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_18_piti_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_18_piti_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_0f_18_piti_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_0f_18_piti_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_18_piti_mem_06_auxiliary, - /* 07 */ (const void *)&gRootTable_root_0f_18_piti_mem_07_auxiliary, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_18_piti_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_piti_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_0f_18_piti_reg_modrmreg, - } -}; - -const ND_TABLE_FEATURE gRootTable_root_0f_18_feature = -{ - ND_ILUT_FEATURE, - { - /* 00 */ (const void *)&gRootTable_root_0f_18_None_modrmmod, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_18_piti_modrmmod, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_19_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[773] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[787] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_1f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[789] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[834] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_56_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[835] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_56_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_56_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_56_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[852] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6b_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[853] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6b_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_6b_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_6b_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[854] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_63_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[855] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_63_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_63_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_63_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[857] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_67_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[858] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_67_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_67_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_67_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[859] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fc_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[860] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_fc_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_fc_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_fc_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[861] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fe_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[862] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_fe_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_fe_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_fe_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[863] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d4_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[864] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d4_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d4_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d4_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[865] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ec_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[866] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ec_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ec_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ec_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[867] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ed_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[868] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ed_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ed_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ed_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[869] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_dc_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[870] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_dc_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_dc_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_dc_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[871] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_dd_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[872] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_dd_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_dd_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_dd_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[873] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fd_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[874] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_fd_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_fd_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_fd_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[877] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_db_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[878] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_db_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_db_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_db_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[879] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_df_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[880] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_df_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_df_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_df_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[882] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e0_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[883] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e0_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e0_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e0_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bf_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[884] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[922] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_1c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[923] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_ae_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[924] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[925] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[926] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_90_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[927] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[928] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[929] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_94_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[930] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[931] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[932] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_8e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[933] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_96_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[934] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[935] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[936] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_86_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[937] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_a7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[938] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_97_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[939] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_87_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[940] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_9a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[941] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_aa_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[942] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[956] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_0c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[957] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_b7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1003] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0f_bb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1118] -}; - -const ND_TABLE_OPCODE gRootTable_root_0f_0f_opcode_3dnow = -{ - ND_ILUT_OPCODE_3DNOW, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ (const void *)&gRootTable_root_0f_0f_0c_leaf, - /* 0d */ (const void *)&gRootTable_root_0f_0f_0d_leaf, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ (const void *)&gRootTable_root_0f_0f_1c_leaf, - /* 1d */ (const void *)&gRootTable_root_0f_0f_1d_leaf, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ (const void *)&gRootTable_root_0f_0f_86_leaf, - /* 87 */ (const void *)&gRootTable_root_0f_0f_87_leaf, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ (const void *)&gRootTable_root_0f_0f_8a_leaf, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ (const void *)&gRootTable_root_0f_0f_8e_leaf, - /* 8f */ ND_NULL, - /* 90 */ (const void *)&gRootTable_root_0f_0f_90_leaf, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ (const void *)&gRootTable_root_0f_0f_94_leaf, - /* 95 */ ND_NULL, - /* 96 */ (const void *)&gRootTable_root_0f_0f_96_leaf, - /* 97 */ (const void *)&gRootTable_root_0f_0f_97_leaf, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ (const void *)&gRootTable_root_0f_0f_9a_leaf, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ (const void *)&gRootTable_root_0f_0f_9e_leaf, - /* 9f */ ND_NULL, - /* a0 */ (const void *)&gRootTable_root_0f_0f_a0_leaf, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ (const void *)&gRootTable_root_0f_0f_a4_leaf, - /* a5 */ ND_NULL, - /* a6 */ (const void *)&gRootTable_root_0f_0f_a6_leaf, - /* a7 */ (const void *)&gRootTable_root_0f_0f_a7_leaf, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ (const void *)&gRootTable_root_0f_0f_aa_leaf, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ (const void *)&gRootTable_root_0f_0f_ae_leaf, - /* af */ ND_NULL, - /* b0 */ (const void *)&gRootTable_root_0f_0f_b0_leaf, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ (const void *)&gRootTable_root_0f_0f_b4_leaf, - /* b5 */ ND_NULL, - /* b6 */ (const void *)&gRootTable_root_0f_0f_b6_leaf, - /* b7 */ (const void *)&gRootTable_root_0f_0f_b7_leaf, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ (const void *)&gRootTable_root_0f_0f_bb_leaf, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ (const void *)&gRootTable_root_0f_0f_bf_leaf, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[885] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e3_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[886] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e3_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e3_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e3_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[891] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_74_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[892] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_74_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_74_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_74_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[893] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_76_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[894] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_76_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_76_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_76_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[896] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_75_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[897] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_75_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_75_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_75_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[900] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_64_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[901] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_64_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_64_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_64_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[902] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_66_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[903] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_66_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_66_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_66_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[905] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_65_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[906] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_65_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_65_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_65_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[918] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c5_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[919] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c5_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c5_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_c5_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_c5_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[962] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[964] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c4_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c4_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c4_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[963] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c4_mem_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[965] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c4_mem_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c4_mem_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c4_mem_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_c4_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_c4_mem_mprefix, - /* 01 */ (const void *)&gRootTable_root_0f_c4_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[968] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f5_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[969] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f5_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f5_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f5_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[972] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ee_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[973] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ee_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ee_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ee_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[974] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_de_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[975] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_de_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_de_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_de_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[980] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ea_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[981] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ea_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ea_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ea_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[982] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_da_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[983] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_da_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_da_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_da_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[986] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d7_reg_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[987] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d7_reg_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d7_reg_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_d7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_d7_reg_mprefix, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1004] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e4_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1005] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e4_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e4_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e4_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1006] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e5_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1007] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e5_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e5_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e5_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1009] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d5_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1010] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d5_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d5_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d5_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1011] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f4_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1012] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f4_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f4_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f4_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1013] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1014] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1033] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_eb_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1034] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_eb_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_eb_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_eb_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1053] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f6_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1054] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f6_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f6_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f6_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1057] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1058] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1059] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_70_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1060] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_70_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_70_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_70_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_70_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_70_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1067] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1068] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_72_reg_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_72_reg_06_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1081] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_04_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1082] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_72_reg_04_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_72_reg_04_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1089] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_72_reg_02_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1090] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_72_reg_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_72_reg_02_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_72_reg_02_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_72_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_72_reg_02_mprefix, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_72_reg_04_mprefix, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_72_reg_06_mprefix, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_72_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_72_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1069] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1070] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f2_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_07_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1071] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_07_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_73_reg_07_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1072] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1073] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_73_reg_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_73_reg_06_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_03_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1093] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_03_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_73_reg_03_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1094] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_73_reg_02_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1095] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_73_reg_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_73_reg_02_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_73_reg_02_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_73_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_73_reg_02_mprefix, - /* 03 */ (const void *)&gRootTable_root_0f_73_reg_03_mprefix, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_73_reg_06_mprefix, - /* 07 */ (const void *)&gRootTable_root_0f_73_reg_07_mprefix, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_73_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_73_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1074] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f3_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1075] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f3_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f3_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f3_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1076] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_06_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1077] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_06_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_71_reg_06_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_71_reg_06_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1085] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_04_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1086] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_04_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_71_reg_04_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_71_reg_04_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1098] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_71_reg_02_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1099] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_71_reg_02_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_71_reg_02_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_71_reg_02_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_71_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_71_reg_02_mprefix, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_71_reg_04_mprefix, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_0f_71_reg_06_mprefix, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_71_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_71_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1078] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f1_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1079] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f1_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f1_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f1_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1083] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1084] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e2_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1087] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e1_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1088] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e1_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e1_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e1_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1091] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d2_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1092] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d2_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d2_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d2_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1096] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d3_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1097] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d3_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d3_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d3_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1100] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d1_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1101] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d1_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d1_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d1_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1102] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f8_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1103] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f8_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f8_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f8_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1104] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fa_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1105] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_fa_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_fa_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_fa_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1106] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_fb_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1107] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_fb_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_fb_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_fb_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1108] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e8_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1109] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e8_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e8_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e8_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1110] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_e9_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1111] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_e9_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_e9_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_e9_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1112] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d8_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1113] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d8_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d8_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d8_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1114] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_d9_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1115] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_d9_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_d9_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_d9_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1116] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_f9_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1117] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_f9_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_f9_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_f9_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1121] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_68_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1122] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_68_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_68_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_68_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1123] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6a_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1124] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6a_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_6a_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_6a_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6d_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1125] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6d_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_6d_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1126] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_69_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1127] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_69_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_69_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_69_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1128] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_60_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1129] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_60_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_60_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_60_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1130] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_62_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1131] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_62_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_62_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_62_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_6c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1132] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_6c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_6c_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1133] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_61_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1134] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_61_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_61_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_61_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1135] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1136] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1158] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ef_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1159] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_ef_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_ef_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_ef_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1166] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_53_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1167] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_53_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_53_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_53_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1176] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_33_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1180] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_36_cyrix_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1186] -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_36_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_36_cyrix_leaf, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_31_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1189] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7b_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1216] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_7b_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_7b_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_7b_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_7b_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_aa_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1217] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1218] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_52_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1219] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_52_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_52_NP_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_52_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_96_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1261] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_92_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1262] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1263] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1264] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_97_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1265] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_93_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1266] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1267] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1268] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_91_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1269] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1270] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_99_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1271] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_95_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1272] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_90_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1273] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_9a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1274] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_98_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1275] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_94_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1277] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1293] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a5_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1294] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ac_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1302] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ad_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1303] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1305] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c6_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1306] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_c6_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_c6_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_c6_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1316] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1317] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1318] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_51_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1319] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_51_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_51_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_51_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_51_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_51_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1348] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1349] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1350] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_5c_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1351] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_5c_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_5c_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_5c_66_leaf, - /* 02 */ (const void *)&gRootTable_root_0f_5c_F3_leaf, - /* 03 */ (const void *)&gRootTable_root_0f_5c_F2_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_7a_cyrix_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1353] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_7a_cyrix_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_0f_7a_cyrix_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VENDOR gRootTable_root_0f_7a_vendor = -{ - ND_ILUT_VENDOR, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_7a_cyrix_modrmmod, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1356] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_34_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1357] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_35_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1358] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1359] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1388] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1389] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_2e_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_2e_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1390] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1391] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1392] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1396] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1397] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_15_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_15_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1398] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1399] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_14_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_14_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2713] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2714] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_0f_09_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_0f_09_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2717] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2727] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2728] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2740] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_02_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2741] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_04_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2742] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_03_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2743] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_01_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2744] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_05_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2776] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2777] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_F3_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_00_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_00_mprefix, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_0f_a7_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_0f_a7_reg_00_modrmrm, - /* 01 */ (const void *)&gRootTable_root_0f_a7_reg_01_modrmrm, - /* 02 */ (const void *)&gRootTable_root_0f_a7_reg_02_modrmrm, - /* 03 */ (const void *)&gRootTable_root_0f_a7_reg_03_modrmrm, - /* 04 */ (const void *)&gRootTable_root_0f_a7_reg_04_modrmrm, - /* 05 */ (const void *)&gRootTable_root_0f_a7_reg_05_modrmrm, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_0f_a7_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2758] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2759] -}; - -const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix = -{ - ND_ILUT_MAN_PREFIX, - { - /* 00 */ (const void *)&gRootTable_root_0f_57_NP_leaf, - /* 01 */ (const void *)&gRootTable_root_0f_57_66_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gRootTable_root_0f_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gRootTable_root_0f_00_modrmmod, - /* 01 */ (const void *)&gRootTable_root_0f_01_modrmmod, - /* 02 */ (const void *)&gRootTable_root_0f_02_modrmmod, - /* 03 */ (const void *)&gRootTable_root_0f_03_modrmmod, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_0f_05_leaf, - /* 06 */ (const void *)&gRootTable_root_0f_06_leaf, - /* 07 */ (const void *)&gRootTable_root_0f_07_leaf, - /* 08 */ (const void *)&gRootTable_root_0f_08_leaf, - /* 09 */ (const void *)&gRootTable_root_0f_09_auxiliary, - /* 0a */ ND_NULL, - /* 0b */ (const void *)&gRootTable_root_0f_0b_leaf, - /* 0c */ ND_NULL, - /* 0d */ (const void *)&gRootTable_root_0f_0d_modrmmod, - /* 0e */ (const void *)&gRootTable_root_0f_0e_leaf, - /* 0f */ (const void *)&gRootTable_root_0f_0f_opcode_3dnow, - /* 10 */ (const void *)&gRootTable_root_0f_10_mprefix, - /* 11 */ (const void *)&gRootTable_root_0f_11_mprefix, - /* 12 */ (const void *)&gRootTable_root_0f_12_modrmmod, - /* 13 */ (const void *)&gRootTable_root_0f_13_modrmmod, - /* 14 */ (const void *)&gRootTable_root_0f_14_mprefix, - /* 15 */ (const void *)&gRootTable_root_0f_15_mprefix, - /* 16 */ (const void *)&gRootTable_root_0f_16_modrmmod, - /* 17 */ (const void *)&gRootTable_root_0f_17_modrmmod, - /* 18 */ (const void *)&gRootTable_root_0f_18_feature, - /* 19 */ (const void *)&gRootTable_root_0f_19_leaf, - /* 1a */ (const void *)&gRootTable_root_0f_1a_feature, - /* 1b */ (const void *)&gRootTable_root_0f_1b_feature, - /* 1c */ (const void *)&gRootTable_root_0f_1c_feature, - /* 1d */ (const void *)&gRootTable_root_0f_1d_leaf, - /* 1e */ (const void *)&gRootTable_root_0f_1e_feature, - /* 1f */ (const void *)&gRootTable_root_0f_1f_leaf, - /* 20 */ (const void *)&gRootTable_root_0f_20_leaf, - /* 21 */ (const void *)&gRootTable_root_0f_21_leaf, - /* 22 */ (const void *)&gRootTable_root_0f_22_leaf, - /* 23 */ (const void *)&gRootTable_root_0f_23_leaf, - /* 24 */ (const void *)&gRootTable_root_0f_24_leaf, - /* 25 */ ND_NULL, - /* 26 */ (const void *)&gRootTable_root_0f_26_leaf, - /* 27 */ ND_NULL, - /* 28 */ (const void *)&gRootTable_root_0f_28_mprefix, - /* 29 */ (const void *)&gRootTable_root_0f_29_mprefix, - /* 2a */ (const void *)&gRootTable_root_0f_2a_mprefix, - /* 2b */ (const void *)&gRootTable_root_0f_2b_modrmmod, - /* 2c */ (const void *)&gRootTable_root_0f_2c_mprefix, - /* 2d */ (const void *)&gRootTable_root_0f_2d_mprefix, - /* 2e */ (const void *)&gRootTable_root_0f_2e_mprefix, - /* 2f */ (const void *)&gRootTable_root_0f_2f_mprefix, - /* 30 */ (const void *)&gRootTable_root_0f_30_leaf, - /* 31 */ (const void *)&gRootTable_root_0f_31_leaf, - /* 32 */ (const void *)&gRootTable_root_0f_32_leaf, - /* 33 */ (const void *)&gRootTable_root_0f_33_leaf, - /* 34 */ (const void *)&gRootTable_root_0f_34_leaf, - /* 35 */ (const void *)&gRootTable_root_0f_35_leaf, - /* 36 */ (const void *)&gRootTable_root_0f_36_vendor, - /* 37 */ (const void *)&gRootTable_root_0f_37_vendor, - /* 38 */ (const void *)&gRootTable_root_0f_38_opcode, - /* 39 */ (const void *)&gRootTable_root_0f_39_leaf, - /* 3a */ (const void *)&gRootTable_root_0f_3a_opcode, - /* 3b */ ND_NULL, - /* 3c */ (const void *)&gRootTable_root_0f_3c_leaf, - /* 3d */ (const void *)&gRootTable_root_0f_3d_leaf, - /* 3e */ ND_NULL, - /* 3f */ (const void *)&gRootTable_root_0f_3f_leaf, - /* 40 */ (const void *)&gRootTable_root_0f_40_leaf, - /* 41 */ (const void *)&gRootTable_root_0f_41_leaf, - /* 42 */ (const void *)&gRootTable_root_0f_42_leaf, - /* 43 */ (const void *)&gRootTable_root_0f_43_leaf, - /* 44 */ (const void *)&gRootTable_root_0f_44_leaf, - /* 45 */ (const void *)&gRootTable_root_0f_45_leaf, - /* 46 */ (const void *)&gRootTable_root_0f_46_leaf, - /* 47 */ (const void *)&gRootTable_root_0f_47_leaf, - /* 48 */ (const void *)&gRootTable_root_0f_48_leaf, - /* 49 */ (const void *)&gRootTable_root_0f_49_leaf, - /* 4a */ (const void *)&gRootTable_root_0f_4a_leaf, - /* 4b */ (const void *)&gRootTable_root_0f_4b_leaf, - /* 4c */ (const void *)&gRootTable_root_0f_4c_leaf, - /* 4d */ (const void *)&gRootTable_root_0f_4d_leaf, - /* 4e */ (const void *)&gRootTable_root_0f_4e_leaf, - /* 4f */ (const void *)&gRootTable_root_0f_4f_leaf, - /* 50 */ (const void *)&gRootTable_root_0f_50_modrmmod, - /* 51 */ (const void *)&gRootTable_root_0f_51_mprefix, - /* 52 */ (const void *)&gRootTable_root_0f_52_mprefix, - /* 53 */ (const void *)&gRootTable_root_0f_53_mprefix, - /* 54 */ (const void *)&gRootTable_root_0f_54_mprefix, - /* 55 */ (const void *)&gRootTable_root_0f_55_mprefix, - /* 56 */ (const void *)&gRootTable_root_0f_56_mprefix, - /* 57 */ (const void *)&gRootTable_root_0f_57_mprefix, - /* 58 */ (const void *)&gRootTable_root_0f_58_mprefix, - /* 59 */ (const void *)&gRootTable_root_0f_59_mprefix, - /* 5a */ (const void *)&gRootTable_root_0f_5a_mprefix, - /* 5b */ (const void *)&gRootTable_root_0f_5b_mprefix, - /* 5c */ (const void *)&gRootTable_root_0f_5c_mprefix, - /* 5d */ (const void *)&gRootTable_root_0f_5d_mprefix, - /* 5e */ (const void *)&gRootTable_root_0f_5e_mprefix, - /* 5f */ (const void *)&gRootTable_root_0f_5f_mprefix, - /* 60 */ (const void *)&gRootTable_root_0f_60_mprefix, - /* 61 */ (const void *)&gRootTable_root_0f_61_mprefix, - /* 62 */ (const void *)&gRootTable_root_0f_62_mprefix, - /* 63 */ (const void *)&gRootTable_root_0f_63_mprefix, - /* 64 */ (const void *)&gRootTable_root_0f_64_mprefix, - /* 65 */ (const void *)&gRootTable_root_0f_65_mprefix, - /* 66 */ (const void *)&gRootTable_root_0f_66_mprefix, - /* 67 */ (const void *)&gRootTable_root_0f_67_mprefix, - /* 68 */ (const void *)&gRootTable_root_0f_68_mprefix, - /* 69 */ (const void *)&gRootTable_root_0f_69_mprefix, - /* 6a */ (const void *)&gRootTable_root_0f_6a_mprefix, - /* 6b */ (const void *)&gRootTable_root_0f_6b_mprefix, - /* 6c */ (const void *)&gRootTable_root_0f_6c_mprefix, - /* 6d */ (const void *)&gRootTable_root_0f_6d_mprefix, - /* 6e */ (const void *)&gRootTable_root_0f_6e_mprefix, - /* 6f */ (const void *)&gRootTable_root_0f_6f_mprefix, - /* 70 */ (const void *)&gRootTable_root_0f_70_mprefix, - /* 71 */ (const void *)&gRootTable_root_0f_71_modrmmod, - /* 72 */ (const void *)&gRootTable_root_0f_72_modrmmod, - /* 73 */ (const void *)&gRootTable_root_0f_73_modrmmod, - /* 74 */ (const void *)&gRootTable_root_0f_74_mprefix, - /* 75 */ (const void *)&gRootTable_root_0f_75_mprefix, - /* 76 */ (const void *)&gRootTable_root_0f_76_mprefix, - /* 77 */ (const void *)&gRootTable_root_0f_77_mprefix, - /* 78 */ (const void *)&gRootTable_root_0f_78_vendor, - /* 79 */ (const void *)&gRootTable_root_0f_79_vendor, - /* 7a */ (const void *)&gRootTable_root_0f_7a_vendor, - /* 7b */ (const void *)&gRootTable_root_0f_7b_vendor, - /* 7c */ (const void *)&gRootTable_root_0f_7c_vendor, - /* 7d */ (const void *)&gRootTable_root_0f_7d_vendor, - /* 7e */ (const void *)&gRootTable_root_0f_7e_vendor, - /* 7f */ (const void *)&gRootTable_root_0f_7f_mprefix, - /* 80 */ (const void *)&gRootTable_root_0f_80_leaf, - /* 81 */ (const void *)&gRootTable_root_0f_81_leaf, - /* 82 */ (const void *)&gRootTable_root_0f_82_leaf, - /* 83 */ (const void *)&gRootTable_root_0f_83_leaf, - /* 84 */ (const void *)&gRootTable_root_0f_84_leaf, - /* 85 */ (const void *)&gRootTable_root_0f_85_leaf, - /* 86 */ (const void *)&gRootTable_root_0f_86_leaf, - /* 87 */ (const void *)&gRootTable_root_0f_87_leaf, - /* 88 */ (const void *)&gRootTable_root_0f_88_leaf, - /* 89 */ (const void *)&gRootTable_root_0f_89_leaf, - /* 8a */ (const void *)&gRootTable_root_0f_8a_leaf, - /* 8b */ (const void *)&gRootTable_root_0f_8b_leaf, - /* 8c */ (const void *)&gRootTable_root_0f_8c_leaf, - /* 8d */ (const void *)&gRootTable_root_0f_8d_leaf, - /* 8e */ (const void *)&gRootTable_root_0f_8e_leaf, - /* 8f */ (const void *)&gRootTable_root_0f_8f_leaf, - /* 90 */ (const void *)&gRootTable_root_0f_90_leaf, - /* 91 */ (const void *)&gRootTable_root_0f_91_leaf, - /* 92 */ (const void *)&gRootTable_root_0f_92_leaf, - /* 93 */ (const void *)&gRootTable_root_0f_93_leaf, - /* 94 */ (const void *)&gRootTable_root_0f_94_leaf, - /* 95 */ (const void *)&gRootTable_root_0f_95_leaf, - /* 96 */ (const void *)&gRootTable_root_0f_96_leaf, - /* 97 */ (const void *)&gRootTable_root_0f_97_leaf, - /* 98 */ (const void *)&gRootTable_root_0f_98_leaf, - /* 99 */ (const void *)&gRootTable_root_0f_99_leaf, - /* 9a */ (const void *)&gRootTable_root_0f_9a_leaf, - /* 9b */ (const void *)&gRootTable_root_0f_9b_leaf, - /* 9c */ (const void *)&gRootTable_root_0f_9c_leaf, - /* 9d */ (const void *)&gRootTable_root_0f_9d_leaf, - /* 9e */ (const void *)&gRootTable_root_0f_9e_leaf, - /* 9f */ (const void *)&gRootTable_root_0f_9f_leaf, - /* a0 */ (const void *)&gRootTable_root_0f_a0_leaf, - /* a1 */ (const void *)&gRootTable_root_0f_a1_leaf, - /* a2 */ (const void *)&gRootTable_root_0f_a2_leaf, - /* a3 */ (const void *)&gRootTable_root_0f_a3_leaf, - /* a4 */ (const void *)&gRootTable_root_0f_a4_leaf, - /* a5 */ (const void *)&gRootTable_root_0f_a5_leaf, - /* a6 */ (const void *)&gRootTable_root_0f_a6_modrmmod, - /* a7 */ (const void *)&gRootTable_root_0f_a7_modrmmod, - /* a8 */ (const void *)&gRootTable_root_0f_a8_leaf, - /* a9 */ (const void *)&gRootTable_root_0f_a9_leaf, - /* aa */ (const void *)&gRootTable_root_0f_aa_leaf, - /* ab */ (const void *)&gRootTable_root_0f_ab_leaf, - /* ac */ (const void *)&gRootTable_root_0f_ac_leaf, - /* ad */ (const void *)&gRootTable_root_0f_ad_leaf, - /* ae */ (const void *)&gRootTable_root_0f_ae_modrmmod, - /* af */ (const void *)&gRootTable_root_0f_af_leaf, - /* b0 */ (const void *)&gRootTable_root_0f_b0_leaf, - /* b1 */ (const void *)&gRootTable_root_0f_b1_leaf, - /* b2 */ (const void *)&gRootTable_root_0f_b2_modrmmod, - /* b3 */ (const void *)&gRootTable_root_0f_b3_leaf, - /* b4 */ (const void *)&gRootTable_root_0f_b4_modrmmod, - /* b5 */ (const void *)&gRootTable_root_0f_b5_modrmmod, - /* b6 */ (const void *)&gRootTable_root_0f_b6_leaf, - /* b7 */ (const void *)&gRootTable_root_0f_b7_leaf, - /* b8 */ (const void *)&gRootTable_root_0f_b8_auxiliary, - /* b9 */ (const void *)&gRootTable_root_0f_b9_leaf, - /* ba */ (const void *)&gRootTable_root_0f_ba_modrmreg, - /* bb */ (const void *)&gRootTable_root_0f_bb_leaf, - /* bc */ (const void *)&gRootTable_root_0f_bc_auxiliary, - /* bd */ (const void *)&gRootTable_root_0f_bd_auxiliary, - /* be */ (const void *)&gRootTable_root_0f_be_leaf, - /* bf */ (const void *)&gRootTable_root_0f_bf_leaf, - /* c0 */ (const void *)&gRootTable_root_0f_c0_leaf, - /* c1 */ (const void *)&gRootTable_root_0f_c1_leaf, - /* c2 */ (const void *)&gRootTable_root_0f_c2_mprefix, - /* c3 */ (const void *)&gRootTable_root_0f_c3_modrmmod, - /* c4 */ (const void *)&gRootTable_root_0f_c4_modrmmod, - /* c5 */ (const void *)&gRootTable_root_0f_c5_modrmmod, - /* c6 */ (const void *)&gRootTable_root_0f_c6_mprefix, - /* c7 */ (const void *)&gRootTable_root_0f_c7_modrmmod, - /* c8 */ (const void *)&gRootTable_root_0f_c8_leaf, - /* c9 */ (const void *)&gRootTable_root_0f_c9_leaf, - /* ca */ (const void *)&gRootTable_root_0f_ca_leaf, - /* cb */ (const void *)&gRootTable_root_0f_cb_leaf, - /* cc */ (const void *)&gRootTable_root_0f_cc_leaf, - /* cd */ (const void *)&gRootTable_root_0f_cd_leaf, - /* ce */ (const void *)&gRootTable_root_0f_ce_leaf, - /* cf */ (const void *)&gRootTable_root_0f_cf_leaf, - /* d0 */ (const void *)&gRootTable_root_0f_d0_mprefix, - /* d1 */ (const void *)&gRootTable_root_0f_d1_mprefix, - /* d2 */ (const void *)&gRootTable_root_0f_d2_mprefix, - /* d3 */ (const void *)&gRootTable_root_0f_d3_mprefix, - /* d4 */ (const void *)&gRootTable_root_0f_d4_mprefix, - /* d5 */ (const void *)&gRootTable_root_0f_d5_mprefix, - /* d6 */ (const void *)&gRootTable_root_0f_d6_modrmmod, - /* d7 */ (const void *)&gRootTable_root_0f_d7_modrmmod, - /* d8 */ (const void *)&gRootTable_root_0f_d8_mprefix, - /* d9 */ (const void *)&gRootTable_root_0f_d9_mprefix, - /* da */ (const void *)&gRootTable_root_0f_da_mprefix, - /* db */ (const void *)&gRootTable_root_0f_db_mprefix, - /* dc */ (const void *)&gRootTable_root_0f_dc_mprefix, - /* dd */ (const void *)&gRootTable_root_0f_dd_mprefix, - /* de */ (const void *)&gRootTable_root_0f_de_mprefix, - /* df */ (const void *)&gRootTable_root_0f_df_mprefix, - /* e0 */ (const void *)&gRootTable_root_0f_e0_mprefix, - /* e1 */ (const void *)&gRootTable_root_0f_e1_mprefix, - /* e2 */ (const void *)&gRootTable_root_0f_e2_mprefix, - /* e3 */ (const void *)&gRootTable_root_0f_e3_mprefix, - /* e4 */ (const void *)&gRootTable_root_0f_e4_mprefix, - /* e5 */ (const void *)&gRootTable_root_0f_e5_mprefix, - /* e6 */ (const void *)&gRootTable_root_0f_e6_mprefix, - /* e7 */ (const void *)&gRootTable_root_0f_e7_modrmmod, - /* e8 */ (const void *)&gRootTable_root_0f_e8_mprefix, - /* e9 */ (const void *)&gRootTable_root_0f_e9_mprefix, - /* ea */ (const void *)&gRootTable_root_0f_ea_mprefix, - /* eb */ (const void *)&gRootTable_root_0f_eb_mprefix, - /* ec */ (const void *)&gRootTable_root_0f_ec_mprefix, - /* ed */ (const void *)&gRootTable_root_0f_ed_mprefix, - /* ee */ (const void *)&gRootTable_root_0f_ee_mprefix, - /* ef */ (const void *)&gRootTable_root_0f_ef_mprefix, - /* f0 */ (const void *)&gRootTable_root_0f_f0_modrmmod, - /* f1 */ (const void *)&gRootTable_root_0f_f1_mprefix, - /* f2 */ (const void *)&gRootTable_root_0f_f2_mprefix, - /* f3 */ (const void *)&gRootTable_root_0f_f3_mprefix, - /* f4 */ (const void *)&gRootTable_root_0f_f4_mprefix, - /* f5 */ (const void *)&gRootTable_root_0f_f5_mprefix, - /* f6 */ (const void *)&gRootTable_root_0f_f6_mprefix, - /* f7 */ (const void *)&gRootTable_root_0f_f7_modrmmod, - /* f8 */ (const void *)&gRootTable_root_0f_f8_mprefix, - /* f9 */ (const void *)&gRootTable_root_0f_f9_mprefix, - /* fa */ (const void *)&gRootTable_root_0f_fa_mprefix, - /* fb */ (const void *)&gRootTable_root_0f_fb_mprefix, - /* fc */ (const void *)&gRootTable_root_0f_fc_mprefix, - /* fd */ (const void *)&gRootTable_root_0f_fd_mprefix, - /* fe */ (const void *)&gRootTable_root_0f_fe_mprefix, - /* ff */ (const void *)&gRootTable_root_0f_ff_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[3] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_3f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[5] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_10_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[6] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_11_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[7] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_12_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[8] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_13_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[9] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_14_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[10] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_15_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[11] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[12] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[23] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[55] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[156] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[830] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1244] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1344] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2754] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_80_00_leaf, - /* 01 */ (const void *)&gRootTable_root_80_01_leaf, - /* 02 */ (const void *)&gRootTable_root_80_02_leaf, - /* 03 */ (const void *)&gRootTable_root_80_03_leaf, - /* 04 */ (const void *)&gRootTable_root_80_04_leaf, - /* 05 */ (const void *)&gRootTable_root_80_05_leaf, - /* 06 */ (const void *)&gRootTable_root_80_06_leaf, - /* 07 */ (const void *)&gRootTable_root_80_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[13] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[24] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[56] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[157] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[831] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1245] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1345] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2755] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_81_00_leaf, - /* 01 */ (const void *)&gRootTable_root_81_01_leaf, - /* 02 */ (const void *)&gRootTable_root_81_02_leaf, - /* 03 */ (const void *)&gRootTable_root_81_03_leaf, - /* 04 */ (const void *)&gRootTable_root_81_04_leaf, - /* 05 */ (const void *)&gRootTable_root_81_05_leaf, - /* 06 */ (const void *)&gRootTable_root_81_06_leaf, - /* 07 */ (const void *)&gRootTable_root_81_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[14] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[25] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[57] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[158] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[832] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1246] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1346] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2756] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_82_00_leaf, - /* 01 */ (const void *)&gRootTable_root_82_01_leaf, - /* 02 */ (const void *)&gRootTable_root_82_02_leaf, - /* 03 */ (const void *)&gRootTable_root_82_03_leaf, - /* 04 */ (const void *)&gRootTable_root_82_04_leaf, - /* 05 */ (const void *)&gRootTable_root_82_05_leaf, - /* 06 */ (const void *)&gRootTable_root_82_06_leaf, - /* 07 */ (const void *)&gRootTable_root_82_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[15] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[26] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[58] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[159] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[833] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1247] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1347] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2757] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_83_00_leaf, - /* 01 */ (const void *)&gRootTable_root_83_01_leaf, - /* 02 */ (const void *)&gRootTable_root_83_02_leaf, - /* 03 */ (const void *)&gRootTable_root_83_03_leaf, - /* 04 */ (const void *)&gRootTable_root_83_04_leaf, - /* 05 */ (const void *)&gRootTable_root_83_05_leaf, - /* 06 */ (const void *)&gRootTable_root_83_06_leaf, - /* 07 */ (const void *)&gRootTable_root_83_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[17] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[18] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[19] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[20] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[21] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[22] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_20_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[49] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_21_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[50] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_22_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[51] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_23_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[52] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_24_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[53] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_25_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[54] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_63_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[65] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_63_64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[738] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_63_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_63_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gRootTable_root_63_64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_62_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[91] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_62_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_62_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[111] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[112] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[114] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[237] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[446] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[485] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[489] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1151] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_ff_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_ff_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_ff_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_ff_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_ff_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_ff_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_ff_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_ff_mem_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[112] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[237] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[446] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[485] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ff_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1151] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_ff_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_ff_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_ff_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_ff_reg_02_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_ff_reg_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_ff_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_ff_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_ff_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_ff_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[113] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_98_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[115] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_98_ds64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[117] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_98_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[225] -}; - -const ND_TABLE_DSIZE gRootTable_root_98_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_98_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_98_ds32_leaf, - /* 03 */ (const void *)&gRootTable_root_98_ds64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_99_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[116] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_99_ds64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[197] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_99_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[224] -}; - -const ND_TABLE_DSIZE gRootTable_root_99_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_99_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_99_ds32_leaf, - /* 03 */ (const void *)&gRootTable_root_99_ds64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[119] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fc_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[120] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fa_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[127] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f5_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[133] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_38_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[150] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_39_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[151] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_3a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[152] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_3b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[153] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_3c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[154] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_3d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[155] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a6_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[176] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a6_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[177] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a6_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a6_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a6_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[179] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds32_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[180] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a7_ds32_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a7_ds32_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a7_ds32_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[181] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds64_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[182] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a7_ds64_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a7_ds64_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a7_ds64_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[184] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a7_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[185] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a7_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a7_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a7_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_a7_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_a7_ds16_auxiliary, - /* 02 */ (const void *)&gRootTable_root_a7_ds32_auxiliary, - /* 03 */ (const void *)&gRootTable_root_a7_ds64_auxiliary, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_27_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[226] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_2f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[227] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_48_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[228] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_49_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[229] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[230] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[231] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[232] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[233] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[234] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_4f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[235] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fe_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[236] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fe_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[445] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_fe_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_fe_00_leaf, - /* 01 */ (const void *)&gRootTable_root_fe_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[239] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[426] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[431] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[746] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[755] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[822] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1374] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1375] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_f6_00_leaf, - /* 01 */ (const void *)&gRootTable_root_f6_01_leaf, - /* 02 */ (const void *)&gRootTable_root_f6_02_leaf, - /* 03 */ (const void *)&gRootTable_root_f6_03_leaf, - /* 04 */ (const void *)&gRootTable_root_f6_04_leaf, - /* 05 */ (const void *)&gRootTable_root_f6_05_leaf, - /* 06 */ (const void *)&gRootTable_root_f6_06_leaf, - /* 07 */ (const void *)&gRootTable_root_f6_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[240] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[427] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[432] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[747] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[756] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[823] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1376] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1377] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_f7_00_leaf, - /* 01 */ (const void *)&gRootTable_root_f7_01_leaf, - /* 02 */ (const void *)&gRootTable_root_f7_02_leaf, - /* 03 */ (const void *)&gRootTable_root_f7_03_leaf, - /* 04 */ (const void *)&gRootTable_root_f7_04_leaf, - /* 05 */ (const void *)&gRootTable_root_f7_05_leaf, - /* 06 */ (const void *)&gRootTable_root_f7_06_leaf, - /* 07 */ (const void *)&gRootTable_root_f7_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[258] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[264] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[295] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[324] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[366] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[368] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[369] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[413] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_06_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[414] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_06_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_06_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d9_reg_06_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d9_reg_06_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d9_reg_06_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d9_reg_06_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d9_reg_06_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d9_reg_06_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d9_reg_06_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[265] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[273] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[399] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_04_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[405] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_04_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_04_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d9_reg_04_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_d9_reg_04_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d9_reg_04_05_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[294] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[367] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[371] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[373] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[374] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[375] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[376] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_07_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[415] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_07_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d9_reg_07_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d9_reg_07_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d9_reg_07_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d9_reg_07_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d9_reg_07_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d9_reg_07_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d9_reg_07_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[338] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[341] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[344] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[345] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[346] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[347] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[348] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_05_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[349] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_05_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_05_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d9_reg_05_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d9_reg_05_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d9_reg_05_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d9_reg_05_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d9_reg_05_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d9_reg_05_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[358] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_d9_reg_02_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_02_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[387] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[406] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d9_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d9_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d9_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d9_reg_02_modrmrm, - /* 03 */ (const void *)&gRootTable_root_d9_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d9_reg_04_modrmrm, - /* 05 */ (const void *)&gRootTable_root_d9_reg_05_modrmrm, - /* 06 */ (const void *)&gRootTable_root_d9_reg_06_modrmrm, - /* 07 */ (const void *)&gRootTable_root_d9_reg_07_modrmrm, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[337] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[342] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[343] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[362] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[363] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[377] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d9_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[381] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d9_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d9_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gRootTable_root_d9_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d9_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d9_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d9_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d9_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d9_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_d9_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_d9_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_d9_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[266] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[282] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[288] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[296] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[301] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[350] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[389] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[394] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d8_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d8_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d8_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d8_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d8_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d8_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d8_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d8_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d8_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[267] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[283] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[289] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[297] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[302] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[351] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[390] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d8_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[395] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d8_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d8_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d8_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d8_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d8_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d8_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d8_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d8_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d8_reg_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_d8_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_d8_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_d8_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[268] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[284] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[290] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[298] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[303] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[352] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[391] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[396] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_dc_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_dc_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_dc_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_dc_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_dc_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_dc_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_dc_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_dc_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_dc_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[269] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[285] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[291] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[299] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[304] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[353] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[392] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dc_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[397] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_dc_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_dc_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_dc_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_dc_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_dc_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_dc_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_dc_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_dc_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_dc_reg_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_dc_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_dc_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_dc_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[270] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[292] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[293] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_de_reg_03_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_de_reg_03_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[300] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[305] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[354] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[393] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[398] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_de_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_de_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_de_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_de_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_de_reg_03_modrmrm, - /* 04 */ (const void *)&gRootTable_root_de_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_de_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_de_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_de_reg_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[310] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[312] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[314] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[316] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[318] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[323] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[334] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_de_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[336] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_de_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_de_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_de_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_de_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_de_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_de_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_de_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_de_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_de_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_de_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_de_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_de_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[271] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[272] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[320] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[321] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[326] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[328] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[329] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[332] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_df_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_df_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_df_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_df_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_df_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_df_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_df_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_df_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_df_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[287] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[308] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[365] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[380] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_04_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[388] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_df_reg_04_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_df_reg_04_00_leaf, - /* 01 */ (const void *)&gRootTable_root_df_reg_04_01_leaf, - /* 02 */ (const void *)&gRootTable_root_df_reg_04_02_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_07_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[370] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_df_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_df_reg_07_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[385] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[386] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[402] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_df_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[408] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_df_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_df_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_df_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_df_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_df_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_df_reg_04_modrmrm, - /* 05 */ (const void *)&gRootTable_root_df_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_df_reg_06_leaf, - /* 07 */ (const void *)&gRootTable_root_df_reg_07_modrmrm, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_df_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_df_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_df_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[274] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[275] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[276] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[281] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_reg_05_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[404] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_da_reg_05_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_da_reg_05_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_da_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_da_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_da_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_da_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_da_reg_03_leaf, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_da_reg_05_modrmrm, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[309] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[311] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[313] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[315] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[317] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[322] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[333] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_da_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[335] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_da_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_da_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_da_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_da_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_da_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_da_mem_04_leaf, - /* 05 */ (const void *)&gRootTable_root_da_mem_05_leaf, - /* 06 */ (const void *)&gRootTable_root_da_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_da_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_da_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_da_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_da_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[277] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[278] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[279] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[280] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[286] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[355] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[356] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[357] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[359] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_04_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[360] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_db_reg_04_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_db_reg_04_00_leaf, - /* 01 */ (const void *)&gRootTable_root_db_reg_04_01_leaf, - /* 02 */ (const void *)&gRootTable_root_db_reg_04_02_leaf, - /* 03 */ (const void *)&gRootTable_root_db_reg_04_03_leaf, - /* 04 */ (const void *)&gRootTable_root_db_reg_04_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[401] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_db_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_db_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_db_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_db_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_db_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_db_reg_04_modrmrm, - /* 05 */ (const void *)&gRootTable_root_db_reg_05_leaf, - /* 06 */ (const void *)&gRootTable_root_db_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[319] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[325] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[327] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[330] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[339] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_db_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[382] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_db_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_db_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_db_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_db_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_db_mem_03_leaf, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_db_mem_05_leaf, - /* 06 */ ND_NULL, - /* 07 */ (const void *)&gRootTable_root_db_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_db_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_db_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_db_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[307] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[379] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[384] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[400] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[403] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[407] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_dd_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_dd_reg_00_leaf, - /* 01 */ (const void *)&gRootTable_root_dd_reg_01_leaf, - /* 02 */ (const void *)&gRootTable_root_dd_reg_02_leaf, - /* 03 */ (const void *)&gRootTable_root_dd_reg_03_leaf, - /* 04 */ (const void *)&gRootTable_root_dd_reg_04_leaf, - /* 05 */ (const void *)&gRootTable_root_dd_reg_05_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[331] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[340] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[361] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[364] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[372] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[378] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_dd_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[383] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_dd_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_dd_mem_00_leaf, - /* 01 */ (const void *)&gRootTable_root_dd_mem_01_leaf, - /* 02 */ (const void *)&gRootTable_root_dd_mem_02_leaf, - /* 03 */ (const void *)&gRootTable_root_dd_mem_03_leaf, - /* 04 */ (const void *)&gRootTable_root_dd_mem_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gRootTable_root_dd_mem_06_leaf, - /* 07 */ (const void *)&gRootTable_root_dd_mem_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_dd_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_dd_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_dd_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[422] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_69_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[429] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[430] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[433] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e5_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[434] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ec_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[435] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ed_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[436] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_40_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[437] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_41_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[438] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_42_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[439] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_43_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[440] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_44_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[441] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_45_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[442] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_46_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[443] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_47_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[444] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6c_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[449] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6c_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[450] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6c_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6c_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6c_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[451] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6d_None_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[452] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6d_None_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6d_None_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6d_None_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[457] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6d_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[458] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6d_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6d_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6d_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_6d_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ (const void *)&gRootTable_root_6d_None_auxiliary, - /* 01 */ (const void *)&gRootTable_root_6d_ds16_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cd_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[459] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[460] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cc_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[461] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ce_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[462] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[470] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[471] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cf_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[472] -}; - -const ND_TABLE_DSIZE gRootTable_root_cf_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_cf_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_cf_ds32_leaf, - /* 03 */ (const void *)&gRootTable_root_cf_ds64_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_76_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[474] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_72_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[476] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e3_as16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[477] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e3_as32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[478] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e3_as64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[510] -}; - -const ND_TABLE_ASIZE gRootTable_root_e3_asize = -{ - ND_ILUT_ASIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_e3_as16_leaf, - /* 02 */ (const void *)&gRootTable_root_e3_as32_leaf, - /* 03 */ (const void *)&gRootTable_root_e3_as64_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[480] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[482] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[483] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_eb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[484] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ea_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[488] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_77_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[491] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_73_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[493] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[495] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[497] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_71_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[499] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[501] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_79_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[503] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_75_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[505] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_70_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[507] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_7a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[509] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_78_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[512] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_74_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[514] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[584] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c5_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[589] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_c5_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_c5_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8d_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[591] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_8d_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_8d_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[592] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c4_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[593] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_c4_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_c4_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ac_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[605] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ac_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[606] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ac_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ac_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ac_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[607] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds32_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[608] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ad_ds32_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ad_ds32_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ad_ds32_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[609] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds64_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[610] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ad_ds64_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ad_ds64_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ad_ds64_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[611] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ad_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[612] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ad_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ad_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ad_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_ad_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_ad_ds16_auxiliary, - /* 02 */ (const void *)&gRootTable_root_ad_ds32_auxiliary, - /* 03 */ (const void *)&gRootTable_root_ad_ds64_auxiliary, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[613] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[614] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[615] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_88_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[644] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_89_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[645] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[646] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[647] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8c_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[648] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8c_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[649] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_8c_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_8c_mem_leaf, - /* 01 */ (const void *)&gRootTable_root_8c_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8e_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[650] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8e_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[651] -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_8e_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_8e_mem_leaf, - /* 01 */ (const void *)&gRootTable_root_8e_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[652] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[653] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[654] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[655] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[656] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[657] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[658] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[659] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b4_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[660] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b5_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[661] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[662] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[663] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[664] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_b9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[665] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ba_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[666] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_bb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[667] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_bc_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[668] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_bd_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[669] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_be_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[670] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_bf_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[671] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c6_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[672] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c6_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c6_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[672] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2726] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_c6_reg_07_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c6_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c6_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ (const void *)&gRootTable_root_c6_reg_07_modrmrm, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_c6_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_c6_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_c6_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c7_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[673] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c7_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c7_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[673] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2729] -}; - -const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gRootTable_root_c7_reg_07_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c7_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c7_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ (const void *)&gRootTable_root_c7_reg_07_modrmrm, - } -}; - -const ND_TABLE_MODRM_MOD gRootTable_root_c7_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gRootTable_root_c7_mem_modrmreg, - /* 01 */ (const void *)&gRootTable_root_c7_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a4_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[722] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a4_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[723] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a4_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a4_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a4_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[726] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds32_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[727] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a5_ds32_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a5_ds32_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a5_ds32_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[730] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds64_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[731] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a5_ds64_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a5_ds64_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a5_ds64_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[734] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a5_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[735] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_a5_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_a5_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_a5_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_a5_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_a5_ds16_auxiliary, - /* 02 */ (const void *)&gRootTable_root_a5_ds32_auxiliary, - /* 03 */ (const void *)&gRootTable_root_a5_ds64_auxiliary, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_90_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[821] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[881] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2732] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_90_None_leaf, - /* 01 */ (const void *)&gRootTable_root_90_rexb_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_90_aF3_leaf, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_08_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[824] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_09_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[825] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[826] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[827] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[828] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[829] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[836] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_e7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[837] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ee_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[838] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ef_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[839] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6e_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[840] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6e_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[841] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6e_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6e_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6e_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[842] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6f_None_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[843] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6f_None_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6f_None_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6f_None_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[844] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6f_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[845] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_6f_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_6f_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_6f_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_6f_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ (const void *)&gRootTable_root_6f_None_auxiliary, - /* 01 */ (const void *)&gRootTable_root_6f_ds16_auxiliary, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1015] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_17_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1016] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1017] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_58_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1018] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_59_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1019] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1020] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1021] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1022] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1023] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1024] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_5f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1025] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_8f_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1026] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_8f_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_8f_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_61_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1027] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_61_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1028] -}; - -const ND_TABLE_DSIZE gRootTable_root_61_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_61_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_61_ds32_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1030] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9d_dds64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1031] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9d_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1032] -}; - -const ND_TABLE_DSIZE gRootTable_root_9d_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_9d_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_9d_ds32_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_9d_dds64_leaf, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1137] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_0e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1138] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1139] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1140] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_50_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1141] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_51_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1142] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_52_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1143] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_53_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1144] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_54_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1145] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_55_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1146] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_56_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1147] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_57_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1148] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_68_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1149] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_6a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1150] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_60_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1152] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_60_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1153] -}; - -const ND_TABLE_DSIZE gRootTable_root_60_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_60_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_60_ds32_leaf, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1154] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9c_dds64_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1155] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9c_ds16_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1156] -}; - -const ND_TABLE_DSIZE gRootTable_root_9c_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_9c_ds16_leaf, - /* 02 */ (const void *)&gRootTable_root_9c_ds32_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gRootTable_root_9c_dds64_leaf, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1160] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1168] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1198] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1204] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1223] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1230] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1287] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c0_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1296] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c0_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c0_00_leaf, - /* 01 */ (const void *)&gRootTable_root_c0_01_leaf, - /* 02 */ (const void *)&gRootTable_root_c0_02_leaf, - /* 03 */ (const void *)&gRootTable_root_c0_03_leaf, - /* 04 */ (const void *)&gRootTable_root_c0_04_leaf, - /* 05 */ (const void *)&gRootTable_root_c0_05_leaf, - /* 06 */ (const void *)&gRootTable_root_c0_06_leaf, - /* 07 */ (const void *)&gRootTable_root_c0_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1161] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1169] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1199] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1205] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1224] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1231] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1288] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c1_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1297] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_c1_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_c1_00_leaf, - /* 01 */ (const void *)&gRootTable_root_c1_01_leaf, - /* 02 */ (const void *)&gRootTable_root_c1_02_leaf, - /* 03 */ (const void *)&gRootTable_root_c1_03_leaf, - /* 04 */ (const void *)&gRootTable_root_c1_04_leaf, - /* 05 */ (const void *)&gRootTable_root_c1_05_leaf, - /* 06 */ (const void *)&gRootTable_root_c1_06_leaf, - /* 07 */ (const void *)&gRootTable_root_c1_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1162] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1170] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1200] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1206] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1225] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1232] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1289] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d0_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1298] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d0_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d0_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d0_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d0_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d0_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d0_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d0_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d0_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d0_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1163] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1171] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1201] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1207] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1226] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1233] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1290] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d1_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1299] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d1_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d1_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d1_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d1_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d1_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d1_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d1_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d1_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d1_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1164] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1172] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1202] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1208] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1227] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1234] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1291] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d2_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1300] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d2_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d2_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d2_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d2_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d2_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d2_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d2_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d2_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d2_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1165] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1173] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1203] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1209] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1228] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1235] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1292] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d3_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1301] -}; - -const ND_TABLE_MODRM_REG gRootTable_root_d3_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gRootTable_root_d3_00_leaf, - /* 01 */ (const void *)&gRootTable_root_d3_01_leaf, - /* 02 */ (const void *)&gRootTable_root_d3_02_leaf, - /* 03 */ (const void *)&gRootTable_root_d3_03_leaf, - /* 04 */ (const void *)&gRootTable_root_d3_04_leaf, - /* 05 */ (const void *)&gRootTable_root_d3_05_leaf, - /* 06 */ (const void *)&gRootTable_root_d3_06_leaf, - /* 07 */ (const void *)&gRootTable_root_d3_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ca_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1191] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_cb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1192] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1193] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_c3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1194] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1222] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1229] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_18_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1238] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_19_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1239] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1240] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1241] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1242] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_1d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1243] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ae_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1248] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ae_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1249] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ae_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ae_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ae_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1250] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds32_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1251] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_af_ds32_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_af_ds32_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_af_ds32_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1252] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds64_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1253] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_af_ds64_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_af_ds64_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_af_ds64_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1254] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_af_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1255] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_af_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_af_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_af_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_af_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_af_ds16_auxiliary, - /* 02 */ (const void *)&gRootTable_root_af_ds32_auxiliary, - /* 03 */ (const void *)&gRootTable_root_af_ds64_auxiliary, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_f9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1321] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fd_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1322] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_fb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1324] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_aa_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1326] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_aa_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1327] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_aa_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_aa_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_aa_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1328] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds32_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1329] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ab_ds32_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ab_ds32_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ab_ds32_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1330] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds64_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1331] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ab_ds64_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ab_ds64_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ab_ds64_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_None_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1332] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_ab_ds16_rep_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1333] -}; - -const ND_TABLE_AUXILIARY gRootTable_root_ab_ds16_auxiliary = -{ - ND_ILUT_AUXILIARY, - { - /* 00 */ (const void *)&gRootTable_root_ab_ds16_None_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ (const void *)&gRootTable_root_ab_ds16_rep_leaf, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_DSIZE gRootTable_root_ab_dsize = -{ - ND_ILUT_DSIZE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gRootTable_root_ab_ds16_auxiliary, - /* 02 */ (const void *)&gRootTable_root_ab_ds32_auxiliary, - /* 03 */ (const void *)&gRootTable_root_ab_ds64_auxiliary, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_28_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1338] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_29_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1339] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_2a_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1340] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_2b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1341] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_2c_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1342] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1343] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1370] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1371] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1372] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1373] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2712] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2730] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2731] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2733] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2734] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2735] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2736] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2737] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2738] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2739] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2747] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2748] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2749] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2750] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2751] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2752] -}; - -const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2753] -}; - -const ND_TABLE_OPCODE gRootTable_root_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gRootTable_root_00_leaf, - /* 01 */ (const void *)&gRootTable_root_01_leaf, - /* 02 */ (const void *)&gRootTable_root_02_leaf, - /* 03 */ (const void *)&gRootTable_root_03_leaf, - /* 04 */ (const void *)&gRootTable_root_04_leaf, - /* 05 */ (const void *)&gRootTable_root_05_leaf, - /* 06 */ (const void *)&gRootTable_root_06_leaf, - /* 07 */ (const void *)&gRootTable_root_07_leaf, - /* 08 */ (const void *)&gRootTable_root_08_leaf, - /* 09 */ (const void *)&gRootTable_root_09_leaf, - /* 0a */ (const void *)&gRootTable_root_0a_leaf, - /* 0b */ (const void *)&gRootTable_root_0b_leaf, - /* 0c */ (const void *)&gRootTable_root_0c_leaf, - /* 0d */ (const void *)&gRootTable_root_0d_leaf, - /* 0e */ (const void *)&gRootTable_root_0e_leaf, - /* 0f */ (const void *)&gRootTable_root_0f_opcode, - /* 10 */ (const void *)&gRootTable_root_10_leaf, - /* 11 */ (const void *)&gRootTable_root_11_leaf, - /* 12 */ (const void *)&gRootTable_root_12_leaf, - /* 13 */ (const void *)&gRootTable_root_13_leaf, - /* 14 */ (const void *)&gRootTable_root_14_leaf, - /* 15 */ (const void *)&gRootTable_root_15_leaf, - /* 16 */ (const void *)&gRootTable_root_16_leaf, - /* 17 */ (const void *)&gRootTable_root_17_leaf, - /* 18 */ (const void *)&gRootTable_root_18_leaf, - /* 19 */ (const void *)&gRootTable_root_19_leaf, - /* 1a */ (const void *)&gRootTable_root_1a_leaf, - /* 1b */ (const void *)&gRootTable_root_1b_leaf, - /* 1c */ (const void *)&gRootTable_root_1c_leaf, - /* 1d */ (const void *)&gRootTable_root_1d_leaf, - /* 1e */ (const void *)&gRootTable_root_1e_leaf, - /* 1f */ (const void *)&gRootTable_root_1f_leaf, - /* 20 */ (const void *)&gRootTable_root_20_leaf, - /* 21 */ (const void *)&gRootTable_root_21_leaf, - /* 22 */ (const void *)&gRootTable_root_22_leaf, - /* 23 */ (const void *)&gRootTable_root_23_leaf, - /* 24 */ (const void *)&gRootTable_root_24_leaf, - /* 25 */ (const void *)&gRootTable_root_25_leaf, - /* 26 */ ND_NULL, - /* 27 */ (const void *)&gRootTable_root_27_leaf, - /* 28 */ (const void *)&gRootTable_root_28_leaf, - /* 29 */ (const void *)&gRootTable_root_29_leaf, - /* 2a */ (const void *)&gRootTable_root_2a_leaf, - /* 2b */ (const void *)&gRootTable_root_2b_leaf, - /* 2c */ (const void *)&gRootTable_root_2c_leaf, - /* 2d */ (const void *)&gRootTable_root_2d_leaf, - /* 2e */ ND_NULL, - /* 2f */ (const void *)&gRootTable_root_2f_leaf, - /* 30 */ (const void *)&gRootTable_root_30_leaf, - /* 31 */ (const void *)&gRootTable_root_31_leaf, - /* 32 */ (const void *)&gRootTable_root_32_leaf, - /* 33 */ (const void *)&gRootTable_root_33_leaf, - /* 34 */ (const void *)&gRootTable_root_34_leaf, - /* 35 */ (const void *)&gRootTable_root_35_leaf, - /* 36 */ ND_NULL, - /* 37 */ (const void *)&gRootTable_root_37_leaf, - /* 38 */ (const void *)&gRootTable_root_38_leaf, - /* 39 */ (const void *)&gRootTable_root_39_leaf, - /* 3a */ (const void *)&gRootTable_root_3a_leaf, - /* 3b */ (const void *)&gRootTable_root_3b_leaf, - /* 3c */ (const void *)&gRootTable_root_3c_leaf, - /* 3d */ (const void *)&gRootTable_root_3d_leaf, - /* 3e */ ND_NULL, - /* 3f */ (const void *)&gRootTable_root_3f_leaf, - /* 40 */ (const void *)&gRootTable_root_40_leaf, - /* 41 */ (const void *)&gRootTable_root_41_leaf, - /* 42 */ (const void *)&gRootTable_root_42_leaf, - /* 43 */ (const void *)&gRootTable_root_43_leaf, - /* 44 */ (const void *)&gRootTable_root_44_leaf, - /* 45 */ (const void *)&gRootTable_root_45_leaf, - /* 46 */ (const void *)&gRootTable_root_46_leaf, - /* 47 */ (const void *)&gRootTable_root_47_leaf, - /* 48 */ (const void *)&gRootTable_root_48_leaf, - /* 49 */ (const void *)&gRootTable_root_49_leaf, - /* 4a */ (const void *)&gRootTable_root_4a_leaf, - /* 4b */ (const void *)&gRootTable_root_4b_leaf, - /* 4c */ (const void *)&gRootTable_root_4c_leaf, - /* 4d */ (const void *)&gRootTable_root_4d_leaf, - /* 4e */ (const void *)&gRootTable_root_4e_leaf, - /* 4f */ (const void *)&gRootTable_root_4f_leaf, - /* 50 */ (const void *)&gRootTable_root_50_leaf, - /* 51 */ (const void *)&gRootTable_root_51_leaf, - /* 52 */ (const void *)&gRootTable_root_52_leaf, - /* 53 */ (const void *)&gRootTable_root_53_leaf, - /* 54 */ (const void *)&gRootTable_root_54_leaf, - /* 55 */ (const void *)&gRootTable_root_55_leaf, - /* 56 */ (const void *)&gRootTable_root_56_leaf, - /* 57 */ (const void *)&gRootTable_root_57_leaf, - /* 58 */ (const void *)&gRootTable_root_58_leaf, - /* 59 */ (const void *)&gRootTable_root_59_leaf, - /* 5a */ (const void *)&gRootTable_root_5a_leaf, - /* 5b */ (const void *)&gRootTable_root_5b_leaf, - /* 5c */ (const void *)&gRootTable_root_5c_leaf, - /* 5d */ (const void *)&gRootTable_root_5d_leaf, - /* 5e */ (const void *)&gRootTable_root_5e_leaf, - /* 5f */ (const void *)&gRootTable_root_5f_leaf, - /* 60 */ (const void *)&gRootTable_root_60_dsize, - /* 61 */ (const void *)&gRootTable_root_61_dsize, - /* 62 */ (const void *)&gRootTable_root_62_modrmmod, - /* 63 */ (const void *)&gRootTable_root_63_auxiliary, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ (const void *)&gRootTable_root_68_leaf, - /* 69 */ (const void *)&gRootTable_root_69_leaf, - /* 6a */ (const void *)&gRootTable_root_6a_leaf, - /* 6b */ (const void *)&gRootTable_root_6b_leaf, - /* 6c */ (const void *)&gRootTable_root_6c_auxiliary, - /* 6d */ (const void *)&gRootTable_root_6d_dsize, - /* 6e */ (const void *)&gRootTable_root_6e_auxiliary, - /* 6f */ (const void *)&gRootTable_root_6f_dsize, - /* 70 */ (const void *)&gRootTable_root_70_leaf, - /* 71 */ (const void *)&gRootTable_root_71_leaf, - /* 72 */ (const void *)&gRootTable_root_72_leaf, - /* 73 */ (const void *)&gRootTable_root_73_leaf, - /* 74 */ (const void *)&gRootTable_root_74_leaf, - /* 75 */ (const void *)&gRootTable_root_75_leaf, - /* 76 */ (const void *)&gRootTable_root_76_leaf, - /* 77 */ (const void *)&gRootTable_root_77_leaf, - /* 78 */ (const void *)&gRootTable_root_78_leaf, - /* 79 */ (const void *)&gRootTable_root_79_leaf, - /* 7a */ (const void *)&gRootTable_root_7a_leaf, - /* 7b */ (const void *)&gRootTable_root_7b_leaf, - /* 7c */ (const void *)&gRootTable_root_7c_leaf, - /* 7d */ (const void *)&gRootTable_root_7d_leaf, - /* 7e */ (const void *)&gRootTable_root_7e_leaf, - /* 7f */ (const void *)&gRootTable_root_7f_leaf, - /* 80 */ (const void *)&gRootTable_root_80_modrmreg, - /* 81 */ (const void *)&gRootTable_root_81_modrmreg, - /* 82 */ (const void *)&gRootTable_root_82_modrmreg, - /* 83 */ (const void *)&gRootTable_root_83_modrmreg, - /* 84 */ (const void *)&gRootTable_root_84_leaf, - /* 85 */ (const void *)&gRootTable_root_85_leaf, - /* 86 */ (const void *)&gRootTable_root_86_leaf, - /* 87 */ (const void *)&gRootTable_root_87_leaf, - /* 88 */ (const void *)&gRootTable_root_88_leaf, - /* 89 */ (const void *)&gRootTable_root_89_leaf, - /* 8a */ (const void *)&gRootTable_root_8a_leaf, - /* 8b */ (const void *)&gRootTable_root_8b_leaf, - /* 8c */ (const void *)&gRootTable_root_8c_modrmmod, - /* 8d */ (const void *)&gRootTable_root_8d_modrmmod, - /* 8e */ (const void *)&gRootTable_root_8e_modrmmod, - /* 8f */ (const void *)&gRootTable_root_8f_modrmreg, - /* 90 */ (const void *)&gRootTable_root_90_auxiliary, - /* 91 */ (const void *)&gRootTable_root_91_leaf, - /* 92 */ (const void *)&gRootTable_root_92_leaf, - /* 93 */ (const void *)&gRootTable_root_93_leaf, - /* 94 */ (const void *)&gRootTable_root_94_leaf, - /* 95 */ (const void *)&gRootTable_root_95_leaf, - /* 96 */ (const void *)&gRootTable_root_96_leaf, - /* 97 */ (const void *)&gRootTable_root_97_leaf, - /* 98 */ (const void *)&gRootTable_root_98_dsize, - /* 99 */ (const void *)&gRootTable_root_99_dsize, - /* 9a */ (const void *)&gRootTable_root_9a_leaf, - /* 9b */ (const void *)&gRootTable_root_9b_leaf, - /* 9c */ (const void *)&gRootTable_root_9c_dsize, - /* 9d */ (const void *)&gRootTable_root_9d_dsize, - /* 9e */ (const void *)&gRootTable_root_9e_leaf, - /* 9f */ (const void *)&gRootTable_root_9f_leaf, - /* a0 */ (const void *)&gRootTable_root_a0_leaf, - /* a1 */ (const void *)&gRootTable_root_a1_leaf, - /* a2 */ (const void *)&gRootTable_root_a2_leaf, - /* a3 */ (const void *)&gRootTable_root_a3_leaf, - /* a4 */ (const void *)&gRootTable_root_a4_auxiliary, - /* a5 */ (const void *)&gRootTable_root_a5_dsize, - /* a6 */ (const void *)&gRootTable_root_a6_auxiliary, - /* a7 */ (const void *)&gRootTable_root_a7_dsize, - /* a8 */ (const void *)&gRootTable_root_a8_leaf, - /* a9 */ (const void *)&gRootTable_root_a9_leaf, - /* aa */ (const void *)&gRootTable_root_aa_auxiliary, - /* ab */ (const void *)&gRootTable_root_ab_dsize, - /* ac */ (const void *)&gRootTable_root_ac_auxiliary, - /* ad */ (const void *)&gRootTable_root_ad_dsize, - /* ae */ (const void *)&gRootTable_root_ae_auxiliary, - /* af */ (const void *)&gRootTable_root_af_dsize, - /* b0 */ (const void *)&gRootTable_root_b0_leaf, - /* b1 */ (const void *)&gRootTable_root_b1_leaf, - /* b2 */ (const void *)&gRootTable_root_b2_leaf, - /* b3 */ (const void *)&gRootTable_root_b3_leaf, - /* b4 */ (const void *)&gRootTable_root_b4_leaf, - /* b5 */ (const void *)&gRootTable_root_b5_leaf, - /* b6 */ (const void *)&gRootTable_root_b6_leaf, - /* b7 */ (const void *)&gRootTable_root_b7_leaf, - /* b8 */ (const void *)&gRootTable_root_b8_leaf, - /* b9 */ (const void *)&gRootTable_root_b9_leaf, - /* ba */ (const void *)&gRootTable_root_ba_leaf, - /* bb */ (const void *)&gRootTable_root_bb_leaf, - /* bc */ (const void *)&gRootTable_root_bc_leaf, - /* bd */ (const void *)&gRootTable_root_bd_leaf, - /* be */ (const void *)&gRootTable_root_be_leaf, - /* bf */ (const void *)&gRootTable_root_bf_leaf, - /* c0 */ (const void *)&gRootTable_root_c0_modrmreg, - /* c1 */ (const void *)&gRootTable_root_c1_modrmreg, - /* c2 */ (const void *)&gRootTable_root_c2_leaf, - /* c3 */ (const void *)&gRootTable_root_c3_leaf, - /* c4 */ (const void *)&gRootTable_root_c4_modrmmod, - /* c5 */ (const void *)&gRootTable_root_c5_modrmmod, - /* c6 */ (const void *)&gRootTable_root_c6_modrmmod, - /* c7 */ (const void *)&gRootTable_root_c7_modrmmod, - /* c8 */ (const void *)&gRootTable_root_c8_leaf, - /* c9 */ (const void *)&gRootTable_root_c9_leaf, - /* ca */ (const void *)&gRootTable_root_ca_leaf, - /* cb */ (const void *)&gRootTable_root_cb_leaf, - /* cc */ (const void *)&gRootTable_root_cc_leaf, - /* cd */ (const void *)&gRootTable_root_cd_leaf, - /* ce */ (const void *)&gRootTable_root_ce_leaf, - /* cf */ (const void *)&gRootTable_root_cf_dsize, - /* d0 */ (const void *)&gRootTable_root_d0_modrmreg, - /* d1 */ (const void *)&gRootTable_root_d1_modrmreg, - /* d2 */ (const void *)&gRootTable_root_d2_modrmreg, - /* d3 */ (const void *)&gRootTable_root_d3_modrmreg, - /* d4 */ (const void *)&gRootTable_root_d4_leaf, - /* d5 */ (const void *)&gRootTable_root_d5_leaf, - /* d6 */ (const void *)&gRootTable_root_d6_leaf, - /* d7 */ (const void *)&gRootTable_root_d7_leaf, - /* d8 */ (const void *)&gRootTable_root_d8_modrmmod, - /* d9 */ (const void *)&gRootTable_root_d9_modrmmod, - /* da */ (const void *)&gRootTable_root_da_modrmmod, - /* db */ (const void *)&gRootTable_root_db_modrmmod, - /* dc */ (const void *)&gRootTable_root_dc_modrmmod, - /* dd */ (const void *)&gRootTable_root_dd_modrmmod, - /* de */ (const void *)&gRootTable_root_de_modrmmod, - /* df */ (const void *)&gRootTable_root_df_modrmmod, - /* e0 */ (const void *)&gRootTable_root_e0_leaf, - /* e1 */ (const void *)&gRootTable_root_e1_leaf, - /* e2 */ (const void *)&gRootTable_root_e2_leaf, - /* e3 */ (const void *)&gRootTable_root_e3_asize, - /* e4 */ (const void *)&gRootTable_root_e4_leaf, - /* e5 */ (const void *)&gRootTable_root_e5_leaf, - /* e6 */ (const void *)&gRootTable_root_e6_leaf, - /* e7 */ (const void *)&gRootTable_root_e7_leaf, - /* e8 */ (const void *)&gRootTable_root_e8_leaf, - /* e9 */ (const void *)&gRootTable_root_e9_leaf, - /* ea */ (const void *)&gRootTable_root_ea_leaf, - /* eb */ (const void *)&gRootTable_root_eb_leaf, - /* ec */ (const void *)&gRootTable_root_ec_leaf, - /* ed */ (const void *)&gRootTable_root_ed_leaf, - /* ee */ (const void *)&gRootTable_root_ee_leaf, - /* ef */ (const void *)&gRootTable_root_ef_leaf, - /* f0 */ ND_NULL, - /* f1 */ (const void *)&gRootTable_root_f1_leaf, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ (const void *)&gRootTable_root_f4_leaf, - /* f5 */ (const void *)&gRootTable_root_f5_leaf, - /* f6 */ (const void *)&gRootTable_root_f6_modrmreg, - /* f7 */ (const void *)&gRootTable_root_f7_modrmreg, - /* f8 */ (const void *)&gRootTable_root_f8_leaf, - /* f9 */ (const void *)&gRootTable_root_f9_leaf, - /* fa */ (const void *)&gRootTable_root_fa_leaf, - /* fb */ (const void *)&gRootTable_root_fb_leaf, - /* fc */ (const void *)&gRootTable_root_fc_leaf, - /* fd */ (const void *)&gRootTable_root_fd_leaf, - /* fe */ (const void *)&gRootTable_root_fe_modrmreg, - /* ff */ (const void *)&gRootTable_root_ff_modrmmod, - } -}; - -const PND_TABLE gRootTable = (const PND_TABLE)&gRootTable_root_opcode; - - -#endif - diff --git a/bddisasm/include/table_vex.h b/bddisasm/include/table_vex.h deleted file mode 100644 index 900d9e5..0000000 --- a/bddisasm/include/table_vex.h +++ /dev/null @@ -1,13047 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ - -// -// This file was auto-generated by generate_tables.py. DO NOT MODIFY! -// - -#ifndef TABLE_VEX_H -#define TABLE_VEX_H - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f2_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[59] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f2_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f2_00_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_f2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_f2_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[67] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f7_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f7_00_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1236] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f7_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f7_02_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1295] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f7_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f7_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f7_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1304] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f7_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f7_03_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_f7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_f7_00_l, - /* 01 */ (const void *)&gVexTable_root_02_f7_01_l, - /* 02 */ (const void *)&gVexTable_root_02_f7_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f7_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[79] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_03_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[81] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_02_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f3_00_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[82] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f3_00_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gVexTable_root_02_f3_00_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_f3_00_01_l, - /* 02 */ (const void *)&gVexTable_root_02_f3_00_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f3_00_03_l, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_f3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_f3_00_modrmreg, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[110] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f5_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f5_00_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[910] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f5_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f5_03_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f5_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[911] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f5_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f5_02_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_f5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_f5_00_l, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_02_f5_02_l, - /* 03 */ (const void *)&gVexTable_root_02_f5_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e6_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[160] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e6_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e6_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e6_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e6_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e6_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e2_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[161] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e2_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e2_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e2_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e2_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e2_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ee_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[162] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_ee_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_ee_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_ee_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_ee_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ee_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ee_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ec_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[163] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_ec_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_ec_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_ec_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_ec_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ec_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ec_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e7_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[164] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e7_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e7_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e7_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e3_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[165] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e3_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e3_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e3_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e3_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e3_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ef_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[166] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_ef_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_ef_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_ef_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_ef_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ef_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ef_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ed_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[167] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_ed_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_ed_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_ed_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_ed_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ed_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ed_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e1_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[168] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e1_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e1_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e1_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e1_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e1_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_eb_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[169] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_eb_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_eb_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_eb_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_eb_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_eb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_eb_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e9_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[170] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e9_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e9_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e9_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e9_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e9_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e5_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[171] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e5_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e5_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e5_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e5_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e5_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e0_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[172] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e0_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e0_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e0_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e0_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e0_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ea_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[175] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_ea_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_ea_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_ea_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_ea_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ea_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ea_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e8_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[186] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e8_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e8_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e8_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e8_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e8_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_e4_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[191] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_e4_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_e4_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_e4_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_e4_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_e4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_e4_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_mem_00_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[590] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_49_00_mem_00_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_49_00_mem_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_49_00_reg_00_00_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1381] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_49_00_reg_00_00_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_49_00_reg_00_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gVexTable_root_02_49_00_reg_00_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gVexTable_root_02_49_00_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_reg_00_modrmrm, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_49_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_mem_modrmreg, - /* 01 */ (const void *)&gVexTable_root_02_49_00_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_49_01_mem_00_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1336] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_49_01_mem_00_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_49_01_mem_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_REG gVexTable_root_02_49_01_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_49_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_49_01_mem_modrmreg, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_49_03_reg_00_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1383] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_49_03_reg_00_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_49_03_reg_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_RM gVexTable_root_02_49_03_reg_modrmrm = -{ - ND_ILUT_MODRM_RM, - { - /* 00 */ (const void *)&gVexTable_root_02_49_03_reg_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_49_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_49_03_reg_modrmrm, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_49_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_49_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_02_49_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_02_49_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_f6_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[752] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_f6_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_f6_03_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_f6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_02_f6_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_6c_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1361] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_6c_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_6c_01_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_6c_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_6c_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_6c_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_6c_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_6c_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1362] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_6c_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_6c_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_6c_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_6c_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_6c_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_6c_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_6c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_6c_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_02_6c_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_02_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1364] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5c_02_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5c_02_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5c_02_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5c_02_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5c_03_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1369] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5c_03_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5c_03_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5c_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5c_03_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5c_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5c_03_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_5c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_02_5c_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_02_5c_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_03_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1365] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5e_03_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5e_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_03_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5e_03_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_02_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1366] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5e_02_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5e_02_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_02_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5e_02_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1367] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5e_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5e_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5e_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5e_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1368] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5e_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5e_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5e_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5e_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_5e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_5e_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_02_5e_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_02_5e_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_02_5e_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_03_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1379] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_4b_03_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_4b_03_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_03_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_01_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1380] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_4b_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_4b_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_4b_02_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1382] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_4b_02_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_4b_02_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_4b_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_4b_02_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_4b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_4b_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_02_4b_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_02_4b_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_de_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1417] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_de_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_de_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_df_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1419] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_df_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_df_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_dc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1421] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_dc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_dc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_dd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1423] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_dd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_dd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_db_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1424] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_db_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_db_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_db_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_db_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1436] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b1_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b1_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b1_02_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b1_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1437] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b1_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b1_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b1_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b1_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b1_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_02_b1_02_modrmmod, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_1a_01_mem_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1444] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_1a_01_mem_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_1a_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_1a_01_mem_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_1a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_1a_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_1a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_1a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_5a_01_mem_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1450] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_5a_01_mem_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_5a_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5a_01_mem_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_5a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_5a_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_5a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_5a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_19_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1457] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_19_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_19_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_19_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_19_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_18_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1459] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_18_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_18_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_18_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_18_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_02_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1484] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b0_02_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_02_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_02_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1485] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b0_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_03_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1486] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b0_03_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_03_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_03_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b0_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1487] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b0_00_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_00_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_b0_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_00_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_b0_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_02_b0_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_02_b0_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_02_b0_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_72_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1489] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_72_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_72_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_72_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_02_72_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1502] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_13_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_13_01_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_13_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1503] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_13_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_13_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_13_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_13_01_00_w, - /* 01 */ (const void *)&gVexTable_root_02_13_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_13_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_13_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1626] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_98_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1629] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_98_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_98_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_98_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_98_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_98_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1631] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_99_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1634] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_99_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_99_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_99_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_99_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_99_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1636] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1639] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_a8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_a8_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_a8_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_a8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_a8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1641] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1644] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_a9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_a9_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_a9_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_a9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_a9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1646] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b8_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1649] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b8_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b8_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_b8_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b8_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1651] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b9_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1654] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b9_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b9_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_b9_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b9_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1666] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_96_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1669] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_96_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_96_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_96_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_96_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_96_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1671] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1674] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_a6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_a6_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_a6_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_a6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_a6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1676] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1679] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b6_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b6_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_b6_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b6_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1685] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1688] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9a_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9a_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1690] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1693] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9b_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1695] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_aa_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1698] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_aa_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_aa_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_aa_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_aa_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_aa_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1700] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ab_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1703] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_ab_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_ab_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_ab_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ab_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ab_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1705] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ba_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1708] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_ba_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_ba_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_ba_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ba_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ba_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1710] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bb_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1713] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_bb_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_bb_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_bb_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_bb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_bb_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1715] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_97_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1718] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_97_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_97_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_97_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_97_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_97_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1720] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_a7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1723] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_a7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_a7_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_a7_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_a7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_a7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1725] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b7_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1728] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b7_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_b7_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_b7_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b7_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1744] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1747] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9c_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1749] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1752] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9d_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1754] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ac_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1757] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_ac_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_ac_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_ac_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ac_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ac_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1759] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ad_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1762] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_ad_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_ad_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_ad_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ad_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ad_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1764] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bc_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1767] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_bc_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_bc_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_bc_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_bc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_bc_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1769] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bd_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1772] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_bd_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_bd_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_bd_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_bd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_bd_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1782] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1785] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9e_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1787] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_9f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1790] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_9f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_9f_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_9f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_9f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_9f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1792] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_ae_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1795] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_ae_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_ae_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_ae_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_ae_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_ae_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1797] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_af_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1800] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_af_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_af_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_af_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_af_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_af_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1802] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_be_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1805] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_be_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_be_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_be_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_be_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_be_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1807] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_bf_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1810] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_bf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_bf_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_bf_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_bf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_bf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1830] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_92_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1832] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_92_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_92_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_92_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_92_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_92_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_92_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_92_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1842] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_93_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1844] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_93_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_93_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_93_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_93_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_93_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_93_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_93_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_cf_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1862] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_cf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_cf_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_cf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2d_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1884] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_2d_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_2d_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_2d_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2d_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2f_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1885] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_2f_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_2f_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_2f_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2f_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2c_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1886] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_2c_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_2c_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_2c_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2c_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2e_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1887] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_2e_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_2e_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_2e_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2e_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2a_01_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1975] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_2a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_2a_01_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_1c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2053] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_1c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_1c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_1e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2055] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_1e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_1e_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_1d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2058] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_1d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_1d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_2b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2064] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_2b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_2b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_78_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2104] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_78_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_78_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_78_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_78_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_58_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2107] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_58_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_58_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_58_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_58_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_59_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2112] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_59_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_59_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_59_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_59_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_79_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2115] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_79_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_79_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_79_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_79_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_29_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2127] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_29_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_29_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_37_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2137] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_37_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_37_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_50_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2162] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_50_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_50_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_50_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2164] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_50_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_50_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_50_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2167] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_50_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_50_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_50_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2170] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_50_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_50_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_50_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_50_00_w, - /* 01 */ (const void *)&gVexTable_root_02_50_01_w, - /* 02 */ (const void *)&gVexTable_root_02_50_02_w, - /* 03 */ (const void *)&gVexTable_root_02_50_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_51_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2163] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_51_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_51_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_51_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2165] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_51_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_51_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_51_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2169] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_51_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_51_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_51_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2171] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_51_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_51_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_51_00_w, - /* 01 */ (const void *)&gVexTable_root_02_51_01_w, - /* 02 */ (const void *)&gVexTable_root_02_51_02_w, - /* 03 */ (const void *)&gVexTable_root_02_51_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_52_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2173] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_52_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_52_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_52_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_52_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_53_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2175] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_53_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_53_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_53_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_53_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2176] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d2_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d2_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2178] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d2_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d2_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d2_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2180] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d2_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d2_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_d2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_d2_00_w, - /* 01 */ (const void *)&gVexTable_root_02_d2_01_w, - /* 02 */ (const void *)&gVexTable_root_02_d2_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2177] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d3_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d3_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2179] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d3_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d3_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_d3_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2181] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_d3_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_d3_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_d3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_d3_00_w, - /* 01 */ (const void *)&gVexTable_root_02_d3_01_w, - /* 02 */ (const void *)&gVexTable_root_02_d3_02_w, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_36_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2186] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_36_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_36_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_36_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_36_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_36_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_36_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2199] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_0d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_0d_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2203] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_0c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_0c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_16_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2211] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_16_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_16_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_16_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_16_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_16_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2245] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_90_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2247] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_90_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_90_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_90_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_90_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_90_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_90_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_90_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2249] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_91_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2251] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_91_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_91_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_91_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_91_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_91_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_91_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_91_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2255] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_02_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_02_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2257] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_03_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_03_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2264] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_01_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_41_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2267] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_41_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_41_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_41_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_41_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_06_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2269] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_06_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_06_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_07_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2271] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_07_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_07_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_05_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2272] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_05_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_05_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b5_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2301] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b5_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b5_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b5_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_b4_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2303] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_b4_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b4_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_b4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_b4_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_04_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2305] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_04_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_04_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2308] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_8c_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2310] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_8c_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_8c_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_8c_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_8c_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_8c_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_8c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_8c_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2309] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_8e_01_mem_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2311] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_8e_01_mem_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_8e_01_mem_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_8e_01_mem_01_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_8e_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_02_8e_01_mem_w, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_8e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_8e_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2313] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2315] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2322] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3f_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2325] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3e_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_38_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2327] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_38_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_38_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_39_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2329] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_39_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_39_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2336] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_3a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2339] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_3a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_3a_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2360] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_21_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2361] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_21_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_21_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_21_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_21_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_21_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2363] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_22_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2364] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_22_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_22_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_22_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_22_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_22_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2366] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_20_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2367] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_20_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_20_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_20_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_20_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_20_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2369] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_25_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2370] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_25_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_25_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_25_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_25_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_25_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2372] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_23_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2373] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_23_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_23_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_23_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_23_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_23_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2375] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_24_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2376] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_24_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_24_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_24_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_24_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_24_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2386] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_31_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2387] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_31_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_31_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_31_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_31_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_31_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2389] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_32_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2390] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_32_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_32_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_32_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_32_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_32_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2392] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_30_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2393] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_30_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_30_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_30_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_30_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_30_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2395] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_35_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2396] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_35_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_35_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_35_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_35_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_35_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2398] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_33_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2399] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_33_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_33_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_33_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_33_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_33_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2401] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_34_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2402] -}; - -const ND_TABLE_VEX_L gVexTable_root_02_34_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_34_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_34_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_34_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_34_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_28_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2404] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_28_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_28_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2406] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_40_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2412] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_40_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_40_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2483] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_00_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_00_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_08_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2491] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_08_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_08_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2492] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0a_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_09_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2493] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_09_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_09_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2505] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_47_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2507] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_47_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_47_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_47_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_47_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_47_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_46_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2520] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_46_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_46_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_46_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_46_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2538] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_45_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2540] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_45_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_45_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_02_45_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_45_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_45_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_17_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2564] -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_17_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_17_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_cc_03_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2654] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_cc_03_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_cc_03_reg_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_cc_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cc_03_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_cc_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cc_03_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_cc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_02_cc_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_cd_03_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2655] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_cd_03_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_cd_03_reg_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_cd_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cd_03_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_cd_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cd_03_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_cd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_02_cd_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_cb_03_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2656] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_cb_03_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_cb_03_reg_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_cb_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cb_03_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_02_cb_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_cb_03_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_cb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_02_cb_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_da_00_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2665] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_da_00_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_da_00_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_da_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_da_00_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_da_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2666] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_da_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_da_01_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_02_da_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_02_da_01_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_da_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2668] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_da_02_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_da_02_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_da_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2669] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_da_03_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_da_03_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_da_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_02_da_00_l, - /* 01 */ (const void *)&gVexTable_root_02_da_01_l, - /* 02 */ (const void *)&gVexTable_root_02_da_02_w, - /* 03 */ (const void *)&gVexTable_root_02_da_03_w, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2691] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_0f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_0f_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_02_0e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2692] -}; - -const ND_TABLE_VEX_W gVexTable_root_02_0e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_02_0e_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_02_0e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_02_0e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gVexTable_root_02_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gVexTable_root_02_00_pp, - /* 01 */ (const void *)&gVexTable_root_02_01_pp, - /* 02 */ (const void *)&gVexTable_root_02_02_pp, - /* 03 */ (const void *)&gVexTable_root_02_03_pp, - /* 04 */ (const void *)&gVexTable_root_02_04_pp, - /* 05 */ (const void *)&gVexTable_root_02_05_pp, - /* 06 */ (const void *)&gVexTable_root_02_06_pp, - /* 07 */ (const void *)&gVexTable_root_02_07_pp, - /* 08 */ (const void *)&gVexTable_root_02_08_pp, - /* 09 */ (const void *)&gVexTable_root_02_09_pp, - /* 0a */ (const void *)&gVexTable_root_02_0a_pp, - /* 0b */ (const void *)&gVexTable_root_02_0b_pp, - /* 0c */ (const void *)&gVexTable_root_02_0c_pp, - /* 0d */ (const void *)&gVexTable_root_02_0d_pp, - /* 0e */ (const void *)&gVexTable_root_02_0e_pp, - /* 0f */ (const void *)&gVexTable_root_02_0f_pp, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ (const void *)&gVexTable_root_02_13_pp, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ (const void *)&gVexTable_root_02_16_pp, - /* 17 */ (const void *)&gVexTable_root_02_17_pp, - /* 18 */ (const void *)&gVexTable_root_02_18_pp, - /* 19 */ (const void *)&gVexTable_root_02_19_pp, - /* 1a */ (const void *)&gVexTable_root_02_1a_pp, - /* 1b */ ND_NULL, - /* 1c */ (const void *)&gVexTable_root_02_1c_pp, - /* 1d */ (const void *)&gVexTable_root_02_1d_pp, - /* 1e */ (const void *)&gVexTable_root_02_1e_pp, - /* 1f */ ND_NULL, - /* 20 */ (const void *)&gVexTable_root_02_20_pp, - /* 21 */ (const void *)&gVexTable_root_02_21_pp, - /* 22 */ (const void *)&gVexTable_root_02_22_pp, - /* 23 */ (const void *)&gVexTable_root_02_23_pp, - /* 24 */ (const void *)&gVexTable_root_02_24_pp, - /* 25 */ (const void *)&gVexTable_root_02_25_pp, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ (const void *)&gVexTable_root_02_28_pp, - /* 29 */ (const void *)&gVexTable_root_02_29_pp, - /* 2a */ (const void *)&gVexTable_root_02_2a_pp, - /* 2b */ (const void *)&gVexTable_root_02_2b_pp, - /* 2c */ (const void *)&gVexTable_root_02_2c_pp, - /* 2d */ (const void *)&gVexTable_root_02_2d_pp, - /* 2e */ (const void *)&gVexTable_root_02_2e_pp, - /* 2f */ (const void *)&gVexTable_root_02_2f_pp, - /* 30 */ (const void *)&gVexTable_root_02_30_pp, - /* 31 */ (const void *)&gVexTable_root_02_31_pp, - /* 32 */ (const void *)&gVexTable_root_02_32_pp, - /* 33 */ (const void *)&gVexTable_root_02_33_pp, - /* 34 */ (const void *)&gVexTable_root_02_34_pp, - /* 35 */ (const void *)&gVexTable_root_02_35_pp, - /* 36 */ (const void *)&gVexTable_root_02_36_pp, - /* 37 */ (const void *)&gVexTable_root_02_37_pp, - /* 38 */ (const void *)&gVexTable_root_02_38_pp, - /* 39 */ (const void *)&gVexTable_root_02_39_pp, - /* 3a */ (const void *)&gVexTable_root_02_3a_pp, - /* 3b */ (const void *)&gVexTable_root_02_3b_pp, - /* 3c */ (const void *)&gVexTable_root_02_3c_pp, - /* 3d */ (const void *)&gVexTable_root_02_3d_pp, - /* 3e */ (const void *)&gVexTable_root_02_3e_pp, - /* 3f */ (const void *)&gVexTable_root_02_3f_pp, - /* 40 */ (const void *)&gVexTable_root_02_40_pp, - /* 41 */ (const void *)&gVexTable_root_02_41_pp, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ (const void *)&gVexTable_root_02_45_pp, - /* 46 */ (const void *)&gVexTable_root_02_46_pp, - /* 47 */ (const void *)&gVexTable_root_02_47_pp, - /* 48 */ ND_NULL, - /* 49 */ (const void *)&gVexTable_root_02_49_pp, - /* 4a */ ND_NULL, - /* 4b */ (const void *)&gVexTable_root_02_4b_pp, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ (const void *)&gVexTable_root_02_50_pp, - /* 51 */ (const void *)&gVexTable_root_02_51_pp, - /* 52 */ (const void *)&gVexTable_root_02_52_pp, - /* 53 */ (const void *)&gVexTable_root_02_53_pp, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ (const void *)&gVexTable_root_02_58_pp, - /* 59 */ (const void *)&gVexTable_root_02_59_pp, - /* 5a */ (const void *)&gVexTable_root_02_5a_pp, - /* 5b */ ND_NULL, - /* 5c */ (const void *)&gVexTable_root_02_5c_pp, - /* 5d */ ND_NULL, - /* 5e */ (const void *)&gVexTable_root_02_5e_pp, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ (const void *)&gVexTable_root_02_6c_pp, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ (const void *)&gVexTable_root_02_72_pp, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ (const void *)&gVexTable_root_02_78_pp, - /* 79 */ (const void *)&gVexTable_root_02_79_pp, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ (const void *)&gVexTable_root_02_8c_pp, - /* 8d */ ND_NULL, - /* 8e */ (const void *)&gVexTable_root_02_8e_pp, - /* 8f */ ND_NULL, - /* 90 */ (const void *)&gVexTable_root_02_90_pp, - /* 91 */ (const void *)&gVexTable_root_02_91_pp, - /* 92 */ (const void *)&gVexTable_root_02_92_pp, - /* 93 */ (const void *)&gVexTable_root_02_93_pp, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ (const void *)&gVexTable_root_02_96_pp, - /* 97 */ (const void *)&gVexTable_root_02_97_pp, - /* 98 */ (const void *)&gVexTable_root_02_98_pp, - /* 99 */ (const void *)&gVexTable_root_02_99_pp, - /* 9a */ (const void *)&gVexTable_root_02_9a_pp, - /* 9b */ (const void *)&gVexTable_root_02_9b_pp, - /* 9c */ (const void *)&gVexTable_root_02_9c_pp, - /* 9d */ (const void *)&gVexTable_root_02_9d_pp, - /* 9e */ (const void *)&gVexTable_root_02_9e_pp, - /* 9f */ (const void *)&gVexTable_root_02_9f_pp, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ (const void *)&gVexTable_root_02_a6_pp, - /* a7 */ (const void *)&gVexTable_root_02_a7_pp, - /* a8 */ (const void *)&gVexTable_root_02_a8_pp, - /* a9 */ (const void *)&gVexTable_root_02_a9_pp, - /* aa */ (const void *)&gVexTable_root_02_aa_pp, - /* ab */ (const void *)&gVexTable_root_02_ab_pp, - /* ac */ (const void *)&gVexTable_root_02_ac_pp, - /* ad */ (const void *)&gVexTable_root_02_ad_pp, - /* ae */ (const void *)&gVexTable_root_02_ae_pp, - /* af */ (const void *)&gVexTable_root_02_af_pp, - /* b0 */ (const void *)&gVexTable_root_02_b0_pp, - /* b1 */ (const void *)&gVexTable_root_02_b1_pp, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ (const void *)&gVexTable_root_02_b4_pp, - /* b5 */ (const void *)&gVexTable_root_02_b5_pp, - /* b6 */ (const void *)&gVexTable_root_02_b6_pp, - /* b7 */ (const void *)&gVexTable_root_02_b7_pp, - /* b8 */ (const void *)&gVexTable_root_02_b8_pp, - /* b9 */ (const void *)&gVexTable_root_02_b9_pp, - /* ba */ (const void *)&gVexTable_root_02_ba_pp, - /* bb */ (const void *)&gVexTable_root_02_bb_pp, - /* bc */ (const void *)&gVexTable_root_02_bc_pp, - /* bd */ (const void *)&gVexTable_root_02_bd_pp, - /* be */ (const void *)&gVexTable_root_02_be_pp, - /* bf */ (const void *)&gVexTable_root_02_bf_pp, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ (const void *)&gVexTable_root_02_cb_pp, - /* cc */ (const void *)&gVexTable_root_02_cc_pp, - /* cd */ (const void *)&gVexTable_root_02_cd_pp, - /* ce */ ND_NULL, - /* cf */ (const void *)&gVexTable_root_02_cf_pp, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ (const void *)&gVexTable_root_02_d2_pp, - /* d3 */ (const void *)&gVexTable_root_02_d3_pp, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ (const void *)&gVexTable_root_02_da_pp, - /* db */ (const void *)&gVexTable_root_02_db_pp, - /* dc */ (const void *)&gVexTable_root_02_dc_pp, - /* dd */ (const void *)&gVexTable_root_02_dd_pp, - /* de */ (const void *)&gVexTable_root_02_de_pp, - /* df */ (const void *)&gVexTable_root_02_df_pp, - /* e0 */ (const void *)&gVexTable_root_02_e0_pp, - /* e1 */ (const void *)&gVexTable_root_02_e1_pp, - /* e2 */ (const void *)&gVexTable_root_02_e2_pp, - /* e3 */ (const void *)&gVexTable_root_02_e3_pp, - /* e4 */ (const void *)&gVexTable_root_02_e4_pp, - /* e5 */ (const void *)&gVexTable_root_02_e5_pp, - /* e6 */ (const void *)&gVexTable_root_02_e6_pp, - /* e7 */ (const void *)&gVexTable_root_02_e7_pp, - /* e8 */ (const void *)&gVexTable_root_02_e8_pp, - /* e9 */ (const void *)&gVexTable_root_02_e9_pp, - /* ea */ (const void *)&gVexTable_root_02_ea_pp, - /* eb */ (const void *)&gVexTable_root_02_eb_pp, - /* ec */ (const void *)&gVexTable_root_02_ec_pp, - /* ed */ (const void *)&gVexTable_root_02_ed_pp, - /* ee */ (const void *)&gVexTable_root_02_ee_pp, - /* ef */ (const void *)&gVexTable_root_02_ef_pp, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ (const void *)&gVexTable_root_02_f2_pp, - /* f3 */ (const void *)&gVexTable_root_02_f3_pp, - /* f4 */ ND_NULL, - /* f5 */ (const void *)&gVexTable_root_02_f5_pp, - /* f6 */ (const void *)&gVexTable_root_02_f6_pp, - /* f7 */ (const void *)&gVexTable_root_02_f7_pp, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[122] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ (const void *)&gVexTable_root_01_ae_03_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_03_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1315] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_ae_03_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gVexTable_root_01_ae_03_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_ae_03_mem_modrmreg, - /* 01 */ (const void *)&gVexTable_root_01_ae_03_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_mem_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[123] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ (const void *)&gVexTable_root_01_ae_02_mem_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_02_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[238] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_ae_02_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gVexTable_root_01_ae_02_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_ae_02_mem_modrmreg, - /* 01 */ (const void *)&gVexTable_root_01_ae_02_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1882] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ae_00_mem_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2680] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_ae_00_mem_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_ae_00_mem_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_ae_00_mem_03_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_ae_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_ae_00_mem_modrmreg, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ae_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_ae_00_modrmmod, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_ae_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_01_ae_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[515] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[516] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_4a_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_4a_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_4a_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4a_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[517] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4a_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[518] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_4a_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_4a_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_4a_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_4a_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4a_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_4a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_4a_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_4a_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[519] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_41_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[520] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_41_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_41_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_41_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_41_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_41_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[525] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_41_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[526] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_41_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_41_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_41_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_41_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_41_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_41_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_41_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_41_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[521] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_42_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[522] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_42_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_42_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_42_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_42_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_42_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[523] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_42_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[524] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_42_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_42_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_42_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_42_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_42_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_42_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_42_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_42_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_48_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[527] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_48_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_48_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_48_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_48_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_48_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_48_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_48_00_modrmmod, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_49_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[528] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_49_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_49_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_49_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_49_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_49_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_49_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_49_00_modrmmod, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[529] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[534] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_90_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_90_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_90_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[530] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[535] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_90_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_90_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_90_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_90_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_90_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_90_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_90_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_01_90_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[539] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[544] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_90_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_90_00_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_90_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[540] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_90_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[545] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_90_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_90_00_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_90_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_90_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_mem_l, - /* 01 */ (const void *)&gVexTable_root_01_90_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_90_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_90_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_90_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[531] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_91_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[536] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_91_01_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_91_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_91_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_91_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_91_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[541] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_91_00_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[546] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_91_00_mem_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_91_00_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_91_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_91_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_91_00_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_91_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_91_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_91_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_92_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[532] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_92_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_92_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_92_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_92_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_92_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[537] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_92_03_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[542] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_92_03_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_92_03_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_92_03_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_92_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_92_03_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_92_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_92_03_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_92_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[547] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_92_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_92_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_92_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_92_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_92_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_92_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_92_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_92_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_92_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_93_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[533] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_93_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_93_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_93_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_93_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_93_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[538] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_93_03_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[543] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_93_03_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_93_03_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_93_03_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_93_03_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_93_03_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_93_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_93_03_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_93_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[548] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_93_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_93_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_93_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_93_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_93_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_93_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_93_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_93_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_93_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[549] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_44_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[550] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_44_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_44_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_44_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_44_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_44_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_44_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_44_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[551] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_44_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[552] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_44_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_44_00_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_44_00_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_44_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_44_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_44_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_44_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_44_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_44_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_44_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[553] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_45_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[554] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_45_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_45_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_45_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_45_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_45_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[555] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_45_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[560] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_45_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_45_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_45_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_45_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_45_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_45_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_45_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_45_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[556] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_98_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[557] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_98_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_98_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_98_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_98_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_98_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_98_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_98_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[558] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_98_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[559] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_98_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_98_00_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_98_00_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_98_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_98_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_98_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_98_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_98_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_98_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_98_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[569] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_99_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[570] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_99_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_99_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_99_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_99_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_99_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_99_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_99_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[571] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_99_00_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[572] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_99_00_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_99_00_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_99_00_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_99_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_99_00_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_99_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_99_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_99_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_99_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_99_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[573] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_4b_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_4b_01_reg_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_4b_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4b_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[574] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_4b_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[575] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_4b_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_4b_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_4b_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_4b_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_4b_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_4b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_4b_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_4b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[576] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_46_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[577] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_46_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_46_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_46_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_46_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_46_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[578] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_46_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[579] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_46_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_46_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_46_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_46_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_46_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_46_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_46_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_46_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[580] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_47_01_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[581] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_47_01_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_47_01_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_47_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_47_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_47_01_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[582] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_47_00_reg_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[583] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_47_00_reg_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_01_47_00_reg_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_47_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_47_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_47_00_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_47_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_47_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_47_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_58_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1405] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_58_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1408] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_58_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1410] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_58_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1413] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_58_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_58_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_58_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_58_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_58_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1414] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d0_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1415] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d0_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_d0_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_55_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1429] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_55_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1431] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_55_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_55_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_55_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_54_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1433] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_54_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1435] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_54_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_54_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_54_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1461] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1464] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1466] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c2_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1469] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_c2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_c2_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_c2_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_c2_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_c2_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1471] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2f_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1474] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_2f_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_2f_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1478] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1479] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_e6_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_e6_02_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_e6_02_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1491] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e6_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1548] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e6_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_e6_02_l, - /* 03 */ (const void *)&gVexTable_root_01_e6_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1482] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1511] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5b_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1559] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5b_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5b_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_5b_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1494] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1495] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_5a_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_5a_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5a_01_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1513] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1514] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_5a_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_5a_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5a_00_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1529] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5a_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1542] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5a_00_l, - /* 01 */ (const void *)&gVexTable_root_01_5a_01_l, - /* 02 */ (const void *)&gVexTable_root_01_5a_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_5a_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1527] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2d_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1545] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_2d_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_2d_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1537] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2a_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1540] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_2a_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_2a_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1564] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2c_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1569] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_2c_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_2c_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1585] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1588] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1590] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5e_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1593] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5e_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5e_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_5e_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_5e_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1863] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7c_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1864] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_7c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_7c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_7c_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1865] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7d_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1866] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_7d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_7d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_7d_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f0_03_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1881] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_f0_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_f0_03_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_01_f0_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f7_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1883] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_f7_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_f7_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_f7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f7_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1889] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1892] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1894] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5f_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1897] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5f_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5f_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_5f_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_5f_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1904] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1907] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1909] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5d_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1912] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5d_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5d_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_5d_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_5d_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_28_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1919] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_28_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1923] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_28_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_28_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_28_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_29_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1920] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_29_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1924] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_29_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_29_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_29_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1927] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6e_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1984] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_6e_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gVexTable_root_01_6e_01_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_6e_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_6e_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_6e_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6e_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1928] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1985] -}; - -const ND_TABLE_VEX_W gVexTable_root_01_7e_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gVexTable_root_01_7e_01_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_7e_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_01_7e_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_7e_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7e_02_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1986] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_7e_02_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_7e_02_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_7e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_7e_01_l, - /* 02 */ (const void *)&gVexTable_root_01_7e_02_l, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1932] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_03_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1933] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_12_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_12_03_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_12_03_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1951] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_12_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_12_00_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1968] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_12_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_12_00_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_12_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_12_00_mem_l, - /* 01 */ (const void *)&gVexTable_root_01_12_00_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1964] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_12_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_12_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_12_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_12_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2003] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_12_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_12_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_12_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_01_12_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_12_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1934] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6f_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1940] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6f_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_6f_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1935] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_7f_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1941] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_7f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_7f_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_7f_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_16_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1954] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_16_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_16_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_16_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1958] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_16_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_16_00_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_16_00_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1961] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_16_00_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_16_00_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_16_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_16_00_mem_l, - /* 01 */ (const void *)&gVexTable_root_01_16_00_reg_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_16_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2001] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_16_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_16_01_modrmmod, - /* 02 */ (const void *)&gVexTable_root_01_16_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_17_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1955] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_17_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_17_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_17_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_17_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1959] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_17_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_17_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_17_00_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_17_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_17_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_17_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_13_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1965] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_13_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_13_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_13_01_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_13_00_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1969] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_13_00_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_13_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_13_00_mem_l, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_13_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_13_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_13_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_50_01_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1970] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_50_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_50_01_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_50_00_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1971] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_50_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_50_00_reg_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_50_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_50_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_50_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e7_01_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1973] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_e7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_e7_01_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_01_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1977] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_2b_01_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2b_00_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1979] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_2b_00_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_2b_00_mem_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_2b_00_modrmmod, - /* 01 */ (const void *)&gVexTable_root_01_2b_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d6_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1987] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_d6_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_d6_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d6_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1992] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_03_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1993] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_10_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_10_03_mem_leaf, - /* 01 */ (const void *)&gVexTable_root_01_10_03_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2008] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_02_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2009] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_10_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_10_02_mem_leaf, - /* 01 */ (const void *)&gVexTable_root_01_10_02_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2014] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_10_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2018] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_10_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_10_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_10_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_10_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_01_10_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1994] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_03_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1995] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_11_03_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_11_03_mem_leaf, - /* 01 */ (const void *)&gVexTable_root_01_11_03_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2010] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_02_mem_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2011] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_11_02_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_11_02_mem_leaf, - /* 01 */ (const void *)&gVexTable_root_01_11_02_reg_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2015] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_11_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2019] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_11_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_11_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_11_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_11_02_modrmmod, - /* 03 */ (const void *)&gVexTable_root_01_11_03_modrmmod, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_59_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2032] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_59_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2035] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_59_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2037] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_59_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2040] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_59_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_59_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_59_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_59_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_59_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_56_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2045] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_56_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2047] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_56_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_56_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_56_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2060] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_63_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2062] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_63_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_63_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_67_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2066] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_67_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_67_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_fc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2068] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_fc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_fc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_fe_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2070] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_fe_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_fe_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d4_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2072] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d4_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ec_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2074] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ec_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_ec_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ed_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2076] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ed_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_ed_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_dc_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2078] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_dc_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_dc_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_dd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2080] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_dd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_dd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_fd_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2082] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_fd_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_fd_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_db_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2085] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_db_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_db_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_df_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2087] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_df_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_df_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e0_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2092] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e0_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2094] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e3_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_74_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2123] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_74_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_74_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_76_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2125] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_76_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_76_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_75_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2129] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_75_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_75_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_64_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2133] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_64_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_64_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_66_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2135] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_66_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_66_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_65_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2139] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_65_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_65_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c5_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2241] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_c5_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_c5_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_c5_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_c5_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_c5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_c5_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2284] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_c4_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c4_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2285] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_c4_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_c4_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_c4_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_01_c4_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_01_c4_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_c4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_c4_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2307] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ee_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2318] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ee_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_ee_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_de_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2320] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_de_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_de_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ea_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2332] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ea_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_ea_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_da_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2334] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_da_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_da_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d7_01_reg_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2348] -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_d7_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d7_01_reg_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d7_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d7_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e4_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2408] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e4_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2410] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d5_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2415] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d5_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d5_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f4_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2418] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f4_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f4_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_eb_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2423] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_eb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_eb_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f6_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2449] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f6_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_70_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2486] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_70_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2488] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_70_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2490] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_70_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_70_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_70_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_70_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2496] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2515] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_72_01_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2529] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_72_01_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_72_01_reg_02_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gVexTable_root_01_72_01_reg_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gVexTable_root_01_72_01_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_72_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_72_01_reg_modrmreg, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_72_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_72_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2497] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f2_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2499] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2502] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2532] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_73_01_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2535] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_73_01_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_73_01_reg_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_73_01_reg_03_leaf, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gVexTable_root_01_73_01_reg_06_leaf, - /* 07 */ (const void *)&gVexTable_root_01_73_01_reg_07_leaf, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_73_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_73_01_reg_modrmreg, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_73_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_73_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2503] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f3_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2511] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2525] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_71_01_reg_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2544] -}; - -const ND_TABLE_MODRM_REG gVexTable_root_01_71_01_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_71_01_reg_02_leaf, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gVexTable_root_01_71_01_reg_04_leaf, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gVexTable_root_01_71_01_reg_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_01_71_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_71_01_reg_modrmreg, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_71_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_71_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2512] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2516] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e2_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2526] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2530] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d2_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d2_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2536] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d3_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d3_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d1_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2545] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d1_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d1_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2547] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_fa_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2549] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_fa_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_fa_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_fb_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2551] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_fb_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_fb_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2553] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_e9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2555] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_e9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_e9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d8_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2557] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d8_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d8_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_d9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2559] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_d9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_d9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_f9_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2561] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_f9_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_f9_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_68_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2574] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_68_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_68_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2576] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6a_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2578] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_69_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2580] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_69_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_69_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_60_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2582] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_60_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_60_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_62_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2584] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_62_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_62_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_6c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2586] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_6c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_6c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_61_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2588] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_61_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_61_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_ef_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2589] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_ef_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_ef_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_53_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2605] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_53_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2607] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_53_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_53_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_53_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_52_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2633] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_52_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2635] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_52_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_52_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ (const void *)&gVexTable_root_01_52_02_leaf, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2662] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_c6_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2664] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_c6_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_c6_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_c6_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_51_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2671] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_51_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2674] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_51_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2676] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_51_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2679] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_51_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_51_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_51_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_51_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_51_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2682] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2685] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2687] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_5c_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2690] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_5c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_5c_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_5c_01_leaf, - /* 02 */ (const void *)&gVexTable_root_01_5c_02_leaf, - /* 03 */ (const void *)&gVexTable_root_01_5c_03_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2694] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_2e_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2697] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_2e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_2e_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_2e_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_15_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2699] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_15_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2701] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_15_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_15_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_15_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_14_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2703] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_14_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2705] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_14_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_14_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_14_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_57_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2707] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_57_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2709] -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_57_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_57_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_57_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2710] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_01_77_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2711] -}; - -const ND_TABLE_VEX_L gVexTable_root_01_77_00_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_01_77_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_01_77_00_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_01_77_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ (const void *)&gVexTable_root_01_77_00_l, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gVexTable_root_01_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gVexTable_root_01_10_pp, - /* 11 */ (const void *)&gVexTable_root_01_11_pp, - /* 12 */ (const void *)&gVexTable_root_01_12_pp, - /* 13 */ (const void *)&gVexTable_root_01_13_pp, - /* 14 */ (const void *)&gVexTable_root_01_14_pp, - /* 15 */ (const void *)&gVexTable_root_01_15_pp, - /* 16 */ (const void *)&gVexTable_root_01_16_pp, - /* 17 */ (const void *)&gVexTable_root_01_17_pp, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ (const void *)&gVexTable_root_01_28_pp, - /* 29 */ (const void *)&gVexTable_root_01_29_pp, - /* 2a */ (const void *)&gVexTable_root_01_2a_pp, - /* 2b */ (const void *)&gVexTable_root_01_2b_pp, - /* 2c */ (const void *)&gVexTable_root_01_2c_pp, - /* 2d */ (const void *)&gVexTable_root_01_2d_pp, - /* 2e */ (const void *)&gVexTable_root_01_2e_pp, - /* 2f */ (const void *)&gVexTable_root_01_2f_pp, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ (const void *)&gVexTable_root_01_41_pp, - /* 42 */ (const void *)&gVexTable_root_01_42_pp, - /* 43 */ ND_NULL, - /* 44 */ (const void *)&gVexTable_root_01_44_pp, - /* 45 */ (const void *)&gVexTable_root_01_45_pp, - /* 46 */ (const void *)&gVexTable_root_01_46_pp, - /* 47 */ (const void *)&gVexTable_root_01_47_pp, - /* 48 */ (const void *)&gVexTable_root_01_48_pp, - /* 49 */ (const void *)&gVexTable_root_01_49_pp, - /* 4a */ (const void *)&gVexTable_root_01_4a_pp, - /* 4b */ (const void *)&gVexTable_root_01_4b_pp, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ (const void *)&gVexTable_root_01_50_pp, - /* 51 */ (const void *)&gVexTable_root_01_51_pp, - /* 52 */ (const void *)&gVexTable_root_01_52_pp, - /* 53 */ (const void *)&gVexTable_root_01_53_pp, - /* 54 */ (const void *)&gVexTable_root_01_54_pp, - /* 55 */ (const void *)&gVexTable_root_01_55_pp, - /* 56 */ (const void *)&gVexTable_root_01_56_pp, - /* 57 */ (const void *)&gVexTable_root_01_57_pp, - /* 58 */ (const void *)&gVexTable_root_01_58_pp, - /* 59 */ (const void *)&gVexTable_root_01_59_pp, - /* 5a */ (const void *)&gVexTable_root_01_5a_pp, - /* 5b */ (const void *)&gVexTable_root_01_5b_pp, - /* 5c */ (const void *)&gVexTable_root_01_5c_pp, - /* 5d */ (const void *)&gVexTable_root_01_5d_pp, - /* 5e */ (const void *)&gVexTable_root_01_5e_pp, - /* 5f */ (const void *)&gVexTable_root_01_5f_pp, - /* 60 */ (const void *)&gVexTable_root_01_60_pp, - /* 61 */ (const void *)&gVexTable_root_01_61_pp, - /* 62 */ (const void *)&gVexTable_root_01_62_pp, - /* 63 */ (const void *)&gVexTable_root_01_63_pp, - /* 64 */ (const void *)&gVexTable_root_01_64_pp, - /* 65 */ (const void *)&gVexTable_root_01_65_pp, - /* 66 */ (const void *)&gVexTable_root_01_66_pp, - /* 67 */ (const void *)&gVexTable_root_01_67_pp, - /* 68 */ (const void *)&gVexTable_root_01_68_pp, - /* 69 */ (const void *)&gVexTable_root_01_69_pp, - /* 6a */ (const void *)&gVexTable_root_01_6a_pp, - /* 6b */ (const void *)&gVexTable_root_01_6b_pp, - /* 6c */ (const void *)&gVexTable_root_01_6c_pp, - /* 6d */ (const void *)&gVexTable_root_01_6d_pp, - /* 6e */ (const void *)&gVexTable_root_01_6e_pp, - /* 6f */ (const void *)&gVexTable_root_01_6f_pp, - /* 70 */ (const void *)&gVexTable_root_01_70_pp, - /* 71 */ (const void *)&gVexTable_root_01_71_pp, - /* 72 */ (const void *)&gVexTable_root_01_72_pp, - /* 73 */ (const void *)&gVexTable_root_01_73_pp, - /* 74 */ (const void *)&gVexTable_root_01_74_pp, - /* 75 */ (const void *)&gVexTable_root_01_75_pp, - /* 76 */ (const void *)&gVexTable_root_01_76_pp, - /* 77 */ (const void *)&gVexTable_root_01_77_pp, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ (const void *)&gVexTable_root_01_7c_pp, - /* 7d */ (const void *)&gVexTable_root_01_7d_pp, - /* 7e */ (const void *)&gVexTable_root_01_7e_pp, - /* 7f */ (const void *)&gVexTable_root_01_7f_pp, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ (const void *)&gVexTable_root_01_90_pp, - /* 91 */ (const void *)&gVexTable_root_01_91_pp, - /* 92 */ (const void *)&gVexTable_root_01_92_pp, - /* 93 */ (const void *)&gVexTable_root_01_93_pp, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ (const void *)&gVexTable_root_01_98_pp, - /* 99 */ (const void *)&gVexTable_root_01_99_pp, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ (const void *)&gVexTable_root_01_ae_pp, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ (const void *)&gVexTable_root_01_c2_pp, - /* c3 */ ND_NULL, - /* c4 */ (const void *)&gVexTable_root_01_c4_pp, - /* c5 */ (const void *)&gVexTable_root_01_c5_pp, - /* c6 */ (const void *)&gVexTable_root_01_c6_pp, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ (const void *)&gVexTable_root_01_d0_pp, - /* d1 */ (const void *)&gVexTable_root_01_d1_pp, - /* d2 */ (const void *)&gVexTable_root_01_d2_pp, - /* d3 */ (const void *)&gVexTable_root_01_d3_pp, - /* d4 */ (const void *)&gVexTable_root_01_d4_pp, - /* d5 */ (const void *)&gVexTable_root_01_d5_pp, - /* d6 */ (const void *)&gVexTable_root_01_d6_pp, - /* d7 */ (const void *)&gVexTable_root_01_d7_pp, - /* d8 */ (const void *)&gVexTable_root_01_d8_pp, - /* d9 */ (const void *)&gVexTable_root_01_d9_pp, - /* da */ (const void *)&gVexTable_root_01_da_pp, - /* db */ (const void *)&gVexTable_root_01_db_pp, - /* dc */ (const void *)&gVexTable_root_01_dc_pp, - /* dd */ (const void *)&gVexTable_root_01_dd_pp, - /* de */ (const void *)&gVexTable_root_01_de_pp, - /* df */ (const void *)&gVexTable_root_01_df_pp, - /* e0 */ (const void *)&gVexTable_root_01_e0_pp, - /* e1 */ (const void *)&gVexTable_root_01_e1_pp, - /* e2 */ (const void *)&gVexTable_root_01_e2_pp, - /* e3 */ (const void *)&gVexTable_root_01_e3_pp, - /* e4 */ (const void *)&gVexTable_root_01_e4_pp, - /* e5 */ (const void *)&gVexTable_root_01_e5_pp, - /* e6 */ (const void *)&gVexTable_root_01_e6_pp, - /* e7 */ (const void *)&gVexTable_root_01_e7_pp, - /* e8 */ (const void *)&gVexTable_root_01_e8_pp, - /* e9 */ (const void *)&gVexTable_root_01_e9_pp, - /* ea */ (const void *)&gVexTable_root_01_ea_pp, - /* eb */ (const void *)&gVexTable_root_01_eb_pp, - /* ec */ (const void *)&gVexTable_root_01_ec_pp, - /* ed */ (const void *)&gVexTable_root_01_ed_pp, - /* ee */ (const void *)&gVexTable_root_01_ee_pp, - /* ef */ (const void *)&gVexTable_root_01_ef_pp, - /* f0 */ (const void *)&gVexTable_root_01_f0_pp, - /* f1 */ (const void *)&gVexTable_root_01_f1_pp, - /* f2 */ (const void *)&gVexTable_root_01_f2_pp, - /* f3 */ (const void *)&gVexTable_root_01_f3_pp, - /* f4 */ (const void *)&gVexTable_root_01_f4_pp, - /* f5 */ (const void *)&gVexTable_root_01_f5_pp, - /* f6 */ (const void *)&gVexTable_root_01_f6_pp, - /* f7 */ (const void *)&gVexTable_root_01_f7_pp, - /* f8 */ (const void *)&gVexTable_root_01_f8_pp, - /* f9 */ (const void *)&gVexTable_root_01_f9_pp, - /* fa */ (const void *)&gVexTable_root_01_fa_pp, - /* fb */ (const void *)&gVexTable_root_01_fb_pp, - /* fc */ (const void *)&gVexTable_root_01_fc_pp, - /* fd */ (const void *)&gVexTable_root_01_fd_pp, - /* fe */ (const void *)&gVexTable_root_01_fe_pp, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[561] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_32_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[564] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_32_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_32_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_32_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_32_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_32_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_32_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_32_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_32_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_32_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[562] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_33_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[563] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_33_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_33_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_33_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_33_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_33_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_33_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_33_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_33_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_33_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[565] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_30_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[568] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_30_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_30_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_30_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_30_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_30_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_30_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_30_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_30_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_30_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[566] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_31_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[567] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_31_01_reg_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_31_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_31_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_31_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_31_01_reg_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_31_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_31_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_31_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_31_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_f0_03_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1210] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_f0_03_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_f0_03_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_f0_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ (const void *)&gVexTable_root_03_f0_03_l, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_df_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1425] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_df_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_df_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_df_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_df_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0d_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1440] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0d_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0c_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1441] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0c_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_4b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1442] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_4b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_4b_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_4b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_4b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_4a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1443] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_4a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_4a_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_4a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_4a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1516] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_1d_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_1d_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1517] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_1d_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_1d_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_1d_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_1d_01_00_w, - /* 01 */ (const void *)&gVexTable_root_03_1d_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_1d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_1d_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_41_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1595] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_41_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_41_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_41_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_41_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_40_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1596] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_40_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_40_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_19_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1603] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_19_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_19_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_19_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_19_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_19_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_19_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_39_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1608] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_39_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_39_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_39_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_39_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_39_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_39_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1615] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_17_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_17_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_17_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1616] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_17_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_17_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_17_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_17_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_17_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_17_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_17_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1657] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_69_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1658] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_69_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_69_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_69_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_69_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_69_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1659] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_68_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1660] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_68_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_68_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_68_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_68_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_68_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1661] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1662] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6b_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1663] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1664] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6a_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6a_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1680] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1681] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_5d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_5d_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_5d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_5d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_5d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1682] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1683] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_5c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_5c_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_5c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_5c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_5c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1729] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1730] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_5f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_5f_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_5f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_5f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_5f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1731] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_5e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1732] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_5e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_5e_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_5e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_5e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_5e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1733] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1734] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6d_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1735] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1736] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6c_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1737] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1738] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6f_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1739] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_6e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1740] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_6e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_6e_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_6e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_6e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_6e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1773] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_79_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1774] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_79_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_79_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_79_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_79_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_79_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1775] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_78_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1776] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_78_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_78_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_78_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_78_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_78_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1777] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7b_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1778] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7b_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7b_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7b_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7b_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1779] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7a_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1780] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7a_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7a_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7a_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7a_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1811] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7d_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1812] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7d_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7d_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7d_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7d_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7d_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1813] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7c_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1814] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7c_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7c_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1815] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7f_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1816] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7f_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7f_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7f_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7f_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1817] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_7e_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1818] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_7e_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_7e_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_7e_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_7e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_7e_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_cf_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1858] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_cf_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_cf_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_cf_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_cf_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_ce_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1860] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_ce_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_ce_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_ce_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_ce_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_18_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1867] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_18_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_18_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_18_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_18_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_18_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_18_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_38_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1872] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_38_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_38_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_38_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_38_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_38_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_38_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1879] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_21_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_21_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_21_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1880] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_21_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_21_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_21_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_21_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_21_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_21_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_21_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_42_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2024] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_42_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_42_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0f_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2084] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0f_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0f_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_02_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2095] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_02_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_02_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_02_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_02_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_4c_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2100] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_4c_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_4c_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_4c_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_4c_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0e_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2101] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0e_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0e_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_44_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2117] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_44_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_44_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_61_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2130] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_61_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_61_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_61_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_61_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_60_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2131] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_60_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_60_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_60_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_60_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_63_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2140] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_63_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_63_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_63_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_63_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_62_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2141] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_62_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_62_01_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_62_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_62_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_06_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2182] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_06_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_06_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_06_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_06_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_06_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_06_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_46_01_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2183] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_46_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_46_01_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_46_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_46_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_46_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_46_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2193] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_49_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2194] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_49_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_49_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_49_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_49_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_49_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2195] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_48_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2196] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_48_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_48_01_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_48_01_01_leaf, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_48_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_48_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_05_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2200] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_05_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_05_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_05_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_05_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_04_01_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2204] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_04_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_04_01_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_04_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_04_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_01_01_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2208] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_01_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_01_01_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_01_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_01_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_01_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_01_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_00_01_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2214] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_00_01_01_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_00_01_01_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_00_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_00_01_01_w, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_00_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_00_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2228] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_14_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_14_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2229] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_14_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_14_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_14_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_14_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_14_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_14_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_14_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2232] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_mem_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2236] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_16_01_mem_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_16_01_mem_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_16_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2233] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_16_01_reg_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2237] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_16_01_reg_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gVexTable_root_03_16_01_reg_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_16_01_reg_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_16_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_16_01_reg_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_16_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_16_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_16_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_16_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_16_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2242] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_15_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_15_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2243] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_15_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_15_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_15_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_15_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_15_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_15_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_15_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_mem_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2276] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_20_01_mem_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_20_01_mem_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_20_01_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2277] -}; - -const ND_TABLE_VEX_L gVexTable_root_03_20_01_reg_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_20_01_reg_00_leaf, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gVexTable_root_03_20_01_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ (const void *)&gVexTable_root_03_20_01_mem_l, - /* 01 */ (const void *)&gVexTable_root_03_20_01_reg_l, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_20_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_20_01_modrmmod, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2279] -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_22_01_00_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2281] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_22_01_00_wi = -{ - ND_ILUT_VEX_WI, - { - /* 00 */ (const void *)&gVexTable_root_03_22_01_00_00_leaf, - /* 01 */ (const void *)&gVexTable_root_03_22_01_00_01_leaf, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_22_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_22_01_00_wi, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_22_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_22_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_09_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2620] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_09_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_09_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_08_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2621] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_08_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_08_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2622] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0b_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0b_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_0a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2623] -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_0a_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_0a_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gVexTable_root_03_de_01_00_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2667] -}; - -const ND_TABLE_VEX_W gVexTable_root_03_de_01_00_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gVexTable_root_03_de_01_00_00_leaf, - /* 01 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_L gVexTable_root_03_de_01_l = -{ - ND_ILUT_VEX_L, - { - /* 00 */ (const void *)&gVexTable_root_03_de_01_00_w, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_VEX_PP gVexTable_root_03_de_pp = -{ - ND_ILUT_VEX_PP, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_03_de_01_l, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gVexTable_root_03_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ (const void *)&gVexTable_root_03_00_pp, - /* 01 */ (const void *)&gVexTable_root_03_01_pp, - /* 02 */ (const void *)&gVexTable_root_03_02_pp, - /* 03 */ ND_NULL, - /* 04 */ (const void *)&gVexTable_root_03_04_pp, - /* 05 */ (const void *)&gVexTable_root_03_05_pp, - /* 06 */ (const void *)&gVexTable_root_03_06_pp, - /* 07 */ ND_NULL, - /* 08 */ (const void *)&gVexTable_root_03_08_pp, - /* 09 */ (const void *)&gVexTable_root_03_09_pp, - /* 0a */ (const void *)&gVexTable_root_03_0a_pp, - /* 0b */ (const void *)&gVexTable_root_03_0b_pp, - /* 0c */ (const void *)&gVexTable_root_03_0c_pp, - /* 0d */ (const void *)&gVexTable_root_03_0d_pp, - /* 0e */ (const void *)&gVexTable_root_03_0e_pp, - /* 0f */ (const void *)&gVexTable_root_03_0f_pp, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ (const void *)&gVexTable_root_03_14_pp, - /* 15 */ (const void *)&gVexTable_root_03_15_pp, - /* 16 */ (const void *)&gVexTable_root_03_16_pp, - /* 17 */ (const void *)&gVexTable_root_03_17_pp, - /* 18 */ (const void *)&gVexTable_root_03_18_pp, - /* 19 */ (const void *)&gVexTable_root_03_19_pp, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ (const void *)&gVexTable_root_03_1d_pp, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ (const void *)&gVexTable_root_03_20_pp, - /* 21 */ (const void *)&gVexTable_root_03_21_pp, - /* 22 */ (const void *)&gVexTable_root_03_22_pp, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ (const void *)&gVexTable_root_03_30_pp, - /* 31 */ (const void *)&gVexTable_root_03_31_pp, - /* 32 */ (const void *)&gVexTable_root_03_32_pp, - /* 33 */ (const void *)&gVexTable_root_03_33_pp, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ (const void *)&gVexTable_root_03_38_pp, - /* 39 */ (const void *)&gVexTable_root_03_39_pp, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ (const void *)&gVexTable_root_03_40_pp, - /* 41 */ (const void *)&gVexTable_root_03_41_pp, - /* 42 */ (const void *)&gVexTable_root_03_42_pp, - /* 43 */ ND_NULL, - /* 44 */ (const void *)&gVexTable_root_03_44_pp, - /* 45 */ ND_NULL, - /* 46 */ (const void *)&gVexTable_root_03_46_pp, - /* 47 */ ND_NULL, - /* 48 */ (const void *)&gVexTable_root_03_48_pp, - /* 49 */ (const void *)&gVexTable_root_03_49_pp, - /* 4a */ (const void *)&gVexTable_root_03_4a_pp, - /* 4b */ (const void *)&gVexTable_root_03_4b_pp, - /* 4c */ (const void *)&gVexTable_root_03_4c_pp, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ (const void *)&gVexTable_root_03_5c_pp, - /* 5d */ (const void *)&gVexTable_root_03_5d_pp, - /* 5e */ (const void *)&gVexTable_root_03_5e_pp, - /* 5f */ (const void *)&gVexTable_root_03_5f_pp, - /* 60 */ (const void *)&gVexTable_root_03_60_pp, - /* 61 */ (const void *)&gVexTable_root_03_61_pp, - /* 62 */ (const void *)&gVexTable_root_03_62_pp, - /* 63 */ (const void *)&gVexTable_root_03_63_pp, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ (const void *)&gVexTable_root_03_68_pp, - /* 69 */ (const void *)&gVexTable_root_03_69_pp, - /* 6a */ (const void *)&gVexTable_root_03_6a_pp, - /* 6b */ (const void *)&gVexTable_root_03_6b_pp, - /* 6c */ (const void *)&gVexTable_root_03_6c_pp, - /* 6d */ (const void *)&gVexTable_root_03_6d_pp, - /* 6e */ (const void *)&gVexTable_root_03_6e_pp, - /* 6f */ (const void *)&gVexTable_root_03_6f_pp, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ (const void *)&gVexTable_root_03_78_pp, - /* 79 */ (const void *)&gVexTable_root_03_79_pp, - /* 7a */ (const void *)&gVexTable_root_03_7a_pp, - /* 7b */ (const void *)&gVexTable_root_03_7b_pp, - /* 7c */ (const void *)&gVexTable_root_03_7c_pp, - /* 7d */ (const void *)&gVexTable_root_03_7d_pp, - /* 7e */ (const void *)&gVexTable_root_03_7e_pp, - /* 7f */ (const void *)&gVexTable_root_03_7f_pp, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ (const void *)&gVexTable_root_03_ce_pp, - /* cf */ (const void *)&gVexTable_root_03_cf_pp, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ (const void *)&gVexTable_root_03_de_pp, - /* df */ (const void *)&gVexTable_root_03_df_pp, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ (const void *)&gVexTable_root_03_f0_pp, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_VEX_MMMMM gVexTable_root_mmmmm = -{ - ND_ILUT_VEX_MMMMM, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gVexTable_root_01_opcode, - /* 02 */ (const void *)&gVexTable_root_02_opcode, - /* 03 */ (const void *)&gVexTable_root_03_opcode, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - } -}; - -const PND_TABLE gVexTable = (const PND_TABLE)&gVexTable_root_mmmmm; - - -#endif - diff --git a/bddisasm/include/table_xop.h b/bddisasm/include/table_xop.h deleted file mode 100644 index c77115a..0000000 --- a/bddisasm/include/table_xop.h +++ /dev/null @@ -1,1550 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ - -// -// This file was auto-generated by generate_tables.py. DO NOT MODIFY! -// - -#ifndef TABLE_XOP_H -#define TABLE_XOP_H - -const ND_TABLE_INSTRUCTION gXopTable_root_0a_10_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[68] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[620] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_0a_12_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[621] -}; - -const ND_TABLE_MODRM_REG gXopTable_root_0a_12_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gXopTable_root_0a_12_00_leaf, - /* 01 */ (const void *)&gXopTable_root_0a_12_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_OPCODE gXopTable_root_0a_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ (const void *)&gXopTable_root_0a_10_leaf, - /* 11 */ ND_NULL, - /* 12 */ (const void *)&gXopTable_root_0a_12_modrmreg, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ ND_NULL, - /* 96 */ ND_NULL, - /* 97 */ ND_NULL, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ ND_NULL, - /* c2 */ ND_NULL, - /* c3 */ ND_NULL, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[69] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_05_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[71] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_03_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[73] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_02_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[78] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[80] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1360] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1387] -}; - -const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gXopTable_root_09_01_01_leaf, - /* 02 */ (const void *)&gXopTable_root_09_01_02_leaf, - /* 03 */ (const void *)&gXopTable_root_09_01_03_leaf, - /* 04 */ (const void *)&gXopTable_root_09_01_04_leaf, - /* 05 */ (const void *)&gXopTable_root_09_01_05_leaf, - /* 06 */ (const void *)&gXopTable_root_09_01_06_leaf, - /* 07 */ (const void *)&gXopTable_root_09_01_07_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_02_06_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[70] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_02_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[72] -}; - -const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gXopTable_root_09_02_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ (const void *)&gXopTable_root_09_02_06_leaf, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[602] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1311] -}; - -const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg = -{ - ND_ILUT_MODRM_REG, - { - /* 00 */ (const void *)&gXopTable_root_09_12_reg_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_12_reg_01_leaf, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - } -}; - -const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod = -{ - ND_ILUT_MODRM_MOD, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gXopTable_root_09_12_reg_modrmreg, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1825] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1826] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1827] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[1828] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2252] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2253] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2254] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2256] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2258] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2259] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2260] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2261] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2262] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2263] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2265] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2266] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2268] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2270] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2273] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2437] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2438] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_90_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_90_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_90_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2440] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2441] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_92_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_92_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_92_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2443] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2444] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_93_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_93_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_93_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2446] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2447] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_91_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_91_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_91_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2454] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2455] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_98_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_98_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_98_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2456] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2457] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_9a_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_9a_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_9a_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2458] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2459] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_9b_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_9b_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_9b_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2460] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2461] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_99_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_99_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_99_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2462] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2463] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_94_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_94_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_94_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2464] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2475] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_95_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_95_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_95_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2465] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2466] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_96_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_96_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_96_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2473] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2474] -}; - -const ND_TABLE_VEX_W gXopTable_root_09_97_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_09_97_00_leaf, - /* 01 */ (const void *)&gXopTable_root_09_97_01_leaf, - } -}; - -const ND_TABLE_OPCODE gXopTable_root_09_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ (const void *)&gXopTable_root_09_01_modrmreg, - /* 02 */ (const void *)&gXopTable_root_09_02_modrmreg, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ (const void *)&gXopTable_root_09_12_modrmmod, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ (const void *)&gXopTable_root_09_80_leaf, - /* 81 */ (const void *)&gXopTable_root_09_81_leaf, - /* 82 */ (const void *)&gXopTable_root_09_82_leaf, - /* 83 */ (const void *)&gXopTable_root_09_83_leaf, - /* 84 */ ND_NULL, - /* 85 */ ND_NULL, - /* 86 */ ND_NULL, - /* 87 */ ND_NULL, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ ND_NULL, - /* 8f */ ND_NULL, - /* 90 */ (const void *)&gXopTable_root_09_90_w, - /* 91 */ (const void *)&gXopTable_root_09_91_w, - /* 92 */ (const void *)&gXopTable_root_09_92_w, - /* 93 */ (const void *)&gXopTable_root_09_93_w, - /* 94 */ (const void *)&gXopTable_root_09_94_w, - /* 95 */ (const void *)&gXopTable_root_09_95_w, - /* 96 */ (const void *)&gXopTable_root_09_96_w, - /* 97 */ (const void *)&gXopTable_root_09_97_w, - /* 98 */ (const void *)&gXopTable_root_09_98_w, - /* 99 */ (const void *)&gXopTable_root_09_99_w, - /* 9a */ (const void *)&gXopTable_root_09_9a_w, - /* 9b */ (const void *)&gXopTable_root_09_9b_w, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ ND_NULL, - /* 9f */ ND_NULL, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ ND_NULL, - /* a3 */ ND_NULL, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ ND_NULL, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ ND_NULL, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ ND_NULL, - /* c1 */ (const void *)&gXopTable_root_09_c1_leaf, - /* c2 */ (const void *)&gXopTable_root_09_c2_leaf, - /* c3 */ (const void *)&gXopTable_root_09_c3_leaf, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ (const void *)&gXopTable_root_09_c6_leaf, - /* c7 */ (const void *)&gXopTable_root_09_c7_leaf, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ (const void *)&gXopTable_root_09_cb_leaf, - /* cc */ ND_NULL, - /* cd */ ND_NULL, - /* ce */ ND_NULL, - /* cf */ ND_NULL, - /* d0 */ ND_NULL, - /* d1 */ (const void *)&gXopTable_root_09_d1_leaf, - /* d2 */ (const void *)&gXopTable_root_09_d2_leaf, - /* d3 */ (const void *)&gXopTable_root_09_d3_leaf, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ (const void *)&gXopTable_root_09_d6_leaf, - /* d7 */ (const void *)&gXopTable_root_09_d7_leaf, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ (const void *)&gXopTable_root_09_db_leaf, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ (const void *)&gXopTable_root_09_e1_leaf, - /* e2 */ (const void *)&gXopTable_root_09_e2_leaf, - /* e3 */ (const void *)&gXopTable_root_09_e3_leaf, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ ND_NULL, - /* ed */ ND_NULL, - /* ee */ ND_NULL, - /* ef */ ND_NULL, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2118] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2119] -}; - -const ND_TABLE_VEX_W gXopTable_root_08_a2_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_08_a2_00_leaf, - /* 01 */ (const void *)&gXopTable_root_08_a2_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2148] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2149] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2154] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2155] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2156] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2157] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2158] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2159] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2288] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2289] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2290] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2291] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2292] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2293] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2294] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2295] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2296] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2297] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2298] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2299] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2426] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2427] -}; - -const ND_TABLE_VEX_W gXopTable_root_08_a3_w = -{ - ND_ILUT_VEX_W, - { - /* 00 */ (const void *)&gXopTable_root_08_a3_00_leaf, - /* 01 */ (const void *)&gXopTable_root_08_a3_01_leaf, - } -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2436] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2439] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2442] -}; - -const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf = -{ - ND_ILUT_INSTRUCTION, - (const void *)&gInstructions[2445] -}; - -const ND_TABLE_OPCODE gXopTable_root_08_opcode = -{ - ND_ILUT_OPCODE, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ ND_NULL, - /* 09 */ ND_NULL, - /* 0a */ ND_NULL, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - /* 20 */ ND_NULL, - /* 21 */ ND_NULL, - /* 22 */ ND_NULL, - /* 23 */ ND_NULL, - /* 24 */ ND_NULL, - /* 25 */ ND_NULL, - /* 26 */ ND_NULL, - /* 27 */ ND_NULL, - /* 28 */ ND_NULL, - /* 29 */ ND_NULL, - /* 2a */ ND_NULL, - /* 2b */ ND_NULL, - /* 2c */ ND_NULL, - /* 2d */ ND_NULL, - /* 2e */ ND_NULL, - /* 2f */ ND_NULL, - /* 30 */ ND_NULL, - /* 31 */ ND_NULL, - /* 32 */ ND_NULL, - /* 33 */ ND_NULL, - /* 34 */ ND_NULL, - /* 35 */ ND_NULL, - /* 36 */ ND_NULL, - /* 37 */ ND_NULL, - /* 38 */ ND_NULL, - /* 39 */ ND_NULL, - /* 3a */ ND_NULL, - /* 3b */ ND_NULL, - /* 3c */ ND_NULL, - /* 3d */ ND_NULL, - /* 3e */ ND_NULL, - /* 3f */ ND_NULL, - /* 40 */ ND_NULL, - /* 41 */ ND_NULL, - /* 42 */ ND_NULL, - /* 43 */ ND_NULL, - /* 44 */ ND_NULL, - /* 45 */ ND_NULL, - /* 46 */ ND_NULL, - /* 47 */ ND_NULL, - /* 48 */ ND_NULL, - /* 49 */ ND_NULL, - /* 4a */ ND_NULL, - /* 4b */ ND_NULL, - /* 4c */ ND_NULL, - /* 4d */ ND_NULL, - /* 4e */ ND_NULL, - /* 4f */ ND_NULL, - /* 50 */ ND_NULL, - /* 51 */ ND_NULL, - /* 52 */ ND_NULL, - /* 53 */ ND_NULL, - /* 54 */ ND_NULL, - /* 55 */ ND_NULL, - /* 56 */ ND_NULL, - /* 57 */ ND_NULL, - /* 58 */ ND_NULL, - /* 59 */ ND_NULL, - /* 5a */ ND_NULL, - /* 5b */ ND_NULL, - /* 5c */ ND_NULL, - /* 5d */ ND_NULL, - /* 5e */ ND_NULL, - /* 5f */ ND_NULL, - /* 60 */ ND_NULL, - /* 61 */ ND_NULL, - /* 62 */ ND_NULL, - /* 63 */ ND_NULL, - /* 64 */ ND_NULL, - /* 65 */ ND_NULL, - /* 66 */ ND_NULL, - /* 67 */ ND_NULL, - /* 68 */ ND_NULL, - /* 69 */ ND_NULL, - /* 6a */ ND_NULL, - /* 6b */ ND_NULL, - /* 6c */ ND_NULL, - /* 6d */ ND_NULL, - /* 6e */ ND_NULL, - /* 6f */ ND_NULL, - /* 70 */ ND_NULL, - /* 71 */ ND_NULL, - /* 72 */ ND_NULL, - /* 73 */ ND_NULL, - /* 74 */ ND_NULL, - /* 75 */ ND_NULL, - /* 76 */ ND_NULL, - /* 77 */ ND_NULL, - /* 78 */ ND_NULL, - /* 79 */ ND_NULL, - /* 7a */ ND_NULL, - /* 7b */ ND_NULL, - /* 7c */ ND_NULL, - /* 7d */ ND_NULL, - /* 7e */ ND_NULL, - /* 7f */ ND_NULL, - /* 80 */ ND_NULL, - /* 81 */ ND_NULL, - /* 82 */ ND_NULL, - /* 83 */ ND_NULL, - /* 84 */ ND_NULL, - /* 85 */ (const void *)&gXopTable_root_08_85_leaf, - /* 86 */ (const void *)&gXopTable_root_08_86_leaf, - /* 87 */ (const void *)&gXopTable_root_08_87_leaf, - /* 88 */ ND_NULL, - /* 89 */ ND_NULL, - /* 8a */ ND_NULL, - /* 8b */ ND_NULL, - /* 8c */ ND_NULL, - /* 8d */ ND_NULL, - /* 8e */ (const void *)&gXopTable_root_08_8e_leaf, - /* 8f */ (const void *)&gXopTable_root_08_8f_leaf, - /* 90 */ ND_NULL, - /* 91 */ ND_NULL, - /* 92 */ ND_NULL, - /* 93 */ ND_NULL, - /* 94 */ ND_NULL, - /* 95 */ (const void *)&gXopTable_root_08_95_leaf, - /* 96 */ (const void *)&gXopTable_root_08_96_leaf, - /* 97 */ (const void *)&gXopTable_root_08_97_leaf, - /* 98 */ ND_NULL, - /* 99 */ ND_NULL, - /* 9a */ ND_NULL, - /* 9b */ ND_NULL, - /* 9c */ ND_NULL, - /* 9d */ ND_NULL, - /* 9e */ (const void *)&gXopTable_root_08_9e_leaf, - /* 9f */ (const void *)&gXopTable_root_08_9f_leaf, - /* a0 */ ND_NULL, - /* a1 */ ND_NULL, - /* a2 */ (const void *)&gXopTable_root_08_a2_w, - /* a3 */ (const void *)&gXopTable_root_08_a3_w, - /* a4 */ ND_NULL, - /* a5 */ ND_NULL, - /* a6 */ (const void *)&gXopTable_root_08_a6_leaf, - /* a7 */ ND_NULL, - /* a8 */ ND_NULL, - /* a9 */ ND_NULL, - /* aa */ ND_NULL, - /* ab */ ND_NULL, - /* ac */ ND_NULL, - /* ad */ ND_NULL, - /* ae */ ND_NULL, - /* af */ ND_NULL, - /* b0 */ ND_NULL, - /* b1 */ ND_NULL, - /* b2 */ ND_NULL, - /* b3 */ ND_NULL, - /* b4 */ ND_NULL, - /* b5 */ ND_NULL, - /* b6 */ (const void *)&gXopTable_root_08_b6_leaf, - /* b7 */ ND_NULL, - /* b8 */ ND_NULL, - /* b9 */ ND_NULL, - /* ba */ ND_NULL, - /* bb */ ND_NULL, - /* bc */ ND_NULL, - /* bd */ ND_NULL, - /* be */ ND_NULL, - /* bf */ ND_NULL, - /* c0 */ (const void *)&gXopTable_root_08_c0_leaf, - /* c1 */ (const void *)&gXopTable_root_08_c1_leaf, - /* c2 */ (const void *)&gXopTable_root_08_c2_leaf, - /* c3 */ (const void *)&gXopTable_root_08_c3_leaf, - /* c4 */ ND_NULL, - /* c5 */ ND_NULL, - /* c6 */ ND_NULL, - /* c7 */ ND_NULL, - /* c8 */ ND_NULL, - /* c9 */ ND_NULL, - /* ca */ ND_NULL, - /* cb */ ND_NULL, - /* cc */ (const void *)&gXopTable_root_08_cc_leaf, - /* cd */ (const void *)&gXopTable_root_08_cd_leaf, - /* ce */ (const void *)&gXopTable_root_08_ce_leaf, - /* cf */ (const void *)&gXopTable_root_08_cf_leaf, - /* d0 */ ND_NULL, - /* d1 */ ND_NULL, - /* d2 */ ND_NULL, - /* d3 */ ND_NULL, - /* d4 */ ND_NULL, - /* d5 */ ND_NULL, - /* d6 */ ND_NULL, - /* d7 */ ND_NULL, - /* d8 */ ND_NULL, - /* d9 */ ND_NULL, - /* da */ ND_NULL, - /* db */ ND_NULL, - /* dc */ ND_NULL, - /* dd */ ND_NULL, - /* de */ ND_NULL, - /* df */ ND_NULL, - /* e0 */ ND_NULL, - /* e1 */ ND_NULL, - /* e2 */ ND_NULL, - /* e3 */ ND_NULL, - /* e4 */ ND_NULL, - /* e5 */ ND_NULL, - /* e6 */ ND_NULL, - /* e7 */ ND_NULL, - /* e8 */ ND_NULL, - /* e9 */ ND_NULL, - /* ea */ ND_NULL, - /* eb */ ND_NULL, - /* ec */ (const void *)&gXopTable_root_08_ec_leaf, - /* ed */ (const void *)&gXopTable_root_08_ed_leaf, - /* ee */ (const void *)&gXopTable_root_08_ee_leaf, - /* ef */ (const void *)&gXopTable_root_08_ef_leaf, - /* f0 */ ND_NULL, - /* f1 */ ND_NULL, - /* f2 */ ND_NULL, - /* f3 */ ND_NULL, - /* f4 */ ND_NULL, - /* f5 */ ND_NULL, - /* f6 */ ND_NULL, - /* f7 */ ND_NULL, - /* f8 */ ND_NULL, - /* f9 */ ND_NULL, - /* fa */ ND_NULL, - /* fb */ ND_NULL, - /* fc */ ND_NULL, - /* fd */ ND_NULL, - /* fe */ ND_NULL, - /* ff */ ND_NULL, - } -}; - -const ND_TABLE_VEX_MMMMM gXopTable_root_mmmmm = -{ - ND_ILUT_VEX_MMMMM, - { - /* 00 */ ND_NULL, - /* 01 */ ND_NULL, - /* 02 */ ND_NULL, - /* 03 */ ND_NULL, - /* 04 */ ND_NULL, - /* 05 */ ND_NULL, - /* 06 */ ND_NULL, - /* 07 */ ND_NULL, - /* 08 */ (const void *)&gXopTable_root_08_opcode, - /* 09 */ (const void *)&gXopTable_root_09_opcode, - /* 0a */ (const void *)&gXopTable_root_0a_opcode, - /* 0b */ ND_NULL, - /* 0c */ ND_NULL, - /* 0d */ ND_NULL, - /* 0e */ ND_NULL, - /* 0f */ ND_NULL, - /* 10 */ ND_NULL, - /* 11 */ ND_NULL, - /* 12 */ ND_NULL, - /* 13 */ ND_NULL, - /* 14 */ ND_NULL, - /* 15 */ ND_NULL, - /* 16 */ ND_NULL, - /* 17 */ ND_NULL, - /* 18 */ ND_NULL, - /* 19 */ ND_NULL, - /* 1a */ ND_NULL, - /* 1b */ ND_NULL, - /* 1c */ ND_NULL, - /* 1d */ ND_NULL, - /* 1e */ ND_NULL, - /* 1f */ ND_NULL, - } -}; - -const PND_TABLE gXopTable = (const PND_TABLE)&gXopTable_root_mmmmm; - - -#endif - diff --git a/bddisasm_test/README.md b/bddisasm_test/README.md index 32841d4..02fbac0 100644 --- a/bddisasm_test/README.md +++ b/bddisasm_test/README.md @@ -1,7 +1,7 @@ # Disassembler Tests These tests are used to validate bddisasm. Each test consists of up to three files: -* The binary test file. The name format for this type of file is `name_16|32|64`. No extension must be provided; 16/32/64 indicates disassembly mode +* The binary test file. The name format for this type of file is `name_16|32|64.test`. 16/32/64 indicates disassembly mode * The output result file. Must be named the same as the binary test file, but with the extension .result * Optional assembly file, used to generate the binary test file diff --git a/bddisasm_test/x86/apx/apx1_64.result b/bddisasm_test/x86/apx/apx1_64.result new file mode 100644 index 0000000..72aef0c --- /dev/null +++ b/bddisasm_test/x86/apx/apx1_64.result @@ -0,0 +1,102913 @@ +0000000000000000 626c7808101e ADC byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000006 626c780810de ADC r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000000C 626cf808101e ADC byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000012 626cf80810de ADC r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000018 626c7808111e ADC dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000001E 626c780811de ADC r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000024 626cf808111e ADC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000002A 626cf80811de ADC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000030 626c7908111e ADC word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000036 626c790811de ADC r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000003C 626cf908111e ADC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000042 626cf90811de ADC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000048 626c7808121e ADC r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000004E 626c780812de ADC r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000054 626cf808121e ADC r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000005A 626cf80812de ADC r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000060 626c7808131e ADC r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000066 626c780813de ADC r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000006C 626cf808131e ADC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000072 626cf80813de ADC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000078 626c7908131e ADC r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000007E 626c790813de ADC r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000084 626cf908131e ADC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000008A 626cf90813de ADC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000090 626c78088016bd ADC byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000097 626c780880d6bd ADC r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000009E 626cf8088016bd ADC byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000A5 626cf80880d6bd ADC r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000AC 626c78088116bdbdbdbd ADC dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000B6 626c780881d6bdbdbdbd ADC r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000C0 626cf8088116bdbdbdbd ADC qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000CA 626cf80881d6bdbdbdbd ADC r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000D4 626c79088116bdbd ADC word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000DC 626c790881d6bdbd ADC r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000000E4 626cf9088116bdbdbdbd ADC qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000EE 626cf90881d6bdbdbdbd ADC r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000000F8 626c78088316bd ADC dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000000FF 626c780883d6bd ADC r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000106 626cf8088316bd ADC qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000010D 626cf80883d6bd ADC r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000114 626c79088316bd ADC word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000011B 626c790883d6bd ADC r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000122 626cf9088316bd ADC qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000129 626cf90883d6bd ADC r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000130 626c7818101e ADC al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000136 626c781810de ADC al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000013C 626cf818101e ADC al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000142 626cf81810de ADC al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000148 626c7818111e ADC eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000014E 626c781811de ADC eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000154 626cf818111e ADC rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000015A 626cf81811de ADC rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000160 626c7918111e ADC ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000166 626c791811de ADC ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000016C 626cf918111e ADC rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000172 626cf91811de ADC rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000178 626c7818121e ADC al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000017E 626c781812de ADC al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000184 626cf818121e ADC al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000018A 626cf81812de ADC al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000190 626c7818131e ADC eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000196 626c781813de ADC eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000019C 626cf818131e ADC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001A2 626cf81813de ADC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001A8 626c7918131e ADC ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001AE 626c791813de ADC ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000001B4 626cf918131e ADC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001BA 626cf91813de ADC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001C0 626c78188016bd ADC al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001C7 626c781880d6bd ADC al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001CE 626cf8188016bd ADC al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001D5 626cf81880d6bd ADC al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001DC 626c78188116bdbdbdbd ADC eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001E6 626c781881d6bdbdbdbd ADC eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000001F0 626cf8188116bdbdbdbd ADC rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000001FA 626cf81881d6bdbdbdbd ADC rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000204 626c79188116bdbd ADC ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000020C 626c791881d6bdbd ADC ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000214 626cf9188116bdbdbdbd ADC rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000021E 626cf91881d6bdbdbdbd ADC rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000228 626c78188316bd ADC eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000022F 626c781883d6bd ADC eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000236 626cf8188316bd ADC rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000023D 626cf81883d6bd ADC rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000244 626c79188316bd ADC ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000024B 626c791883d6bd ADC ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000252 626cf9188316bd ADC rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000259 626cf91883d6bd ADC rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000260 626c7908661e ADCX r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000266 626c790866de ADCX r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000026C 626cf908661e ADCX r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000272 626cf90866de ADCX r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000278 626c7918661e ADCX eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000027E 626c791866de ADCX eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000284 626cf918661e ADCX rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000028A 626cf91866de ADCX rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000290 626c7808001e ADD byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000296 626c780800de ADD r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000029C 626cf808001e ADD byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002A2 626cf80800de ADD r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002A8 626c7808011e ADD dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002AE 626c780801de ADD r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002B4 626cf808011e ADD qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002BA 626cf80801de ADD r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002C0 626c7908011e ADD word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000002C6 626c790801de ADD r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000002CC 626cf908011e ADD qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002D2 626cf90801de ADD r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002D8 626c7808021e ADD r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002DE 626c780802de ADD r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002E4 626cf808021e ADD r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002EA 626cf80802de ADD r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000002F0 626c7808031e ADD r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002F6 626c780803de ADD r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000002FC 626cf808031e ADD r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000302 626cf80803de ADD r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000308 626c7908031e ADD r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000030E 626c790803de ADD r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000314 626cf908031e ADD r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000031A 626cf90803de ADD r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000320 626c78088006bd ADD byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000327 626c780880c6bd ADD r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000032E 626cf8088006bd ADD byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000335 626cf80880c6bd ADD r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000033C 626c78088106bdbdbdbd ADD dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000346 626c780881c6bdbdbdbd ADD r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000350 626cf8088106bdbdbdbd ADD qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000035A 626cf80881c6bdbdbdbd ADD r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000364 626c79088106bdbd ADD word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000036C 626c790881c6bdbd ADD r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000374 626cf9088106bdbdbdbd ADD qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000037E 626cf90881c6bdbdbdbd ADD r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000388 626c78088306bd ADD dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000038F 626c780883c6bd ADD r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000396 626cf8088306bd ADD qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000039D 626cf80883c6bd ADD r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003A4 626c79088306bd ADD word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003AB 626c790883c6bd ADD r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000003B2 626cf9088306bd ADD qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003B9 626cf90883c6bd ADD r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000003C0 626c780c001e ADD{NF} byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000003C6 626c780c00de ADD{NF} r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000003CC 626cf80c001e ADD{NF} byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000003D2 626cf80c00de ADD{NF} r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000003D8 626c780c011e ADD{NF} dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +00000000000003DE 626c780c01de ADD{NF} r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +00000000000003E4 626cf80c011e ADD{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000003EA 626cf80c01de ADD{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000003F0 626c790c011e ADD{NF} word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +00000000000003F6 626c790c01de ADD{NF} r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +00000000000003FC 626cf90c011e ADD{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000402 626cf90c01de ADD{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000408 626c780c021e ADD{NF} r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000040E 626c780c02de ADD{NF} r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000414 626cf80c021e ADD{NF} r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000041A 626cf80c02de ADD{NF} r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000420 626c780c031e ADD{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000426 626c780c03de ADD{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +000000000000042C 626cf80c031e ADD{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000432 626cf80c03de ADD{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000438 626c790c031e ADD{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +000000000000043E 626c790c03de ADD{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000000444 626cf90c031e ADD{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000044A 626cf90c03de ADD{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000450 626c780c8006bd ADD{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000457 626c780c80c6bd ADD{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000045E 626cf80c8006bd ADD{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000465 626cf80c80c6bd ADD{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000046C 626c780c8106bdbdbdbd ADD{NF} dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000476 626c780c81c6bdbdbdbd ADD{NF} r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000480 626cf80c8106bdbdbdbd ADD{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000048A 626cf80c81c6bdbdbdbd ADD{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000494 626c790c8106bdbd ADD{NF} word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +000000000000049C 626c790c81c6bdbd ADD{NF} r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +00000000000004A4 626cf90c8106bdbdbdbd ADD{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000004AE 626cf90c81c6bdbdbdbd ADD{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000004B8 626c780c8306bd ADD{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004BF 626c780c83c6bd ADD{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004C6 626cf80c8306bd ADD{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004CD 626cf80c83c6bd ADD{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004D4 626c790c8306bd ADD{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004DB 626c790c83c6bd ADD{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004E2 626cf90c8306bd ADD{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004E9 626cf90c83c6bd ADD{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000004F0 626c7818001e ADD al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004F6 626c781800de ADD al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000004FC 626cf818001e ADD al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000502 626cf81800de ADD al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000508 626c7818011e ADD eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000050E 626c781801de ADD eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000514 626cf818011e ADD rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000051A 626cf81801de ADD rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000520 626c7918011e ADD ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000526 626c791801de ADD ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000052C 626cf918011e ADD rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000532 626cf91801de ADD rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000538 626c7818021e ADD al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000053E 626c781802de ADD al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000544 626cf818021e ADD al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000054A 626cf81802de ADD al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000550 626c7818031e ADD eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000556 626c781803de ADD eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000055C 626cf818031e ADD rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000562 626cf81803de ADD rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000568 626c7918031e ADD ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000056E 626c791803de ADD ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000574 626cf918031e ADD rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000057A 626cf91803de ADD rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000580 626c78188006bd ADD al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000587 626c781880c6bd ADD al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000058E 626cf8188006bd ADD al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000595 626cf81880c6bd ADD al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000059C 626c78188106bdbdbdbd ADD eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005A6 626c781881c6bdbdbdbd ADD eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005B0 626cf8188106bdbdbdbd ADD rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005BA 626cf81881c6bdbdbdbd ADD rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005C4 626c79188106bdbd ADD ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005CC 626c791881c6bdbd ADD ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000005D4 626cf9188106bdbdbdbd ADD rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005DE 626cf91881c6bdbdbdbd ADD rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005E8 626c78188306bd ADD eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005EF 626c781883c6bd ADD eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000005F6 626cf8188306bd ADD rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000005FD 626cf81883c6bd ADD rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000604 626c79188306bd ADD ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000060B 626c791883c6bd ADD ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000612 626cf9188306bd ADD rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000619 626cf91883c6bd ADD rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000620 626c781c001e ADD{NF} al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000626 626c781c00de ADD{NF} al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +000000000000062C 626cf81c001e ADD{NF} al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000632 626cf81c00de ADD{NF} al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000638 626c781c011e ADD{NF} eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000063E 626c781c01de ADD{NF} eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000644 626cf81c011e ADD{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000064A 626cf81c01de ADD{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000650 626c791c011e ADD{NF} ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000000656 626c791c01de ADD{NF} ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +000000000000065C 626cf91c011e ADD{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000662 626cf91c01de ADD{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000668 626c781c021e ADD{NF} al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000066E 626c781c02de ADD{NF} al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000674 626cf81c021e ADD{NF} al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000067A 626cf81c02de ADD{NF} al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000680 626c781c031e ADD{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000686 626c781c03de ADD{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +000000000000068C 626cf81c031e ADD{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000692 626cf81c03de ADD{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000698 626c791c031e ADD{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +000000000000069E 626c791c03de ADD{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +00000000000006A4 626cf91c031e ADD{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000006AA 626cf91c03de ADD{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000006B0 626c781c8006bd ADD{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006B7 626c781c80c6bd ADD{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006BE 626cf81c8006bd ADD{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006C5 626cf81c80c6bd ADD{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000006CC 626c781c8106bdbdbdbd ADD{NF} eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000006D6 626c781c81c6bdbdbdbd ADD{NF} eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000006E0 626cf81c8106bdbdbdbd ADD{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000006EA 626cf81c81c6bdbdbdbd ADD{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000006F4 626c791c8106bdbd ADD{NF} ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +00000000000006FC 626c791c81c6bdbd ADD{NF} ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000000704 626cf91c8106bdbdbdbd ADD{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000070E 626cf91c81c6bdbdbdbd ADD{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000718 626c781c8306bd ADD{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000071F 626c781c83c6bd ADD{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000726 626cf81c8306bd ADD{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000072D 626cf81c83c6bd ADD{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000734 626c791c8306bd ADD{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000073B 626c791c83c6bd ADD{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000742 626cf91c8306bd ADD{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000749 626cf91c83c6bd ADD{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000750 626c7a08661e ADOX r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000756 626c7a0866de ADOX r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000075C 626cfa08661e ADOX r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000762 626cfa0866de ADOX r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000768 626c7a18661e ADOX eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000076E 626c7a1866de ADOX eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000774 626cfa18661e ADOX rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000077A 626cfa1866de ADOX rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000780 626c7a08dd1e AESDEC128KL xmm27, m384 ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000786 626cfa08dd1e AESDEC128KL xmm27, m384 ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000078C 626c7a08df1e AESDEC256KL xmm27, zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000792 626cfa08df1e AESDEC256KL xmm27, zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000798 626c7a08d80e AESDECWIDE128KL m384 ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000079E 626cfa08d80e AESDECWIDE128KL m384 ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007A4 626c7a08d81e AESDECWIDE256KL zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007AA 626cfa08d81e AESDECWIDE256KL zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007B0 626c7a08dc1e AESENC128KL xmm27, m384 ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007B6 626cfa08dc1e AESENC128KL xmm27, m384 ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007BC 626c7a08de1e AESENC256KL xmm27, zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007C2 626cfa08de1e AESENC256KL xmm27, zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007C8 626c7a08d806 AESENCWIDE128KL m384 ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007CE 626cfa08d806 AESENCWIDE128KL m384 ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 48, RawSize: 48, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007D4 626c7a08d816 AESENCWIDE256KL zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007DA 626cfa08d816 AESENCWIDE256KL zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: WIDE_KL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 8 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007E0 626c7808201e AND byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007E6 626c780820de AND r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007EC 626cf808201e AND byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007F2 626cf80820de AND r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000007F8 626c7808211e AND dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000007FE 626c780821de AND r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000804 626cf808211e AND qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000080A 626cf80821de AND r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000810 626c7908211e AND word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000816 626c790821de AND r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000081C 626cf908211e AND qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000822 626cf90821de AND r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000828 626c7808221e AND r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000082E 626c780822de AND r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000834 626cf808221e AND r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000083A 626cf80822de AND r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000840 626c7808231e AND r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000846 626c780823de AND r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000084C 626cf808231e AND r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000852 626cf80823de AND r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000858 626c7908231e AND r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000085E 626c790823de AND r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000864 626cf908231e AND r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000086A 626cf90823de AND r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000870 626c78088026bd AND byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000877 626c780880e6bd AND r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000087E 626cf8088026bd AND byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000885 626cf80880e6bd AND r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000088C 626c78088126bdbdbdbd AND dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000896 626c780881e6bdbdbdbd AND r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000008A0 626cf8088126bdbdbdbd AND qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008AA 626cf80881e6bdbdbdbd AND r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008B4 626c79088126bdbd AND word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000008BC 626c790881e6bdbd AND r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000008C4 626cf9088126bdbdbdbd AND qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008CE 626cf90881e6bdbdbdbd AND r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008D8 626c78088326bd AND dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000008DF 626c780883e6bd AND r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000008E6 626cf8088326bd AND qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008ED 626cf80883e6bd AND r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000008F4 626c79088326bd AND word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000008FB 626c790883e6bd AND r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000902 626cf9088326bd AND qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000909 626cf90883e6bd AND r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000910 626c780c201e AND{NF} byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000916 626c780c20de AND{NF} r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +000000000000091C 626cf80c201e AND{NF} byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000922 626cf80c20de AND{NF} r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000928 626c780c211e AND{NF} dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000092E 626c780c21de AND{NF} r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000934 626cf80c211e AND{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000093A 626cf80c21de AND{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000940 626c790c211e AND{NF} word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000000946 626c790c21de AND{NF} r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +000000000000094C 626cf90c211e AND{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000952 626cf90c21de AND{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000958 626c780c221e AND{NF} r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000095E 626c780c22de AND{NF} r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000964 626cf80c221e AND{NF} r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000096A 626cf80c22de AND{NF} r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000970 626c780c231e AND{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000976 626c780c23de AND{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +000000000000097C 626cf80c231e AND{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000982 626cf80c23de AND{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000988 626c790c231e AND{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +000000000000098E 626c790c23de AND{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000000994 626cf90c231e AND{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000099A 626cf90c23de AND{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000009A0 626c780c8026bd AND{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009A7 626c780c80e6bd AND{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009AE 626cf80c8026bd AND{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009B5 626cf80c80e6bd AND{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000009BC 626c780c8126bdbdbdbd AND{NF} dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000009C6 626c780c81e6bdbdbdbd AND{NF} r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000009D0 626cf80c8126bdbdbdbd AND{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000009DA 626cf80c81e6bdbdbdbd AND{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000009E4 626c790c8126bdbd AND{NF} word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +00000000000009EC 626c790c81e6bdbd AND{NF} r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +00000000000009F4 626cf90c8126bdbdbdbd AND{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000009FE 626cf90c81e6bdbdbdbd AND{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000A08 626c780c8326bd AND{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A0F 626c780c83e6bd AND{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A16 626cf80c8326bd AND{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A1D 626cf80c83e6bd AND{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A24 626c790c8326bd AND{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A2B 626c790c83e6bd AND{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A32 626cf90c8326bd AND{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A39 626cf90c83e6bd AND{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000A40 626c7818201e AND al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A46 626c781820de AND al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A4C 626cf818201e AND al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A52 626cf81820de AND al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A58 626c7818211e AND eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A5E 626c781821de AND eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A64 626cf818211e AND rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A6A 626cf81821de AND rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A70 626c7918211e AND ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000A76 626c791821de AND ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000A7C 626cf918211e AND rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A82 626cf91821de AND rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A88 626c7818221e AND al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A8E 626c781822de AND al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000A94 626cf818221e AND al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000A9A 626cf81822de AND al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AA0 626c7818231e AND eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000AA6 626c781823de AND eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000AAC 626cf818231e AND rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AB2 626cf81823de AND rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AB8 626c7918231e AND ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000ABE 626c791823de AND ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000AC4 626cf918231e AND rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000ACA 626cf91823de AND rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AD0 626c78188026bd AND al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000AD7 626c781880e6bd AND al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000ADE 626cf8188026bd AND al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AE5 626cf81880e6bd AND al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000AEC 626c78188126bdbdbdbd AND eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000AF6 626c781881e6bdbdbdbd AND eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000B00 626cf8188126bdbdbdbd AND rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B0A 626cf81881e6bdbdbdbd AND rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B14 626c79188126bdbd AND ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000B1C 626c791881e6bdbd AND ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000B24 626cf9188126bdbdbdbd AND rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B2E 626cf91881e6bdbdbdbd AND rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B38 626c78188326bd AND eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000B3F 626c781883e6bd AND eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000B46 626cf8188326bd AND rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B4D 626cf81883e6bd AND rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B54 626c79188326bd AND ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000B5B 626c791883e6bd AND ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000B62 626cf9188326bd AND rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B69 626cf91883e6bd AND rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000B70 626c781c201e AND{NF} al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000B76 626c781c20de AND{NF} al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000B7C 626cf81c201e AND{NF} al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000B82 626cf81c20de AND{NF} al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000000B88 626c781c211e AND{NF} eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000B8E 626c781c21de AND{NF} eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000B94 626cf81c211e AND{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000B9A 626cf81c21de AND{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000BA0 626c791c211e AND{NF} ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000000BA6 626c791c21de AND{NF} ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000000BAC 626cf91c211e AND{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000BB2 626cf91c21de AND{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000BB8 626c781c221e AND{NF} al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BBE 626c781c22de AND{NF} al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000BC4 626cf81c221e AND{NF} al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BCA 626cf81c22de AND{NF} al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000000BD0 626c781c231e AND{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BD6 626c781c23de AND{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000000BDC 626cf81c231e AND{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BE2 626cf81c23de AND{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000BE8 626c791c231e AND{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BEE 626c791c23de AND{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000000BF4 626cf91c231e AND{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000BFA 626cf91c23de AND{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000C00 626c781c8026bd AND{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C07 626c781c80e6bd AND{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C0E 626cf81c8026bd AND{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C15 626cf81c80e6bd AND{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C1C 626c781c8126bdbdbdbd AND{NF} eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C26 626c781c81e6bdbdbdbd AND{NF} eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C30 626cf81c8126bdbdbdbd AND{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C3A 626cf81c81e6bdbdbdbd AND{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C44 626c791c8126bdbd AND{NF} ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000000C4C 626c791c81e6bdbd AND{NF} ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000000C54 626cf91c8126bdbdbdbd AND{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C5E 626cf91c81e6bdbdbdbd AND{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000000C68 626c781c8326bd AND{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C6F 626c781c83e6bd AND{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C76 626cf81c8326bd AND{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C7D 626cf81c83e6bd AND{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C84 626c791c8326bd AND{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C8B 626c791c83e6bd AND{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C92 626cf91c8326bd AND{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000C99 626cf91c83e6bd AND{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000000CA0 62fa7808f21e ANDN ebx, eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CA6 62fa7808f2de ANDN ebx, eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CAC 62faf808f21e ANDN rbx, rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000CB2 62faf808f2de ANDN rbx, rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000CB8 62fa780cf21e ANDN{NF} ebx, eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000CBE 62fa780cf2de ANDN{NF} ebx, eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000000CC4 62faf80cf21e ANDN{NF} rbx, rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000CCA 62faf80cf2de ANDN{NF} rbx, rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000CD0 62fa7808f71e BEXTR ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CD6 62fa7808f7de BEXTR ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CDC 62faf808f71e BEXTR rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000CE2 62faf808f7de BEXTR rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: 0, PF: u, AF: u, ZF: m, SF: u, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000CE8 62fa780cf71e BEXTR{NF} ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CEE 62fa780cf7de BEXTR{NF} ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000CF4 62faf80cf71e BEXTR{NF} rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000CFA 62faf80cf7de BEXTR{NF} rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D00 62fa7808f31e BLSI eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D06 62fa7808f3de BLSI eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D0C 62faf808f31e BLSI rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D12 62faf808f3de BLSI rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D18 62fa780cf31e BLSI{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D1E 62fa780cf3de BLSI{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000000D24 62faf80cf31e BLSI{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D2A 62faf80cf3de BLSI{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000D30 62fa7808f316 BLSMSK eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D36 62fa7808f3d6 BLSMSK eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D3C 62faf808f316 BLSMSK rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D42 62faf808f3d6 BLSMSK rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: 0, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D48 62fa780cf316 BLSMSK{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D4E 62fa780cf3d6 BLSMSK{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000000D54 62faf80cf316 BLSMSK{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D5A 62faf80cf3d6 BLSMSK{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000D60 62fa7808f30e BLSR eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D66 62fa7808f3ce BLSR eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D6C 62faf808f30e BLSR rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D72 62faf808f3ce BLSR rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000D78 62fa780cf30e BLSR{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D7E 62fa780cf3ce BLSR{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000000D84 62faf80cf30e BLSR{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000000D8A 62faf80cf3ce BLSR{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000D90 62fa7808f51e BZHI ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D96 62fa7808f5de BZHI ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000D9C 62faf808f51e BZHI rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DA2 62faf808f5de BZHI rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DA8 62fa780cf51e BZHI{NF} ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DAE 62fa780cf5de BZHI{NF} ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DB4 62faf80cf51e BZHI{NF} rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DBA 62faf80cf5de BZHI{NF} rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DC0 626c7806381e CCMPBE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DC6 626c780638de CCMPBE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DCC 626cf806381e CCMPBE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DD2 626cf80638de CCMPBE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DD8 626c7806391e CCMPBE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DDE 626c780639de CCMPBE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000DE4 626cf806391e CCMPBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DEA 626cf80639de CCMPBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000DF0 626c7906391e CCMPBE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000DF6 626c790639de CCMPBE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000DFC 626cf906391e CCMPBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E02 626cf90639de CCMPBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E08 626c78063a1e CCMPBE r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E0E 626c78063ade CCMPBE r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E14 626cf8063a1e CCMPBE r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E1A 626cf8063ade CCMPBE r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E20 626c78063b1e CCMPBE r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E26 626c78063bde CCMPBE r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E2C 626cf8063b1e CCMPBE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E32 626cf8063bde CCMPBE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E38 626c79063b1e CCMPBE r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000E3E 626c79063bde CCMPBE r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000E44 626cf9063b1e CCMPBE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E4A 626cf9063bde CCMPBE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E50 626c7806803ebd CCMPBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E57 626c780680febd CCMPBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E5E 626cf806803ebd CCMPBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E65 626cf80680febd CCMPBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E6C 626c7806813ebdbdbdbd CCMPBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E76 626c780681febdbdbdbd CCMPBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000E80 626cf806813ebdbdbdbd CCMPBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E8A 626cf80681febdbdbdbd CCMPBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000E94 626c7906813ebdbd CCMPBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000E9C 626c790681febdbd CCMPBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000EA4 626cf906813ebdbdbdbd CCMPBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000EAE 626cf90681febdbdbdbd CCMPBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000EB8 626c7806833ebd CCMPBE dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000EBF 626c780683febd CCMPBE r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000EC6 626cf806833ebd CCMPBE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000ECD 626cf80683febd CCMPBE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000ED4 626c7906833ebd CCMPBE word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000EDB 626c790683febd CCMPBE r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000EE2 626cf906833ebd CCMPBE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000EE9 626cf90683febd CCMPBE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000EF0 626c7802381e CCMPC byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000EF6 626c780238de CCMPC r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000EFC 626cf802381e CCMPC byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F02 626cf80238de CCMPC r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F08 626c7802391e CCMPC dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F0E 626c780239de CCMPC r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F14 626cf802391e CCMPC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F1A 626cf80239de CCMPC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F20 626c7902391e CCMPC word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000F26 626c790239de CCMPC r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000F2C 626cf902391e CCMPC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F32 626cf90239de CCMPC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F38 626c78023a1e CCMPC r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F3E 626c78023ade CCMPC r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F44 626cf8023a1e CCMPC r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F4A 626cf8023ade CCMPC r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F50 626c78023b1e CCMPC r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F56 626c78023bde CCMPC r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F5C 626cf8023b1e CCMPC r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F62 626cf8023bde CCMPC r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F68 626c79023b1e CCMPC r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000F6E 626c79023bde CCMPC r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000F74 626cf9023b1e CCMPC r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F7A 626cf9023bde CCMPC r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F80 626c7802803ebd CCMPC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F87 626c780280febd CCMPC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000F8E 626cf802803ebd CCMPC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F95 626cf80280febd CCMPC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000F9C 626c7802813ebdbdbdbd CCMPC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000FA6 626c780281febdbdbdbd CCMPC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000FB0 626cf802813ebdbdbdbd CCMPC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000FBA 626cf80281febdbdbdbd CCMPC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000FC4 626c7902813ebdbd CCMPC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000FCC 626c790281febdbd CCMPC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000000FD4 626cf902813ebdbdbdbd CCMPC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000FDE 626cf90281febdbdbdbd CCMPC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000FE8 626c7802833ebd CCMPC dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000FEF 626c780283febd CCMPC r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000000FF6 626cf802833ebd CCMPC qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000000FFD 626cf80283febd CCMPC r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001004 626c7902833ebd CCMPC word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000100B 626c790283febd CCMPC r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001012 626cf902833ebd CCMPC qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001019 626cf90283febd CCMPC r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001020 626c780b381e CCMPF byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001026 626c780b38de CCMPF r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000102C 626cf80b381e CCMPF byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001032 626cf80b38de CCMPF r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001038 626c780b391e CCMPF dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000103E 626c780b39de CCMPF r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001044 626cf80b391e CCMPF qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000104A 626cf80b39de CCMPF r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001050 626c790b391e CCMPF word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001056 626c790b39de CCMPF r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000105C 626cf90b391e CCMPF qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001062 626cf90b39de CCMPF r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001068 626c780b3a1e CCMPF r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000106E 626c780b3ade CCMPF r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001074 626cf80b3a1e CCMPF r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000107A 626cf80b3ade CCMPF r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001080 626c780b3b1e CCMPF r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001086 626c780b3bde CCMPF r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000108C 626cf80b3b1e CCMPF r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001092 626cf80b3bde CCMPF r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001098 626c790b3b1e CCMPF r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000109E 626c790b3bde CCMPF r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000010A4 626cf90b3b1e CCMPF r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010AA 626cf90b3bde CCMPF r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010B0 626c780b803ebd CCMPF byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000010B7 626c780b80febd CCMPF r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000010BE 626cf80b803ebd CCMPF byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010C5 626cf80b80febd CCMPF r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010CC 626c780b813ebdbdbdbd CCMPF dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000010D6 626c780b81febdbdbdbd CCMPF r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000010E0 626cf80b813ebdbdbdbd CCMPF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010EA 626cf80b81febdbdbdbd CCMPF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000010F4 626c790b813ebdbd CCMPF word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000010FC 626c790b81febdbd CCMPF r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001104 626cf90b813ebdbdbdbd CCMPF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000110E 626cf90b81febdbdbdbd CCMPF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001118 626c780b833ebd CCMPF dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000111F 626c780b83febd CCMPF r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001126 626cf80b833ebd CCMPF qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000112D 626cf80b83febd CCMPF r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001134 626c790b833ebd CCMPF word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000113B 626c790b83febd CCMPF r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001142 626cf90b833ebd CCMPF qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001149 626cf90b83febd CCMPF r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001150 626c780c381e CCMPL byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001156 626c780c38de CCMPL r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000115C 626cf80c381e CCMPL byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001162 626cf80c38de CCMPL r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001168 626c780c391e CCMPL dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000116E 626c780c39de CCMPL r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001174 626cf80c391e CCMPL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000117A 626cf80c39de CCMPL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001180 626c790c391e CCMPL word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001186 626c790c39de CCMPL r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000118C 626cf90c391e CCMPL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001192 626cf90c39de CCMPL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001198 626c780c3a1e CCMPL r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000119E 626c780c3ade CCMPL r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000011A4 626cf80c3a1e CCMPL r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011AA 626cf80c3ade CCMPL r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011B0 626c780c3b1e CCMPL r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000011B6 626c780c3bde CCMPL r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000011BC 626cf80c3b1e CCMPL r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011C2 626cf80c3bde CCMPL r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011C8 626c790c3b1e CCMPL r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000011CE 626c790c3bde CCMPL r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000011D4 626cf90c3b1e CCMPL r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011DA 626cf90c3bde CCMPL r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011E0 626c780c803ebd CCMPL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000011E7 626c780c80febd CCMPL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000011EE 626cf80c803ebd CCMPL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011F5 626cf80c80febd CCMPL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000011FC 626c780c813ebdbdbdbd CCMPL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001206 626c780c81febdbdbdbd CCMPL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001210 626cf80c813ebdbdbdbd CCMPL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000121A 626cf80c81febdbdbdbd CCMPL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001224 626c790c813ebdbd CCMPL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000122C 626c790c81febdbd CCMPL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001234 626cf90c813ebdbdbdbd CCMPL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000123E 626cf90c81febdbdbdbd CCMPL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001248 626c780c833ebd CCMPL dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000124F 626c780c83febd CCMPL r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001256 626cf80c833ebd CCMPL qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000125D 626cf80c83febd CCMPL r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001264 626c790c833ebd CCMPL word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000126B 626c790c83febd CCMPL r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001272 626cf90c833ebd CCMPL qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001279 626cf90c83febd CCMPL r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001280 626c780e381e CCMPLE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001286 626c780e38de CCMPLE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000128C 626cf80e381e CCMPLE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001292 626cf80e38de CCMPLE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001298 626c780e391e CCMPLE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000129E 626c780e39de CCMPLE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000012A4 626cf80e391e CCMPLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012AA 626cf80e39de CCMPLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012B0 626c790e391e CCMPLE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000012B6 626c790e39de CCMPLE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000012BC 626cf90e391e CCMPLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012C2 626cf90e39de CCMPLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012C8 626c780e3a1e CCMPLE r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000012CE 626c780e3ade CCMPLE r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000012D4 626cf80e3a1e CCMPLE r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012DA 626cf80e3ade CCMPLE r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012E0 626c780e3b1e CCMPLE r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000012E6 626c780e3bde CCMPLE r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000012EC 626cf80e3b1e CCMPLE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012F2 626cf80e3bde CCMPLE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000012F8 626c790e3b1e CCMPLE r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000012FE 626c790e3bde CCMPLE r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001304 626cf90e3b1e CCMPLE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000130A 626cf90e3bde CCMPLE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001310 626c780e803ebd CCMPLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001317 626c780e80febd CCMPLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000131E 626cf80e803ebd CCMPLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001325 626cf80e80febd CCMPLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000132C 626c780e813ebdbdbdbd CCMPLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001336 626c780e81febdbdbdbd CCMPLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001340 626cf80e813ebdbdbdbd CCMPLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000134A 626cf80e81febdbdbdbd CCMPLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001354 626c790e813ebdbd CCMPLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000135C 626c790e81febdbd CCMPLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001364 626cf90e813ebdbdbdbd CCMPLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000136E 626cf90e81febdbdbdbd CCMPLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001378 626c780e833ebd CCMPLE dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000137F 626c780e83febd CCMPLE r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001386 626cf80e833ebd CCMPLE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000138D 626cf80e83febd CCMPLE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001394 626c790e833ebd CCMPLE word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000139B 626c790e83febd CCMPLE r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000013A2 626cf90e833ebd CCMPLE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013A9 626cf90e83febd CCMPLE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013B0 626c7807381e CCMPNBE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000013B6 626c780738de CCMPNBE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000013BC 626cf807381e CCMPNBE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013C2 626cf80738de CCMPNBE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013C8 626c7807391e CCMPNBE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000013CE 626c780739de CCMPNBE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000013D4 626cf807391e CCMPNBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013DA 626cf80739de CCMPNBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013E0 626c7907391e CCMPNBE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000013E6 626c790739de CCMPNBE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000013EC 626cf907391e CCMPNBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013F2 626cf90739de CCMPNBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000013F8 626c78073a1e CCMPNBE r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000013FE 626c78073ade CCMPNBE r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001404 626cf8073a1e CCMPNBE r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000140A 626cf8073ade CCMPNBE r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001410 626c78073b1e CCMPNBE r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001416 626c78073bde CCMPNBE r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000141C 626cf8073b1e CCMPNBE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001422 626cf8073bde CCMPNBE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001428 626c79073b1e CCMPNBE r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000142E 626c79073bde CCMPNBE r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001434 626cf9073b1e CCMPNBE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000143A 626cf9073bde CCMPNBE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001440 626c7807803ebd CCMPNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001447 626c780780febd CCMPNBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000144E 626cf807803ebd CCMPNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001455 626cf80780febd CCMPNBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000145C 626c7807813ebdbdbdbd CCMPNBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001466 626c780781febdbdbdbd CCMPNBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001470 626cf807813ebdbdbdbd CCMPNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000147A 626cf80781febdbdbdbd CCMPNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001484 626c7907813ebdbd CCMPNBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000148C 626c790781febdbd CCMPNBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001494 626cf907813ebdbdbdbd CCMPNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000149E 626cf90781febdbdbdbd CCMPNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014A8 626c7807833ebd CCMPNBE dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000014AF 626c780783febd CCMPNBE r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000014B6 626cf807833ebd CCMPNBE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014BD 626cf80783febd CCMPNBE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014C4 626c7907833ebd CCMPNBE word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000014CB 626c790783febd CCMPNBE r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000014D2 626cf907833ebd CCMPNBE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014D9 626cf90783febd CCMPNBE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014E0 626c7803381e CCMPNC byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000014E6 626c780338de CCMPNC r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000014EC 626cf803381e CCMPNC byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014F2 626cf80338de CCMPNC r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000014F8 626c7803391e CCMPNC dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000014FE 626c780339de CCMPNC r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001504 626cf803391e CCMPNC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000150A 626cf80339de CCMPNC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001510 626c7903391e CCMPNC word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001516 626c790339de CCMPNC r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000151C 626cf903391e CCMPNC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001522 626cf90339de CCMPNC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001528 626c78033a1e CCMPNC r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000152E 626c78033ade CCMPNC r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001534 626cf8033a1e CCMPNC r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000153A 626cf8033ade CCMPNC r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001540 626c78033b1e CCMPNC r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001546 626c78033bde CCMPNC r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000154C 626cf8033b1e CCMPNC r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001552 626cf8033bde CCMPNC r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001558 626c79033b1e CCMPNC r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000155E 626c79033bde CCMPNC r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001564 626cf9033b1e CCMPNC r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000156A 626cf9033bde CCMPNC r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001570 626c7803803ebd CCMPNC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001577 626c780380febd CCMPNC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000157E 626cf803803ebd CCMPNC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001585 626cf80380febd CCMPNC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000158C 626c7803813ebdbdbdbd CCMPNC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001596 626c780381febdbdbdbd CCMPNC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000015A0 626cf803813ebdbdbdbd CCMPNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015AA 626cf80381febdbdbdbd CCMPNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015B4 626c7903813ebdbd CCMPNC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000015BC 626c790381febdbd CCMPNC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000015C4 626cf903813ebdbdbdbd CCMPNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015CE 626cf90381febdbdbdbd CCMPNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015D8 626c7803833ebd CCMPNC dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000015DF 626c780383febd CCMPNC r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000015E6 626cf803833ebd CCMPNC qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015ED 626cf80383febd CCMPNC r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000015F4 626c7903833ebd CCMPNC word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000015FB 626c790383febd CCMPNC r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001602 626cf903833ebd CCMPNC qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001609 626cf90383febd CCMPNC r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001610 626c780d381e CCMPNL byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001616 626c780d38de CCMPNL r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000161C 626cf80d381e CCMPNL byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001622 626cf80d38de CCMPNL r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001628 626c780d391e CCMPNL dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000162E 626c780d39de CCMPNL r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001634 626cf80d391e CCMPNL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000163A 626cf80d39de CCMPNL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001640 626c790d391e CCMPNL word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001646 626c790d39de CCMPNL r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000164C 626cf90d391e CCMPNL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001652 626cf90d39de CCMPNL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001658 626c780d3a1e CCMPNL r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000165E 626c780d3ade CCMPNL r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001664 626cf80d3a1e CCMPNL r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000166A 626cf80d3ade CCMPNL r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001670 626c780d3b1e CCMPNL r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001676 626c780d3bde CCMPNL r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000167C 626cf80d3b1e CCMPNL r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001682 626cf80d3bde CCMPNL r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001688 626c790d3b1e CCMPNL r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000168E 626c790d3bde CCMPNL r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001694 626cf90d3b1e CCMPNL r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000169A 626cf90d3bde CCMPNL r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016A0 626c780d803ebd CCMPNL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000016A7 626c780d80febd CCMPNL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000016AE 626cf80d803ebd CCMPNL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016B5 626cf80d80febd CCMPNL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016BC 626c780d813ebdbdbdbd CCMPNL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000016C6 626c780d81febdbdbdbd CCMPNL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000016D0 626cf80d813ebdbdbdbd CCMPNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016DA 626cf80d81febdbdbdbd CCMPNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016E4 626c790d813ebdbd CCMPNL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000016EC 626c790d81febdbd CCMPNL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000016F4 626cf90d813ebdbdbdbd CCMPNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000016FE 626cf90d81febdbdbdbd CCMPNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001708 626c780d833ebd CCMPNL dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000170F 626c780d83febd CCMPNL r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001716 626cf80d833ebd CCMPNL qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000171D 626cf80d83febd CCMPNL r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001724 626c790d833ebd CCMPNL word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000172B 626c790d83febd CCMPNL r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001732 626cf90d833ebd CCMPNL qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001739 626cf90d83febd CCMPNL r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001740 626c780f381e CCMPNLE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001746 626c780f38de CCMPNLE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000174C 626cf80f381e CCMPNLE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001752 626cf80f38de CCMPNLE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001758 626c780f391e CCMPNLE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000175E 626c780f39de CCMPNLE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001764 626cf80f391e CCMPNLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000176A 626cf80f39de CCMPNLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001770 626c790f391e CCMPNLE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001776 626c790f39de CCMPNLE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000177C 626cf90f391e CCMPNLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001782 626cf90f39de CCMPNLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001788 626c780f3a1e CCMPNLE r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000178E 626c780f3ade CCMPNLE r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001794 626cf80f3a1e CCMPNLE r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000179A 626cf80f3ade CCMPNLE r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017A0 626c780f3b1e CCMPNLE r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000017A6 626c780f3bde CCMPNLE r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000017AC 626cf80f3b1e CCMPNLE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017B2 626cf80f3bde CCMPNLE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017B8 626c790f3b1e CCMPNLE r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000017BE 626c790f3bde CCMPNLE r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000017C4 626cf90f3b1e CCMPNLE r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017CA 626cf90f3bde CCMPNLE r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017D0 626c780f803ebd CCMPNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000017D7 626c780f80febd CCMPNLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000017DE 626cf80f803ebd CCMPNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017E5 626cf80f80febd CCMPNLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000017EC 626c780f813ebdbdbdbd CCMPNLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000017F6 626c780f81febdbdbdbd CCMPNLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001800 626cf80f813ebdbdbdbd CCMPNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000180A 626cf80f81febdbdbdbd CCMPNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001814 626c790f813ebdbd CCMPNLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000181C 626c790f81febdbd CCMPNLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001824 626cf90f813ebdbdbdbd CCMPNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000182E 626cf90f81febdbdbdbd CCMPNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001838 626c780f833ebd CCMPNLE dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000183F 626c780f83febd CCMPNLE r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001846 626cf80f833ebd CCMPNLE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000184D 626cf80f83febd CCMPNLE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001854 626c790f833ebd CCMPNLE word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000185B 626c790f83febd CCMPNLE r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001862 626cf90f833ebd CCMPNLE qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001869 626cf90f83febd CCMPNLE r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001870 626c7801381e CCMPNO byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001876 626c780138de CCMPNO r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000187C 626cf801381e CCMPNO byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001882 626cf80138de CCMPNO r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001888 626c7801391e CCMPNO dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000188E 626c780139de CCMPNO r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001894 626cf801391e CCMPNO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000189A 626cf80139de CCMPNO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018A0 626c7901391e CCMPNO word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000018A6 626c790139de CCMPNO r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000018AC 626cf901391e CCMPNO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018B2 626cf90139de CCMPNO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018B8 626c78013a1e CCMPNO r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000018BE 626c78013ade CCMPNO r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000018C4 626cf8013a1e CCMPNO r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018CA 626cf8013ade CCMPNO r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018D0 626c78013b1e CCMPNO r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000018D6 626c78013bde CCMPNO r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000018DC 626cf8013b1e CCMPNO r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018E2 626cf8013bde CCMPNO r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018E8 626c79013b1e CCMPNO r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000018EE 626c79013bde CCMPNO r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000018F4 626cf9013b1e CCMPNO r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000018FA 626cf9013bde CCMPNO r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001900 626c7801803ebd CCMPNO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001907 626c780180febd CCMPNO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000190E 626cf801803ebd CCMPNO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001915 626cf80180febd CCMPNO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000191C 626c7801813ebdbdbdbd CCMPNO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001926 626c780181febdbdbdbd CCMPNO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001930 626cf801813ebdbdbdbd CCMPNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000193A 626cf80181febdbdbdbd CCMPNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001944 626c7901813ebdbd CCMPNO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000194C 626c790181febdbd CCMPNO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001954 626cf901813ebdbdbdbd CCMPNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000195E 626cf90181febdbdbdbd CCMPNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001968 626c7801833ebd CCMPNO dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000196F 626c780183febd CCMPNO r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001976 626cf801833ebd CCMPNO qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000197D 626cf80183febd CCMPNO r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001984 626c7901833ebd CCMPNO word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000198B 626c790183febd CCMPNO r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001992 626cf901833ebd CCMPNO qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001999 626cf90183febd CCMPNO r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019A0 626c7809381e CCMPNS byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019A6 626c780938de CCMPNS r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019AC 626cf809381e CCMPNS byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019B2 626cf80938de CCMPNS r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019B8 626c7809391e CCMPNS dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019BE 626c780939de CCMPNS r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019C4 626cf809391e CCMPNS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019CA 626cf80939de CCMPNS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019D0 626c7909391e CCMPNS word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000019D6 626c790939de CCMPNS r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000019DC 626cf909391e CCMPNS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019E2 626cf90939de CCMPNS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019E8 626c78093a1e CCMPNS r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019EE 626c78093ade CCMPNS r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000019F4 626cf8093a1e CCMPNS r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000019FA 626cf8093ade CCMPNS r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A00 626c78093b1e CCMPNS r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A06 626c78093bde CCMPNS r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A0C 626cf8093b1e CCMPNS r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A12 626cf8093bde CCMPNS r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A18 626c79093b1e CCMPNS r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001A1E 626c79093bde CCMPNS r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001A24 626cf9093b1e CCMPNS r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A2A 626cf9093bde CCMPNS r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A30 626c7809803ebd CCMPNS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A37 626c780980febd CCMPNS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A3E 626cf809803ebd CCMPNS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A45 626cf80980febd CCMPNS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A4C 626c7809813ebdbdbdbd CCMPNS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A56 626c780981febdbdbdbd CCMPNS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A60 626cf809813ebdbdbdbd CCMPNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A6A 626cf80981febdbdbdbd CCMPNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A74 626c7909813ebdbd CCMPNS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001A7C 626c790981febdbd CCMPNS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001A84 626cf909813ebdbdbdbd CCMPNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A8E 626cf90981febdbdbdbd CCMPNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001A98 626c7809833ebd CCMPNS dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001A9F 626c780983febd CCMPNS r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001AA6 626cf809833ebd CCMPNS qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AAD 626cf80983febd CCMPNS r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AB4 626c7909833ebd CCMPNS word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001ABB 626c790983febd CCMPNS r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001AC2 626cf909833ebd CCMPNS qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AC9 626cf90983febd CCMPNS r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AD0 626c7805381e CCMPNZ byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001AD6 626c780538de CCMPNZ r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001ADC 626cf805381e CCMPNZ byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AE2 626cf80538de CCMPNZ r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AE8 626c7805391e CCMPNZ dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001AEE 626c780539de CCMPNZ r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001AF4 626cf805391e CCMPNZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001AFA 626cf80539de CCMPNZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B00 626c7905391e CCMPNZ word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001B06 626c790539de CCMPNZ r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001B0C 626cf905391e CCMPNZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B12 626cf90539de CCMPNZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B18 626c78053a1e CCMPNZ r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B1E 626c78053ade CCMPNZ r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B24 626cf8053a1e CCMPNZ r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B2A 626cf8053ade CCMPNZ r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B30 626c78053b1e CCMPNZ r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B36 626c78053bde CCMPNZ r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B3C 626cf8053b1e CCMPNZ r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B42 626cf8053bde CCMPNZ r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B48 626c79053b1e CCMPNZ r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001B4E 626c79053bde CCMPNZ r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001B54 626cf9053b1e CCMPNZ r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B5A 626cf9053bde CCMPNZ r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B60 626c7805803ebd CCMPNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B67 626c780580febd CCMPNZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B6E 626cf805803ebd CCMPNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B75 626cf80580febd CCMPNZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B7C 626c7805813ebdbdbdbd CCMPNZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B86 626c780581febdbdbdbd CCMPNZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001B90 626cf805813ebdbdbdbd CCMPNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001B9A 626cf80581febdbdbdbd CCMPNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BA4 626c7905813ebdbd CCMPNZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001BAC 626c790581febdbd CCMPNZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001BB4 626cf905813ebdbdbdbd CCMPNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BBE 626cf90581febdbdbdbd CCMPNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BC8 626c7805833ebd CCMPNZ dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001BCF 626c780583febd CCMPNZ r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001BD6 626cf805833ebd CCMPNZ qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BDD 626cf80583febd CCMPNZ r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BE4 626c7905833ebd CCMPNZ word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001BEB 626c790583febd CCMPNZ r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001BF2 626cf905833ebd CCMPNZ qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001BF9 626cf90583febd CCMPNZ r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C00 626c7800381e CCMPO byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C06 626c780038de CCMPO r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C0C 626cf800381e CCMPO byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C12 626cf80038de CCMPO r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C18 626c7800391e CCMPO dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C1E 626c780039de CCMPO r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C24 626cf800391e CCMPO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C2A 626cf80039de CCMPO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C30 626c7900391e CCMPO word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001C36 626c790039de CCMPO r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001C3C 626cf900391e CCMPO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C42 626cf90039de CCMPO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C48 626c78003a1e CCMPO r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C4E 626c78003ade CCMPO r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C54 626cf8003a1e CCMPO r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C5A 626cf8003ade CCMPO r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C60 626c78003b1e CCMPO r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C66 626c78003bde CCMPO r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C6C 626cf8003b1e CCMPO r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C72 626cf8003bde CCMPO r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C78 626c79003b1e CCMPO r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001C7E 626c79003bde CCMPO r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001C84 626cf9003b1e CCMPO r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C8A 626cf9003bde CCMPO r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001C90 626c7800803ebd CCMPO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C97 626c780080febd CCMPO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001C9E 626cf800803ebd CCMPO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CA5 626cf80080febd CCMPO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CAC 626c7800813ebdbdbdbd CCMPO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CB6 626c780081febdbdbdbd CCMPO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CC0 626cf800813ebdbdbdbd CCMPO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CCA 626cf80081febdbdbdbd CCMPO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CD4 626c7900813ebdbd CCMPO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001CDC 626c790081febdbd CCMPO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001CE4 626cf900813ebdbdbdbd CCMPO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CEE 626cf90081febdbdbdbd CCMPO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001CF8 626c7800833ebd CCMPO dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001CFF 626c780083febd CCMPO r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D06 626cf800833ebd CCMPO qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D0D 626cf80083febd CCMPO r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D14 626c7900833ebd CCMPO word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001D1B 626c790083febd CCMPO r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001D22 626cf900833ebd CCMPO qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D29 626cf90083febd CCMPO r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D30 626c7808381e CCMPS byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D36 626c780838de CCMPS r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D3C 626cf808381e CCMPS byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D42 626cf80838de CCMPS r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D48 626c7808391e CCMPS dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D4E 626c780839de CCMPS r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D54 626cf808391e CCMPS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D5A 626cf80839de CCMPS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D60 626c7908391e CCMPS word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001D66 626c790839de CCMPS r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001D6C 626cf908391e CCMPS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D72 626cf90839de CCMPS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D78 626c78083a1e CCMPS r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D7E 626c78083ade CCMPS r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D84 626cf8083a1e CCMPS r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D8A 626cf8083ade CCMPS r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001D90 626c78083b1e CCMPS r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D96 626c78083bde CCMPS r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001D9C 626cf8083b1e CCMPS r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DA2 626cf8083bde CCMPS r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DA8 626c79083b1e CCMPS r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001DAE 626c79083bde CCMPS r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001DB4 626cf9083b1e CCMPS r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DBA 626cf9083bde CCMPS r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DC0 626c7808803ebd CCMPS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DC7 626c780880febd CCMPS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DCE 626cf808803ebd CCMPS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DD5 626cf80880febd CCMPS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DDC 626c7808813ebdbdbdbd CCMPS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DE6 626c780881febdbdbdbd CCMPS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001DF0 626cf808813ebdbdbdbd CCMPS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001DFA 626cf80881febdbdbdbd CCMPS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E04 626c7908813ebdbd CCMPS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E0C 626c790881febdbd CCMPS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E14 626cf908813ebdbdbdbd CCMPS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E1E 626cf90881febdbdbdbd CCMPS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E28 626c7808833ebd CCMPS dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E2F 626c780883febd CCMPS r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E36 626cf808833ebd CCMPS qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E3D 626cf80883febd CCMPS r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E44 626c7908833ebd CCMPS word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E4B 626c790883febd CCMPS r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E52 626cf908833ebd CCMPS qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E59 626cf90883febd CCMPS r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E60 626c780a381e CCMPT byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E66 626c780a38de CCMPT r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E6C 626cf80a381e CCMPT byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E72 626cf80a38de CCMPT r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E78 626c780a391e CCMPT dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E7E 626c780a39de CCMPT r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001E84 626cf80a391e CCMPT qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E8A 626cf80a39de CCMPT r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001E90 626c790a391e CCMPT word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E96 626c790a39de CCMPT r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001E9C 626cf90a391e CCMPT qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EA2 626cf90a39de CCMPT r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EA8 626c780a3a1e CCMPT r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001EAE 626c780a3ade CCMPT r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001EB4 626cf80a3a1e CCMPT r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EBA 626cf80a3ade CCMPT r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EC0 626c780a3b1e CCMPT r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001EC6 626c780a3bde CCMPT r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001ECC 626cf80a3b1e CCMPT r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001ED2 626cf80a3bde CCMPT r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001ED8 626c790a3b1e CCMPT r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001EDE 626c790a3bde CCMPT r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001EE4 626cf90a3b1e CCMPT r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EEA 626cf90a3bde CCMPT r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001EF0 626c780a803ebd CCMPT byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001EF7 626c780a80febd CCMPT r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001EFE 626cf80a803ebd CCMPT byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F05 626cf80a80febd CCMPT r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F0C 626c780a813ebdbdbdbd CCMPT dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F16 626c780a81febdbdbdbd CCMPT r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F20 626cf80a813ebdbdbdbd CCMPT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F2A 626cf80a81febdbdbdbd CCMPT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F34 626c790a813ebdbd CCMPT word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001F3C 626c790a81febdbd CCMPT r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001F44 626cf90a813ebdbdbdbd CCMPT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F4E 626cf90a81febdbdbdbd CCMPT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F58 626c780a833ebd CCMPT dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F5F 626c780a83febd CCMPT r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F66 626cf80a833ebd CCMPT qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F6D 626cf80a83febd CCMPT r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F74 626c790a833ebd CCMPT word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001F7B 626c790a83febd CCMPT r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001F82 626cf90a833ebd CCMPT qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F89 626cf90a83febd CCMPT r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001F90 626c7804381e CCMPZ byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F96 626c780438de CCMPZ r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001F9C 626cf804381e CCMPZ byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FA2 626cf80438de CCMPZ r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FA8 626c7804391e CCMPZ dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FAE 626c780439de CCMPZ r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FB4 626cf804391e CCMPZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FBA 626cf80439de CCMPZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FC0 626c7904391e CCMPZ word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001FC6 626c790439de CCMPZ r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000001FCC 626cf904391e CCMPZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FD2 626cf90439de CCMPZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FD8 626c78043a1e CCMPZ r27b, byte ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FDE 626c78043ade CCMPZ r27b, r22b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FE4 626cf8043a1e CCMPZ r27b, byte ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FEA 626cf8043ade CCMPZ r27b, r22b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000001FF0 626c78043b1e CCMPZ r27d, dword ptr [r22], 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FF6 626c78043bde CCMPZ r27d, r22d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000001FFC 626cf8043b1e CCMPZ r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002002 626cf8043bde CCMPZ r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002008 626c79043b1e CCMPZ r27w, word ptr [r22], 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000200E 626c79043bde CCMPZ r27w, r22w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002014 626cf9043b1e CCMPZ r27, qword ptr [r22], 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000201A 626cf9043bde CCMPZ r27, r22, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002020 626c7804803ebd CCMPZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002027 626c780480febd CCMPZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000202E 626cf804803ebd CCMPZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002035 626cf80480febd CCMPZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000203C 626c7804813ebdbdbdbd CCMPZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002046 626c780481febdbdbdbd CCMPZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002050 626cf804813ebdbdbdbd CCMPZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000205A 626cf80481febdbdbdbd CCMPZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002064 626c7904813ebdbd CCMPZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000206C 626c790481febdbd CCMPZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002074 626cf904813ebdbdbdbd CCMPZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000207E 626cf90481febdbdbdbd CCMPZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002088 626c7804833ebd CCMPZ dword ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000208F 626c780483febd CCMPZ r22d, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002096 626cf804833ebd CCMPZ qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000209D 626cf80483febd CCMPZ r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020A4 626c7904833ebd CCMPZ word ptr [r22], 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000020AB 626c790483febd CCMPZ r22w, 0xbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000020B2 626cf904833ebd CCMPZ qword ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020B9 626cf90483febd CCMPZ r22, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020C0 626c7808461e CFCMOVBE r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000020C6 626c780846de CFCMOVBE r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000020CC 626cf808461e CFCMOVBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020D2 626cf80846de CFCMOVBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020D8 626c780c46de CFCMOVBE r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000020DE 626cf80c46de CFCMOVBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020E4 626c780c461e CFCMOVBE dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000020EA 626cf80c461e CFCMOVBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000020F0 626c7908461e CFCMOVBE r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000020F6 626c790846de CFCMOVBE r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000020FC 626cf908461e CFCMOVBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002102 626cf90846de CFCMOVBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002108 626c790c46de CFCMOVBE r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000210E 626cf90c46de CFCMOVBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002114 626c790c461e CFCMOVBE word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000211A 626cf90c461e CFCMOVBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002120 626c781c461e CFCMOVBE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002126 626c781c46de CFCMOVBE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000212C 626cf81c461e CFCMOVBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002132 626cf81c46de CFCMOVBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002138 626c791c461e CFCMOVBE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000213E 626c791c46de CFCMOVBE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002144 626cf91c461e CFCMOVBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000214A 626cf91c46de CFCMOVBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002150 626c7808421e CFCMOVC r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002156 626c780842de CFCMOVC r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000215C 626cf808421e CFCMOVC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002162 626cf80842de CFCMOVC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002168 626c780c42de CFCMOVC r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000216E 626cf80c42de CFCMOVC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002174 626c780c421e CFCMOVC dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000217A 626cf80c421e CFCMOVC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002180 626c7908421e CFCMOVC r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002186 626c790842de CFCMOVC r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000218C 626cf908421e CFCMOVC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002192 626cf90842de CFCMOVC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002198 626c790c42de CFCMOVC r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000219E 626cf90c42de CFCMOVC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021A4 626c790c421e CFCMOVC word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000021AA 626cf90c421e CFCMOVC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021B0 626c781c421e CFCMOVC eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000021B6 626c781c42de CFCMOVC eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000021BC 626cf81c421e CFCMOVC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021C2 626cf81c42de CFCMOVC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021C8 626c791c421e CFCMOVC ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000021CE 626c791c42de CFCMOVC ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000021D4 626cf91c421e CFCMOVC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021DA 626cf91c42de CFCMOVC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021E0 626c78084c1e CFCMOVL r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000021E6 626c78084cde CFCMOVL r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000021EC 626cf8084c1e CFCMOVL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021F2 626cf8084cde CFCMOVL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000021F8 626c780c4cde CFCMOVL r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000021FE 626cf80c4cde CFCMOVL r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002204 626c780c4c1e CFCMOVL dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000220A 626cf80c4c1e CFCMOVL qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002210 626c79084c1e CFCMOVL r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002216 626c79084cde CFCMOVL r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000221C 626cf9084c1e CFCMOVL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002222 626cf9084cde CFCMOVL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002228 626c790c4cde CFCMOVL r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000222E 626cf90c4cde CFCMOVL r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002234 626c790c4c1e CFCMOVL word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000223A 626cf90c4c1e CFCMOVL qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002240 626c781c4c1e CFCMOVL eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002246 626c781c4cde CFCMOVL eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000224C 626cf81c4c1e CFCMOVL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002252 626cf81c4cde CFCMOVL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002258 626c791c4c1e CFCMOVL ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000225E 626c791c4cde CFCMOVL ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002264 626cf91c4c1e CFCMOVL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000226A 626cf91c4cde CFCMOVL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002270 626c78084e1e CFCMOVLE r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002276 626c78084ede CFCMOVLE r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000227C 626cf8084e1e CFCMOVLE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002282 626cf8084ede CFCMOVLE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002288 626c780c4ede CFCMOVLE r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000228E 626cf80c4ede CFCMOVLE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002294 626c780c4e1e CFCMOVLE dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000229A 626cf80c4e1e CFCMOVLE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022A0 626c79084e1e CFCMOVLE r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022A6 626c79084ede CFCMOVLE r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022AC 626cf9084e1e CFCMOVLE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022B2 626cf9084ede CFCMOVLE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022B8 626c790c4ede CFCMOVLE r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022BE 626cf90c4ede CFCMOVLE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022C4 626c790c4e1e CFCMOVLE word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022CA 626cf90c4e1e CFCMOVLE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022D0 626c781c4e1e CFCMOVLE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000022D6 626c781c4ede CFCMOVLE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000022DC 626cf81c4e1e CFCMOVLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022E2 626cf81c4ede CFCMOVLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022E8 626c791c4e1e CFCMOVLE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022EE 626c791c4ede CFCMOVLE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000022F4 626cf91c4e1e CFCMOVLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000022FA 626cf91c4ede CFCMOVLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002300 626c7808471e CFCMOVNBE r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002306 626c780847de CFCMOVNBE r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000230C 626cf808471e CFCMOVNBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002312 626cf80847de CFCMOVNBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002318 626c780c47de CFCMOVNBE r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000231E 626cf80c47de CFCMOVNBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002324 626c780c471e CFCMOVNBE dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000232A 626cf80c471e CFCMOVNBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002330 626c7908471e CFCMOVNBE r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002336 626c790847de CFCMOVNBE r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000233C 626cf908471e CFCMOVNBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002342 626cf90847de CFCMOVNBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002348 626c790c47de CFCMOVNBE r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000234E 626cf90c47de CFCMOVNBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002354 626c790c471e CFCMOVNBE word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000235A 626cf90c471e CFCMOVNBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002360 626c781c471e CFCMOVNBE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002366 626c781c47de CFCMOVNBE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000236C 626cf81c471e CFCMOVNBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002372 626cf81c47de CFCMOVNBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002378 626c791c471e CFCMOVNBE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000237E 626c791c47de CFCMOVNBE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002384 626cf91c471e CFCMOVNBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000238A 626cf91c47de CFCMOVNBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002390 626c7808431e CFCMOVNC r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002396 626c780843de CFCMOVNC r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000239C 626cf808431e CFCMOVNC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023A2 626cf80843de CFCMOVNC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023A8 626c780c43de CFCMOVNC r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000023AE 626cf80c43de CFCMOVNC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023B4 626c780c431e CFCMOVNC dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000023BA 626cf80c431e CFCMOVNC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023C0 626c7908431e CFCMOVNC r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000023C6 626c790843de CFCMOVNC r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000023CC 626cf908431e CFCMOVNC r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023D2 626cf90843de CFCMOVNC r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023D8 626c790c43de CFCMOVNC r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000023DE 626cf90c43de CFCMOVNC r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023E4 626c790c431e CFCMOVNC word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000023EA 626cf90c431e CFCMOVNC qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000023F0 626c781c431e CFCMOVNC eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000023F6 626c781c43de CFCMOVNC eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000023FC 626cf81c431e CFCMOVNC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002402 626cf81c43de CFCMOVNC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002408 626c791c431e CFCMOVNC ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000240E 626c791c43de CFCMOVNC ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002414 626cf91c431e CFCMOVNC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000241A 626cf91c43de CFCMOVNC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002420 626c78084d1e CFCMOVNL r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002426 626c78084dde CFCMOVNL r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000242C 626cf8084d1e CFCMOVNL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002432 626cf8084dde CFCMOVNL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002438 626c780c4dde CFCMOVNL r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000243E 626cf80c4dde CFCMOVNL r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002444 626c780c4d1e CFCMOVNL dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000244A 626cf80c4d1e CFCMOVNL qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002450 626c79084d1e CFCMOVNL r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002456 626c79084dde CFCMOVNL r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000245C 626cf9084d1e CFCMOVNL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002462 626cf9084dde CFCMOVNL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002468 626c790c4dde CFCMOVNL r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000246E 626cf90c4dde CFCMOVNL r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002474 626c790c4d1e CFCMOVNL word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000247A 626cf90c4d1e CFCMOVNL qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002480 626c781c4d1e CFCMOVNL eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002486 626c781c4dde CFCMOVNL eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000248C 626cf81c4d1e CFCMOVNL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002492 626cf81c4dde CFCMOVNL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002498 626c791c4d1e CFCMOVNL ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000249E 626c791c4dde CFCMOVNL ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000024A4 626cf91c4d1e CFCMOVNL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024AA 626cf91c4dde CFCMOVNL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024B0 626c78084f1e CFCMOVNLE r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000024B6 626c78084fde CFCMOVNLE r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000024BC 626cf8084f1e CFCMOVNLE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024C2 626cf8084fde CFCMOVNLE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024C8 626c780c4fde CFCMOVNLE r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000024CE 626cf80c4fde CFCMOVNLE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024D4 626c780c4f1e CFCMOVNLE dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000024DA 626cf80c4f1e CFCMOVNLE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024E0 626c79084f1e CFCMOVNLE r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000024E6 626c79084fde CFCMOVNLE r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000024EC 626cf9084f1e CFCMOVNLE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024F2 626cf9084fde CFCMOVNLE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000024F8 626c790c4fde CFCMOVNLE r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000024FE 626cf90c4fde CFCMOVNLE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002504 626c790c4f1e CFCMOVNLE word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000250A 626cf90c4f1e CFCMOVNLE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002510 626c781c4f1e CFCMOVNLE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002516 626c781c4fde CFCMOVNLE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000251C 626cf81c4f1e CFCMOVNLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002522 626cf81c4fde CFCMOVNLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002528 626c791c4f1e CFCMOVNLE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000252E 626c791c4fde CFCMOVNLE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002534 626cf91c4f1e CFCMOVNLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000253A 626cf91c4fde CFCMOVNLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002540 626c7808411e CFCMOVNO r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002546 626c780841de CFCMOVNO r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000254C 626cf808411e CFCMOVNO r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002552 626cf80841de CFCMOVNO r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002558 626c780c41de CFCMOVNO r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000255E 626cf80c41de CFCMOVNO r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002564 626c780c411e CFCMOVNO dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000256A 626cf80c411e CFCMOVNO qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002570 626c7908411e CFCMOVNO r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002576 626c790841de CFCMOVNO r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000257C 626cf908411e CFCMOVNO r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002582 626cf90841de CFCMOVNO r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002588 626c790c41de CFCMOVNO r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000258E 626cf90c41de CFCMOVNO r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002594 626c790c411e CFCMOVNO word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000259A 626cf90c411e CFCMOVNO qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025A0 626c781c411e CFCMOVNO eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025A6 626c781c41de CFCMOVNO eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025AC 626cf81c411e CFCMOVNO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025B2 626cf81c41de CFCMOVNO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025B8 626c791c411e CFCMOVNO ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000025BE 626c791c41de CFCMOVNO ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000025C4 626cf91c411e CFCMOVNO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025CA 626cf91c41de CFCMOVNO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025D0 626c78084b1e CFCMOVNP r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025D6 626c78084bde CFCMOVNP r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025DC 626cf8084b1e CFCMOVNP r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025E2 626cf8084bde CFCMOVNP r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025E8 626c780c4bde CFCMOVNP r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025EE 626cf80c4bde CFCMOVNP r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000025F4 626c780c4b1e CFCMOVNP dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000025FA 626cf80c4b1e CFCMOVNP qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002600 626c79084b1e CFCMOVNP r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002606 626c79084bde CFCMOVNP r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000260C 626cf9084b1e CFCMOVNP r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002612 626cf9084bde CFCMOVNP r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002618 626c790c4bde CFCMOVNP r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000261E 626cf90c4bde CFCMOVNP r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002624 626c790c4b1e CFCMOVNP word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000262A 626cf90c4b1e CFCMOVNP qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002630 626c781c4b1e CFCMOVNP eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002636 626c781c4bde CFCMOVNP eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000263C 626cf81c4b1e CFCMOVNP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002642 626cf81c4bde CFCMOVNP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002648 626c791c4b1e CFCMOVNP ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000264E 626c791c4bde CFCMOVNP ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002654 626cf91c4b1e CFCMOVNP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000265A 626cf91c4bde CFCMOVNP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002660 626c7808491e CFCMOVNS r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002666 626c780849de CFCMOVNS r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000266C 626cf808491e CFCMOVNS r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002672 626cf80849de CFCMOVNS r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002678 626c780c49de CFCMOVNS r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000267E 626cf80c49de CFCMOVNS r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002684 626c780c491e CFCMOVNS dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000268A 626cf80c491e CFCMOVNS qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002690 626c7908491e CFCMOVNS r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002696 626c790849de CFCMOVNS r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000269C 626cf908491e CFCMOVNS r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026A2 626cf90849de CFCMOVNS r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026A8 626c790c49de CFCMOVNS r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000026AE 626cf90c49de CFCMOVNS r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026B4 626c790c491e CFCMOVNS word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000026BA 626cf90c491e CFCMOVNS qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026C0 626c781c491e CFCMOVNS eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000026C6 626c781c49de CFCMOVNS eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000026CC 626cf81c491e CFCMOVNS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026D2 626cf81c49de CFCMOVNS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026D8 626c791c491e CFCMOVNS ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000026DE 626c791c49de CFCMOVNS ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000026E4 626cf91c491e CFCMOVNS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026EA 626cf91c49de CFCMOVNS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000026F0 626c7808451e CFCMOVNZ r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000026F6 626c780845de CFCMOVNZ r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000026FC 626cf808451e CFCMOVNZ r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002702 626cf80845de CFCMOVNZ r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002708 626c780c45de CFCMOVNZ r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000270E 626cf80c45de CFCMOVNZ r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002714 626c780c451e CFCMOVNZ dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000271A 626cf80c451e CFCMOVNZ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002720 626c7908451e CFCMOVNZ r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002726 626c790845de CFCMOVNZ r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000272C 626cf908451e CFCMOVNZ r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002732 626cf90845de CFCMOVNZ r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002738 626c790c45de CFCMOVNZ r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000273E 626cf90c45de CFCMOVNZ r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002744 626c790c451e CFCMOVNZ word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000274A 626cf90c451e CFCMOVNZ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002750 626c781c451e CFCMOVNZ eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002756 626c781c45de CFCMOVNZ eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000275C 626cf81c451e CFCMOVNZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002762 626cf81c45de CFCMOVNZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002768 626c791c451e CFCMOVNZ ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000276E 626c791c45de CFCMOVNZ ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002774 626cf91c451e CFCMOVNZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000277A 626cf91c45de CFCMOVNZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002780 626c7808401e CFCMOVO r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002786 626c780840de CFCMOVO r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000278C 626cf808401e CFCMOVO r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002792 626cf80840de CFCMOVO r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002798 626c780c40de CFCMOVO r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000279E 626cf80c40de CFCMOVO r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027A4 626c780c401e CFCMOVO dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000027AA 626cf80c401e CFCMOVO qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027B0 626c7908401e CFCMOVO r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000027B6 626c790840de CFCMOVO r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000027BC 626cf908401e CFCMOVO r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027C2 626cf90840de CFCMOVO r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027C8 626c790c40de CFCMOVO r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000027CE 626cf90c40de CFCMOVO r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027D4 626c790c401e CFCMOVO word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000027DA 626cf90c401e CFCMOVO qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027E0 626c781c401e CFCMOVO eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000027E6 626c781c40de CFCMOVO eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000027EC 626cf81c401e CFCMOVO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027F2 626cf81c40de CFCMOVO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000027F8 626c791c401e CFCMOVO ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000027FE 626c791c40de CFCMOVO ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002804 626cf91c401e CFCMOVO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000280A 626cf91c40de CFCMOVO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002810 626c78084a1e CFCMOVP r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002816 626c78084ade CFCMOVP r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000281C 626cf8084a1e CFCMOVP r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002822 626cf8084ade CFCMOVP r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002828 626c780c4ade CFCMOVP r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000282E 626cf80c4ade CFCMOVP r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002834 626c780c4a1e CFCMOVP dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000283A 626cf80c4a1e CFCMOVP qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002840 626c79084a1e CFCMOVP r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002846 626c79084ade CFCMOVP r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000284C 626cf9084a1e CFCMOVP r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002852 626cf9084ade CFCMOVP r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002858 626c790c4ade CFCMOVP r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000285E 626cf90c4ade CFCMOVP r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002864 626c790c4a1e CFCMOVP word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000286A 626cf90c4a1e CFCMOVP qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002870 626c781c4a1e CFCMOVP eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002876 626c781c4ade CFCMOVP eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000287C 626cf81c4a1e CFCMOVP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002882 626cf81c4ade CFCMOVP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002888 626c791c4a1e CFCMOVP ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000288E 626c791c4ade CFCMOVP ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002894 626cf91c4a1e CFCMOVP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000289A 626cf91c4ade CFCMOVP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028A0 626c7808481e CFCMOVS r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000028A6 626c780848de CFCMOVS r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000028AC 626cf808481e CFCMOVS r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028B2 626cf80848de CFCMOVS r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028B8 626c780c48de CFCMOVS r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000028BE 626cf80c48de CFCMOVS r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028C4 626c780c481e CFCMOVS dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000028CA 626cf80c481e CFCMOVS qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028D0 626c7908481e CFCMOVS r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000028D6 626c790848de CFCMOVS r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000028DC 626cf908481e CFCMOVS r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028E2 626cf90848de CFCMOVS r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028E8 626c790c48de CFCMOVS r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000028EE 626cf90c48de CFCMOVS r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000028F4 626c790c481e CFCMOVS word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000028FA 626cf90c481e CFCMOVS qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002900 626c781c481e CFCMOVS eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002906 626c781c48de CFCMOVS eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000290C 626cf81c481e CFCMOVS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002912 626cf81c48de CFCMOVS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002918 626c791c481e CFCMOVS ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000291E 626c791c48de CFCMOVS ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002924 626cf91c481e CFCMOVS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000292A 626cf91c48de CFCMOVS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002930 626c7808441e CFCMOVZ r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002936 626c780844de CFCMOVZ r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000293C 626cf808441e CFCMOVZ r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002942 626cf80844de CFCMOVZ r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002948 626c780c44de CFCMOVZ r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000294E 626cf80c44de CFCMOVZ r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002954 626c780c441e CFCMOVZ dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000295A 626cf80c441e CFCMOVZ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002960 626c7908441e CFCMOVZ r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002966 626c790844de CFCMOVZ r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000296C 626cf908441e CFCMOVZ r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002972 626cf90844de CFCMOVZ r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002978 626c790c44de CFCMOVZ r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000297E 626cf90c44de CFCMOVZ r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002984 626c790c441e CFCMOVZ word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000298A 626cf90c441e CFCMOVZ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: CW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002990 626c781c441e CFCMOVZ eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002996 626c781c44de CFCMOVZ eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000299C 626cf81c441e CFCMOVZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029A2 626cf81c44de CFCMOVZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029A8 626c791c441e CFCMOVZ ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000029AE 626c791c44de CFCMOVZ ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000029B4 626cf91c441e CFCMOVZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029BA 626cf91c44de CFCMOVZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CFCMOV + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029C0 626c7818461e CMOVBE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000029C6 626c781846de CMOVBE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000029CC 626cf818461e CMOVBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029D2 626cf81846de CMOVBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029D8 626c7918461e CMOVBE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000029DE 626c791846de CMOVBE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000029E4 626cf918461e CMOVBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029EA 626cf91846de CMOVBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000029F0 626c7818421e CMOVC eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000029F6 626c781842de CMOVC eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000029FC 626cf818421e CMOVC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A02 626cf81842de CMOVC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A08 626c7918421e CMOVC ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A0E 626c791842de CMOVC ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A14 626cf918421e CMOVC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A1A 626cf91842de CMOVC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A20 626c78184c1e CMOVL eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A26 626c78184cde CMOVL eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A2C 626cf8184c1e CMOVL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A32 626cf8184cde CMOVL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A38 626c79184c1e CMOVL ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A3E 626c79184cde CMOVL ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A44 626cf9184c1e CMOVL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A4A 626cf9184cde CMOVL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A50 626c78184e1e CMOVLE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A56 626c78184ede CMOVLE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A5C 626cf8184e1e CMOVLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A62 626cf8184ede CMOVLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A68 626c79184e1e CMOVLE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A6E 626c79184ede CMOVLE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A74 626cf9184e1e CMOVLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A7A 626cf9184ede CMOVLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A80 626c7818471e CMOVNBE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A86 626c781847de CMOVNBE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002A8C 626cf818471e CMOVNBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A92 626cf81847de CMOVNBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002A98 626c7918471e CMOVNBE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002A9E 626c791847de CMOVNBE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002AA4 626cf918471e CMOVNBE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AAA 626cf91847de CMOVNBE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AB0 626c7818431e CMOVNC eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002AB6 626c781843de CMOVNC eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002ABC 626cf818431e CMOVNC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AC2 626cf81843de CMOVNC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AC8 626c7918431e CMOVNC ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002ACE 626c791843de CMOVNC ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002AD4 626cf918431e CMOVNC rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002ADA 626cf91843de CMOVNC rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AE0 626c78184d1e CMOVNL eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002AE6 626c78184dde CMOVNL eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002AEC 626cf8184d1e CMOVNL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AF2 626cf8184dde CMOVNL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002AF8 626c79184d1e CMOVNL ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002AFE 626c79184dde CMOVNL ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B04 626cf9184d1e CMOVNL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B0A 626cf9184dde CMOVNL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B10 626c78184f1e CMOVNLE eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B16 626c78184fde CMOVNLE eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B1C 626cf8184f1e CMOVNLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B22 626cf8184fde CMOVNLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B28 626c79184f1e CMOVNLE ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B2E 626c79184fde CMOVNLE ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B34 626cf9184f1e CMOVNLE rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B3A 626cf9184fde CMOVNLE rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B40 626c7818411e CMOVNO eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B46 626c781841de CMOVNO eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B4C 626cf818411e CMOVNO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B52 626cf81841de CMOVNO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B58 626c7918411e CMOVNO ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B5E 626c791841de CMOVNO ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B64 626cf918411e CMOVNO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B6A 626cf91841de CMOVNO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B70 626c78184b1e CMOVNP eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B76 626c78184bde CMOVNP eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002B7C 626cf8184b1e CMOVNP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B82 626cf8184bde CMOVNP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B88 626c79184b1e CMOVNP ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B8E 626c79184bde CMOVNP ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002B94 626cf9184b1e CMOVNP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002B9A 626cf9184bde CMOVNP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BA0 626c7818491e CMOVNS eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002BA6 626c781849de CMOVNS eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002BAC 626cf818491e CMOVNS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BB2 626cf81849de CMOVNS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BB8 626c7918491e CMOVNS ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002BBE 626c791849de CMOVNS ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002BC4 626cf918491e CMOVNS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BCA 626cf91849de CMOVNS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BD0 626c7818451e CMOVNZ eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002BD6 626c781845de CMOVNZ eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002BDC 626cf818451e CMOVNZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BE2 626cf81845de CMOVNZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BE8 626c7918451e CMOVNZ ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002BEE 626c791845de CMOVNZ ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002BF4 626cf918451e CMOVNZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002BFA 626cf91845de CMOVNZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C00 626c7818401e CMOVO eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C06 626c781840de CMOVO eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C0C 626cf818401e CMOVO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C12 626cf81840de CMOVO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C18 626c7918401e CMOVO ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C1E 626c791840de CMOVO ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C24 626cf918401e CMOVO rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C2A 626cf91840de CMOVO rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C30 626c78184a1e CMOVP eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C36 626c78184ade CMOVP eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C3C 626cf8184a1e CMOVP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C42 626cf8184ade CMOVP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C48 626c79184a1e CMOVP ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C4E 626c79184ade CMOVP ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C54 626cf9184a1e CMOVP rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C5A 626cf9184ade CMOVP rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C60 626c7818481e CMOVS eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C66 626c781848de CMOVS eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C6C 626cf818481e CMOVS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C72 626cf81848de CMOVS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C78 626c7918481e CMOVS ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C7E 626c791848de CMOVS ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002C84 626cf918481e CMOVS rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C8A 626cf91848de CMOVS rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002C90 626c7818441e CMOVZ eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C96 626c781844de CMOVZ eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002C9C 626cf818441e CMOVZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CA2 626cf81844de CMOVZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CA8 626c7918441e CMOVZ ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002CAE 626c791844de CMOVZ ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002CB4 626cf918441e CMOVZ rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CBA 626cf91844de CMOVZ rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CC0 62fa7908e61e CMPBEXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002CC6 62faf908e61e CMPBEXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CCC 62fa7908e21e CMPCXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002CD2 62faf908e21e CMPCXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CD8 62fa7908ee1e CMPLEXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002CDE 62faf908ee1e CMPLEXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CE4 62fa7908ec1e CMPLXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002CEA 62faf908ec1e CMPLXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CF0 62fa7908e71e CMPNBEXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002CF6 62faf908e71e CMPNBEXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002CFC 62fa7908e31e CMPNCXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D02 62faf908e31e CMPNCXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D08 62fa7908ef1e CMPNLEXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D0E 62faf908ef1e CMPNLEXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D14 62fa7908ed1e CMPNLXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D1A 62faf908ed1e CMPNLXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D20 62fa7908e11e CMPNOXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D26 62faf908e11e CMPNOXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D2C 62fa7908eb1e CMPNPXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D32 62faf908eb1e CMPNPXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D38 62fa7908e91e CMPNSXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D3E 62faf908e91e CMPNSXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D44 62fa7908e51e CMPNZXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D4A 62faf908e51e CMPNZXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D50 62fa7908e01e CMPOXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D56 62faf908e01e CMPOXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D5C 62fa7908ea1e CMPPXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D62 62faf908ea1e CMPPXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D68 62fa7908e81e CMPSXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D6E 62faf908e81e CMPSXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D74 62fa7908e41e CMPZXADD dword ptr [r22], ebx, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002D7A 62faf908e41e CMPZXADD qword ptr [r22], rbx, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CMPCCXADD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CMPCCXADD + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002D80 626c7808f01e CRC32 r27d, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000002D86 626c7808f0de CRC32 r27d, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000002D8C 626cf808f01e CRC32 r27, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000002D92 626cf808f0de CRC32 r27, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000002D98 626c7808f11e CRC32 r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000002D9E 626c7808f1de CRC32 r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000002DA4 626cf808f11e CRC32 r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000002DAA 626cf808f1de CRC32 r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000002DB0 626c7908f11e CRC32 r27d, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000002DB6 626c7908f1de CRC32 r27d, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000002DBC 626cf908f11e CRC32 r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000002DC2 626cf908f1de CRC32 r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000002DC8 626c7806841e CTESTBE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002DCE 626c780684de CTESTBE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002DD4 626cf806841e CTESTBE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002DDA 626cf80684de CTESTBE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002DE0 626c7806851e CTESTBE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002DE6 626c780685de CTESTBE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002DEC 626cf806851e CTESTBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002DF2 626cf80685de CTESTBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002DF8 626c7906851e CTESTBE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002DFE 626c790685de CTESTBE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002E04 626cf906851e CTESTBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E0A 626cf90685de CTESTBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E10 626c7806f606bd CTESTBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E17 626c7806f6c6bd CTESTBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E1E 626cf806f606bd CTESTBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E25 626cf806f6c6bd CTESTBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E2C 626c7806f60ebd CTESTBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E33 626c7806f6cebd CTESTBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E3A 626cf806f60ebd CTESTBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E41 626cf806f6cebd CTESTBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E48 626c7806f706bdbdbdbd CTESTBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E52 626c7806f7c6bdbdbdbd CTESTBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E5C 626cf806f706bdbdbdbd CTESTBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E66 626cf806f7c6bdbdbdbd CTESTBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E70 626c7906f706bdbd CTESTBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002E78 626c7906f7c6bdbd CTESTBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002E80 626cf906f706bdbdbdbd CTESTBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E8A 626cf906f7c6bdbdbdbd CTESTBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002E94 626c7806f70ebdbdbdbd CTESTBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002E9E 626c7806f7cebdbdbdbd CTESTBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002EA8 626cf806f70ebdbdbdbd CTESTBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002EB2 626cf806f7cebdbdbdbd CTESTBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002EBC 626c7906f70ebdbd CTESTBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002EC4 626c7906f7cebdbd CTESTBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002ECC 626cf906f70ebdbdbdbd CTESTBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002ED6 626cf906f7cebdbdbdbd CTESTBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002EE0 626c7802841e CTESTC byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002EE6 626c780284de CTESTC r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002EEC 626cf802841e CTESTC byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002EF2 626cf80284de CTESTC r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002EF8 626c7802851e CTESTC dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002EFE 626c780285de CTESTC r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F04 626cf802851e CTESTC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F0A 626cf80285de CTESTC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F10 626c7902851e CTESTC word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002F16 626c790285de CTESTC r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002F1C 626cf902851e CTESTC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F22 626cf90285de CTESTC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F28 626c7802f606bd CTESTC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F2F 626c7802f6c6bd CTESTC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F36 626cf802f606bd CTESTC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F3D 626cf802f6c6bd CTESTC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F44 626c7802f60ebd CTESTC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F4B 626c7802f6cebd CTESTC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F52 626cf802f60ebd CTESTC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F59 626cf802f6cebd CTESTC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F60 626c7802f706bdbdbdbd CTESTC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F6A 626c7802f7c6bdbdbdbd CTESTC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002F74 626cf802f706bdbdbdbd CTESTC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F7E 626cf802f7c6bdbdbdbd CTESTC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002F88 626c7902f706bdbd CTESTC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002F90 626c7902f7c6bdbd CTESTC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002F98 626cf902f706bdbdbdbd CTESTC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FA2 626cf902f7c6bdbdbdbd CTESTC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FAC 626c7802f70ebdbdbdbd CTESTC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002FB6 626c7802f7cebdbdbdbd CTESTC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002FC0 626cf802f70ebdbdbdbd CTESTC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FCA 626cf802f7cebdbdbdbd CTESTC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FD4 626c7902f70ebdbd CTESTC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002FDC 626c7902f7cebdbd CTESTC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000002FE4 626cf902f70ebdbdbdbd CTESTC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FEE 626cf902f7cebdbdbdbd CTESTC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000002FF8 626c780b841e CTESTF byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000002FFE 626c780b84de CTESTF r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003004 626cf80b841e CTESTF byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000300A 626cf80b84de CTESTF r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003010 626c780b851e CTESTF dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003016 626c780b85de CTESTF r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000301C 626cf80b851e CTESTF qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003022 626cf80b85de CTESTF r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003028 626c790b851e CTESTF word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000302E 626c790b85de CTESTF r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003034 626cf90b851e CTESTF qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000303A 626cf90b85de CTESTF r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003040 626c780bf606bd CTESTF byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003047 626c780bf6c6bd CTESTF r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000304E 626cf80bf606bd CTESTF byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003055 626cf80bf6c6bd CTESTF r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000305C 626c780bf60ebd CTESTF byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003063 626c780bf6cebd CTESTF r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000306A 626cf80bf60ebd CTESTF byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003071 626cf80bf6cebd CTESTF r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003078 626c780bf706bdbdbdbd CTESTF dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003082 626c780bf7c6bdbdbdbd CTESTF r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000308C 626cf80bf706bdbdbdbd CTESTF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003096 626cf80bf7c6bdbdbdbd CTESTF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000030A0 626c790bf706bdbd CTESTF word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000030A8 626c790bf7c6bdbd CTESTF r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000030B0 626cf90bf706bdbdbdbd CTESTF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000030BA 626cf90bf7c6bdbdbdbd CTESTF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000030C4 626c780bf70ebdbdbdbd CTESTF dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000030CE 626c780bf7cebdbdbdbd CTESTF r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000030D8 626cf80bf70ebdbdbdbd CTESTF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000030E2 626cf80bf7cebdbdbdbd CTESTF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000030EC 626c790bf70ebdbd CTESTF word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000030F4 626c790bf7cebdbd CTESTF r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000030FC 626cf90bf70ebdbdbdbd CTESTF qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003106 626cf90bf7cebdbdbdbd CTESTF r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003110 626c780c841e CTESTL byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003116 626c780c84de CTESTL r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000311C 626cf80c841e CTESTL byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003122 626cf80c84de CTESTL r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003128 626c780c851e CTESTL dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000312E 626c780c85de CTESTL r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003134 626cf80c851e CTESTL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000313A 626cf80c85de CTESTL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003140 626c790c851e CTESTL word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003146 626c790c85de CTESTL r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000314C 626cf90c851e CTESTL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003152 626cf90c85de CTESTL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003158 626c780cf606bd CTESTL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000315F 626c780cf6c6bd CTESTL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003166 626cf80cf606bd CTESTL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000316D 626cf80cf6c6bd CTESTL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003174 626c780cf60ebd CTESTL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000317B 626c780cf6cebd CTESTL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003182 626cf80cf60ebd CTESTL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003189 626cf80cf6cebd CTESTL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003190 626c780cf706bdbdbdbd CTESTL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000319A 626c780cf7c6bdbdbdbd CTESTL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000031A4 626cf80cf706bdbdbdbd CTESTL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000031AE 626cf80cf7c6bdbdbdbd CTESTL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000031B8 626c790cf706bdbd CTESTL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000031C0 626c790cf7c6bdbd CTESTL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000031C8 626cf90cf706bdbdbdbd CTESTL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000031D2 626cf90cf7c6bdbdbdbd CTESTL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000031DC 626c780cf70ebdbdbdbd CTESTL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000031E6 626c780cf7cebdbdbdbd CTESTL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000031F0 626cf80cf70ebdbdbdbd CTESTL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000031FA 626cf80cf7cebdbdbdbd CTESTL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003204 626c790cf70ebdbd CTESTL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000320C 626c790cf7cebdbd CTESTL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003214 626cf90cf70ebdbdbdbd CTESTL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000321E 626cf90cf7cebdbdbdbd CTESTL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003228 626c780e841e CTESTLE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000322E 626c780e84de CTESTLE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003234 626cf80e841e CTESTLE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000323A 626cf80e84de CTESTLE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003240 626c780e851e CTESTLE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003246 626c780e85de CTESTLE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000324C 626cf80e851e CTESTLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003252 626cf80e85de CTESTLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003258 626c790e851e CTESTLE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000325E 626c790e85de CTESTLE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003264 626cf90e851e CTESTLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000326A 626cf90e85de CTESTLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003270 626c780ef606bd CTESTLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003277 626c780ef6c6bd CTESTLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000327E 626cf80ef606bd CTESTLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003285 626cf80ef6c6bd CTESTLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000328C 626c780ef60ebd CTESTLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003293 626c780ef6cebd CTESTLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000329A 626cf80ef60ebd CTESTLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032A1 626cf80ef6cebd CTESTLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032A8 626c780ef706bdbdbdbd CTESTLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000032B2 626c780ef7c6bdbdbdbd CTESTLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000032BC 626cf80ef706bdbdbdbd CTESTLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032C6 626cf80ef7c6bdbdbdbd CTESTLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032D0 626c790ef706bdbd CTESTLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000032D8 626c790ef7c6bdbd CTESTLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000032E0 626cf90ef706bdbdbdbd CTESTLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032EA 626cf90ef7c6bdbdbdbd CTESTLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000032F4 626c780ef70ebdbdbdbd CTESTLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000032FE 626c780ef7cebdbdbdbd CTESTLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003308 626cf80ef70ebdbdbdbd CTESTLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003312 626cf80ef7cebdbdbdbd CTESTLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000331C 626c790ef70ebdbd CTESTLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003324 626c790ef7cebdbd CTESTLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000332C 626cf90ef70ebdbdbdbd CTESTLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003336 626cf90ef7cebdbdbdbd CTESTLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003340 626c7807841e CTESTNBE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003346 626c780784de CTESTNBE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000334C 626cf807841e CTESTNBE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003352 626cf80784de CTESTNBE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003358 626c7807851e CTESTNBE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000335E 626c780785de CTESTNBE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003364 626cf807851e CTESTNBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000336A 626cf80785de CTESTNBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003370 626c7907851e CTESTNBE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003376 626c790785de CTESTNBE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000337C 626cf907851e CTESTNBE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003382 626cf90785de CTESTNBE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003388 626c7807f606bd CTESTNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000338F 626c7807f6c6bd CTESTNBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003396 626cf807f606bd CTESTNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000339D 626cf807f6c6bd CTESTNBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000033A4 626c7807f60ebd CTESTNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000033AB 626c7807f6cebd CTESTNBE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000033B2 626cf807f60ebd CTESTNBE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000033B9 626cf807f6cebd CTESTNBE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000033C0 626c7807f706bdbdbdbd CTESTNBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000033CA 626c7807f7c6bdbdbdbd CTESTNBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000033D4 626cf807f706bdbdbdbd CTESTNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000033DE 626cf807f7c6bdbdbdbd CTESTNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000033E8 626c7907f706bdbd CTESTNBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000033F0 626c7907f7c6bdbd CTESTNBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000033F8 626cf907f706bdbdbdbd CTESTNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003402 626cf907f7c6bdbdbdbd CTESTNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000340C 626c7807f70ebdbdbdbd CTESTNBE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003416 626c7807f7cebdbdbdbd CTESTNBE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003420 626cf807f70ebdbdbdbd CTESTNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000342A 626cf807f7cebdbdbdbd CTESTNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003434 626c7907f70ebdbd CTESTNBE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000343C 626c7907f7cebdbd CTESTNBE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003444 626cf907f70ebdbdbdbd CTESTNBE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000344E 626cf907f7cebdbdbdbd CTESTNBE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003458 626c7803841e CTESTNC byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000345E 626c780384de CTESTNC r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003464 626cf803841e CTESTNC byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000346A 626cf80384de CTESTNC r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003470 626c7803851e CTESTNC dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003476 626c780385de CTESTNC r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000347C 626cf803851e CTESTNC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003482 626cf80385de CTESTNC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003488 626c7903851e CTESTNC word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000348E 626c790385de CTESTNC r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003494 626cf903851e CTESTNC qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000349A 626cf90385de CTESTNC r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034A0 626c7803f606bd CTESTNC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034A7 626c7803f6c6bd CTESTNC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034AE 626cf803f606bd CTESTNC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034B5 626cf803f6c6bd CTESTNC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034BC 626c7803f60ebd CTESTNC byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034C3 626c7803f6cebd CTESTNC r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034CA 626cf803f60ebd CTESTNC byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034D1 626cf803f6cebd CTESTNC r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034D8 626c7803f706bdbdbdbd CTESTNC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034E2 626c7803f7c6bdbdbdbd CTESTNC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000034EC 626cf803f706bdbdbdbd CTESTNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000034F6 626cf803f7c6bdbdbdbd CTESTNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003500 626c7903f706bdbd CTESTNC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003508 626c7903f7c6bdbd CTESTNC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003510 626cf903f706bdbdbdbd CTESTNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000351A 626cf903f7c6bdbdbdbd CTESTNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003524 626c7803f70ebdbdbdbd CTESTNC dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000352E 626c7803f7cebdbdbdbd CTESTNC r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003538 626cf803f70ebdbdbdbd CTESTNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003542 626cf803f7cebdbdbdbd CTESTNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000354C 626c7903f70ebdbd CTESTNC word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003554 626c7903f7cebdbd CTESTNC r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000355C 626cf903f70ebdbdbdbd CTESTNC qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003566 626cf903f7cebdbdbdbd CTESTNC r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003570 626c780d841e CTESTNL byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003576 626c780d84de CTESTNL r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000357C 626cf80d841e CTESTNL byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003582 626cf80d84de CTESTNL r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003588 626c780d851e CTESTNL dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000358E 626c780d85de CTESTNL r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003594 626cf80d851e CTESTNL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000359A 626cf80d85de CTESTNL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035A0 626c790d851e CTESTNL word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000035A6 626c790d85de CTESTNL r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000035AC 626cf90d851e CTESTNL qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035B2 626cf90d85de CTESTNL r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035B8 626c780df606bd CTESTNL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000035BF 626c780df6c6bd CTESTNL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000035C6 626cf80df606bd CTESTNL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035CD 626cf80df6c6bd CTESTNL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035D4 626c780df60ebd CTESTNL byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000035DB 626c780df6cebd CTESTNL r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000035E2 626cf80df60ebd CTESTNL byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035E9 626cf80df6cebd CTESTNL r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000035F0 626c780df706bdbdbdbd CTESTNL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000035FA 626c780df7c6bdbdbdbd CTESTNL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003604 626cf80df706bdbdbdbd CTESTNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000360E 626cf80df7c6bdbdbdbd CTESTNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003618 626c790df706bdbd CTESTNL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003620 626c790df7c6bdbd CTESTNL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003628 626cf90df706bdbdbdbd CTESTNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003632 626cf90df7c6bdbdbdbd CTESTNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000363C 626c780df70ebdbdbdbd CTESTNL dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003646 626c780df7cebdbdbdbd CTESTNL r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003650 626cf80df70ebdbdbdbd CTESTNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000365A 626cf80df7cebdbdbdbd CTESTNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003664 626c790df70ebdbd CTESTNL word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000366C 626c790df7cebdbd CTESTNL r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003674 626cf90df70ebdbdbdbd CTESTNL qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000367E 626cf90df7cebdbdbdbd CTESTNL r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003688 626c780f841e CTESTNLE byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000368E 626c780f84de CTESTNLE r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003694 626cf80f841e CTESTNLE byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000369A 626cf80f84de CTESTNLE r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036A0 626c780f851e CTESTNLE dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036A6 626c780f85de CTESTNLE r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036AC 626cf80f851e CTESTNLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036B2 626cf80f85de CTESTNLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036B8 626c790f851e CTESTNLE word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000036BE 626c790f85de CTESTNLE r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000036C4 626cf90f851e CTESTNLE qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036CA 626cf90f85de CTESTNLE r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036D0 626c780ff606bd CTESTNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036D7 626c780ff6c6bd CTESTNLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036DE 626cf80ff606bd CTESTNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036E5 626cf80ff6c6bd CTESTNLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000036EC 626c780ff60ebd CTESTNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036F3 626c780ff6cebd CTESTNLE r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000036FA 626cf80ff60ebd CTESTNLE byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003701 626cf80ff6cebd CTESTNLE r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003708 626c780ff706bdbdbdbd CTESTNLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003712 626c780ff7c6bdbdbdbd CTESTNLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000371C 626cf80ff706bdbdbdbd CTESTNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003726 626cf80ff7c6bdbdbdbd CTESTNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003730 626c790ff706bdbd CTESTNLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003738 626c790ff7c6bdbd CTESTNLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003740 626cf90ff706bdbdbdbd CTESTNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000374A 626cf90ff7c6bdbdbdbd CTESTNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003754 626c780ff70ebdbdbdbd CTESTNLE dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000375E 626c780ff7cebdbdbdbd CTESTNLE r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003768 626cf80ff70ebdbdbdbd CTESTNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003772 626cf80ff7cebdbdbdbd CTESTNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000377C 626c790ff70ebdbd CTESTNLE word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003784 626c790ff7cebdbd CTESTNLE r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000378C 626cf90ff70ebdbdbdbd CTESTNLE qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003796 626cf90ff7cebdbdbdbd CTESTNLE r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037A0 626c7801841e CTESTNO byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037A6 626c780184de CTESTNO r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037AC 626cf801841e CTESTNO byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037B2 626cf80184de CTESTNO r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037B8 626c7801851e CTESTNO dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037BE 626c780185de CTESTNO r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037C4 626cf801851e CTESTNO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037CA 626cf80185de CTESTNO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037D0 626c7901851e CTESTNO word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000037D6 626c790185de CTESTNO r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000037DC 626cf901851e CTESTNO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037E2 626cf90185de CTESTNO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037E8 626c7801f606bd CTESTNO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037EF 626c7801f6c6bd CTESTNO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000037F6 626cf801f606bd CTESTNO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000037FD 626cf801f6c6bd CTESTNO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003804 626c7801f60ebd CTESTNO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000380B 626c7801f6cebd CTESTNO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003812 626cf801f60ebd CTESTNO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003819 626cf801f6cebd CTESTNO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003820 626c7801f706bdbdbdbd CTESTNO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000382A 626c7801f7c6bdbdbdbd CTESTNO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003834 626cf801f706bdbdbdbd CTESTNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000383E 626cf801f7c6bdbdbdbd CTESTNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003848 626c7901f706bdbd CTESTNO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003850 626c7901f7c6bdbd CTESTNO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003858 626cf901f706bdbdbdbd CTESTNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003862 626cf901f7c6bdbdbdbd CTESTNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000386C 626c7801f70ebdbdbdbd CTESTNO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003876 626c7801f7cebdbdbdbd CTESTNO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003880 626cf801f70ebdbdbdbd CTESTNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000388A 626cf801f7cebdbdbdbd CTESTNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003894 626c7901f70ebdbd CTESTNO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000389C 626c7901f7cebdbd CTESTNO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000038A4 626cf901f70ebdbdbdbd CTESTNO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038AE 626cf901f7cebdbdbdbd CTESTNO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038B8 626c7809841e CTESTNS byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000038BE 626c780984de CTESTNS r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000038C4 626cf809841e CTESTNS byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038CA 626cf80984de CTESTNS r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038D0 626c7809851e CTESTNS dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000038D6 626c780985de CTESTNS r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000038DC 626cf809851e CTESTNS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038E2 626cf80985de CTESTNS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038E8 626c7909851e CTESTNS word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000038EE 626c790985de CTESTNS r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000038F4 626cf909851e CTESTNS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000038FA 626cf90985de CTESTNS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003900 626c7809f606bd CTESTNS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003907 626c7809f6c6bd CTESTNS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000390E 626cf809f606bd CTESTNS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003915 626cf809f6c6bd CTESTNS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000391C 626c7809f60ebd CTESTNS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003923 626c7809f6cebd CTESTNS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000392A 626cf809f60ebd CTESTNS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003931 626cf809f6cebd CTESTNS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003938 626c7809f706bdbdbdbd CTESTNS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003942 626c7809f7c6bdbdbdbd CTESTNS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000394C 626cf809f706bdbdbdbd CTESTNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003956 626cf809f7c6bdbdbdbd CTESTNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003960 626c7909f706bdbd CTESTNS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003968 626c7909f7c6bdbd CTESTNS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003970 626cf909f706bdbdbdbd CTESTNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000397A 626cf909f7c6bdbdbdbd CTESTNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003984 626c7809f70ebdbdbdbd CTESTNS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000398E 626c7809f7cebdbdbdbd CTESTNS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003998 626cf809f70ebdbdbdbd CTESTNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039A2 626cf809f7cebdbdbdbd CTESTNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039AC 626c7909f70ebdbd CTESTNS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000039B4 626c7909f7cebdbd CTESTNS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000039BC 626cf909f70ebdbdbdbd CTESTNS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039C6 626cf909f7cebdbdbdbd CTESTNS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039D0 626c7805841e CTESTNZ byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039D6 626c780584de CTESTNZ r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039DC 626cf805841e CTESTNZ byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039E2 626cf80584de CTESTNZ r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039E8 626c7805851e CTESTNZ dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039EE 626c780585de CTESTNZ r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000039F4 626cf805851e CTESTNZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000039FA 626cf80585de CTESTNZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A00 626c7905851e CTESTNZ word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003A06 626c790585de CTESTNZ r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003A0C 626cf905851e CTESTNZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A12 626cf90585de CTESTNZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A18 626c7805f606bd CTESTNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A1F 626c7805f6c6bd CTESTNZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A26 626cf805f606bd CTESTNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A2D 626cf805f6c6bd CTESTNZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A34 626c7805f60ebd CTESTNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A3B 626c7805f6cebd CTESTNZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A42 626cf805f60ebd CTESTNZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A49 626cf805f6cebd CTESTNZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A50 626c7805f706bdbdbdbd CTESTNZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A5A 626c7805f7c6bdbdbdbd CTESTNZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003A64 626cf805f706bdbdbdbd CTESTNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A6E 626cf805f7c6bdbdbdbd CTESTNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A78 626c7905f706bdbd CTESTNZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003A80 626c7905f7c6bdbd CTESTNZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003A88 626cf905f706bdbdbdbd CTESTNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A92 626cf905f7c6bdbdbdbd CTESTNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003A9C 626c7805f70ebdbdbdbd CTESTNZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AA6 626c7805f7cebdbdbdbd CTESTNZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AB0 626cf805f70ebdbdbdbd CTESTNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003ABA 626cf805f7cebdbdbdbd CTESTNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003AC4 626c7905f70ebdbd CTESTNZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003ACC 626c7905f7cebdbd CTESTNZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003AD4 626cf905f70ebdbdbdbd CTESTNZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003ADE 626cf905f7cebdbdbdbd CTESTNZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003AE8 626c7800841e CTESTO byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AEE 626c780084de CTESTO r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003AF4 626cf800841e CTESTO byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003AFA 626cf80084de CTESTO r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B00 626c7800851e CTESTO dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B06 626c780085de CTESTO r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B0C 626cf800851e CTESTO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B12 626cf80085de CTESTO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B18 626c7900851e CTESTO word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003B1E 626c790085de CTESTO r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003B24 626cf900851e CTESTO qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B2A 626cf90085de CTESTO r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B30 626c7800f606bd CTESTO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B37 626c7800f6c6bd CTESTO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B3E 626cf800f606bd CTESTO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B45 626cf800f6c6bd CTESTO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B4C 626c7800f60ebd CTESTO byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B53 626c7800f6cebd CTESTO r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B5A 626cf800f60ebd CTESTO byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B61 626cf800f6cebd CTESTO r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B68 626c7800f706bdbdbdbd CTESTO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B72 626c7800f7c6bdbdbdbd CTESTO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003B7C 626cf800f706bdbdbdbd CTESTO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B86 626cf800f7c6bdbdbdbd CTESTO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003B90 626c7900f706bdbd CTESTO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003B98 626c7900f7c6bdbd CTESTO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003BA0 626cf900f706bdbdbdbd CTESTO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003BAA 626cf900f7c6bdbdbdbd CTESTO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003BB4 626c7800f70ebdbdbdbd CTESTO dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003BBE 626c7800f7cebdbdbdbd CTESTO r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003BC8 626cf800f70ebdbdbdbd CTESTO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003BD2 626cf800f7cebdbdbdbd CTESTO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003BDC 626c7900f70ebdbd CTESTO word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003BE4 626c7900f7cebdbd CTESTO r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003BEC 626cf900f70ebdbdbdbd CTESTO qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003BF6 626cf900f7cebdbdbdbd CTESTO r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C00 626c7808841e CTESTS byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C06 626c780884de CTESTS r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C0C 626cf808841e CTESTS byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C12 626cf80884de CTESTS r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C18 626c7808851e CTESTS dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C1E 626c780885de CTESTS r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C24 626cf808851e CTESTS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C2A 626cf80885de CTESTS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C30 626c7908851e CTESTS word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003C36 626c790885de CTESTS r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003C3C 626cf908851e CTESTS qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C42 626cf90885de CTESTS r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C48 626c7808f606bd CTESTS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C4F 626c7808f6c6bd CTESTS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C56 626cf808f606bd CTESTS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C5D 626cf808f6c6bd CTESTS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C64 626c7808f60ebd CTESTS byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C6B 626c7808f6cebd CTESTS r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C72 626cf808f60ebd CTESTS byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C79 626cf808f6cebd CTESTS r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C80 626c7808f706bdbdbdbd CTESTS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C8A 626c7808f7c6bdbdbdbd CTESTS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003C94 626cf808f706bdbdbdbd CTESTS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003C9E 626cf808f7c6bdbdbdbd CTESTS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003CA8 626c7908f706bdbd CTESTS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003CB0 626c7908f7c6bdbd CTESTS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003CB8 626cf908f706bdbdbdbd CTESTS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003CC2 626cf908f7c6bdbdbdbd CTESTS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003CCC 626c7808f70ebdbdbdbd CTESTS dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003CD6 626c7808f7cebdbdbdbd CTESTS r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003CE0 626cf808f70ebdbdbdbd CTESTS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003CEA 626cf808f7cebdbdbdbd CTESTS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003CF4 626c7908f70ebdbd CTESTS word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003CFC 626c7908f7cebdbd CTESTS r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003D04 626cf908f70ebdbdbdbd CTESTS qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D0E 626cf908f7cebdbdbdbd CTESTS r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D18 626c780a841e CTESTT byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D1E 626c780a84de CTESTT r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D24 626cf80a841e CTESTT byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D2A 626cf80a84de CTESTT r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D30 626c780a851e CTESTT dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D36 626c780a85de CTESTT r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D3C 626cf80a851e CTESTT qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D42 626cf80a85de CTESTT r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D48 626c790a851e CTESTT word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003D4E 626c790a85de CTESTT r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003D54 626cf90a851e CTESTT qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D5A 626cf90a85de CTESTT r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D60 626c780af606bd CTESTT byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D67 626c780af6c6bd CTESTT r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D6E 626cf80af606bd CTESTT byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D75 626cf80af6c6bd CTESTT r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D7C 626c780af60ebd CTESTT byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D83 626c780af6cebd CTESTT r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003D8A 626cf80af60ebd CTESTT byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D91 626cf80af6cebd CTESTT r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003D98 626c780af706bdbdbdbd CTESTT dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003DA2 626c780af7c6bdbdbdbd CTESTT r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003DAC 626cf80af706bdbdbdbd CTESTT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003DB6 626cf80af7c6bdbdbdbd CTESTT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003DC0 626c790af706bdbd CTESTT word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003DC8 626c790af7c6bdbd CTESTT r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003DD0 626cf90af706bdbdbdbd CTESTT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003DDA 626cf90af7c6bdbdbdbd CTESTT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003DE4 626c780af70ebdbdbdbd CTESTT dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003DEE 626c780af7cebdbdbdbd CTESTT r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003DF8 626cf80af70ebdbdbdbd CTESTT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E02 626cf80af7cebdbdbdbd CTESTT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E0C 626c790af70ebdbd CTESTT word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003E14 626c790af7cebdbd CTESTT r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003E1C 626cf90af70ebdbdbdbd CTESTT qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E26 626cf90af7cebdbdbdbd CTESTT r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + Entire register + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E30 626c7804841e CTESTZ byte ptr [r22], r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E36 626c780484de CTESTZ r22b, r27b, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E3C 626cf804841e CTESTZ byte ptr [r22], r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E42 626cf80484de CTESTZ r22b, r27b, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E48 626c7804851e CTESTZ dword ptr [r22], r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E4E 626c780485de CTESTZ r22d, r27d, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E54 626cf804851e CTESTZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E5A 626cf80485de CTESTZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E60 626c7904851e CTESTZ word ptr [r22], r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003E66 626c790485de CTESTZ r22w, r27w, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003E6C 626cf904851e CTESTZ qword ptr [r22], r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E72 626cf90485de CTESTZ r22, r27, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E78 626c7804f606bd CTESTZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E7F 626c7804f6c6bd CTESTZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E86 626cf804f606bd CTESTZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E8D 626cf804f6c6bd CTESTZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003E94 626c7804f60ebd CTESTZ byte ptr [r22], 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003E9B 626c7804f6cebd CTESTZ r22b, 0xbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003EA2 626cf804f60ebd CTESTZ byte ptr [r22], 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003EA9 626cf804f6cebd CTESTZ r22b, 0xbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003EB0 626c7804f706bdbdbdbd CTESTZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003EBA 626c7804f7c6bdbdbdbd CTESTZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003EC4 626cf804f706bdbdbdbd CTESTZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003ECE 626cf804f7c6bdbdbdbd CTESTZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003ED8 626c7904f706bdbd CTESTZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003EE0 626c7904f7c6bdbd CTESTZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003EE8 626cf904f706bdbdbdbd CTESTZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003EF2 626cf904f7c6bdbdbdbd CTESTZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003EFC 626c7804f70ebdbdbdbd CTESTZ dword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F06 626c7804f7cebdbdbdbd CTESTZ r22d, 0xbdbdbdbd, 0000 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F10 626cf804f70ebdbdbdbd CTESTZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F1A 626cf804f7cebdbdbdbd CTESTZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F24 626c7904f70ebdbd CTESTZ word ptr [r22], 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003F2C 626c7904f7cebdbd CTESTZ r22w, 0xbdbd, 0000 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003F34 626cf904f70ebdbdbdbd CTESTZ qword ptr [r22], 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F3E 626cf904f7cebdbdbdbd CTESTZ r22, 0xbdbdbdbd, 0000 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-CCMP + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Default flags, Size: 0, RawSize: 0, Encoding: V + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F48 626c7808fe0e DEC byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F4E 626c7808fece DEC r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F54 626cf808fe0e DEC byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F5A 626cf808fece DEC r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F60 626c7808ff0e DEC dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F66 626c7808ffce DEC r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003F6C 626cf808ff0e DEC qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F72 626cf808ffce DEC r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F78 626c7908ff0e DEC word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003F7E 626c7908ffce DEC r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000003F84 626cf908ff0e DEC qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F8A 626cf908ffce DEC r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003F90 626c780cfe0e DEC{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000003F96 626c780cfece DEC{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000003F9C 626cf80cfe0e DEC{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000003FA2 626cf80cfece DEC{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000003FA8 626c780cff0e DEC{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000003FAE 626c780cffce DEC{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000003FB4 626cf80cff0e DEC{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000003FBA 626cf80cffce DEC{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000003FC0 626c790cff0e DEC{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000003FC6 626c790cffce DEC{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000003FCC 626cf90cff0e DEC{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000003FD2 626cf90cffce DEC{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000003FD8 626c7818fe0e DEC al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003FDE 626c7818fece DEC al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003FE4 626cf818fe0e DEC al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003FEA 626cf818fece DEC al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000003FF0 626c7818ff0e DEC eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003FF6 626c7818ffce DEC eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000003FFC 626cf818ff0e DEC rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004002 626cf818ffce DEC rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004008 626c7918ff0e DEC ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000400E 626c7918ffce DEC ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004014 626cf918ff0e DEC rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000401A 626cf918ffce DEC rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004020 626c781cfe0e DEC{NF} al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004026 626c781cfece DEC{NF} al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +000000000000402C 626cf81cfe0e DEC{NF} al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004032 626cf81cfece DEC{NF} al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004038 626c781cff0e DEC{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +000000000000403E 626c781cffce DEC{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004044 626cf81cff0e DEC{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000404A 626cf81cffce DEC{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004050 626c791cff0e DEC{NF} ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004056 626c791cffce DEC{NF} ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000405C 626cf91cff0e DEC{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004062 626cf91cffce DEC{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004068 626c7808f636 DIV byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000406E 626c7808f6f6 DIV r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004074 626cf808f636 DIV byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000407A 626cf808f6f6 DIV r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004080 626c7808f736 DIV dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004086 626c7808f7f6 DIV r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000408C 626cf808f736 DIV qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004092 626cf808f7f6 DIV r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004098 626c7908f736 DIV word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000409E 626c7908f7f6 DIV r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000040A4 626cf908f736 DIV qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000040AA 626cf908f7f6 DIV r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000040B0 626c780cf636 DIV{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +00000000000040B6 626c780cf6f6 DIV{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +00000000000040BC 626cf80cf636 DIV{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +00000000000040C2 626cf80cf6f6 DIV{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +00000000000040C8 626c780cf736 DIV{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +00000000000040CE 626c780cf7f6 DIV{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +00000000000040D4 626cf80cf736 DIV{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000040DA 626cf80cf7f6 DIV{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000040E0 626c790cf736 DIV{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000040E6 626c790cf7f6 DIV{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000040EC 626cf90cf736 DIV{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000040F2 626cf90cf7f6 DIV{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000040F8 626c7a08dade ENCODEKEY128 r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 3 + Operand: 4, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 3 + Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000040FE 626cfa08dade ENCODEKEY128 r27d, r22d + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 3 + Operand: 4, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 4, RegCount: 3 + Operand: 5, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004104 626c7a08dbde ENCODEKEY256 r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 2 + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 5 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000410A 626cfa08dbde ENCODEKEY256 r27d, r22d + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AESKL, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KEYLOCKER + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: 0, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 2 + Operand: 3, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 2, RegCount: 5 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004110 626c7b08f81e ENQCMD [r27], zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ENQCMD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-ENQCMD + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004116 626cfb08f81e ENQCMD [r27], zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ENQCMD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-ENQCMD + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000411C 626c7a08f81e ENQCMDS [r27], zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ENQCMD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-ENQCMD + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004122 626cfa08f81e ENQCMDS [r27], zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ENQCMD, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-ENQCMD + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: -1, RawSize: -1, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004128 626c7808f63e IDIV byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000412E 626c7808f6fe IDIV r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004134 626cf808f63e IDIV byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000413A 626cf808f6fe IDIV r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004140 626c7808f73e IDIV dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004146 626c7808f7fe IDIV r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000414C 626cf808f73e IDIV qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004152 626cf808f7fe IDIV r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004158 626c7908f73e IDIV word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000415E 626c7908f7fe IDIV r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004164 626cf908f73e IDIV qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000416A 626cf908f7fe IDIV r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: u, AF: u, ZF: u, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004170 626c780cf63e IDIV{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +0000000000004176 626c780cf6fe IDIV{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +000000000000417C 626cf80cf63e IDIV{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +0000000000004182 626cf80cf6fe IDIV{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 4, RegCount: 1 + +0000000000004188 626c780cf73e IDIV{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000418E 626c780cf7fe IDIV{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000004194 626cf80cf73e IDIV{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +000000000000419A 626cf80cf7fe IDIV{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000041A0 626c790cf73e IDIV{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000041A6 626c790cf7fe IDIV{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000041AC 626cf90cf73e IDIV{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000041B2 626cf90cf7fe IDIV{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000041B8 626c7808691ebdbdbdbd IMUL r27d, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000041C2 626c780869debdbdbdbd IMUL r27d, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000041CC 626cf808691ebdbdbdbd IMUL r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000041D6 626cf80869debdbdbdbd IMUL r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000041E0 626c7908691ebdbd IMUL r27w, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000041E8 626c790869debdbd IMUL r27w, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000041F0 626cf908691ebdbdbdbd IMUL r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000041FA 626cf90869debdbdbdbd IMUL r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004204 626c78086b1ebd IMUL r27d, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000420B 626c78086bdebd IMUL r27d, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004212 626cf8086b1ebd IMUL r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004219 626cf8086bdebd IMUL r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004220 626c79086b1ebd IMUL r27w, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004227 626c79086bdebd IMUL r27w, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000422E 626cf9086b1ebd IMUL r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004235 626cf9086bdebd IMUL r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000423C 626c780c691ebdbdbdbd IMUL{NF} r27d, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004246 626c780c69debdbdbdbd IMUL{NF} r27d, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004250 626cf80c691ebdbdbdbd IMUL{NF} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000425A 626cf80c69debdbdbdbd IMUL{NF} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004264 626c790c691ebdbd IMUL{NF} r27w, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +000000000000426C 626c790c69debdbd IMUL{NF} r27w, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004274 626cf90c691ebdbdbdbd IMUL{NF} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000427E 626cf90c69debdbdbdbd IMUL{NF} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004288 626c780c6b1ebd IMUL{NF} r27d, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000428F 626c780c6bdebd IMUL{NF} r27d, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004296 626cf80c6b1ebd IMUL{NF} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000429D 626cf80c6bdebd IMUL{NF} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000042A4 626c790c6b1ebd IMUL{NF} r27w, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000042AB 626c790c6bdebd IMUL{NF} r27w, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000042B2 626cf90c6b1ebd IMUL{NF} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000042B9 626cf90c6bdebd IMUL{NF} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000042C0 626c7818691ebdbdbdbd IMUL{ZU} r27d, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000042CA 626c781869debdbdbdbd IMUL{ZU} r27d, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000042D4 626cf818691ebdbdbdbd IMUL{ZU} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000042DE 626cf81869debdbdbdbd IMUL{ZU} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000042E8 626c7918691ebdbd IMUL{ZU} r27w, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000042F0 626c791869debdbd IMUL{ZU} r27w, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000042F8 626cf918691ebdbdbdbd IMUL{ZU} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004302 626cf91869debdbdbdbd IMUL{ZU} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000430C 626c78186b1ebd IMUL{ZU} r27d, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004313 626c78186bdebd IMUL{ZU} r27d, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000431A 626cf8186b1ebd IMUL{ZU} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004321 626cf8186bdebd IMUL{ZU} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004328 626c79186b1ebd IMUL{ZU} r27w, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000432F 626c79186bdebd IMUL{ZU} r27w, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004336 626cf9186b1ebd IMUL{ZU} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000433D 626cf9186bdebd IMUL{ZU} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004344 626c781c691ebdbdbdbd IMUL{NF}{ZU} r27d, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000434E 626c781c69debdbdbdbd IMUL{NF}{ZU} r27d, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004358 626cf81c691ebdbdbdbd IMUL{NF}{ZU} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004362 626cf81c69debdbdbdbd IMUL{NF}{ZU} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000436C 626c791c691ebdbd IMUL{NF}{ZU} r27w, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004374 626c791c69debdbd IMUL{NF}{ZU} r27w, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +000000000000437C 626cf91c691ebdbdbdbd IMUL{NF}{ZU} r27, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004386 626cf91c69debdbdbdbd IMUL{NF}{ZU} r27, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004390 626c781c6b1ebd IMUL{NF}{ZU} r27d, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004397 626c781c6bdebd IMUL{NF}{ZU} r27d, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000439E 626cf81c6b1ebd IMUL{NF}{ZU} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043A5 626cf81c6bdebd IMUL{NF}{ZU} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043AC 626c791c6b1ebd IMUL{NF}{ZU} r27w, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043B3 626c791c6bdebd IMUL{NF}{ZU} r27w, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043BA 626cf91c6b1ebd IMUL{NF}{ZU} r27, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043C1 626cf91c6bdebd IMUL{NF}{ZU} r27, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000043C8 626c7808af1e IMUL r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000043CE 626c7808afde IMUL r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000043D4 626cf808af1e IMUL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000043DA 626cf808afde IMUL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000043E0 626c7908af1e IMUL r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000043E6 626c7908afde IMUL r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000043EC 626cf908af1e IMUL r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000043F2 626cf908afde IMUL r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000043F8 626c7808f62e IMUL byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000043FE 626c7808f6ee IMUL r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004404 626cf808f62e IMUL byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000440A 626cf808f6ee IMUL r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004410 626c7808f72e IMUL dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004416 626c7808f7ee IMUL r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000441C 626cf808f72e IMUL qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004422 626cf808f7ee IMUL r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004428 626c7908f72e IMUL word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000442E 626c7908f7ee IMUL r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004434 626cf908f72e IMUL qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000443A 626cf908f7ee IMUL r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004440 626c780caf1e IMUL{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004446 626c780cafde IMUL{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +000000000000444C 626cf80caf1e IMUL{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004452 626cf80cafde IMUL{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004458 626c790caf1e IMUL{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +000000000000445E 626c790cafde IMUL{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000004464 626cf90caf1e IMUL{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000446A 626cf90cafde IMUL{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004470 626c780cf62e IMUL{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004476 626c780cf6ee IMUL{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000447C 626cf80cf62e IMUL{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004482 626cf80cf6ee IMUL{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004488 626c780cf72e IMUL{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000448E 626c780cf7ee IMUL{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000004494 626cf80cf72e IMUL{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +000000000000449A 626cf80cf7ee IMUL{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000044A0 626c790cf72e IMUL{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000044A6 626c790cf7ee IMUL{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +00000000000044AC 626cf90cf72e IMUL{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000044B2 626cf90cf7ee IMUL{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +00000000000044B8 626c7818af1e IMUL eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000044BE 626c7818afde IMUL eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000044C4 626cf818af1e IMUL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000044CA 626cf818afde IMUL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000044D0 626c7918af1e IMUL ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000044D6 626c7918afde IMUL ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000044DC 626cf918af1e IMUL rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000044E2 626cf918afde IMUL rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000044E8 626c781caf1e IMUL{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +00000000000044EE 626c781cafde IMUL{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +00000000000044F4 626cf81caf1e IMUL{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000044FA 626cf81cafde IMUL{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004500 626c791caf1e IMUL{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004506 626c791cafde IMUL{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000450C 626cf91caf1e IMUL{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004512 626cf91cafde IMUL{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004518 626c7808fe06 INC byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000451E 626c7808fec6 INC r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004524 626cf808fe06 INC byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000452A 626cf808fec6 INC r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004530 626c7808ff06 INC dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004536 626c7808ffc6 INC r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000453C 626cf808ff06 INC qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004542 626cf808ffc6 INC r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004548 626c7908ff06 INC word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000454E 626c7908ffc6 INC r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004554 626cf908ff06 INC qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000455A 626cf908ffc6 INC r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004560 626c780cfe06 INC{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004566 626c780cfec6 INC{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +000000000000456C 626cf80cfe06 INC{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004572 626cf80cfec6 INC{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004578 626c780cff06 INC{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +000000000000457E 626c780cffc6 INC{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004584 626cf80cff06 INC{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000458A 626cf80cffc6 INC{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004590 626c790cff06 INC{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004596 626c790cffc6 INC{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000459C 626cf90cff06 INC{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000045A2 626cf90cffc6 INC{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000045A8 626c7818fe06 INC al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000045AE 626c7818fec6 INC al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000045B4 626cf818fe06 INC al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045BA 626cf818fec6 INC al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045C0 626c7818ff06 INC eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000045C6 626c7818ffc6 INC eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000045CC 626cf818ff06 INC rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045D2 626cf818ffc6 INC rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045D8 626c7918ff06 INC ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000045DE 626c7918ffc6 INC ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000045E4 626cf918ff06 INC rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045EA 626cf918ffc6 INC rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000045F0 626c781cfe06 INC{NF} al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000045F6 626c781cfec6 INC{NF} al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000045FC 626cf81cfe06 INC{NF} al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004602 626cf81cfec6 INC{NF} al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004608 626c781cff06 INC{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +000000000000460E 626c781cffc6 INC{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004614 626cf81cff06 INC{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000461A 626cf81cffc6 INC{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004620 626c791cff06 INC{NF} ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004626 626c791cffc6 INC{NF} ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000462C 626cf91cff06 INC{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004632 626cf91cffc6 INC{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004638 626c7a08f01e INVEPT r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: VTX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVEPT + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000463E 626cfa08f01e INVEPT r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: VTX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVEPT + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004644 626c7a08f21e INVPCID r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVPCID + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +000000000000464A 626cfa08f21e INVPCID r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MISC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVPCID + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000004650 626c7a08f11e INVVPID r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: VTX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVVPID + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004656 626cfa08f11e INVVPID r27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: VTX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INVVPID + FLAGS access + CF: m, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: no, Long: yes + SMM on: no, SMM off: yes, SGX on: no, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: no, VMXRoot SEAM: yes, VMXNonRoot SEAM: no, VMX off: no + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000465C 62f97908901e KMOVB k3, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004662 62f9790890de KMOVB k3, k6 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +0000000000004668 62f97908911e KMOVB byte ptr [r22], k3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +000000000000466E 62f9790892de KMOVB k3, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004674 62f9790893de KMOVB ebx, k6 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +000000000000467A 62f9f908901e KMOVD k3, dword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004680 62f9f90890de KMOVD k3, k6 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +0000000000004686 62f9f908911e KMOVD dword ptr [r22], k3 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +000000000000468C 62f97b0892de KMOVD k3, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004692 62f97b0893de KMOVD ebx, k6 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +0000000000004698 62f9f808901e KMOVQ k3, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000469E 62f9f80890de KMOVQ k3, k6 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +00000000000046A4 62f9f808911e KMOVQ qword ptr [r22], k3 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +00000000000046AA 62f9fb0892de KMOVQ k3, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000046B0 62f9fb0893de KMOVQ rbx, k6 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +00000000000046B6 62f97808901e KMOVW k3, word ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +00000000000046BC 62f9780890de KMOVW k3, k6 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +00000000000046C2 62f97808911e KMOVW word ptr [r22], k3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + +00000000000046C8 62f9780892de KMOVW k3, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: Mask, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +00000000000046CE 62f9780893de KMOVW ebx, k6 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: KMASK, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-KMOV + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: Mask, RegSize: 8, RegId: 6, RegCount: 1 + +00000000000046D4 62fa78084906 LDTILECFG zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: AMX-EVEX-E1 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + +00000000000046DA 626c7808f51e LZCNT r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000046E0 626c7808f5de LZCNT r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000046E6 626cf808f51e LZCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000046EC 626cf808f5de LZCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000046F2 626c7908f51e LZCNT r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000046F8 626c7908f5de LZCNT r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000046FE 626cf908f51e LZCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004704 626cf908f5de LZCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000470A 626c780cf51e LZCNT{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004710 626c780cf5de LZCNT{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004716 626cf80cf51e LZCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000471C 626cf80cf5de LZCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004722 626c790cf51e LZCNT{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004728 626c790cf5de LZCNT{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000472E 626cf90cf51e LZCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004734 626cf90cf5de LZCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LZCNT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +000000000000473A 626c7808601e MOVBE r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004740 626c780860de MOVBE r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004746 626cf808601e MOVBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000474C 626cf80860de MOVBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004752 626c7908601e MOVBE r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004758 626c790860de MOVBE r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000475E 626cf908601e MOVBE r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004764 626cf90860de MOVBE r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +000000000000476A 626c7808611e MOVBE dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004770 626c780861de MOVBE r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004776 626cf808611e MOVBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000477C 626cf80861de MOVBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004782 626c7908611e MOVBE word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000004788 626c790861de MOVBE r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +000000000000478E 626cf908611e MOVBE qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004794 626cf90861de MOVBE r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: DATAXFER, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000479A 626c7908f81e MOVDIR64B zmmword ptr [r27], zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MOVDIR64B, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + +00000000000047A0 626cf908f81e MOVDIR64B zmmword ptr [r27], zmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MOVDIR64B, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: R, + Segment: 0, Base: 27, + Operand: 1, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + +00000000000047A6 626c7808f91e MOVDIRI dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MOVDIRI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +00000000000047AC 626cf808f91e MOVDIRI qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: MOVDIRI, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000047B2 626c7808f626 MUL byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000047B8 626c7808f6e6 MUL r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000047BE 626cf808f626 MUL byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047C4 626cf808f6e6 MUL r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047CA 626c7808f726 MUL dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000047D0 626c7808f7e6 MUL r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000047D6 626cf808f726 MUL qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047DC 626cf808f7e6 MUL r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047E2 626c7908f726 MUL word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000047E8 626c7908f7e6 MUL r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000047EE 626cf908f726 MUL qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047F4 626cf908f7e6 MUL r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: u, SF: u, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000047FA 626c780cf626 MUL{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004800 626c780cf6e6 MUL{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004806 626cf80cf626 MUL{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000480C 626cf80cf6e6 MUL{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004812 626c780cf726 MUL{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000004818 626c780cf7e6 MUL{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000481E 626cf80cf726 MUL{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000004824 626cf80cf7e6 MUL{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +000000000000482A 626c790cf726 MUL{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000004830 626c790cf7e6 MUL{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1 + +0000000000004836 626cf90cf726 MUL{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +000000000000483C 626cf90cf7e6 MUL{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000004842 62fa7b08f61e MULX ebx, eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +0000000000004848 62fa7b08f6de MULX ebx, eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1 + +000000000000484E 62fafb08f61e MULX rbx, rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +0000000000004854 62fafb08f6de MULX rbx, rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1 + +000000000000485A 626c7808f61e NEG byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004860 626c7808f6de NEG r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004866 626cf808f61e NEG byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000486C 626cf808f6de NEG r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004872 626c7808f71e NEG dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004878 626c7808f7de NEG r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000487E 626cf808f71e NEG qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004884 626cf808f7de NEG r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000488A 626c7908f71e NEG word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004890 626c7908f7de NEG r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004896 626cf908f71e NEG qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000489C 626cf908f7de NEG r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000048A2 626c780cf61e NEG{NF} byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000048A8 626c780cf6de NEG{NF} r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000048AE 626cf80cf61e NEG{NF} byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000048B4 626cf80cf6de NEG{NF} r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000048BA 626c780cf71e NEG{NF} dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +00000000000048C0 626c780cf7de NEG{NF} r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +00000000000048C6 626cf80cf71e NEG{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000048CC 626cf80cf7de NEG{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000048D2 626c790cf71e NEG{NF} word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +00000000000048D8 626c790cf7de NEG{NF} r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +00000000000048DE 626cf90cf71e NEG{NF} qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000048E4 626cf90cf7de NEG{NF} r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000048EA 626c7818f61e NEG al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000048F0 626c7818f6de NEG al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000048F6 626cf818f61e NEG al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000048FC 626cf818f6de NEG al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004902 626c7818f71e NEG eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004908 626c7818f7de NEG eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000490E 626cf818f71e NEG rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004914 626cf818f7de NEG rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000491A 626c7918f71e NEG ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004920 626c7918f7de NEG ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004926 626cf918f71e NEG rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000492C 626cf918f7de NEG rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004932 626c781cf61e NEG{NF} al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004938 626c781cf6de NEG{NF} al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +000000000000493E 626cf81cf61e NEG{NF} al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004944 626cf81cf6de NEG{NF} al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +000000000000494A 626c781cf71e NEG{NF} eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004950 626c781cf7de NEG{NF} eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004956 626cf81cf71e NEG{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000495C 626cf81cf7de NEG{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004962 626c791cf71e NEG{NF} ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004968 626c791cf7de NEG{NF} ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000496E 626cf91cf71e NEG{NF} rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004974 626cf91cf7de NEG{NF} rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +000000000000497A 626c7808f616 NOT byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004980 626c7808f6d6 NOT r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004986 626cf808f616 NOT byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +000000000000498C 626cf808f6d6 NOT r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004992 626c7808f716 NOT dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004998 626c7808f7d6 NOT r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +000000000000499E 626cf808f716 NOT qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000049A4 626cf808f7d6 NOT r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000049AA 626c7908f716 NOT word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +00000000000049B0 626c7908f7d6 NOT r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +00000000000049B6 626cf908f716 NOT qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000049BC 626cf908f7d6 NOT r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000049C2 626c7818f616 NOT al, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000049C8 626c7818f6d6 NOT al, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000049CE 626cf818f616 NOT al, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000049D4 626cf818f6d6 NOT al, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000049DA 626c7818f716 NOT eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +00000000000049E0 626c7818f7d6 NOT eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +00000000000049E6 626cf818f716 NOT rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000049EC 626cf818f7d6 NOT rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000049F2 626c7918f716 NOT ax, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +00000000000049F8 626c7918f7d6 NOT ax, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +00000000000049FE 626cf918f716 NOT rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004A04 626cf918f7d6 NOT rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004A0A 626c7808081e OR byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A10 626c780808de OR r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A16 626cf808081e OR byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A1C 626cf80808de OR r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A22 626c7808091e OR dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A28 626c780809de OR r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A2E 626cf808091e OR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A34 626cf80809de OR r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A3A 626c7908091e OR word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004A40 626c790809de OR r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004A46 626cf908091e OR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A4C 626cf90809de OR r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A52 626c78080a1e OR r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A58 626c78080ade OR r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A5E 626cf8080a1e OR r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A64 626cf8080ade OR r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A6A 626c78080b1e OR r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A70 626c78080bde OR r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004A76 626cf8080b1e OR r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A7C 626cf8080bde OR r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A82 626c79080b1e OR r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004A88 626c79080bde OR r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004A8E 626cf9080b1e OR r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A94 626cf9080bde OR r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004A9A 626c7808800ebd OR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004AA1 626c780880cebd OR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004AA8 626cf808800ebd OR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004AAF 626cf80880cebd OR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004AB6 626c7808810ebdbdbdbd OR dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004AC0 626c780881cebdbdbdbd OR r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004ACA 626cf808810ebdbdbdbd OR qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004AD4 626cf80881cebdbdbdbd OR r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004ADE 626c7908810ebdbd OR word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004AE6 626c790881cebdbd OR r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004AEE 626cf908810ebdbdbdbd OR qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004AF8 626cf90881cebdbdbdbd OR r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004B02 626c7808830ebd OR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004B09 626c780883cebd OR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004B10 626cf808830ebd OR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004B17 626cf80883cebd OR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004B1E 626c7908830ebd OR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004B25 626c790883cebd OR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004B2C 626cf908830ebd OR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004B33 626cf90883cebd OR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004B3A 626c780c081e OR{NF} byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004B40 626c780c08de OR{NF} r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004B46 626cf80c081e OR{NF} byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004B4C 626cf80c08de OR{NF} r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004B52 626c780c091e OR{NF} dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004B58 626c780c09de OR{NF} r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004B5E 626cf80c091e OR{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004B64 626cf80c09de OR{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004B6A 626c790c091e OR{NF} word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000004B70 626c790c09de OR{NF} r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000004B76 626cf90c091e OR{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004B7C 626cf90c09de OR{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004B82 626c780c0a1e OR{NF} r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004B88 626c780c0ade OR{NF} r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004B8E 626cf80c0a1e OR{NF} r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004B94 626cf80c0ade OR{NF} r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004B9A 626c780c0b1e OR{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004BA0 626c780c0bde OR{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004BA6 626cf80c0b1e OR{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004BAC 626cf80c0bde OR{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004BB2 626c790c0b1e OR{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004BB8 626c790c0bde OR{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000004BBE 626cf90c0b1e OR{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004BC4 626cf90c0bde OR{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004BCA 626c780c800ebd OR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004BD1 626c780c80cebd OR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004BD8 626cf80c800ebd OR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004BDF 626cf80c80cebd OR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004BE6 626c780c810ebdbdbdbd OR{NF} dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004BF0 626c780c81cebdbdbdbd OR{NF} r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004BFA 626cf80c810ebdbdbdbd OR{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004C04 626cf80c81cebdbdbdbd OR{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004C0E 626c790c810ebdbd OR{NF} word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004C16 626c790c81cebdbd OR{NF} r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004C1E 626cf90c810ebdbdbdbd OR{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004C28 626cf90c81cebdbdbdbd OR{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004C32 626c780c830ebd OR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C39 626c780c83cebd OR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C40 626cf80c830ebd OR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C47 626cf80c83cebd OR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C4E 626c790c830ebd OR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C55 626c790c83cebd OR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C5C 626cf90c830ebd OR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C63 626cf90c83cebd OR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004C6A 626c7818081e OR al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004C70 626c781808de OR al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004C76 626cf818081e OR al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004C7C 626cf81808de OR al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004C82 626c7818091e OR eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004C88 626c781809de OR eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004C8E 626cf818091e OR rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004C94 626cf81809de OR rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004C9A 626c7918091e OR ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004CA0 626c791809de OR ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004CA6 626cf918091e OR rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CAC 626cf91809de OR rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CB2 626c78180a1e OR al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004CB8 626c78180ade OR al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004CBE 626cf8180a1e OR al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CC4 626cf8180ade OR al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CCA 626c78180b1e OR eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004CD0 626c78180bde OR eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004CD6 626cf8180b1e OR rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CDC 626cf8180bde OR rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CE2 626c79180b1e OR ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004CE8 626c79180bde OR ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004CEE 626cf9180b1e OR rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CF4 626cf9180bde OR rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004CFA 626c7818800ebd OR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D01 626c781880cebd OR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D08 626cf818800ebd OR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D0F 626cf81880cebd OR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D16 626c7818810ebdbdbdbd OR eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D20 626c781881cebdbdbdbd OR eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D2A 626cf818810ebdbdbdbd OR rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D34 626cf81881cebdbdbdbd OR rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D3E 626c7918810ebdbd OR ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004D46 626c791881cebdbd OR ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004D4E 626cf918810ebdbdbdbd OR rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D58 626cf91881cebdbdbdbd OR rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D62 626c7818830ebd OR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D69 626c781883cebd OR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004D70 626cf818830ebd OR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D77 626cf81883cebd OR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D7E 626c7918830ebd OR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004D85 626c791883cebd OR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004D8C 626cf918830ebd OR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D93 626cf91883cebd OR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004D9A 626c781c081e OR{NF} al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004DA0 626c781c08de OR{NF} al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004DA6 626cf81c081e OR{NF} al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004DAC 626cf81c08de OR{NF} al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000004DB2 626c781c091e OR{NF} eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004DB8 626c781c09de OR{NF} eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000004DBE 626cf81c091e OR{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004DC4 626cf81c09de OR{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004DCA 626c791c091e OR{NF} ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000004DD0 626c791c09de OR{NF} ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000004DD6 626cf91c091e OR{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004DDC 626cf91c09de OR{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000004DE2 626c781c0a1e OR{NF} al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004DE8 626c781c0ade OR{NF} al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004DEE 626cf81c0a1e OR{NF} al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000004DF4 626cf81c0ade OR{NF} al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000004DFA 626c781c0b1e OR{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004E00 626c781c0bde OR{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004E06 626cf81c0b1e OR{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004E0C 626cf81c0bde OR{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004E12 626c791c0b1e OR{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004E18 626c791c0bde OR{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000004E1E 626cf91c0b1e OR{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004E24 626cf91c0bde OR{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004E2A 626c781c800ebd OR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004E31 626c781c80cebd OR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004E38 626cf81c800ebd OR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004E3F 626cf81c80cebd OR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004E46 626c781c810ebdbdbdbd OR{NF} eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E50 626c781c81cebdbdbdbd OR{NF} eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E5A 626cf81c810ebdbdbdbd OR{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E64 626cf81c81cebdbdbdbd OR{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E6E 626c791c810ebdbd OR{NF} ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004E76 626c791c81cebdbd OR{NF} ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000004E7E 626cf91c810ebdbdbdbd OR{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E88 626cf91c81cebdbdbdbd OR{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000004E92 626c781c830ebd OR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004E99 626c781c83cebd OR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EA0 626cf81c830ebd OR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EA7 626cf81c83cebd OR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EAE 626c791c830ebd OR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EB5 626c791c83cebd OR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EBC 626cf91c830ebd OR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004EC3 626cf91c83cebd OR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000004ECA 62fa7b08f51e PDEP ebx, eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004ED0 62fa7b08f5de PDEP ebx, eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004ED6 62fafb08f51e PDEP rbx, rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004EDC 62fafb08f5de PDEP rbx, rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004EE2 62fa7a08f51e PEXT ebx, eax, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004EE8 62fa7a08f5de PEXT ebx, eax, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004EEE 62fafa08f51e PEXT rbx, rax, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004EF4 62fafa08f5de PEXT rbx, rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004EFA 626c78188fc6 POP2 rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: POP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-PP2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000004F00 626cf8188fc6 POP2P rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: POP, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-PP2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000004F06 626c7808881e POPCNT r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F0C 626c780888de POPCNT r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F12 626cf808881e POPCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F18 626cf80888de POPCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F1E 626c7908881e POPCNT r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004F24 626c790888de POPCNT r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004F2A 626cf908881e POPCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F30 626cf90888de POPCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: 0, AF: 0, ZF: m, SF: 0, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F36 626c780c881e POPCNT{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000004F3C 626c780c88de POPCNT{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000004F42 626cf80c881e POPCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004F48 626cf80c88de POPCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004F4E 626c790c881e POPCNT{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000004F54 626c790c88de POPCNT{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000004F5A 626cf90c881e POPCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000004F60 626cf90c88de POPCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: APX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000004F66 626c7818fff6 PUSH2 rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: PUSH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-PP2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000004F6C 626cf818fff6 PUSH2P rax, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: PUSH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-PP2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Memory, Size: 16, RawSize: 16, Encoding: S, Stack: yes, + Segment: 2, Base: 4, + +0000000000004F72 626c7808c016bd RCL byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F79 626c7808c0d6bd RCL r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F80 626cf808c016bd RCL byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F87 626cf808c0d6bd RCL r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004F8E 626c7808c116bd RCL dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F95 626c7808c1d6bd RCL r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004F9C 626cf808c116bd RCL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FA3 626cf808c1d6bd RCL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FAA 626c7908c116bd RCL word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004FB1 626c7908c1d6bd RCL r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004FB8 626cf908c116bd RCL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FBF 626cf908c1d6bd RCL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FC6 626c7808d016 RCL byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004FCC 626c7808d0d6 RCL r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004FD2 626cf808d016 RCL byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FD8 626cf808d0d6 RCL r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FDE 626c7808d116 RCL dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004FE4 626c7808d1d6 RCL r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000004FEA 626cf808d116 RCL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FF0 626cf808d1d6 RCL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000004FF6 626c7908d116 RCL word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000004FFC 626c7908d1d6 RCL r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005002 626cf908d116 RCL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005008 626cf908d1d6 RCL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000500E 626c7808d216 RCL byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005014 626c7808d2d6 RCL r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000501A 626cf808d216 RCL byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005020 626cf808d2d6 RCL r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005026 626c7808d316 RCL dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000502C 626c7808d3d6 RCL r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005032 626cf808d316 RCL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005038 626cf808d3d6 RCL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000503E 626c7908d316 RCL word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005044 626c7908d3d6 RCL r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000504A 626cf908d316 RCL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005050 626cf908d3d6 RCL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005056 626c780cc016bd RCL{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000505D 626c780cc0d6bd RCL{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005064 626cf80cc016bd RCL{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000506B 626cf80cc0d6bd RCL{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005072 626c780cc116bd RCL{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005079 626c780cc1d6bd RCL{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005080 626cf80cc116bd RCL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005087 626cf80cc1d6bd RCL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000508E 626c790cc116bd RCL{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005095 626c790cc1d6bd RCL{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000509C 626cf90cc116bd RCL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000050A3 626cf90cc1d6bd RCL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000050AA 626c780cd016 RCL{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050B0 626c780cd0d6 RCL{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050B6 626cf80cd016 RCL{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050BC 626cf80cd0d6 RCL{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050C2 626c780cd116 RCL{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050C8 626c780cd1d6 RCL{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050CE 626cf80cd116 RCL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050D4 626cf80cd1d6 RCL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050DA 626c790cd116 RCL{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050E0 626c790cd1d6 RCL{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050E6 626cf90cd116 RCL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050EC 626cf90cd1d6 RCL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000050F2 626c780cd216 RCL{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000050F8 626c780cd2d6 RCL{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000050FE 626cf80cd216 RCL{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005104 626cf80cd2d6 RCL{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000510A 626c780cd316 RCL{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005110 626c780cd3d6 RCL{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005116 626cf80cd316 RCL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000511C 626cf80cd3d6 RCL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005122 626c790cd316 RCL{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005128 626c790cd3d6 RCL{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000512E 626cf90cd316 RCL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005134 626cf90cd3d6 RCL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000513A 626c7818c016bd RCL al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005141 626c7818c0d6bd RCL al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005148 626cf818c016bd RCL al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000514F 626cf818c0d6bd RCL al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005156 626c7818c116bd RCL eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000515D 626c7818c1d6bd RCL eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005164 626cf818c116bd RCL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000516B 626cf818c1d6bd RCL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005172 626c7918c116bd RCL ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005179 626c7918c1d6bd RCL ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005180 626cf918c116bd RCL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005187 626cf918c1d6bd RCL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000518E 626c7818d016 RCL al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005194 626c7818d0d6 RCL al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000519A 626cf818d016 RCL al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051A0 626cf818d0d6 RCL al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051A6 626c7818d116 RCL eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051AC 626c7818d1d6 RCL eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051B2 626cf818d116 RCL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051B8 626cf818d1d6 RCL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051BE 626c7918d116 RCL ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000051C4 626c7918d1d6 RCL ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000051CA 626cf918d116 RCL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051D0 626cf918d1d6 RCL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051D6 626c7818d216 RCL al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051DC 626c7818d2d6 RCL al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051E2 626cf818d216 RCL al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051E8 626cf818d2d6 RCL al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000051EE 626c7818d316 RCL eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051F4 626c7818d3d6 RCL eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000051FA 626cf818d316 RCL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005200 626cf818d3d6 RCL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005206 626c7918d316 RCL ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000520C 626c7918d3d6 RCL ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005212 626cf918d316 RCL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005218 626cf918d3d6 RCL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000521E 626c781cc016bd RCL{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005225 626c781cc0d6bd RCL{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000522C 626cf81cc016bd RCL{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005233 626cf81cc0d6bd RCL{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000523A 626c781cc116bd RCL{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005241 626c781cc1d6bd RCL{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005248 626cf81cc116bd RCL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000524F 626cf81cc1d6bd RCL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005256 626c791cc116bd RCL{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000525D 626c791cc1d6bd RCL{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005264 626cf91cc116bd RCL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000526B 626cf91cc1d6bd RCL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005272 626c781cd016 RCL{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005278 626c781cd0d6 RCL{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000527E 626cf81cd016 RCL{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005284 626cf81cd0d6 RCL{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000528A 626c781cd116 RCL{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005290 626c781cd1d6 RCL{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005296 626cf81cd116 RCL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000529C 626cf81cd1d6 RCL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000052A2 626c791cd116 RCL{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000052A8 626c791cd1d6 RCL{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000052AE 626cf91cd116 RCL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000052B4 626cf91cd1d6 RCL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000052BA 626c781cd216 RCL{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052C0 626c781cd2d6 RCL{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052C6 626cf81cd216 RCL{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052CC 626cf81cd2d6 RCL{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052D2 626c781cd316 RCL{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052D8 626c781cd3d6 RCL{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052DE 626cf81cd316 RCL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052E4 626cf81cd3d6 RCL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052EA 626c791cd316 RCL{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052F0 626c791cd3d6 RCL{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052F6 626cf91cd316 RCL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000052FC 626cf91cd3d6 RCL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005302 626c7808c01ebd RCR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005309 626c7808c0debd RCR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005310 626cf808c01ebd RCR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005317 626cf808c0debd RCR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000531E 626c7808c11ebd RCR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005325 626c7808c1debd RCR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000532C 626cf808c11ebd RCR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005333 626cf808c1debd RCR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000533A 626c7908c11ebd RCR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005341 626c7908c1debd RCR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005348 626cf908c11ebd RCR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000534F 626cf908c1debd RCR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005356 626c7808d01e RCR byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000535C 626c7808d0de RCR r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005362 626cf808d01e RCR byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005368 626cf808d0de RCR r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000536E 626c7808d11e RCR dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005374 626c7808d1de RCR r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000537A 626cf808d11e RCR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005380 626cf808d1de RCR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005386 626c7908d11e RCR word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000538C 626c7908d1de RCR r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005392 626cf908d11e RCR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005398 626cf908d1de RCR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000539E 626c7808d21e RCR byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000053A4 626c7808d2de RCR r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000053AA 626cf808d21e RCR byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053B0 626cf808d2de RCR r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053B6 626c7808d31e RCR dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000053BC 626c7808d3de RCR r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000053C2 626cf808d31e RCR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053C8 626cf808d3de RCR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053CE 626c7908d31e RCR word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000053D4 626c7908d3de RCR r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000053DA 626cf908d31e RCR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053E0 626cf908d3de RCR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000053E6 626c780cc01ebd RCR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000053ED 626c780cc0debd RCR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000053F4 626cf80cc01ebd RCR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000053FB 626cf80cc0debd RCR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005402 626c780cc11ebd RCR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005409 626c780cc1debd RCR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005410 626cf80cc11ebd RCR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005417 626cf80cc1debd RCR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000541E 626c790cc11ebd RCR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005425 626c790cc1debd RCR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000542C 626cf90cc11ebd RCR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005433 626cf90cc1debd RCR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000543A 626c780cd01e RCR{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005440 626c780cd0de RCR{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005446 626cf80cd01e RCR{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000544C 626cf80cd0de RCR{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005452 626c780cd11e RCR{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005458 626c780cd1de RCR{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000545E 626cf80cd11e RCR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005464 626cf80cd1de RCR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000546A 626c790cd11e RCR{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005470 626c790cd1de RCR{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005476 626cf90cd11e RCR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000547C 626cf90cd1de RCR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005482 626c780cd21e RCR{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005488 626c780cd2de RCR{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000548E 626cf80cd21e RCR{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005494 626cf80cd2de RCR{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000549A 626c780cd31e RCR{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054A0 626c780cd3de RCR{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054A6 626cf80cd31e RCR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054AC 626cf80cd3de RCR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054B2 626c790cd31e RCR{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054B8 626c790cd3de RCR{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054BE 626cf90cd31e RCR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054C4 626cf90cd3de RCR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000054CA 626c7818c01ebd RCR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000054D1 626c7818c0debd RCR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000054D8 626cf818c01ebd RCR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000054DF 626cf818c0debd RCR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000054E6 626c7818c11ebd RCR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000054ED 626c7818c1debd RCR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000054F4 626cf818c11ebd RCR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000054FB 626cf818c1debd RCR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005502 626c7918c11ebd RCR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005509 626c7918c1debd RCR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005510 626cf918c11ebd RCR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005517 626cf918c1debd RCR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000551E 626c7818d01e RCR al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005524 626c7818d0de RCR al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000552A 626cf818d01e RCR al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005530 626cf818d0de RCR al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005536 626c7818d11e RCR eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000553C 626c7818d1de RCR eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005542 626cf818d11e RCR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005548 626cf818d1de RCR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000554E 626c7918d11e RCR ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005554 626c7918d1de RCR ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000555A 626cf918d11e RCR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005560 626cf918d1de RCR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005566 626c7818d21e RCR al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000556C 626c7818d2de RCR al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005572 626cf818d21e RCR al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005578 626cf818d2de RCR al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000557E 626c7818d31e RCR eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005584 626c7818d3de RCR eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000558A 626cf818d31e RCR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005590 626cf818d3de RCR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005596 626c7918d31e RCR ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000559C 626c7918d3de RCR ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000055A2 626cf918d31e RCR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000055A8 626cf918d3de RCR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000055AE 626c781cc01ebd RCR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055B5 626c781cc0debd RCR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055BC 626cf81cc01ebd RCR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055C3 626cf81cc0debd RCR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055CA 626c781cc11ebd RCR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055D1 626c781cc1debd RCR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055D8 626cf81cc11ebd RCR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055DF 626cf81cc1debd RCR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055E6 626c791cc11ebd RCR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055ED 626c791cc1debd RCR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055F4 626cf91cc11ebd RCR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000055FB 626cf91cc1debd RCR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005602 626c781cd01e RCR{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005608 626c781cd0de RCR{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000560E 626cf81cd01e RCR{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005614 626cf81cd0de RCR{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000561A 626c781cd11e RCR{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005620 626c781cd1de RCR{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005626 626cf81cd11e RCR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000562C 626cf81cd1de RCR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005632 626c791cd11e RCR{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005638 626c791cd1de RCR{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000563E 626cf91cd11e RCR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005644 626cf91cd1de RCR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000564A 626c781cd21e RCR{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005650 626c781cd2de RCR{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005656 626cf81cd21e RCR{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000565C 626cf81cd2de RCR{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005662 626c781cd31e RCR{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005668 626c781cd3de RCR{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000566E 626cf81cd31e RCR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005674 626cf81cd3de RCR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000567A 626c791cd31e RCR{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005680 626c791cd3de RCR{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005686 626cf91cd31e RCR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000568C 626cf91cd3de RCR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005692 626c7808c006bd ROL byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005699 626c7808c0c6bd ROL r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000056A0 626cf808c006bd ROL byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056A7 626cf808c0c6bd ROL r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056AE 626c7808c106bd ROL dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000056B5 626c7808c1c6bd ROL r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000056BC 626cf808c106bd ROL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056C3 626cf808c1c6bd ROL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056CA 626c7908c106bd ROL word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000056D1 626c7908c1c6bd ROL r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000056D8 626cf908c106bd ROL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056DF 626cf908c1c6bd ROL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056E6 626c7808d006 ROL byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000056EC 626c7808d0c6 ROL r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000056F2 626cf808d006 ROL byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056F8 626cf808d0c6 ROL r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000056FE 626c7808d106 ROL dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005704 626c7808d1c6 ROL r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000570A 626cf808d106 ROL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005710 626cf808d1c6 ROL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005716 626c7908d106 ROL word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000571C 626c7908d1c6 ROL r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005722 626cf908d106 ROL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005728 626cf908d1c6 ROL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000572E 626c7808d206 ROL byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005734 626c7808d2c6 ROL r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000573A 626cf808d206 ROL byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005740 626cf808d2c6 ROL r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005746 626c7808d306 ROL dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000574C 626c7808d3c6 ROL r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005752 626cf808d306 ROL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005758 626cf808d3c6 ROL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000575E 626c7908d306 ROL word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005764 626c7908d3c6 ROL r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000576A 626cf908d306 ROL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005770 626cf908d3c6 ROL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005776 626c780cc006bd ROL{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000577D 626c780cc0c6bd ROL{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005784 626cf80cc006bd ROL{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000578B 626cf80cc0c6bd ROL{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005792 626c780cc106bd ROL{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005799 626c780cc1c6bd ROL{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057A0 626cf80cc106bd ROL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057A7 626cf80cc1c6bd ROL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057AE 626c790cc106bd ROL{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057B5 626c790cc1c6bd ROL{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057BC 626cf90cc106bd ROL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057C3 626cf90cc1c6bd ROL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000057CA 626c780cd006 ROL{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057D0 626c780cd0c6 ROL{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057D6 626cf80cd006 ROL{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057DC 626cf80cd0c6 ROL{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057E2 626c780cd106 ROL{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057E8 626c780cd1c6 ROL{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057EE 626cf80cd106 ROL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057F4 626cf80cd1c6 ROL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000057FA 626c790cd106 ROL{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005800 626c790cd1c6 ROL{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005806 626cf90cd106 ROL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000580C 626cf90cd1c6 ROL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005812 626c780cd206 ROL{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005818 626c780cd2c6 ROL{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000581E 626cf80cd206 ROL{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005824 626cf80cd2c6 ROL{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000582A 626c780cd306 ROL{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005830 626c780cd3c6 ROL{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005836 626cf80cd306 ROL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000583C 626cf80cd3c6 ROL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005842 626c790cd306 ROL{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005848 626c790cd3c6 ROL{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000584E 626cf90cd306 ROL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005854 626cf90cd3c6 ROL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000585A 626c7818c006bd ROL al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005861 626c7818c0c6bd ROL al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005868 626cf818c006bd ROL al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000586F 626cf818c0c6bd ROL al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005876 626c7818c106bd ROL eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000587D 626c7818c1c6bd ROL eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005884 626cf818c106bd ROL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000588B 626cf818c1c6bd ROL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005892 626c7918c106bd ROL ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005899 626c7918c1c6bd ROL ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000058A0 626cf918c106bd ROL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058A7 626cf918c1c6bd ROL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058AE 626c7818d006 ROL al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000058B4 626c7818d0c6 ROL al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000058BA 626cf818d006 ROL al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058C0 626cf818d0c6 ROL al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058C6 626c7818d106 ROL eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000058CC 626c7818d1c6 ROL eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000058D2 626cf818d106 ROL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058D8 626cf818d1c6 ROL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058DE 626c7918d106 ROL ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000058E4 626c7918d1c6 ROL ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000058EA 626cf918d106 ROL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058F0 626cf918d1c6 ROL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000058F6 626c7818d206 ROL al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000058FC 626c7818d2c6 ROL al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005902 626cf818d206 ROL al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005908 626cf818d2c6 ROL al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000590E 626c7818d306 ROL eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005914 626c7818d3c6 ROL eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000591A 626cf818d306 ROL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005920 626cf818d3c6 ROL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005926 626c7918d306 ROL ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000592C 626c7918d3c6 ROL ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005932 626cf918d306 ROL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005938 626cf918d3c6 ROL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000593E 626c781cc006bd ROL{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005945 626c781cc0c6bd ROL{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000594C 626cf81cc006bd ROL{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005953 626cf81cc0c6bd ROL{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000595A 626c781cc106bd ROL{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005961 626c781cc1c6bd ROL{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005968 626cf81cc106bd ROL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000596F 626cf81cc1c6bd ROL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005976 626c791cc106bd ROL{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000597D 626c791cc1c6bd ROL{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005984 626cf91cc106bd ROL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000598B 626cf91cc1c6bd ROL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005992 626c781cd006 ROL{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005998 626c781cd0c6 ROL{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000599E 626cf81cd006 ROL{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059A4 626cf81cd0c6 ROL{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059AA 626c781cd106 ROL{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059B0 626c781cd1c6 ROL{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059B6 626cf81cd106 ROL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059BC 626cf81cd1c6 ROL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059C2 626c791cd106 ROL{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059C8 626c791cd1c6 ROL{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059CE 626cf91cd106 ROL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059D4 626cf91cd1c6 ROL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000059DA 626c781cd206 ROL{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059E0 626c781cd2c6 ROL{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059E6 626cf81cd206 ROL{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059EC 626cf81cd2c6 ROL{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059F2 626c781cd306 ROL{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059F8 626c781cd3c6 ROL{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000059FE 626cf81cd306 ROL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A04 626cf81cd3c6 ROL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A0A 626c791cd306 ROL{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A10 626c791cd3c6 ROL{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A16 626cf91cd306 ROL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A1C 626cf91cd3c6 ROL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005A22 626c7808c00ebd ROR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A29 626c7808c0cebd ROR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A30 626cf808c00ebd ROR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A37 626cf808c0cebd ROR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A3E 626c7808c10ebd ROR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A45 626c7808c1cebd ROR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A4C 626cf808c10ebd ROR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A53 626cf808c1cebd ROR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A5A 626c7908c10ebd ROR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005A61 626c7908c1cebd ROR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005A68 626cf908c10ebd ROR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A6F 626cf908c1cebd ROR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A76 626c7808d00e ROR byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A7C 626c7808d0ce ROR r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A82 626cf808d00e ROR byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A88 626cf808d0ce ROR r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005A8E 626c7808d10e ROR dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A94 626c7808d1ce ROR r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005A9A 626cf808d10e ROR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AA0 626cf808d1ce ROR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AA6 626c7908d10e ROR word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005AAC 626c7908d1ce ROR r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005AB2 626cf908d10e ROR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AB8 626cf908d1ce ROR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005ABE 626c7808d20e ROR byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005AC4 626c7808d2ce ROR r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005ACA 626cf808d20e ROR byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AD0 626cf808d2ce ROR r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AD6 626c7808d30e ROR dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005ADC 626c7808d3ce ROR r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005AE2 626cf808d30e ROR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AE8 626cf808d3ce ROR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005AEE 626c7908d30e ROR word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005AF4 626c7908d3ce ROR r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005AFA 626cf908d30e ROR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005B00 626cf908d3ce ROR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005B06 626c780cc00ebd ROR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B0D 626c780cc0cebd ROR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B14 626cf80cc00ebd ROR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B1B 626cf80cc0cebd ROR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B22 626c780cc10ebd ROR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B29 626c780cc1cebd ROR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B30 626cf80cc10ebd ROR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B37 626cf80cc1cebd ROR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B3E 626c790cc10ebd ROR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B45 626c790cc1cebd ROR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B4C 626cf90cc10ebd ROR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B53 626cf90cc1cebd ROR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005B5A 626c780cd00e ROR{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B60 626c780cd0ce ROR{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B66 626cf80cd00e ROR{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B6C 626cf80cd0ce ROR{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B72 626c780cd10e ROR{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B78 626c780cd1ce ROR{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B7E 626cf80cd10e ROR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B84 626cf80cd1ce ROR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B8A 626c790cd10e ROR{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B90 626c790cd1ce ROR{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B96 626cf90cd10e ROR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005B9C 626cf90cd1ce ROR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005BA2 626c780cd20e ROR{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BA8 626c780cd2ce ROR{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BAE 626cf80cd20e ROR{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BB4 626cf80cd2ce ROR{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BBA 626c780cd30e ROR{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BC0 626c780cd3ce ROR{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BC6 626cf80cd30e ROR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BCC 626cf80cd3ce ROR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BD2 626c790cd30e ROR{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BD8 626c790cd3ce ROR{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BDE 626cf90cd30e ROR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BE4 626cf90cd3ce ROR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005BEA 626c7818c00ebd ROR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005BF1 626c7818c0cebd ROR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005BF8 626cf818c00ebd ROR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005BFF 626cf818c0cebd ROR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C06 626c7818c10ebd ROR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C0D 626c7818c1cebd ROR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C14 626cf818c10ebd ROR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C1B 626cf818c1cebd ROR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C22 626c7918c10ebd ROR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005C29 626c7918c1cebd ROR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005C30 626cf918c10ebd ROR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C37 626cf918c1cebd ROR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C3E 626c7818d00e ROR al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C44 626c7818d0ce ROR al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C4A 626cf818d00e ROR al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C50 626cf818d0ce ROR al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C56 626c7818d10e ROR eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C5C 626c7818d1ce ROR eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C62 626cf818d10e ROR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C68 626cf818d1ce ROR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C6E 626c7918d10e ROR ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005C74 626c7918d1ce ROR ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005C7A 626cf918d10e ROR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C80 626cf918d1ce ROR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C86 626c7818d20e ROR al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C8C 626c7818d2ce ROR al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005C92 626cf818d20e ROR al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C98 626cf818d2ce ROR al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005C9E 626c7818d30e ROR eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005CA4 626c7818d3ce ROR eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005CAA 626cf818d30e ROR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005CB0 626cf818d3ce ROR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005CB6 626c7918d30e ROR ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005CBC 626c7918d3ce ROR ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005CC2 626cf918d30e ROR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005CC8 626cf918d3ce ROR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005CCE 626c781cc00ebd ROR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CD5 626c781cc0cebd ROR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CDC 626cf81cc00ebd ROR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CE3 626cf81cc0cebd ROR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CEA 626c781cc10ebd ROR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CF1 626c781cc1cebd ROR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CF8 626cf81cc10ebd ROR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005CFF 626cf81cc1cebd ROR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005D06 626c791cc10ebd ROR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005D0D 626c791cc1cebd ROR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005D14 626cf91cc10ebd ROR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005D1B 626cf91cc1cebd ROR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005D22 626c781cd00e ROR{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D28 626c781cd0ce ROR{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D2E 626cf81cd00e ROR{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D34 626cf81cd0ce ROR{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D3A 626c781cd10e ROR{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D40 626c781cd1ce ROR{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D46 626cf81cd10e ROR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D4C 626cf81cd1ce ROR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D52 626c791cd10e ROR{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D58 626c791cd1ce ROR{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D5E 626cf91cd10e ROR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D64 626cf91cd1ce ROR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005D6A 626c781cd20e ROR{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D70 626c781cd2ce ROR{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D76 626cf81cd20e ROR{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D7C 626cf81cd2ce ROR{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D82 626c781cd30e ROR{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D88 626c781cd3ce ROR{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D8E 626cf81cd30e ROR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D94 626cf81cd3ce ROR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005D9A 626c791cd30e ROR{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005DA0 626c791cd3ce ROR{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005DA6 626cf91cd30e ROR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005DAC 626cf91cd3ce ROR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ROTATE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005DB2 62fb7b08f01ebd RORX ebx, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005DB9 62fb7b08f0debd RORX ebx, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005DC0 62fbfb08f01ebd RORX rbx, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005DC7 62fbfb08f0debd RORX rbx, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005DCE 626c7808c036bd SAL byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005DD5 626c7808c0f6bd SAL r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005DDC 626cf808c036bd SAL byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005DE3 626cf808c0f6bd SAL r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005DEA 626c7808c136bd SAL dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005DF1 626c7808c1f6bd SAL r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005DF8 626cf808c136bd SAL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005DFF 626cf808c1f6bd SAL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E06 626c7908c136bd SAL word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005E0D 626c7908c1f6bd SAL r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005E14 626cf908c136bd SAL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E1B 626cf908c1f6bd SAL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E22 626c7808d036 SAL byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E28 626c7808d0f6 SAL r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E2E 626cf808d036 SAL byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E34 626cf808d0f6 SAL r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E3A 626c7808d136 SAL dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E40 626c7808d1f6 SAL r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E46 626cf808d136 SAL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E4C 626cf808d1f6 SAL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E52 626c7908d136 SAL word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005E58 626c7908d1f6 SAL r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005E5E 626cf908d136 SAL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E64 626cf908d1f6 SAL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E6A 626c7808d236 SAL byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E70 626c7808d2f6 SAL r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E76 626cf808d236 SAL byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E7C 626cf808d2f6 SAL r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E82 626c7808d336 SAL dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E88 626c7808d3f6 SAL r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005E8E 626cf808d336 SAL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E94 626cf808d3f6 SAL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005E9A 626c7908d336 SAL word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005EA0 626c7908d3f6 SAL r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005EA6 626cf908d336 SAL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005EAC 626cf908d3f6 SAL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005EB2 626c780cc036bd SAL{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EB9 626c780cc0f6bd SAL{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EC0 626cf80cc036bd SAL{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EC7 626cf80cc0f6bd SAL{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005ECE 626c780cc136bd SAL{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005ED5 626c780cc1f6bd SAL{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EDC 626cf80cc136bd SAL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EE3 626cf80cc1f6bd SAL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EEA 626c790cc136bd SAL{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EF1 626c790cc1f6bd SAL{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EF8 626cf90cc136bd SAL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005EFF 626cf90cc1f6bd SAL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000005F06 626c780cd036 SAL{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F0C 626c780cd0f6 SAL{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F12 626cf80cd036 SAL{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F18 626cf80cd0f6 SAL{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F1E 626c780cd136 SAL{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F24 626c780cd1f6 SAL{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F2A 626cf80cd136 SAL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F30 626cf80cd1f6 SAL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F36 626c790cd136 SAL{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F3C 626c790cd1f6 SAL{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F42 626cf90cd136 SAL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F48 626cf90cd1f6 SAL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000005F4E 626c780cd236 SAL{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F54 626c780cd2f6 SAL{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F5A 626cf80cd236 SAL{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F60 626cf80cd2f6 SAL{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F66 626c780cd336 SAL{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F6C 626c780cd3f6 SAL{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F72 626cf80cd336 SAL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F78 626cf80cd3f6 SAL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F7E 626c790cd336 SAL{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F84 626c790cd3f6 SAL{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F8A 626cf90cd336 SAL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F90 626cf90cd3f6 SAL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000005F96 626c7818c036bd SAL al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005F9D 626c7818c0f6bd SAL al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005FA4 626cf818c036bd SAL al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FAB 626cf818c0f6bd SAL al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FB2 626c7818c136bd SAL eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005FB9 626c7818c1f6bd SAL eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005FC0 626cf818c136bd SAL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FC7 626cf818c1f6bd SAL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FCE 626c7918c136bd SAL ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005FD5 626c7918c1f6bd SAL ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000005FDC 626cf918c136bd SAL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FE3 626cf918c1f6bd SAL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FEA 626c7818d036 SAL al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005FF0 626c7818d0f6 SAL al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000005FF6 626cf818d036 SAL al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000005FFC 626cf818d0f6 SAL al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006002 626c7818d136 SAL eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006008 626c7818d1f6 SAL eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000600E 626cf818d136 SAL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006014 626cf818d1f6 SAL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000601A 626c7918d136 SAL ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006020 626c7918d1f6 SAL ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006026 626cf918d136 SAL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000602C 626cf918d1f6 SAL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006032 626c7818d236 SAL al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006038 626c7818d2f6 SAL al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000603E 626cf818d236 SAL al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006044 626cf818d2f6 SAL al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000604A 626c7818d336 SAL eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006050 626c7818d3f6 SAL eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006056 626cf818d336 SAL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000605C 626cf818d3f6 SAL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006062 626c7918d336 SAL ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006068 626c7918d3f6 SAL ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000606E 626cf918d336 SAL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006074 626cf918d3f6 SAL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000607A 626c781cc036bd SAL{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006081 626c781cc0f6bd SAL{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006088 626cf81cc036bd SAL{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000608F 626cf81cc0f6bd SAL{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006096 626c781cc136bd SAL{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000609D 626c781cc1f6bd SAL{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060A4 626cf81cc136bd SAL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060AB 626cf81cc1f6bd SAL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060B2 626c791cc136bd SAL{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060B9 626c791cc1f6bd SAL{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060C0 626cf91cc136bd SAL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060C7 626cf91cc1f6bd SAL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000060CE 626c781cd036 SAL{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060D4 626c781cd0f6 SAL{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060DA 626cf81cd036 SAL{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060E0 626cf81cd0f6 SAL{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060E6 626c781cd136 SAL{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060EC 626c781cd1f6 SAL{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060F2 626cf81cd136 SAL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060F8 626cf81cd1f6 SAL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000060FE 626c791cd136 SAL{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006104 626c791cd1f6 SAL{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000610A 626cf91cd136 SAL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006110 626cf91cd1f6 SAL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006116 626c781cd236 SAL{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000611C 626c781cd2f6 SAL{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006122 626cf81cd236 SAL{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006128 626cf81cd2f6 SAL{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000612E 626c781cd336 SAL{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006134 626c781cd3f6 SAL{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000613A 626cf81cd336 SAL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006140 626cf81cd3f6 SAL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006146 626c791cd336 SAL{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000614C 626c791cd3f6 SAL{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006152 626cf91cd336 SAL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006158 626cf91cd3f6 SAL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000615E 626c7808c03ebd SAR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006165 626c7808c0febd SAR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000616C 626cf808c03ebd SAR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006173 626cf808c0febd SAR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000617A 626c7808c13ebd SAR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006181 626c7808c1febd SAR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006188 626cf808c13ebd SAR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000618F 626cf808c1febd SAR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006196 626c7908c13ebd SAR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000619D 626c7908c1febd SAR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000061A4 626cf908c13ebd SAR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061AB 626cf908c1febd SAR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061B2 626c7808d03e SAR byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000061B8 626c7808d0fe SAR r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000061BE 626cf808d03e SAR byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061C4 626cf808d0fe SAR r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061CA 626c7808d13e SAR dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000061D0 626c7808d1fe SAR r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000061D6 626cf808d13e SAR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061DC 626cf808d1fe SAR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061E2 626c7908d13e SAR word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000061E8 626c7908d1fe SAR r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000061EE 626cf908d13e SAR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061F4 626cf908d1fe SAR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000061FA 626c7808d23e SAR byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006200 626c7808d2fe SAR r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006206 626cf808d23e SAR byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000620C 626cf808d2fe SAR r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006212 626c7808d33e SAR dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006218 626c7808d3fe SAR r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000621E 626cf808d33e SAR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006224 626cf808d3fe SAR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000622A 626c7908d33e SAR word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006230 626c7908d3fe SAR r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006236 626cf908d33e SAR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000623C 626cf908d3fe SAR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006242 626c780cc03ebd SAR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006249 626c780cc0febd SAR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006250 626cf80cc03ebd SAR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006257 626cf80cc0febd SAR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000625E 626c780cc13ebd SAR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006265 626c780cc1febd SAR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000626C 626cf80cc13ebd SAR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006273 626cf80cc1febd SAR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000627A 626c790cc13ebd SAR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006281 626c790cc1febd SAR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006288 626cf90cc13ebd SAR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000628F 626cf90cc1febd SAR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006296 626c780cd03e SAR{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000629C 626c780cd0fe SAR{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062A2 626cf80cd03e SAR{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062A8 626cf80cd0fe SAR{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062AE 626c780cd13e SAR{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062B4 626c780cd1fe SAR{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062BA 626cf80cd13e SAR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062C0 626cf80cd1fe SAR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062C6 626c790cd13e SAR{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062CC 626c790cd1fe SAR{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062D2 626cf90cd13e SAR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062D8 626cf90cd1fe SAR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000062DE 626c780cd23e SAR{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000062E4 626c780cd2fe SAR{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000062EA 626cf80cd23e SAR{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000062F0 626cf80cd2fe SAR{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000062F6 626c780cd33e SAR{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000062FC 626c780cd3fe SAR{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006302 626cf80cd33e SAR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006308 626cf80cd3fe SAR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000630E 626c790cd33e SAR{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006314 626c790cd3fe SAR{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000631A 626cf90cd33e SAR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006320 626cf90cd3fe SAR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006326 626c7818c03ebd SAR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000632D 626c7818c0febd SAR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006334 626cf818c03ebd SAR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000633B 626cf818c0febd SAR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006342 626c7818c13ebd SAR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006349 626c7818c1febd SAR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006350 626cf818c13ebd SAR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006357 626cf818c1febd SAR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000635E 626c7918c13ebd SAR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006365 626c7918c1febd SAR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000636C 626cf918c13ebd SAR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006373 626cf918c1febd SAR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000637A 626c7818d03e SAR al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006380 626c7818d0fe SAR al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006386 626cf818d03e SAR al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000638C 626cf818d0fe SAR al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006392 626c7818d13e SAR eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006398 626c7818d1fe SAR eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000639E 626cf818d13e SAR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063A4 626cf818d1fe SAR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063AA 626c7918d13e SAR ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000063B0 626c7918d1fe SAR ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000063B6 626cf918d13e SAR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063BC 626cf918d1fe SAR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063C2 626c7818d23e SAR al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000063C8 626c7818d2fe SAR al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000063CE 626cf818d23e SAR al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063D4 626cf818d2fe SAR al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063DA 626c7818d33e SAR eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000063E0 626c7818d3fe SAR eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000063E6 626cf818d33e SAR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063EC 626cf818d3fe SAR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000063F2 626c7918d33e SAR ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000063F8 626c7918d3fe SAR ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000063FE 626cf918d33e SAR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006404 626cf918d3fe SAR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000640A 626c781cc03ebd SAR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006411 626c781cc0febd SAR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006418 626cf81cc03ebd SAR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000641F 626cf81cc0febd SAR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006426 626c781cc13ebd SAR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000642D 626c781cc1febd SAR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006434 626cf81cc13ebd SAR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000643B 626cf81cc1febd SAR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006442 626c791cc13ebd SAR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006449 626c791cc1febd SAR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006450 626cf91cc13ebd SAR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006457 626cf91cc1febd SAR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000645E 626c781cd03e SAR{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006464 626c781cd0fe SAR{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000646A 626cf81cd03e SAR{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006470 626cf81cd0fe SAR{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006476 626c781cd13e SAR{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000647C 626c781cd1fe SAR{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006482 626cf81cd13e SAR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006488 626cf81cd1fe SAR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000648E 626c791cd13e SAR{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006494 626c791cd1fe SAR{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000649A 626cf91cd13e SAR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000064A0 626cf91cd1fe SAR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000064A6 626c781cd23e SAR{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064AC 626c781cd2fe SAR{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064B2 626cf81cd23e SAR{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064B8 626cf81cd2fe SAR{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064BE 626c781cd33e SAR{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064C4 626c781cd3fe SAR{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064CA 626cf81cd33e SAR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064D0 626cf81cd3fe SAR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064D6 626c791cd33e SAR{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064DC 626c791cd3fe SAR{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064E2 626cf91cd33e SAR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064E8 626cf91cd3fe SAR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000064EE 62fa7a08f71e SARX ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000064F4 62fa7a08f7de SARX ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000064FA 62fafa08f71e SARX rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006500 62fafa08f7de SARX rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006506 626c7808181e SBB byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000650C 626c780818de SBB r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006512 626cf808181e SBB byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006518 626cf80818de SBB r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000651E 626c7808191e SBB dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006524 626c780819de SBB r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000652A 626cf808191e SBB qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006530 626cf80819de SBB r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006536 626c7908191e SBB word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000653C 626c790819de SBB r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006542 626cf908191e SBB qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006548 626cf90819de SBB r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000654E 626c78081a1e SBB r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006554 626c78081ade SBB r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000655A 626cf8081a1e SBB r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006560 626cf8081ade SBB r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006566 626c78081b1e SBB r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000656C 626c78081bde SBB r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006572 626cf8081b1e SBB r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006578 626cf8081bde SBB r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000657E 626c79081b1e SBB r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006584 626c79081bde SBB r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000658A 626cf9081b1e SBB r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006590 626cf9081bde SBB r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006596 626c7808801ebd SBB byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000659D 626c780880debd SBB r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000065A4 626cf808801ebd SBB byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065AB 626cf80880debd SBB r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065B2 626c7808811ebdbdbdbd SBB dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000065BC 626c780881debdbdbdbd SBB r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000065C6 626cf808811ebdbdbdbd SBB qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065D0 626cf80881debdbdbdbd SBB r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065DA 626c7908811ebdbd SBB word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000065E2 626c790881debdbd SBB r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000065EA 626cf908811ebdbdbdbd SBB qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065F4 626cf90881debdbdbdbd SBB r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000065FE 626c7808831ebd SBB dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006605 626c780883debd SBB r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000660C 626cf808831ebd SBB qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006613 626cf80883debd SBB r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000661A 626c7908831ebd SBB word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006621 626c790883debd SBB r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006628 626cf908831ebd SBB qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000662F 626cf90883debd SBB r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006636 626c7818181e SBB al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000663C 626c781818de SBB al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006642 626cf818181e SBB al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006648 626cf81818de SBB al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000664E 626c7818191e SBB eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006654 626c781819de SBB eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000665A 626cf818191e SBB rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006660 626cf81819de SBB rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006666 626c7918191e SBB ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000666C 626c791819de SBB ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006672 626cf918191e SBB rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006678 626cf91819de SBB rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000667E 626c78181a1e SBB al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006684 626c78181ade SBB al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000668A 626cf8181a1e SBB al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006690 626cf8181ade SBB al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006696 626c78181b1e SBB eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000669C 626c78181bde SBB eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000066A2 626cf8181b1e SBB rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066A8 626cf8181bde SBB rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066AE 626c79181b1e SBB ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000066B4 626c79181bde SBB ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000066BA 626cf9181b1e SBB rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066C0 626cf9181bde SBB rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066C6 626c7818801ebd SBB al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000066CD 626c781880debd SBB al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000066D4 626cf818801ebd SBB al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066DB 626cf81880debd SBB al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000066E2 626c7818811ebdbdbdbd SBB eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000066EC 626c781881debdbdbdbd SBB eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000066F6 626cf818811ebdbdbdbd SBB rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006700 626cf81881debdbdbdbd SBB rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000670A 626c7918811ebdbd SBB ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006712 626c791881debdbd SBB ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000671A 626cf918811ebdbdbdbd SBB rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006724 626cf91881debdbdbdbd SBB rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000672E 626c7818831ebd SBB eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006735 626c781883debd SBB eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000673C 626cf818831ebd SBB rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006743 626cf81883debd SBB rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000674A 626c7918831ebd SBB ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006751 626c791883debd SBB ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006758 626cf918831ebd SBB rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000675F 626cf91883debd SBB rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: tm, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006766 626c7b08461e SETBE byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000676C 626c7b0846de SETBE r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006772 626cfb08461e SETBE byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006778 626cfb0846de SETBE r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000677E 626c7b08421e SETC byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006784 626c7b0842de SETC r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000678A 626cfb08421e SETC byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006790 626cfb0842de SETC r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006796 626c7b084c1e SETL byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000679C 626c7b084cde SETL r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067A2 626cfb084c1e SETL byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067A8 626cfb084cde SETL r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067AE 626c7b084e1e SETLE byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067B4 626c7b084ede SETLE r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067BA 626cfb084e1e SETLE byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067C0 626cfb084ede SETLE r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067C6 626c7b08471e SETNBE byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067CC 626c7b0847de SETNBE r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067D2 626cfb08471e SETNBE byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067D8 626cfb0847de SETNBE r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067DE 626c7b08431e SETNC byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067E4 626c7b0843de SETNC r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067EA 626cfb08431e SETNC byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067F0 626cfb0843de SETNC r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000067F6 626c7b084d1e SETNL byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000067FC 626c7b084dde SETNL r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006802 626cfb084d1e SETNL byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006808 626cfb084dde SETNL r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000680E 626c7b084f1e SETNLE byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006814 626c7b084fde SETNLE r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000681A 626cfb084f1e SETNLE byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006820 626cfb084fde SETNLE r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, SF: t, OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006826 626c7b08411e SETNO byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000682C 626c7b0841de SETNO r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006832 626cfb08411e SETNO byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006838 626cfb0841de SETNO r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000683E 626c7b084b1e SETNP byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006844 626c7b084bde SETNP r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000684A 626cfb084b1e SETNP byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006850 626cfb084bde SETNP r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006856 626c7b08491e SETNS byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000685C 626c7b0849de SETNS r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006862 626cfb08491e SETNS byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006868 626cfb0849de SETNS r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000686E 626c7b08451e SETNZ byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006874 626c7b0845de SETNZ r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000687A 626cfb08451e SETNZ byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006880 626cfb0845de SETNZ r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006886 626c7b08401e SETO byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000688C 626c7b0840de SETO r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006892 626cfb08401e SETO byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006898 626cfb0840de SETO r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + OF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000689E 626c7b084a1e SETP byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068A4 626c7b084ade SETP r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068AA 626cfb084a1e SETP byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068B0 626cfb084ade SETP r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + PF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068B6 626c7b08481e SETS byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068BC 626c7b0848de SETS r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068C2 626cfb08481e SETS byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068C8 626cfb0848de SETS r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + SF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068CE 626c7b08441e SETZ byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068D4 626c7b0844de SETZ r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000068DA 626cfb08441e SETZ byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068E0 626cfb0844de SETZ r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BITBYTE, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + ZF: t, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000068E6 626c7808d91e SHA1MSG1 xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +00000000000068EC 626c7808d9de SHA1MSG1 xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +00000000000068F2 626cf808d91e SHA1MSG1 xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +00000000000068F8 626cf808d9de SHA1MSG1 xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +00000000000068FE 626c7808da1e SHA1MSG2 xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006904 626c7808dade SHA1MSG2 xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +000000000000690A 626cf808da1e SHA1MSG2 xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006910 626cf808dade SHA1MSG2 xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +0000000000006916 626c7808d81e SHA1NEXTE xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +000000000000691C 626c7808d8de SHA1NEXTE xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +0000000000006922 626cf808d81e SHA1NEXTE xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006928 626cf808d8de SHA1NEXTE xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +000000000000692E 626c7808d41ebd SHA1RNDS4 xmm27, xmmword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006935 626c7808d4debd SHA1RNDS4 xmm27, xmm6, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000693C 626cf808d41ebd SHA1RNDS4 xmm27, xmmword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006943 626cf808d4debd SHA1RNDS4 xmm27, xmm6, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000694A 626c7808dc1e SHA256MSG1 xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006950 626c7808dcde SHA256MSG1 xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +0000000000006956 626cf808dc1e SHA256MSG1 xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +000000000000695C 626cf808dcde SHA256MSG1 xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +0000000000006962 626c7808dd1e SHA256MSG2 xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006968 626c7808ddde SHA256MSG2 xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +000000000000696E 626cf808dd1e SHA256MSG2 xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + +0000000000006974 626cf808ddde SHA256MSG2 xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + +000000000000697A 626c7808db1e SHA256RNDS2 xmm27, xmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000006980 626c7808dbde SHA256RNDS2 xmm27, xmm6 + DSIZE: 32, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000006986 626cf808db1e SHA256RNDS2 xmm27, xmmword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +000000000000698C 626cf808dbde SHA256RNDS2 xmm27, xmm6 + DSIZE: 64, ASIZE: 64, VLEN: 128 + ISA Set: APX_F, Ins cat: SHA, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-SHA + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: S, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1 + +0000000000006992 626c7808c026bd SHL byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006999 626c7808c0e6bd SHL r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000069A0 626cf808c026bd SHL byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069A7 626cf808c0e6bd SHL r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069AE 626c7808c126bd SHL dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000069B5 626c7808c1e6bd SHL r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000069BC 626cf808c126bd SHL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069C3 626cf808c1e6bd SHL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069CA 626c7908c126bd SHL word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000069D1 626c7908c1e6bd SHL r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000069D8 626cf908c126bd SHL qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069DF 626cf908c1e6bd SHL r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069E6 626c7808d026 SHL byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000069EC 626c7808d0e6 SHL r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000069F2 626cf808d026 SHL byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069F8 626cf808d0e6 SHL r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000069FE 626c7808d126 SHL dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A04 626c7808d1e6 SHL r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A0A 626cf808d126 SHL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A10 626cf808d1e6 SHL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A16 626c7908d126 SHL word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006A1C 626c7908d1e6 SHL r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006A22 626cf908d126 SHL qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A28 626cf908d1e6 SHL r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A2E 626c7808d226 SHL byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A34 626c7808d2e6 SHL r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A3A 626cf808d226 SHL byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A40 626cf808d2e6 SHL r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A46 626c7808d326 SHL dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A4C 626c7808d3e6 SHL r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006A52 626cf808d326 SHL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A58 626cf808d3e6 SHL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A5E 626c7908d326 SHL word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006A64 626c7908d3e6 SHL r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006A6A 626cf908d326 SHL qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A70 626cf908d3e6 SHL r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006A76 626c780cc026bd SHL{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006A7D 626c780cc0e6bd SHL{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006A84 626cf80cc026bd SHL{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006A8B 626cf80cc0e6bd SHL{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006A92 626c780cc126bd SHL{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006A99 626c780cc1e6bd SHL{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006AA0 626cf80cc126bd SHL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006AA7 626cf80cc1e6bd SHL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006AAE 626c790cc126bd SHL{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006AB5 626c790cc1e6bd SHL{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006ABC 626cf90cc126bd SHL{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006AC3 626cf90cc1e6bd SHL{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006ACA 626c780cd026 SHL{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AD0 626c780cd0e6 SHL{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AD6 626cf80cd026 SHL{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006ADC 626cf80cd0e6 SHL{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AE2 626c780cd126 SHL{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AE8 626c780cd1e6 SHL{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AEE 626cf80cd126 SHL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AF4 626cf80cd1e6 SHL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006AFA 626c790cd126 SHL{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006B00 626c790cd1e6 SHL{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006B06 626cf90cd126 SHL{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006B0C 626cf90cd1e6 SHL{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006B12 626c780cd226 SHL{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B18 626c780cd2e6 SHL{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B1E 626cf80cd226 SHL{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B24 626cf80cd2e6 SHL{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B2A 626c780cd326 SHL{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B30 626c780cd3e6 SHL{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B36 626cf80cd326 SHL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B3C 626cf80cd3e6 SHL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B42 626c790cd326 SHL{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B48 626c790cd3e6 SHL{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B4E 626cf90cd326 SHL{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B54 626cf90cd3e6 SHL{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006B5A 626c7818c026bd SHL al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006B61 626c7818c0e6bd SHL al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006B68 626cf818c026bd SHL al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006B6F 626cf818c0e6bd SHL al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006B76 626c7818c126bd SHL eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006B7D 626c7818c1e6bd SHL eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006B84 626cf818c126bd SHL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006B8B 626cf818c1e6bd SHL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006B92 626c7918c126bd SHL ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006B99 626c7918c1e6bd SHL ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006BA0 626cf918c126bd SHL rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BA7 626cf918c1e6bd SHL rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BAE 626c7818d026 SHL al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006BB4 626c7818d0e6 SHL al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006BBA 626cf818d026 SHL al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BC0 626cf818d0e6 SHL al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BC6 626c7818d126 SHL eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006BCC 626c7818d1e6 SHL eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006BD2 626cf818d126 SHL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BD8 626cf818d1e6 SHL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BDE 626c7918d126 SHL ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006BE4 626c7918d1e6 SHL ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006BEA 626cf918d126 SHL rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BF0 626cf918d1e6 SHL rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006BF6 626c7818d226 SHL al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006BFC 626c7818d2e6 SHL al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006C02 626cf818d226 SHL al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C08 626cf818d2e6 SHL al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C0E 626c7818d326 SHL eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006C14 626c7818d3e6 SHL eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006C1A 626cf818d326 SHL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C20 626cf818d3e6 SHL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C26 626c7918d326 SHL ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006C2C 626c7918d3e6 SHL ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006C32 626cf918d326 SHL rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C38 626cf918d3e6 SHL rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006C3E 626c781cc026bd SHL{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C45 626c781cc0e6bd SHL{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C4C 626cf81cc026bd SHL{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C53 626cf81cc0e6bd SHL{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C5A 626c781cc126bd SHL{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C61 626c781cc1e6bd SHL{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C68 626cf81cc126bd SHL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C6F 626cf81cc1e6bd SHL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C76 626c791cc126bd SHL{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C7D 626c791cc1e6bd SHL{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C84 626cf91cc126bd SHL{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C8B 626cf91cc1e6bd SHL{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006C92 626c781cd026 SHL{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006C98 626c781cd0e6 SHL{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006C9E 626cf81cd026 SHL{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CA4 626cf81cd0e6 SHL{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CAA 626c781cd126 SHL{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CB0 626c781cd1e6 SHL{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CB6 626cf81cd126 SHL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CBC 626cf81cd1e6 SHL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CC2 626c791cd126 SHL{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CC8 626c791cd1e6 SHL{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CCE 626cf91cd126 SHL{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CD4 626cf91cd1e6 SHL{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000006CDA 626c781cd226 SHL{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CE0 626c781cd2e6 SHL{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CE6 626cf81cd226 SHL{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CEC 626cf81cd2e6 SHL{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CF2 626c781cd326 SHL{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CF8 626c781cd3e6 SHL{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006CFE 626cf81cd326 SHL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D04 626cf81cd3e6 SHL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D0A 626c791cd326 SHL{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D10 626c791cd3e6 SHL{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D16 626cf91cd326 SHL{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D1C 626cf91cd3e6 SHL{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006D22 626c7808241ebd SHLD dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006D29 626c780824debd SHLD r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006D30 626cf808241ebd SHLD qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D37 626cf80824debd SHLD r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D3E 626c7808a51e SHLD dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006D44 626c7808a5de SHLD r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006D4A 626cf808a51e SHLD qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D50 626cf808a5de SHLD r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D56 626c7908241ebd SHLD word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006D5D 626c790824debd SHLD r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006D64 626cf908241ebd SHLD qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D6B 626cf90824debd SHLD r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D72 626c7908a51e SHLD word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006D78 626c7908a5de SHLD r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006D7E 626cf908a51e SHLD qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D84 626cf908a5de SHLD r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006D8A 626c780c241ebd SHLD{NF} dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006D91 626c780c24debd SHLD{NF} r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006D98 626cf80c241ebd SHLD{NF} qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006D9F 626cf80c24debd SHLD{NF} r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006DA6 626c780ca51e SHLD{NF} dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DAC 626c780ca5de SHLD{NF} r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DB2 626cf80ca51e SHLD{NF} qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DB8 626cf80ca5de SHLD{NF} r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DBE 626c790c241ebd SHLD{NF} word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006DC5 626c790c24debd SHLD{NF} r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006DCC 626cf90c241ebd SHLD{NF} qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006DD3 626cf90c24debd SHLD{NF} r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006DDA 626c790ca51e SHLD{NF} word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DE0 626c790ca5de SHLD{NF} r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DE6 626cf90ca51e SHLD{NF} qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DEC 626cf90ca5de SHLD{NF} r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006DF2 626c7818241ebd SHLD eax, dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006DF9 626c781824debd SHLD eax, r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006E00 626cf818241ebd SHLD rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E07 626cf81824debd SHLD rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E0E 626c7818a51e SHLD eax, dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006E14 626c7818a5de SHLD eax, r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006E1A 626cf818a51e SHLD rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E20 626cf818a5de SHLD rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E26 626c7918241ebd SHLD ax, word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006E2D 626c791824debd SHLD ax, r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006E34 626cf918241ebd SHLD rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E3B 626cf91824debd SHLD rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E42 626c7918a51e SHLD ax, word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006E48 626c7918a5de SHLD ax, r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006E4E 626cf918a51e SHLD rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E54 626cf918a5de SHLD rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006E5A 626c781c241ebd SHLD{NF} eax, dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E61 626c781c24debd SHLD{NF} eax, r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E68 626cf81c241ebd SHLD{NF} rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E6F 626cf81c24debd SHLD{NF} rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E76 626c781ca51e SHLD{NF} eax, dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006E7C 626c781ca5de SHLD{NF} eax, r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006E82 626cf81ca51e SHLD{NF} rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006E88 626cf81ca5de SHLD{NF} rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006E8E 626c791c241ebd SHLD{NF} ax, word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E95 626c791c24debd SHLD{NF} ax, r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006E9C 626cf91c241ebd SHLD{NF} rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006EA3 626cf91c24debd SHLD{NF} rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006EAA 626c791ca51e SHLD{NF} ax, word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006EB0 626c791ca5de SHLD{NF} ax, r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006EB6 626cf91ca51e SHLD{NF} rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006EBC 626cf91ca5de SHLD{NF} rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000006EC2 62fa7908f71e SHLX ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006EC8 62fa7908f7de SHLX ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006ECE 62faf908f71e SHLX rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006ED4 62faf908f7de SHLX rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006EDA 626c7808c02ebd SHR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006EE1 626c7808c0eebd SHR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006EE8 626cf808c02ebd SHR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006EEF 626cf808c0eebd SHR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006EF6 626c7808c12ebd SHR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006EFD 626c7808c1eebd SHR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F04 626cf808c12ebd SHR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F0B 626cf808c1eebd SHR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F12 626c7908c12ebd SHR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006F19 626c7908c1eebd SHR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006F20 626cf908c12ebd SHR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F27 626cf908c1eebd SHR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F2E 626c7808d02e SHR byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F34 626c7808d0ee SHR r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F3A 626cf808d02e SHR byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F40 626cf808d0ee SHR r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F46 626c7808d12e SHR dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F4C 626c7808d1ee SHR r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F52 626cf808d12e SHR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F58 626cf808d1ee SHR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F5E 626c7908d12e SHR word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006F64 626c7908d1ee SHR r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006F6A 626cf908d12e SHR qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F70 626cf908d1ee SHR r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F76 626c7808d22e SHR byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F7C 626c7808d2ee SHR r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F82 626cf808d22e SHR byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F88 626cf808d2ee SHR r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006F8E 626c7808d32e SHR dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F94 626c7808d3ee SHR r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000006F9A 626cf808d32e SHR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006FA0 626cf808d3ee SHR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006FA6 626c7908d32e SHR word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006FAC 626c7908d3ee SHR r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000006FB2 626cf908d32e SHR qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006FB8 626cf908d3ee SHR r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 2, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000006FBE 626c780cc02ebd SHR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FC5 626c780cc0eebd SHR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FCC 626cf80cc02ebd SHR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FD3 626cf80cc0eebd SHR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FDA 626c780cc12ebd SHR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FE1 626c780cc1eebd SHR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FE8 626cf80cc12ebd SHR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FEF 626cf80cc1eebd SHR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FF6 626c790cc12ebd SHR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000006FFD 626c790cc1eebd SHR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007004 626cf90cc12ebd SHR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000700B 626cf90cc1eebd SHR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007012 626c780cd02e SHR{NF} byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007018 626c780cd0ee SHR{NF} r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000701E 626cf80cd02e SHR{NF} byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007024 626cf80cd0ee SHR{NF} r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000702A 626c780cd12e SHR{NF} dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007030 626c780cd1ee SHR{NF} r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007036 626cf80cd12e SHR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000703C 626cf80cd1ee SHR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007042 626c790cd12e SHR{NF} word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007048 626c790cd1ee SHR{NF} r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000704E 626cf90cd12e SHR{NF} qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007054 626cf90cd1ee SHR{NF} r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000705A 626c780cd22e SHR{NF} byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007060 626c780cd2ee SHR{NF} r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007066 626cf80cd22e SHR{NF} byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000706C 626cf80cd2ee SHR{NF} r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007072 626c780cd32e SHR{NF} dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007078 626c780cd3ee SHR{NF} r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000707E 626cf80cd32e SHR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007084 626cf80cd3ee SHR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000708A 626c790cd32e SHR{NF} word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007090 626c790cd3ee SHR{NF} r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007096 626cf90cd32e SHR{NF} qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000709C 626cf90cd3ee SHR{NF} r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000070A2 626c7818c02ebd SHR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000070A9 626c7818c0eebd SHR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000070B0 626cf818c02ebd SHR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070B7 626cf818c0eebd SHR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070BE 626c7818c12ebd SHR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000070C5 626c7818c1eebd SHR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000070CC 626cf818c12ebd SHR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070D3 626cf818c1eebd SHR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070DA 626c7918c12ebd SHR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000070E1 626c7918c1eebd SHR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000070E8 626cf918c12ebd SHR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070EF 626cf918c1eebd SHR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000070F6 626c7818d02e SHR al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000070FC 626c7818d0ee SHR al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007102 626cf818d02e SHR al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007108 626cf818d0ee SHR al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000710E 626c7818d12e SHR eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007114 626c7818d1ee SHR eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000711A 626cf818d12e SHR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007120 626cf818d1ee SHR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007126 626c7918d12e SHR ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000712C 626c7918d1ee SHR ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007132 626cf918d12e SHR rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007138 626cf918d1ee SHR rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000713E 626c7818d22e SHR al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007144 626c7818d2ee SHR al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000714A 626cf818d22e SHR al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007150 626cf818d2ee SHR al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007156 626c7818d32e SHR eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000715C 626c7818d3ee SHR eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007162 626cf818d32e SHR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007168 626cf818d3ee SHR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000716E 626c7918d32e SHR ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007174 626c7918d3ee SHR ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000717A 626cf918d32e SHR rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007180 626cf918d3ee SHR rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: u, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007186 626c781cc02ebd SHR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000718D 626c781cc0eebd SHR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007194 626cf81cc02ebd SHR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000719B 626cf81cc0eebd SHR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071A2 626c781cc12ebd SHR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071A9 626c781cc1eebd SHR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071B0 626cf81cc12ebd SHR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071B7 626cf81cc1eebd SHR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071BE 626c791cc12ebd SHR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071C5 626c791cc1eebd SHR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071CC 626cf91cc12ebd SHR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071D3 626cf91cc1eebd SHR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000071DA 626c781cd02e SHR{NF} al, byte ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071E0 626c781cd0ee SHR{NF} al, r22b, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071E6 626cf81cd02e SHR{NF} al, byte ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071EC 626cf81cd0ee SHR{NF} al, r22b, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071F2 626c781cd12e SHR{NF} eax, dword ptr [r22], 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071F8 626c781cd1ee SHR{NF} eax, r22d, 1 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +00000000000071FE 626cf81cd12e SHR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007204 626cf81cd1ee SHR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000720A 626c791cd12e SHR{NF} ax, word ptr [r22], 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007210 626c791cd1ee SHR{NF} ax, r22w, 1 + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007216 626cf91cd12e SHR{NF} rax, qword ptr [r22], 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +000000000000721C 626cf91cd1ee SHR{NF} rax, r22, 1 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Constant, Size: 1, RawSize: 1, Encoding: 1 + +0000000000007222 626c781cd22e SHR{NF} al, byte ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007228 626c781cd2ee SHR{NF} al, r22b, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000722E 626cf81cd22e SHR{NF} al, byte ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007234 626cf81cd2ee SHR{NF} al, r22b, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000723A 626c781cd32e SHR{NF} eax, dword ptr [r22], cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007240 626c781cd3ee SHR{NF} eax, r22d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007246 626cf81cd32e SHR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000724C 626cf81cd3ee SHR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007252 626c791cd32e SHR{NF} ax, word ptr [r22], cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007258 626c791cd3ee SHR{NF} ax, r22w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000725E 626cf91cd32e SHR{NF} rax, qword ptr [r22], cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007264 626cf91cd3ee SHR{NF} rax, r22, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000726A 626c78082c1ebd SHRD dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007271 626c78082cdebd SHRD r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007278 626cf8082c1ebd SHRD qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000727F 626cf8082cdebd SHRD r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007286 626c7808ad1e SHRD dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000728C 626c7808adde SHRD r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007292 626cf808ad1e SHRD qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007298 626cf808adde SHRD r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000729E 626c79082c1ebd SHRD word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000072A5 626c79082cdebd SHRD r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000072AC 626cf9082c1ebd SHRD qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000072B3 626cf9082cdebd SHRD r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000072BA 626c7908ad1e SHRD word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000072C0 626c7908adde SHRD r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000072C6 626cf908ad1e SHRD qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000072CC 626cf908adde SHRD r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000072D2 626c780c2c1ebd SHRD{NF} dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000072D9 626c780c2cdebd SHRD{NF} r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000072E0 626cf80c2c1ebd SHRD{NF} qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000072E7 626cf80c2cdebd SHRD{NF} r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000072EE 626c780cad1e SHRD{NF} dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000072F4 626c780cadde SHRD{NF} r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000072FA 626cf80cad1e SHRD{NF} qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007300 626cf80cadde SHRD{NF} r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007306 626c790c2c1ebd SHRD{NF} word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000730D 626c790c2cdebd SHRD{NF} r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007314 626cf90c2c1ebd SHRD{NF} qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000731B 626cf90c2cdebd SHRD{NF} r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007322 626c790cad1e SHRD{NF} word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007328 626c790cadde SHRD{NF} r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000732E 626cf90cad1e SHRD{NF} qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007334 626cf90cadde SHRD{NF} r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RCW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000733A 626c78182c1ebd SHRD eax, dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007341 626c78182cdebd SHRD eax, r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007348 626cf8182c1ebd SHRD rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000734F 626cf8182cdebd SHRD rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007356 626c7818ad1e SHRD eax, dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000735C 626c7818adde SHRD eax, r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007362 626cf818ad1e SHRD rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007368 626cf818adde SHRD rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000736E 626c79182c1ebd SHRD ax, word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007375 626c79182cdebd SHRD ax, r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000737C 626cf9182c1ebd SHRD rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007383 626cf9182cdebd SHRD rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000738A 626c7918ad1e SHRD ax, word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007390 626c7918adde SHRD ax, r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007396 626cf918ad1e SHRD rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000739C 626cf918adde SHRD rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: u, PF: m, AF: u, ZF: m, SF: m, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000073A2 626c781c2c1ebd SHRD{NF} eax, dword ptr [r22], r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073A9 626c781c2cdebd SHRD{NF} eax, r22d, r27d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073B0 626cf81c2c1ebd SHRD{NF} rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073B7 626cf81c2cdebd SHRD{NF} rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073BE 626c781cad1e SHRD{NF} eax, dword ptr [r22], r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073C4 626c781cadde SHRD{NF} eax, r22d, r27d, cl + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073CA 626cf81cad1e SHRD{NF} rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073D0 626cf81cadde SHRD{NF} rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073D6 626c791c2c1ebd SHRD{NF} ax, word ptr [r22], r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073DD 626c791c2cdebd SHRD{NF} ax, r22w, r27w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073E4 626cf91c2c1ebd SHRD{NF} rax, qword ptr [r22], r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073EB 626cf91c2cdebd SHRD{NF} rax, r22, r27, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000073F2 626c791cad1e SHRD{NF} ax, word ptr [r22], r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073F8 626c791cadde SHRD{NF} ax, r22w, r27w, cl + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +00000000000073FE 626cf91cad1e SHRD{NF} rax, qword ptr [r22], r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +0000000000007404 626cf91cadde SHRD{NF} rax, r22, r27, cl + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: SHIFT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: S, RegType: General Purpose, RegSize: 1, RegId: 1, RegCount: 1 + +000000000000740A 62fa7b08f71e SHRX ebx, dword ptr [r22], eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007410 62fa7b08f7de SHRX ebx, r22d, eax + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007416 62fafb08f71e SHRX rbx, qword ptr [r22], rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000741C 62fafb08f7de SHRX rbx, r22, rax + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI2, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-BMI + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007422 62fa79084906 STTILECFG zmmword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: AMX-EVEX-E2 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 64, RawSize: 64, Encoding: M, + Segment: 3, Base: 22, + +0000000000007428 626c7808281e SUB byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000742E 626c780828de SUB r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007434 626cf808281e SUB byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000743A 626cf80828de SUB r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007440 626c7808291e SUB dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007446 626c780829de SUB r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000744C 626cf808291e SUB qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007452 626cf80829de SUB r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007458 626c7908291e SUB word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000745E 626c790829de SUB r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007464 626cf908291e SUB qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000746A 626cf90829de SUB r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007470 626c78082a1e SUB r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007476 626c78082ade SUB r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000747C 626cf8082a1e SUB r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007482 626cf8082ade SUB r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007488 626c78082b1e SUB r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000748E 626c78082bde SUB r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007494 626cf8082b1e SUB r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000749A 626cf8082bde SUB r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074A0 626c79082b1e SUB r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000074A6 626c79082bde SUB r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000074AC 626cf9082b1e SUB r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074B2 626cf9082bde SUB r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074B8 626c7808802ebd SUB byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000074BF 626c780880eebd SUB r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000074C6 626cf808802ebd SUB byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074CD 626cf80880eebd SUB r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074D4 626c7808812ebdbdbdbd SUB dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000074DE 626c780881eebdbdbdbd SUB r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000074E8 626cf808812ebdbdbdbd SUB qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074F2 626cf80881eebdbdbdbd SUB r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000074FC 626c7908812ebdbd SUB word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007504 626c790881eebdbd SUB r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000750C 626cf908812ebdbdbdbd SUB qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007516 626cf90881eebdbdbdbd SUB r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007520 626c7808832ebd SUB dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007527 626c780883eebd SUB r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000752E 626cf808832ebd SUB qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007535 626cf80883eebd SUB r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000753C 626c7908832ebd SUB word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007543 626c790883eebd SUB r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000754A 626cf908832ebd SUB qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007551 626cf90883eebd SUB r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007558 626c780c281e SUB{NF} byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +000000000000755E 626c780c28de SUB{NF} r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007564 626cf80c281e SUB{NF} byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +000000000000756A 626cf80c28de SUB{NF} r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007570 626c780c291e SUB{NF} dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007576 626c780c29de SUB{NF} r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000757C 626cf80c291e SUB{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007582 626cf80c29de SUB{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007588 626c790c291e SUB{NF} word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +000000000000758E 626c790c29de SUB{NF} r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000007594 626cf90c291e SUB{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000759A 626cf90c29de SUB{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000075A0 626c780c2a1e SUB{NF} r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000075A6 626c780c2ade SUB{NF} r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000075AC 626cf80c2a1e SUB{NF} r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +00000000000075B2 626cf80c2ade SUB{NF} r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +00000000000075B8 626c780c2b1e SUB{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +00000000000075BE 626c780c2bde SUB{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +00000000000075C4 626cf80c2b1e SUB{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000075CA 626cf80c2bde SUB{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000075D0 626c790c2b1e SUB{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +00000000000075D6 626c790c2bde SUB{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +00000000000075DC 626cf90c2b1e SUB{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +00000000000075E2 626cf90c2bde SUB{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +00000000000075E8 626c780c802ebd SUB{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000075EF 626c780c80eebd SUB{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000075F6 626cf80c802ebd SUB{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000075FD 626cf80c80eebd SUB{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007604 626c780c812ebdbdbdbd SUB{NF} dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000760E 626c780c81eebdbdbdbd SUB{NF} r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007618 626cf80c812ebdbdbdbd SUB{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007622 626cf80c81eebdbdbdbd SUB{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000762C 626c790c812ebdbd SUB{NF} word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007634 626c790c81eebdbd SUB{NF} r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +000000000000763C 626cf90c812ebdbdbdbd SUB{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007646 626cf90c81eebdbdbdbd SUB{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007650 626c780c832ebd SUB{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007657 626c780c83eebd SUB{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000765E 626cf80c832ebd SUB{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007665 626cf80c83eebd SUB{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000766C 626c790c832ebd SUB{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007673 626c790c83eebd SUB{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000767A 626cf90c832ebd SUB{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007681 626cf90c83eebd SUB{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007688 626c7818281e SUB al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000768E 626c781828de SUB al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007694 626cf818281e SUB al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000769A 626cf81828de SUB al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076A0 626c7818291e SUB eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076A6 626c781829de SUB eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076AC 626cf818291e SUB rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076B2 626cf81829de SUB rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076B8 626c7918291e SUB ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000076BE 626c791829de SUB ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000076C4 626cf918291e SUB rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076CA 626cf91829de SUB rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076D0 626c78182a1e SUB al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076D6 626c78182ade SUB al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076DC 626cf8182a1e SUB al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076E2 626cf8182ade SUB al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076E8 626c78182b1e SUB eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076EE 626c78182bde SUB eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000076F4 626cf8182b1e SUB rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000076FA 626cf8182bde SUB rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007700 626c79182b1e SUB ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007706 626c79182bde SUB ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000770C 626cf9182b1e SUB rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007712 626cf9182bde SUB rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007718 626c7818802ebd SUB al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000771F 626c781880eebd SUB al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007726 626cf818802ebd SUB al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000772D 626cf81880eebd SUB al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007734 626c7818812ebdbdbdbd SUB eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000773E 626c781881eebdbdbdbd SUB eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007748 626cf818812ebdbdbdbd SUB rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007752 626cf81881eebdbdbdbd SUB rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000775C 626c7918812ebdbd SUB ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007764 626c791881eebdbd SUB ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000776C 626cf918812ebdbdbdbd SUB rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007776 626cf91881eebdbdbdbd SUB rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007780 626c7818832ebd SUB eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007787 626c781883eebd SUB eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000778E 626cf818832ebd SUB rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007795 626cf81883eebd SUB rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000779C 626c7918832ebd SUB ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000077A3 626c791883eebd SUB ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000077AA 626cf918832ebd SUB rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000077B1 626cf91883eebd SUB rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: m, AF: m, ZF: m, SF: m, OF: m, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000077B8 626c781c281e SUB{NF} al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000077BE 626c781c28de SUB{NF} al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000077C4 626cf81c281e SUB{NF} al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000077CA 626cf81c28de SUB{NF} al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +00000000000077D0 626c781c291e SUB{NF} eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +00000000000077D6 626c781c29de SUB{NF} eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +00000000000077DC 626cf81c291e SUB{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000077E2 626cf81c29de SUB{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000077E8 626c791c291e SUB{NF} ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +00000000000077EE 626c791c29de SUB{NF} ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +00000000000077F4 626cf91c291e SUB{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +00000000000077FA 626cf91c29de SUB{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007800 626c781c2a1e SUB{NF} al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007806 626c781c2ade SUB{NF} al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +000000000000780C 626cf81c2a1e SUB{NF} al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007812 626cf81c2ade SUB{NF} al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000007818 626c781c2b1e SUB{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +000000000000781E 626c781c2bde SUB{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000007824 626cf81c2b1e SUB{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000782A 626cf81c2bde SUB{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007830 626c791c2b1e SUB{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000007836 626c791c2bde SUB{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +000000000000783C 626cf91c2b1e SUB{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007842 626cf91c2bde SUB{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007848 626c781c802ebd SUB{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000784F 626c781c80eebd SUB{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007856 626cf81c802ebd SUB{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +000000000000785D 626cf81c80eebd SUB{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007864 626c781c812ebdbdbdbd SUB{NF} eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000786E 626c781c81eebdbdbdbd SUB{NF} eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007878 626cf81c812ebdbdbdbd SUB{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007882 626cf81c81eebdbdbdbd SUB{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +000000000000788C 626c791c812ebdbd SUB{NF} ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007894 626c791c81eebdbd SUB{NF} ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +000000000000789C 626cf91c812ebdbdbdbd SUB{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000078A6 626cf91c81eebdbdbdbd SUB{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +00000000000078B0 626c781c832ebd SUB{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078B7 626c781c83eebd SUB{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078BE 626cf81c832ebd SUB{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078C5 626cf81c83eebd SUB{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078CC 626c791c832ebd SUB{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078D3 626c791c83eebd SUB{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078DA 626cf91c832ebd SUB{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078E1 626cf91c83eebd SUB{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: ARITH, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +00000000000078E8 62fa7b084b1cfe TILELOADD tmm3, [r22+r23*8] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: AMX-EVEX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 22, Index: 23 * 8, + +00000000000078EF 62fa79084b1cfe TILELOADDT1 tmm3, [r22+r23*8] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: AMX-EVEX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 3, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 22, Index: 23 * 8, + +00000000000078F6 62fa7a084b1cfe TILESTORED [r22+r23*8], tmm3 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: AMX, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: AMX-EVEX-E3 + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes, + Segment: 3, Base: 22, Index: 23 * 8, + Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 3, RegCount: 1 + +00000000000078FD 626c7808f41e TZCNT r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007903 626c7808f4de TZCNT r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007909 626cf808f41e TZCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000790F 626cf808f4de TZCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007915 626c7908f41e TZCNT r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +000000000000791B 626c7908f4de TZCNT r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007921 626cf908f41e TZCNT r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007927 626cf908f4de TZCNT r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: m, PF: u, AF: u, ZF: m, SF: u, OF: u, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000792D 626c780cf41e TZCNT{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000007933 626c780cf4de TZCNT{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000007939 626cf80cf41e TZCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +000000000000793F 626cf80cf4de TZCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007945 626c790cf41e TZCNT{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +000000000000794B 626c790cf4de TZCNT{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000007951 626cf90cf41e TZCNT{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007957 626cf90cf4de TZCNT{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: BMI1, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +000000000000795D 626c7808661e WRSSD dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CET, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-WRSS + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Shadow stack: 1, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007963 626cf808661e WRSSQ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CET, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-WRSS + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Shadow stack: 1, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007969 626c7908651e WRUSSD dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CET, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-WRUSS + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 4, RawSize: 4, Encoding: M, Shadow stack: 1, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000796F 626cf908651e WRUSSQ qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: CET, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-WRUSS + Valid modes + R0: yes, R1: no, R2: no, R3: no + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Memory, Size: 8, RawSize: 8, Encoding: M, Shadow stack: 1, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007975 626c7808301e XOR byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +000000000000797B 626c780830de XOR r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007981 626cf808301e XOR byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007987 626cf80830de XOR r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000798D 626c7808311e XOR dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007993 626c780831de XOR r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007999 626cf808311e XOR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +000000000000799F 626cf80831de XOR r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079A5 626c7908311e XOR word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000079AB 626c790831de XOR r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000079B1 626cf908311e XOR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079B7 626cf90831de XOR r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079BD 626c7808321e XOR r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000079C3 626c780832de XOR r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000079C9 626cf808321e XOR r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079CF 626cf80832de XOR r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079D5 626c7808331e XOR r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000079DB 626c780833de XOR r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +00000000000079E1 626cf808331e XOR r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079E7 626cf80833de XOR r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079ED 626c7908331e XOR r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000079F3 626c790833de XOR r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +00000000000079F9 626cf908331e XOR r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +00000000000079FF 626cf90833de XOR r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A05 626c78088036bd XOR byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A0C 626c780880f6bd XOR r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A13 626cf8088036bd XOR byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A1A 626cf80880f6bd XOR r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A21 626c78088136bdbdbdbd XOR dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A2B 626c780881f6bdbdbdbd XOR r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A35 626cf8088136bdbdbdbd XOR qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A3F 626cf80881f6bdbdbdbd XOR r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A49 626c79088136bdbd XOR word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007A51 626c790881f6bdbd XOR r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007A59 626cf9088136bdbdbdbd XOR qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A63 626cf90881f6bdbdbdbd XOR r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A6D 626c78088336bd XOR dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A74 626c780883f6bd XOR r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007A7B 626cf8088336bd XOR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A82 626cf80883f6bd XOR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A89 626c79088336bd XOR word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007A90 626c790883f6bd XOR r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007A97 626cf9088336bd XOR qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007A9E 626cf90883f6bd XOR r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007AA5 626c780c301e XOR{NF} byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007AAB 626c780c30de XOR{NF} r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007AB1 626cf80c301e XOR{NF} byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007AB7 626cf80c30de XOR{NF} r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007ABD 626c780c311e XOR{NF} dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007AC3 626c780c31de XOR{NF} r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007AC9 626cf80c311e XOR{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007ACF 626cf80c31de XOR{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007AD5 626c790c311e XOR{NF} word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000007ADB 626c790c31de XOR{NF} r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000007AE1 626cf90c311e XOR{NF} qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007AE7 626cf90c31de XOR{NF} r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007AED 626c780c321e XOR{NF} r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007AF3 626c780c32de XOR{NF} r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000007AF9 626cf80c321e XOR{NF} r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007AFF 626cf80c32de XOR{NF} r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000007B05 626c780c331e XOR{NF} r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000007B0B 626c780c33de XOR{NF} r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000007B11 626cf80c331e XOR{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007B17 626cf80c33de XOR{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007B1D 626c790c331e XOR{NF} r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000007B23 626c790c33de XOR{NF} r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000007B29 626cf90c331e XOR{NF} r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007B2F 626cf90c33de XOR{NF} r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007B35 626c780c8036bd XOR{NF} byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007B3C 626c780c80f6bd XOR{NF} r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007B43 626cf80c8036bd XOR{NF} byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007B4A 626cf80c80f6bd XOR{NF} r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007B51 626c780c8136bdbdbdbd XOR{NF} dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B5B 626c780c81f6bdbdbdbd XOR{NF} r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B65 626cf80c8136bdbdbdbd XOR{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B6F 626cf80c81f6bdbdbdbd XOR{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B79 626c790c8136bdbd XOR{NF} word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007B81 626c790c81f6bdbd XOR{NF} r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007B89 626cf90c8136bdbdbdbd XOR{NF} qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B93 626cf90c81f6bdbdbdbd XOR{NF} r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007B9D 626c780c8336bd XOR{NF} dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BA4 626c780c83f6bd XOR{NF} r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BAB 626cf80c8336bd XOR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BB2 626cf80c83f6bd XOR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BB9 626c790c8336bd XOR{NF} word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BC0 626c790c83f6bd XOR{NF} r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BC7 626cf90c8336bd XOR{NF} qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BCE 626cf90c83f6bd XOR{NF} r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007BD5 626c7818301e XOR al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007BDB 626c781830de XOR al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007BE1 626cf818301e XOR al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007BE7 626cf81830de XOR al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007BED 626c7818311e XOR eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007BF3 626c781831de XOR eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007BF9 626cf818311e XOR rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007BFF 626cf81831de XOR rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C05 626c7918311e XOR ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007C0B 626c791831de XOR ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007C11 626cf918311e XOR rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C17 626cf91831de XOR rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C1D 626c7818321e XOR al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C23 626c781832de XOR al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C29 626cf818321e XOR al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C2F 626cf81832de XOR al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C35 626c7818331e XOR eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C3B 626c781833de XOR eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C41 626cf818331e XOR rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C47 626cf81833de XOR rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C4D 626c7918331e XOR ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007C53 626c791833de XOR ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007C59 626cf918331e XOR rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C5F 626cf91833de XOR rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C65 626c78188036bd XOR al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C6C 626c781880f6bd XOR al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C73 626cf8188036bd XOR al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C7A 626cf81880f6bd XOR al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C81 626c78188136bdbdbdbd XOR eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C8B 626c781881f6bdbdbdbd XOR eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007C95 626cf8188136bdbdbdbd XOR rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007C9F 626cf81881f6bdbdbdbd XOR rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CA9 626c79188136bdbd XOR ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007CB1 626c791881f6bdbd XOR ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007CB9 626cf9188136bdbdbdbd XOR rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CC3 626cf91881f6bdbdbdbd XOR rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CCD 626c78188336bd XOR eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007CD4 626c781883f6bd XOR eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1 + +0000000000007CDB 626cf8188336bd XOR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CE2 626cf81883f6bd XOR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CE9 626c79188336bd XOR ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007CF0 626c791883f6bd XOR ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: S, RegType: Flags, RegSize: 2, RegId: 0, RegCount: 1 + +0000000000007CF7 626cf9188336bd XOR rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007CFE 626cf91883f6bd XOR rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + FLAGS access + CF: 0, PF: m, AF: u, ZF: m, SF: m, OF: 0, + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Flags, RegSize: 8, RegId: 0, RegCount: 1 + +0000000000007D05 626c781c301e XOR{NF} al, byte ptr [r22], r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007D0B 626c781c30de XOR{NF} al, r22b, r27b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007D11 626cf81c301e XOR{NF} al, byte ptr [r22], r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007D17 626cf81c30de XOR{NF} al, r22b, r27b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + +0000000000007D1D 626c781c311e XOR{NF} eax, dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007D23 626c781c31de XOR{NF} eax, r22d, r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000007D29 626cf81c311e XOR{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007D2F 626cf81c31de XOR{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007D35 626c791c311e XOR{NF} ax, word ptr [r22], r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000007D3B 626c791c31de XOR{NF} ax, r22w, r27w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + +0000000000007D41 626cf91c311e XOR{NF} rax, qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007D47 626cf91c31de XOR{NF} rax, r22, r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000007D4D 626c781c321e XOR{NF} al, r27b, byte ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D53 626c781c32de XOR{NF} al, r27b, r22b + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000007D59 626cf81c321e XOR{NF} al, r27b, byte ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D5F 626cf81c32de XOR{NF} al, r27b, r22b + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + +0000000000007D65 626c781c331e XOR{NF} eax, r27d, dword ptr [r22] + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D6B 626c781c33de XOR{NF} eax, r27d, r22d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + +0000000000007D71 626cf81c331e XOR{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D77 626cf81c33de XOR{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007D7D 626c791c331e XOR{NF} ax, r27w, word ptr [r22] + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D83 626c791c33de XOR{NF} ax, r27w, r22w + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + +0000000000007D89 626cf91c331e XOR{NF} rax, r27, qword ptr [r22] + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + +0000000000007D8F 626cf91c33de XOR{NF} rax, r27, r22 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000007D95 626c781c8036bd XOR{NF} al, byte ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007D9C 626c781c80f6bd XOR{NF} al, r22b, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007DA3 626cf81c8036bd XOR{NF} al, byte ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007DAA 626cf81c80f6bd XOR{NF} al, r22b, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: V, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 1, RawSize: 1, Encoding: M, RegType: General Purpose, RegSize: 1, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007DB1 626c781c8136bdbdbdbd XOR{NF} eax, dword ptr [r22], 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DBB 626c781c81f6bdbdbdbd XOR{NF} eax, r22d, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DC5 626cf81c8136bdbdbdbd XOR{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DCF 626cf81c81f6bdbdbdbd XOR{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DD9 626c791c8136bdbd XOR{NF} ax, word ptr [r22], 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007DE1 626c791c81f6bdbd XOR{NF} ax, r22w, 0xbdbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 2, RawSize: 2, Encoding: I + +0000000000007DE9 626cf91c8136bdbdbdbd XOR{NF} rax, qword ptr [r22], 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DF3 626cf91c81f6bdbdbdbd XOR{NF} rax, r22, 0xbdbdbdbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + +0000000000007DFD 626c781c8336bd XOR{NF} eax, dword ptr [r22], 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E04 626c781c83f6bd XOR{NF} eax, r22d, 0xbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E0B 626cf81c8336bd XOR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E12 626cf81c83f6bd XOR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E19 626c791c8336bd XOR{NF} ax, word ptr [r22], 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E20 626c791c83f6bd XOR{NF} ax, r22w, 0xbd + DSIZE: 16, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: V, RegType: General Purpose, RegSize: 2, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 2, RawSize: 2, Encoding: M, RegType: General Purpose, RegSize: 2, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E27 626cf91c8336bd XOR{NF} rax, qword ptr [r22], 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + +0000000000007E2E 626cf91c83f6bd XOR{NF} rax, r22, 0xbd + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: LOGIC, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: V, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I + diff --git 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/dev/null +++ b/bddisasm_test/x86/apx/apx2_64.result @@ -0,0 +1,224 @@ +0000000000000000 626c7808fc1e AADD dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000006 626cf808fc1e AADD qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +000000000000000C 626c7908fc1e AAND dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +0000000000000012 626cf908fc1e AAND qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000018 626c7b08fc1e AOR dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000001E 626cfb08fc1e AOR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000024 626c7a08fc1e AXOR dword ptr [r22], r27d + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 4, RawSize: 4, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 27, RegCount: 1 + +000000000000002A 626cfa08fc1e AXOR qword ptr [r22], r27 + DSIZE: 64, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: RAO-INT, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-RAO-INT + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: RW, Type: Memory, Size: 8, RawSize: 8, Encoding: M, + Segment: 3, Base: 22, + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000030 626c7b08f8de URDMSR r22, r27 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-USER-MSR + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + +0000000000000036 62ff7b08f8c6bdbdbdbd URDMSR r22, 0xbdbdbdbd + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1 + +0000000000000040 626c7a08f8de UWRMSR r27, r22 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Exception class: APX, exception type: APX-EVEX-USER-MSR + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 27, RegCount: 1 + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + +0000000000000046 62ff7a08f8c6bdbdbdbd UWRMSR 0xbdbdbdbd, r22 + DSIZE: 32, ASIZE: 64, VLEN: - + ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no + CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21 + EVEX Tuple Type: None + Valid modes + R0: yes, R1: yes, R2: yes, R3: yes + Real: no, V8086: no, Prot: no, Compat: no, Long: yes + SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes + VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes + Valid prefixes + REP: no, REPcc: no, LOCK: no + HLE: no, XACQUIRE only: no, XRELEASE only: no + BND: no, BHINT: no, DNT: no + Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I + Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 22, RegCount: 1 + Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1 + diff --git a/bddisasm_test/x86/apx/apx2_64.test b/bddisasm_test/x86/apx/apx2_64.test new file mode 100644 index 0000000..931e970 --- /dev/null +++ b/bddisasm_test/x86/apx/apx2_64.test @@ -0,0 +1 @@ +blxübløüblyüblùübl{üblûüblzüblúübl{øÞbÿ{øƽ½½½blzøÞbÿzøƽ½½½ \ No newline at end of file diff --git a/bddisasm_test/x86/apx/evex_bad_64_skip.asm b/bddisasm_test/x86/apx/evex_bad_64_skip.asm new file mode 100644 index 0000000..3706585 --- /dev/null +++ b/bddisasm_test/x86/apx/evex_bad_64_skip.asm @@ -0,0 +1,16 @@ + bits 64 + + ; NF not supported. + db 0x62, 0x6C, 0x78, 0x0C, 0x10, 0x1E, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + ; V' set. + db 0x62, 0x6C, 0x78, 0x00, 0x10, 0x1E, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + ; VVVV set. + db 0x62, 0x6C, 0x38, 0x08, 0x10, 0x1E, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + ; Reserved bits set. + db 0x62, 0x6C, 0x78, 0x09, 0x10, 0x1E, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + db 0x62, 0x6C, 0x78, 0x88, 0x10, 0x1E, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + ; Invalid PUSH2 register (RSP). + db 0x62, 0x6C, 0x58, 0x18, 0xFF, 0xF4, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + ; Invalid POP2 registers (same dest register, RAX). + db 0x62, 0x64, 0x78, 0x18, 0x8F, 0xC0, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, + \ No newline at end of file diff --git a/bddisasm_test/x86/apx/evex_bad_64_skip.result b/bddisasm_test/x86/apx/evex_bad_64_skip.result new file mode 100644 index 0000000..9fbdc56 --- /dev/null +++ b/bddisasm_test/x86/apx/evex_bad_64_skip.result @@ -0,0 +1,7 @@ +0000000000000000 62 db 0x62 (0x80000002) +0000000000000010 62 db 0x62 (0x80000040) +0000000000000020 62 db 0x62 (0x80000032) +0000000000000030 62 db 0x62 (0x80000045) +0000000000000040 62 db 0x62 (0x80000045) +0000000000000050 62 db 0x62 (0x80000044) +0000000000000060 62 db 0x62 (0x80000044) diff --git a/bddisasm_test/x86/apx/evex_bad_64_skip.test b/bddisasm_test/x86/apx/evex_bad_64_skip.test new file mode 100644 index 0000000000000000000000000000000000000000..aabbf18249da71478e4e950a37ae1ad2069bcad0 GIT binary patch literal 112 vcmYewso)Win*aw%ITZ}3drR@Id1y1g~z2M|jFu@4Yyfia8mRfdIoq2MY -#else -#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86) -#include -#endif // defined(ND_ARCH_X64) || defined(ND_ARCH_X86) -#endif // __clang__ - -// -// A generic emulator value. -// -typedef struct _SHEMU_VALUE -{ - union - { - ND_UINT8 Bytes[ND_MAX_REGISTER_SIZE]; - ND_UINT16 Words[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT16)]; - ND_UINT32 Dwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT32)]; - ND_UINT64 Qwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT64)]; - - struct - { - ND_UINT16 FpuControlWord; - ND_UINT16 FpuStatusWord; - ND_UINT16 FpuTagWord; - ND_UINT16 Rsvd; - ND_UINT32 FpuDataPointer; - ND_UINT32 FpuInstructionPointer; - ND_UINT32 FpuLastInstructionOpcode; - } FpuEnvironment; - - struct - { - ND_UINT16 FpuControlWord; - ND_UINT16 FpuStatuwsWord; - ND_UINT16 FpuTagWord; - ND_UINT16 FpuOpcode; - ND_UINT64 FpuRip; - ND_UINT64 FpuDataPointer; - ND_UINT32 Mxcsr; - ND_UINT32 MxcsrMask; - } XsaveArea; - - struct - { - ND_UINT16 Limit; - ND_UINT64 Base; - } Descriptor; - - } Value; - - ND_OPERAND_SIZE Size; -} SHEMU_VALUE, *PSHEMU_VALUE; - - -enum -{ - FM_LOGIC, - FM_SHL, - FM_SHR, - FM_SAR, - FM_SUB, - FM_ADD, -} FLAGS_MODE; - - -#define GET_OP(ctx, op, val) { \ - SHEMU_STATUS status = ShemuGetOperandValue(ctx, op, val); \ - if (SHEMU_SUCCESS != status) \ - { \ - return status; \ - } \ -} - -#define SET_OP(ctx, op, val) { \ - SHEMU_STATUS status = ShemuSetOperandValue(ctx, op, val); \ - if (SHEMU_SUCCESS != status) \ - { \ - return status; \ - } \ -} - -#define GET_FLAG(ctx, flg) (!!((ctx)->Registers.RegFlags & (flg))) -#define SET_FLAG(ctx, flg, val) ((ctx)->Registers.RegFlags = (val) ? ((ctx)->Registers.RegFlags | flg) : \ - ((ctx)->Registers.RegFlags & ~(flg))) -#define SET_FLAGS(ctx, dst, src1, src2, fm) ShemuSetFlags(ctx, dst.Value.Qwords[0], src1.Value.Qwords[0], \ - src2.Value.Qwords[0], dst.Size, fm) - -#define SHELLBMP(ctx) ((ctx)->Intbuf) -#define STACKBMP(ctx) ((ctx)->Intbuf + (ctx)->ShellcodeSize) -#define SHELLBMP_SIZE(ctx) ((ctx)->ShellcodeSize) -#define STACKBMP_SIZE(ctx) ((ctx)->StackSize) -#define MAX(a, b) ((a) < (b) ? (b) : (a)) -#define MIN(a, b) ((a) > (b) ? (b) : (a)) +#ifndef UNREFERENCED_PARAMETER +#define UNREFERENCED_PARAMETER(P) ((void)(P)) +#endif // // ShemuPrintf - simple version // #ifndef BDDISASM_NO_FORMAT -static void +void shemu_printf( SHEMU_CONTEXT *Context, char *formatstring, ... ) { - char buff[1024]; + char buff[768]; va_list args; if (ND_NULL == Context->Log) @@ -131,17 +37,26 @@ shemu_printf( va_end(args); - Context->Log(buff); + Context->Log(buff, Context->AuxData); } #else -#define shemu_printf(Context, formatstring, ...) +void +shemu_printf( + SHEMU_CONTEXT *Context, + char *formatstring, + ... + ) +{ + UNREFERENCED_PARAMETER(Context); + UNREFERENCED_PARAMETER(formatstring); +} #endif // !BDDISASM_NO_FORMAT // // shemu_memcpy // -static void * +void * shemu_memcpy( void *Dest, const void *Source, @@ -173,131 +88,104 @@ shemu_memcpy( // -// ShemuBts +// ShemuHexlify // -inline static ND_UINT8 -ShemuBts( - ND_UINT8 *BitMap, - ND_UINT64 Position +void +ShemuHexlify( + ND_UINT8 *Value, + ND_UINT64 ValueSize, + char *Hex, + ND_UINT64 HexSize ) { - ND_UINT8 old; + const char hexDigits[16] = + { + '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F' + }; - old = (BitMap[Position / 8] >> (Position % 8)) & 1; + nd_memzero(Hex, (ND_SIZET)HexSize); - BitMap[Position / 8] |= 1 << (Position % 8); + if (HexSize <= ValueSize * 2) + { + return; + } - return old; + // Convert instruction bytes to string. + for (ND_UINT32 i = 0; i < ValueSize; i++) + { + Hex[(i * 2) + 0] = hexDigits[(Value[i] >> 4) & 0xF]; + Hex[(i * 2) + 1] = hexDigits[(Value[i] >> 0) & 0xF]; + } + + // Since we make sure HexSize is greater than twice the size of the Value, and since we always nd_memzero Hex + // at the beginning, we are guaranteed that Hex will be properly NULL terminated. } // -// ShemuBtr +// ShemuBmpStateUpdate // -inline static ND_UINT8 -ShemuBtr( - ND_UINT8 *BitMap, - ND_UINT64 Position - ) -{ - ND_UINT8 old; - - old = (BitMap[Position / 8] >> (Position % 8)) & 1; - - BitMap[Position / 8] &= ~(1 << (Position % 8)); - - return old; -} - - -// -// ShemuBt -// -inline static ND_UINT8 -ShemuBt( - ND_UINT8 *BitMap, - ND_UINT64 Position - ) -{ - return (BitMap[Position / 8] >> (Position % 8)) & 1; -} - - -// -// ShemuSetBits -// -static void -ShemuSetBits( +void +ShemuBmpStateUpdate( ND_UINT8 *Bitmap, - ND_UINT64 Start, ND_UINT64 Size, - ND_BOOL Val + ND_UINT64 Start, + ND_UINT64 Count, + ND_UINT8 Flags, + ND_BOOL Clear ) // -// No size validations here; the caller has to make sure the ranges are all good. +// Sets the indicated state inside the Bitmap. // { ND_UINT64 i; - for (i = 0; i < Size; i++) + if (ND_NULL == Bitmap || Start >= Size || Count > Size || Start + Count > Size) { - if (Val) + return; + } + + for (i = 0; i < Count; i++) + { + if (!Clear) { - ShemuBts(Bitmap, (ND_UINT64)(Start + i)); + Bitmap[Start + i] |= Flags; } else { - ShemuBtr(Bitmap, (ND_UINT64)(Start + i)); + Bitmap[Start + i] &= ~Flags; } } } -//// -//// ShemuAllBitsSet -//// -//static ND_BOOL -//ShemuAllBitsSet( -// ND_UINT8 *Bitmap, -// ND_UINT64 Start, -// ND_UINT32 Size -// ) -//// -//// No size validations here; the caller has to make sure the ranges are all good. -//// -//{ -// ND_UINT32 i; // -// for (i = 0; i < Size; i++) -// { -// if (!ShemuBt(Bitmap, (ND_UINT64)(Start + i))) -// { -// return ND_FALSE; -// } -// } +// ShemuBmpStateCheck // -// return ND_TRUE; -//} - - -// -// ShemuAnyBitsSet -// -static ND_BOOL -ShemuAnyBitsSet( +ND_BOOL +ShemuBmpStateCheck( ND_UINT8 *Bitmap, + ND_UINT64 Size, ND_UINT64 Start, - ND_UINT32 Size + ND_UINT64 Count, + ND_UINT8 Flags ) // -// No size validations here; the caller has to make sure the ranges are all good. +// Check if any of the state bytes in the Bitmap has any of the Flags set. +// +// @returns ND_TRUE if any state byte contains the indicated Flags. // { - ND_UINT32 i; + ND_UINT64 i; - for (i = 0; i < Size; i++) + if (ND_NULL == Bitmap || Start >= Size || Count > Size || Start + Count > Size) { - if (ShemuBt(Bitmap, (ND_UINT64)(Start + i))) + return ND_FALSE; + } + + for (i = 0; i < Count; i++) + { + if (Bitmap[Start + i] & Flags) { return ND_TRUE; } @@ -307,303 +195,14 @@ ShemuAnyBitsSet( } -// -// ShemuSetFlags -// -static void -ShemuSetFlags( - SHEMU_CONTEXT *Context, - ND_UINT64 Dst, - ND_UINT64 Src1, - ND_UINT64 Src2, - ND_OPERAND_SIZE Size, - ND_UINT8 FlagsMode - ) -{ - ND_UINT8 pfArr[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; - - // Mask the operands with their respective size. - Dst = ND_TRIM(Size, Dst); - Src1 = ND_TRIM(Size, Src1); - Src2 = ND_TRIM(Size, Src2); - - if (FlagsMode == FM_SHL || FlagsMode == FM_SHR || FlagsMode == FM_SAR) - { - // Shift with 0 count does not affect flags. - if (Src2 == 0) - { - return; - } - } - - // PF set if the first bytes has an even number of 1 bits. - if ((pfArr[Dst & 0xF] + pfArr[(Dst >> 4) & 0xF]) % 2 == 0) - { - Context->Registers.RegFlags |= NDR_RFLAG_PF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_PF; - } - - // ZF set if the result is zero. - if (Dst == 0) - { - Context->Registers.RegFlags |= NDR_RFLAG_ZF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_ZF; - } - - // SF is set if the sign flag is set. - if (ND_GET_SIGN(Size, Dst) != 0) - { - Context->Registers.RegFlags |= NDR_RFLAG_SF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_SF; - } - - // OF and CF are handled differently for some instructions. - if (FM_LOGIC == FlagsMode) - { - // OF and CF are cleared on logic instructions. - Context->Registers.RegFlags &= ~(NDR_RFLAG_OF | NDR_RFLAG_CF); - } - else if (FM_SHL == FlagsMode) - { - // CF is the last bit shifted out of the destination. - if (ND_GET_BIT((Size * 8ULL) - Src2, Src1)) - { - Context->Registers.RegFlags |= NDR_RFLAG_CF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_CF; - } - - if (Src2 == 1) - { - if (ND_GET_BIT(Size * 8ULL - 1, Src1) ^ ND_GET_BIT(Size * 8ULL - 2, Src1)) - { - Context->Registers.RegFlags |= NDR_RFLAG_OF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_OF; - } - } - } - else if (FM_SHR == FlagsMode) - { - // CF is the last bit shifted out of the destination. - if (ND_GET_BIT(Src2 - 1, Src1)) - { - Context->Registers.RegFlags |= NDR_RFLAG_CF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_CF; - } - - if (Src2 == 1) - { - if (ND_GET_BIT(Size * 8ULL - 1, Src1)) - { - Context->Registers.RegFlags |= NDR_RFLAG_OF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_OF; - } - } - } - else if (FM_SAR == FlagsMode) - { - // CF is the last bit shifted out of the destination. In case of SAR, if the shift ammount exceeds the operand - // size, CF will be 1 if the result is -1, or 0 if the result is 0. - if (ND_GET_BIT(Src2 - 1, Src1) || ((Src2 >= (ND_UINT64)Size * 8) && Dst != 0)) - { - Context->Registers.RegFlags |= NDR_RFLAG_CF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_CF; - } - - Context->Registers.RegFlags &= ~NDR_RFLAG_OF; - } - else - { - // Set CF. - if ((FM_SUB == FlagsMode) && ((Src1 < Src2) || (Src1 == Src2 && Dst != 0))) - { - Context->Registers.RegFlags |= NDR_RFLAG_CF; - } - else if ((FM_ADD == FlagsMode) && ((Dst < Src1) || (Dst == Src1 && Src2 != 0))) - { - Context->Registers.RegFlags |= NDR_RFLAG_CF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_CF; - } - - // Set OF. - if (FM_SUB == FlagsMode) - { - if ((ND_GET_SIGN(Size, Src1) && !ND_GET_SIGN(Size, Src2) && !ND_GET_SIGN(Size, Dst)) || - (!ND_GET_SIGN(Size, Src1) && ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Dst))) - { - Context->Registers.RegFlags |= NDR_RFLAG_OF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_OF; - } - } - else if (FM_ADD == FlagsMode) - { - if (ND_GET_SIGN(Size, Src1) == ND_GET_SIGN(Size, Src2) && - ND_GET_SIGN(Size, Src1) != ND_GET_SIGN(Size, Dst)) - { - Context->Registers.RegFlags |= NDR_RFLAG_OF; - } - else - { - Context->Registers.RegFlags &= ~NDR_RFLAG_OF; - } - } - } -} - - -// -// ShemuEvalCondition -// -static ND_BOOL -ShemuEvalCondition( - SHEMU_CONTEXT *Context, - ND_UINT8 ConditionCode - ) -{ - switch (ConditionCode) - { - case ND_COND_OVERFLOW: // O - if (GET_FLAG(Context, NDR_RFLAG_OF) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_OVERFLOW): // NO - if (GET_FLAG(Context, NDR_RFLAG_OF) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_CARRY: // C/B/NAE - if (GET_FLAG(Context, NDR_RFLAG_CF) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE - if (GET_FLAG(Context, NDR_RFLAG_CF) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_ZERO: // E/Z - if (GET_FLAG(Context, NDR_RFLAG_ZF) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_ZERO): // NE/NZ - if (GET_FLAG(Context, NDR_RFLAG_ZF) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_BELOW_OR_EQUAL: // BE/NA - if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE - if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_SIGN: // S - if (GET_FLAG(Context, NDR_RFLAG_SF) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_SIGN): // NS - if (GET_FLAG(Context, NDR_RFLAG_SF) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_PARITY: // P - if (GET_FLAG(Context, NDR_RFLAG_PF) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_PARITY): // NP - if (GET_FLAG(Context, NDR_RFLAG_PF) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_LESS: // L/NGE - if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_LESS): // NL/GE - if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 0) - { - return ND_TRUE; - } - break; - case ND_COND_LESS_OR_EQUAL: // LE/NG - if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | - (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) - { - return ND_TRUE; - } - break; - case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G - if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | - (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) - { - return ND_TRUE; - } - break; - } - - return ND_FALSE; - -} - - // // ShemuIsShellcodePtr // -inline static ND_BOOL +ND_BOOL ShemuIsShellcodePtr( SHEMU_CONTEXT *Context, ND_UINT64 Gla, - ND_UINT32 Size + ND_UINT64 Size ) { return (Gla >= Context->ShellcodeBase && Gla < Context->ShellcodeBase + Context->ShellcodeSize && @@ -614,12 +213,12 @@ ShemuIsShellcodePtr( // // ShemuIsStackPtr // -inline static ND_BOOL +ND_BOOL ShemuIsStackPtr( SHEMU_CONTEXT *Context, ND_UINT64 Gla, - ND_UINT32 Size -) + ND_UINT64 Size + ) { return (Gla >= Context->StackBase && Gla < Context->StackBase + Context->StackSize && Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize); @@ -627,354 +226,93 @@ ShemuIsStackPtr( // -// ShemuGetGprValue +// ShemuIsIcachePtr // -static ND_UINT64 -ShemuGetGprValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg, - ND_UINT32 Size, - ND_BOOL High8 - ) -{ - switch (Size) - { - case 1: - if (High8) - { - // AH, CH, DH or BH accessed. - return (*(&Context->Registers.RegRax + Reg - 4) >> 8) & 0xff; - } - else - { - return *(&Context->Registers.RegRax + Reg) & 0xff; - } - - case 2: - return *(&Context->Registers.RegRax + Reg) & 0xffff; - - case 4: - return *(&Context->Registers.RegRax + Reg) & 0xffffffff; - - default: - return *(&Context->Registers.RegRax + Reg); - } -} - - -// -// ShemuGetGprValue -// -static void -ShemuSetGprValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg, - ND_UINT32 Size, - ND_UINT64 Value, - ND_BOOL High8 - ) -{ - ND_UINT32 bit; - - switch (Size) - { - case 1: - if (High8) - { - // AH, CH, DH or BH accessed. - *((ND_UINT8 *)(&Context->Registers.RegRax + Reg - 4) + 1) = Value & 0xFF; - } - else - { - *((ND_UINT8 *)(&Context->Registers.RegRax + Reg)) = Value & 0xff; - } - break; - - case 2: - *((ND_UINT16 *)(&Context->Registers.RegRax + Reg)) = Value & 0xffff; - break; - - case 4: - // Higher ND_UINT32 is always set to zero. - *(&Context->Registers.RegRax + Reg) = Value & 0xffffffff; - break; - - default: - *(&Context->Registers.RegRax + Reg) = Value; - break; - } - - if (High8) - { - bit = Reg - 4; - } - else - { - bit = Reg; - } - - // Mark the GPR as being dirty/written. - Context->DirtyGprBitmap |= (1 << bit); -} - - -// -// ShemuCmpGprValue -// -static ND_BOOL -ShemuCmpGprValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg, - ND_UINT32 Size, - ND_UINT64 Value, - ND_BOOL High8 - ) -{ - switch (Size) - { - case 1: - if (High8) - { - // AH, CH, DH or BH. - return *((ND_UINT8 *)(&Context->Registers.RegRax + Reg - 4) + 1) == (Value & 0xff); - } - else - { - return *((ND_UINT8 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xff); - } - - case 2: - return *((ND_UINT16 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffff); - - case 4: - return *((ND_UINT32 *)(&Context->Registers.RegRax + Reg)) == (Value & 0xffffffff); - - default: - return *(&Context->Registers.RegRax + Reg) == Value; - } -} - - -// -// ShemuGetSegValue -// -static ND_UINT64 -ShemuGetSegValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg - ) -{ - switch (Reg) - { - case NDR_ES: - return Context->Segments.Es.Selector; - case NDR_CS: - return Context->Segments.Cs.Selector; - case NDR_SS: - return Context->Segments.Ss.Selector; - case NDR_DS: - return Context->Segments.Ds.Selector; - case NDR_FS: - return Context->Segments.Fs.Selector; - case NDR_GS: - return Context->Segments.Gs.Selector; - } - - return 0; -} - - -// -// ShemuSetSegValue -// -static void -ShemuSetSegValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg, - ND_UINT16 Value - ) -{ - switch (Reg) - { - case NDR_ES: - Context->Segments.Es.Selector = Value; - break; - case NDR_CS: - Context->Segments.Cs.Selector = Value; - break; - case NDR_SS: - Context->Segments.Ss.Selector = Value; - break; - case NDR_DS: - Context->Segments.Ds.Selector = Value; - break; - case NDR_FS: - Context->Segments.Fs.Selector = Value; - break; - case NDR_GS: - Context->Segments.Gs.Selector = Value; - break; - } -} - - -// -// ShemuGetSegBase -// -static ND_UINT64 -ShemuGetSegBase( - SHEMU_CONTEXT *Context, - ND_UINT32 Reg - ) -{ - switch (Reg) - { - case NDR_ES: - return Context->Segments.Es.Base; - case NDR_CS: - return Context->Segments.Cs.Base; - case NDR_SS: - return Context->Segments.Ss.Base; - case NDR_DS: - return Context->Segments.Ds.Base; - case NDR_FS: - return Context->Segments.Fs.Base; - case NDR_GS: - return Context->Segments.Gs.Base; - } - - return 0; -} - - -// -// ShemuComputeLinearAddress -// -static ND_UINT64 -ShemuComputeLinearAddress( - SHEMU_CONTEXT *Context, - PND_OPERAND Operand - ) -{ - ND_UINT64 gla = 0; - - if (Operand->Info.Memory.HasBase) - { - gla += ShemuGetGprValue(Context, Operand->Info.Memory.Base, Operand->Info.Memory.BaseSize, ND_FALSE); - } - - if (Operand->Info.Memory.HasIndex) - { - gla += ShemuGetGprValue(Context, Operand->Info.Memory.Index, Operand->Info.Memory.IndexSize, ND_FALSE) * - Operand->Info.Memory.Scale; - } - - // Note that this also handles the case where moffset (absolute addressing) is used, as HasDisp will be set when - // IsDirect is also set. - if (Operand->Info.Memory.HasDisp) - { - gla += Operand->Info.Memory.Disp; - } - - if (Operand->Info.Memory.IsRipRel) - { - gla += Context->Registers.RegRip; - } - - // Special handling for BT, BTR, BTS, BTC instructions with bitbase addressing. - if (Operand->Info.Memory.IsBitbase) - { - ND_UINT64 bitbase, op1size, op2size, reg; - - op1size = Context->Instruction.Operands[0].Size; - op2size = Context->Instruction.Operands[1].Size; - - reg = ((ND_UINT64*)&Context->Registers.RegRax)[Context->Instruction.Operands[1].Info.Register.Reg]; - - // Note: only BT* with register source (NOT immediate) support bitbase addressing. - bitbase = ND_SIGN_EX(op2size, reg); - - if (bitbase & (1ULL << 63)) - { - gla -= ((~bitbase >> 3) & ~(op1size - 1)) + op1size; - } - else - { - gla += (bitbase >> 3) & ~(op1size - 1); - } - } - - // Special handling for stack operations: if we have a PUSH, we have to subtract the accessed size, as, in fact, - // [RSP - size] is accessed, not [RSP]. - if (Operand->Info.Memory.IsStack) - { - if (Operand->Access.Write || Operand->Access.CondWrite) - { - gla -= Operand->Size; - } - } - - // Make sure we truncate the linear address to the address size. - switch (Context->Instruction.AddrMode) - { - case ND_ADDR_32: - gla &= 0xFFFFFFFF; - break; - case ND_ADDR_16: - gla &= 0xFFFF; - default: - break; - } - - // Memory operands usually have a segment. Note that we don't care about any segment checks, since we're most - // likely be provided with flat segments. If checks should be needed, dedicated callbacks should be added. - if (Operand->Info.Memory.HasSeg) - { - gla += ShemuGetSegBase(Context, Operand->Info.Memory.Seg); - - if (Context->Mode != ND_CODE_64) - { - // Truncate to 32 bit outside 64 bit. - gla &= 0xFFFFFFFF; - } - } - - return gla; -} - - -// -// ShemuGetMemValue -// -static SHEMU_STATUS -ShemuGetMemValue( +ND_BOOL +ShemuIsIcachePtr( SHEMU_CONTEXT *Context, ND_UINT64 Gla, - ND_UINT32 Size, + ND_UINT64 Size + ) +{ + return (Gla >= Context->Icache.Address && Gla < Context->Icache.Address + Context->Icache.Size && + Gla + Size > Context->Icache.Address && Gla + Size <= Context->Icache.Address + Context->Icache.Size); +} + + +// +// ShemuQuickLoadStore +// +void +ShemuCopyMem( + ND_UINT8 *Destination, + ND_UINT8 *Source, + ND_UINT64 Size + ) +{ + switch (Size) + { + case 1: + *Destination = *Source; + break; + case 2: + *(ND_UINT16 *)Destination = *(ND_UINT16 *)Source; + break; + case 4: + *(ND_UINT32 *)Destination = *(ND_UINT32 *)Source; + break; + case 8: + *(ND_UINT64 *)Destination = *(ND_UINT64 *)Source; + break; + default: + shemu_memcpy(Destination, Source, (ND_SIZET)Size); + break; + } +} + + +// +// ShemuMemLoad +// +SHEMU_STATUS +ShemuMemLoad( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, ND_UINT8 *Value ) { - ND_UINT8 *addr; - ND_UINT32 offset; - if (ShemuIsShellcodePtr(Context, Gla, Size)) { - addr = Context->Shellcode; - offset = (ND_UINT32)(Gla - Context->ShellcodeBase); + // Shellcode access. + if (0 == (Context->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL)) + { + // Shellocode is local copy, we can directly access it. + ShemuCopyMem(Value, Context->Shellcode + (Gla - Context->ShellcodeBase), Size); + } + else + { + // Shellcode is directly mapped, we must go through the shellcode access API. + if ((ND_NULL == Context->AccessShellcode) || + !Context->AccessShellcode(Context, Gla, (ND_SIZET)Size, Value, ND_FALSE)) + { + return SHEMU_ABORT_GLA_OUTSIDE; + } + } } else if (ShemuIsStackPtr(Context, Gla, Size)) { - addr = Context->Stack; - offset = (ND_UINT32)(Gla - Context->StackBase); + ShemuCopyMem(Value, Context->Stack + (Gla - Context->StackBase), Size); } else { + ND_UINT32 selfOffset = 0; ND_BOOL res = ND_FALSE; // We allow a maximum number of external memory accesses, due to performance reasons. if (++Context->ExtMemAccess > Context->MemThreshold) { - return SHEMU_ABORT_GLA_OUTSIDE; + goto _check_special_access; } // NOTE: The accessed GLA may partially access an internal address (shellcode or stack) and an external address. @@ -989,69 +327,95 @@ ShemuGetMemValue( // bdshemu does not care directly about this, and lets the integrator choose his own strategy. if (ND_NULL != Context->AccessMemory) { - res = Context->AccessMemory(Context, Gla, Size, Value, ND_FALSE); + res = Context->AccessMemory(Context, Gla, (ND_SIZET)Size, Value, ND_FALSE); } if (res) { return SHEMU_SUCCESS; } + + _check_special_access: + if (Context->ArchType == SHEMU_ARCH_TYPE_X86) + { + selfOffset = Context->Arch.X86.Mode == ND_CODE_32 ? 0x18 : 0x30; + } + else + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + // If we got here, the external memory access has not been handled. + if (Gla == Context->TibBase + selfOffset) + { + // TEB.Self access. + if (Size == 4) + { + *(ND_UINT32*)Value = (ND_UINT32)Context->TibBase; + return SHEMU_SUCCESS; + } + else if (Size == 8) + { + *(ND_UINT64*)Value = (ND_UINT64)Context->TibBase; + return SHEMU_SUCCESS; + } + } return SHEMU_ABORT_GLA_OUTSIDE; } - switch (Size) - { - case 1: - *Value = *(addr + offset); - break; - case 2: - *(ND_UINT16 *)Value = *(ND_UINT16 *)(addr + offset); - break; - case 4: - *(ND_UINT32 *)Value = *(ND_UINT32 *)(addr + offset); - break; - case 8: - *(ND_UINT64 *)Value = *(ND_UINT64 *)(addr + offset); - break; - default: - shemu_memcpy(Value, addr + offset, Size); - break; - } - return SHEMU_SUCCESS; } // -// ShemuSetMemValue +// ShemuMemStore // -static SHEMU_STATUS -ShemuSetMemValue( +SHEMU_STATUS +ShemuMemStore( SHEMU_CONTEXT *Context, ND_UINT64 Gla, - ND_UINT32 Size, + ND_UINT64 Size, ND_UINT8 *Value ) { - ND_UINT8 *addr; - ND_UINT32 offset; - if (ShemuIsShellcodePtr(Context, Gla, Size)) { - addr = Context->Shellcode; - offset = (ND_UINT32)(Gla - Context->ShellcodeBase); - - // Bypass self-writes, if needed to. + // Bypass self-writes, if needed to. No need to invalidate the icache in this case. if (!!(Context->Options & SHEMU_OPT_BYPASS_SELF_WRITES)) { return SHEMU_SUCCESS; } + + // Flush the instruction cache, if any stored address in it. We can do this AFTER checking + // for SHEMU_OPT_BYPASS_SELF_WRITES - with that flag set, the shellcode will never be modified. + if (ShemuIsIcachePtr(Context, Gla, 1) || ShemuIsIcachePtr(Context, Gla + Size - 1, 1)) + { + ShemuFlushIcache(Context); + } + + // Shellcode access. + if (0 == (Context->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL)) + { + // Shellocode is local copy, we can directly access it. + ShemuCopyMem(Context->Shellcode + (Gla - Context->ShellcodeBase), Value, Size); + } + else + { + // Shellcode is directly mapped, we must go through the memory access API. Note that the integrator + // is free to do whatever it wants with this call - generally, it is a good idea to just discard + // modifications. For safety, currently we force the SHEMU_OPT_BYPASS_SELF_WRITES option whenever + // the SHEMU_OPT_DIRECT_MAPPED_SHELL option is used, to avoid problems. + if ((ND_NULL == Context->AccessShellcode) || + !Context->AccessShellcode(Context, Gla, (ND_SIZET)Size, Value, ND_TRUE)) + { + return SHEMU_ABORT_GLA_OUTSIDE; + } + } } else if (ShemuIsStackPtr(Context, Gla, Size)) { - addr = Context->Stack; - offset = (ND_UINT32)(Gla - Context->StackBase); + ShemuCopyMem(Context->Stack + (Gla - Context->StackBase), Value, Size); } else { @@ -1073,7 +437,7 @@ ShemuSetMemValue( // For obvious reasons, actually storing the value at the indicated address is a very, very bad idea. if (ND_NULL != Context->AccessMemory) { - res = Context->AccessMemory(Context, Gla, Size, Value, ND_TRUE); + res = Context->AccessMemory(Context, Gla, (ND_SIZET)Size, Value, ND_TRUE); } if (res) @@ -1084,658 +448,103 @@ ShemuSetMemValue( return SHEMU_ABORT_GLA_OUTSIDE; } - switch (Size) - { - case 1: - *(addr + offset) = *Value & 0xff; - break; - case 2: - *(ND_UINT16 *)(addr + offset) = *(ND_UINT16 *)Value & 0xffff; - break; - case 4: - *(ND_UINT32 *)(addr + offset) = *(ND_UINT32 *)Value & 0xffffffff; - break; - case 8: - *(ND_UINT64 *)(addr + offset) = *(ND_UINT64 *)Value; - break; - default: - shemu_memcpy(addr + offset, Value, Size); - break; - } - return SHEMU_SUCCESS; } // -// ShemuGetOperandValue +// ShemuMemFetch // -static SHEMU_STATUS -ShemuGetOperandValue( +SHEMU_STATUS +ShemuMemFetch( SHEMU_CONTEXT *Context, - ND_UINT32 Operand, - SHEMU_VALUE *Value + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Bytes ) { - SHEMU_STATUS status; - PND_OPERAND op = &Context->Instruction.Operands[Operand]; + ND_UINT8 *addr; + ND_UINT64 offset; - Value->Size = op->Size; - if (Value->Size > sizeof(Value->Value)) + if (Size > SHEMU_ICACHE_SIZE || Size == 0) { - return SHEMU_ABORT_OP_TOO_LARGE; + return SHEMU_ABORT_INVALID_PARAMETER; } - if (op->Type == ND_OP_REG) + if (!ShemuIsShellcodePtr(Context, Gla, Size)) { - switch (op->Info.Register.Type) + return SHEMU_ABORT_RIP_OUTSIDE; + } + + addr = Context->Shellcode; + offset = Gla - Context->ShellcodeBase; + + if (0 != (Context->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL)) + { + // If the entire address is NOT inside the cache, re-fill the entire line, starting with Gla. + if (!ShemuIsIcachePtr(Context, Gla, 1) || !ShemuIsIcachePtr(Context, Gla + Size - 1, 1)) { - case ND_REG_GPR: - Value->Value.Qwords[0] = ShemuGetGprValue(Context, op->Info.Register.Reg, op->Size, - op->Info.Register.IsHigh8); - break; + // Re-fill the line. + Context->Icache.Address = Gla; + Context->Icache.Size = MIN(SHEMU_ICACHE_SIZE, Context->ShellcodeSize - offset); - case ND_REG_SEG: - Value->Value.Qwords[0] = ShemuGetSegValue(Context, op->Info.Register.Reg); - break; - - case ND_REG_MMX: - Value->Value.Qwords[0] = Context->MmxRegisters[op->Info.Register.Reg]; - break; - - case ND_REG_SSE: - shemu_memcpy(Value->Value.Bytes, - &Context->SseRegisters[op->Info.Register.Reg], - op->Size); - break; - - case ND_REG_RIP: - Value->Value.Qwords[0] = ND_TRIM(op->Size, Context->Registers.RegRip); - break; - - case ND_REG_FLG: - Value->Value.Qwords[0] = ND_TRIM(op->Size, Context->Registers.RegFlags); - break; - - case ND_REG_CR: - switch (op->Info.Register.Reg) + if (Context->Icache.Size < Size) { - case NDR_CR0: - Value->Value.Qwords[0] = Context->Registers.RegCr0; - break; - case NDR_CR2: - Value->Value.Qwords[0] = Context->Registers.RegCr2; - break; - case NDR_CR3: - Value->Value.Qwords[0] = Context->Registers.RegCr3; - break; - case NDR_CR4: - Value->Value.Qwords[0] = Context->Registers.RegCr4; - break; - case NDR_CR8: - Value->Value.Qwords[0] = Context->Registers.RegCr8; - break; - default: - return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + return SHEMU_ABORT_RIP_OUTSIDE; } - break; - - default: - return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + if ((ND_NULL == Context->AccessShellcode) || + !Context->AccessShellcode(Context, Gla, (ND_SIZET)Context->Icache.Size, Context->Icache.Icache, ND_FALSE)) + { + return SHEMU_ABORT_FETCH_ERROR; + } } + + addr = Context->Icache.Icache; + offset = Gla - Context->Icache.Address; } - else if (op->Type == ND_OP_MEM) - { - ND_UINT64 gla = ShemuComputeLinearAddress(Context, op); - ND_UINT32 offset; - ND_UINT8 seg; - if (op->Info.Memory.IsAG) - { - // Address generation instruction, the result is the linear address itself. - Value->Value.Qwords[0] = gla; - goto done_gla; - } - - if (Context->Ring == 3) - { - // User-mode TIB offset that contains the PEB address. - offset = Context->Mode == ND_CODE_32 ? 0x30 : 0x60; - seg = Context->Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; - } - else - { - // Kernel-mode KPCR offset that contains the current KTHREAD address. - offset = Context->Mode == ND_CODE_32 ? 0x124 : 0x188; - seg = Context->Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; - } - - // Check if this is a TIB/PCR access. Make sure the FS/GS register is used for the access, in order to avoid - // ND_FALSE positives where legitimate code accesses a linear TIB directly. - // Note that this covers accesses to the PEB field inside the TIB. - if (gla == Context->TibBase + offset && Context->Instruction.Seg == seg) - { - Context->Flags |= SHEMU_FLAG_TIB_ACCESS; - } - - // Note that this covers accesses to the Wow32Reserved in Wow64 mode. That field can be used to issue - // syscalls. - if (gla == Context->TibBase + 0xC0 && Context->Instruction.Seg == seg && Context->Mode == ND_CODE_32) - { - Context->Flags |= SHEMU_FLAG_TIB_ACCESS_WOW32; - } - - // Check for accesses inside the KUSER_SHARED_DATA (SharedUserData). This page contains some - // global system information, it may host shellcodes, and is hard-coded at this address. - if (gla >= 0x7FFE0000 && gla < 0x7FFE1000) - { - Context->Flags |= SHEMU_FLAG_SUD_ACCESS; - } - - // Check if we are reading a previously saved RIP. Ignore RET category, which naturally uses the saved RIP. - // Also, ignore RMW instruction which naturally read the current value - this could happen if the code - // modifies the return value, for example "ADD qword [rsp], r8". - if (Context->Instruction.Category != ND_CAT_RET && !(op->Access.Access & ND_ACCESS_ANY_WRITE) && - ShemuIsStackPtr(Context, gla, op->Size) && - ShemuAnyBitsSet(STACKBMP(Context), gla - Context->StackBase, op->Size)) - { - Context->Flags |= SHEMU_FLAG_LOAD_RIP; - } - - // Get the memory value. - status = ShemuGetMemValue(Context, gla, MIN(op->Size, Value->Size), Value->Value.Bytes); - if (SHEMU_SUCCESS != status) - { - return status; - } - - // If this is a stack access, we need to update the stack pointer. - if (op->Info.Memory.IsStack) - { - ND_UINT64 regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), ND_FALSE); - - regval += op->Size; - - ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, ND_FALSE); - } - - // If this is a string operation, make sure we update RSI/RDI. - if (op->Info.Memory.IsString) - { - ND_UINT64 regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE); - - regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; - - ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE); - } - -done_gla:; - } - else if (op->Type == ND_OP_IMM) - { - Value->Value.Qwords[0] = op->Info.Immediate.Imm; - } - else if (op->Type == ND_OP_CONST) - { - Value->Value.Qwords[0] = op->Info.Constant.Const; - } - else if (op->Type == ND_OP_OFFS) - { - Value->Value.Qwords[0] = op->Info.RelativeOffset.Rel; - } - else - { - return SHEMU_ABORT_UNSUPPORTED_INSTRUX; - } + shemu_memcpy(Bytes, addr + offset, (ND_SIZET)Size); return SHEMU_SUCCESS; } -// -// ShemuSetOperandValue -// -static SHEMU_STATUS -ShemuSetOperandValue( - SHEMU_CONTEXT *Context, - ND_UINT32 Operand, - SHEMU_VALUE *Value - ) -{ - SHEMU_STATUS status; - PND_OPERAND op = &Context->Instruction.Operands[Operand]; - - if (op->Type == ND_OP_REG) - { - switch (op->Info.Register.Type) - { - case ND_REG_GPR: - if (Context->Instruction.Instruction == ND_INS_XCHG && - op->Info.Register.Reg == NDR_RSP) - { - Context->Flags |= SHEMU_FLAG_STACK_PIVOT; - } - - ShemuSetGprValue(Context, op->Info.Register.Reg, op->Size, Value->Value.Qwords[0], - op->Info.Register.IsHigh8); - break; - - case ND_REG_SEG: - ShemuSetSegValue(Context, op->Info.Register.Reg, Value->Value.Words[0]); - break; - - case ND_REG_MMX: - Context->MmxRegisters[op->Info.Register.Reg] = Value->Value.Qwords[0]; - // Only log these when they're written. - if (Context->Options & SHEMU_OPT_TRACE_EMULATION) - { - shemu_printf(Context, " MM%d = 0x%016llx\n", op->Info.Register.Reg, Value->Value.Qwords[0]); - } - break; - - case ND_REG_SSE: - if (Context->Instruction.EncMode != ND_ENCM_LEGACY) - { - // Zero the entire register first, if we have a VEX/EVEX encoded instruction. - nd_memzero(&Context->SseRegisters[op->Info.Register.Reg], ND_MAX_REGISTER_SIZE); - } - else - { - // Zero upper bits in the 128 bits register, if operand size is less than 16 bytes. - // Upper bits in the YMM/ZMM register are preserved. - nd_memzero(&Context->SseRegisters[op->Info.Register.Reg], 16); - } - // Copy the value. - shemu_memcpy(&Context->SseRegisters[op->Info.Register.Reg], - Value->Value.Bytes, - op->Size); - // Only log these when they're written. - if (Context->Options & SHEMU_OPT_TRACE_EMULATION) - { - shemu_printf(Context, - " %cMM%d (HI_32) = 0x%016llx%016llx%016llx%016llx\n", - op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, - Value->Value.Qwords[7], Value->Value.Qwords[6], - Value->Value.Qwords[5], Value->Value.Qwords[4]); - shemu_printf(Context, - " %cMM%d (LO_32) = 0x%016llx%016llx%016llx%016llx\n", - op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, - Value->Value.Qwords[3], Value->Value.Qwords[2], - Value->Value.Qwords[1], Value->Value.Qwords[0]); - } - break; - - case ND_REG_RIP: - Context->Registers.RegRip = ND_TRIM(op->Size, Value->Value.Qwords[0]); - break; - - case ND_REG_FLG: - if (op->Size == 2) - { - *((ND_UINT16*)&Context->Registers.RegFlags) = Value->Value.Words[0]; - } - else - { - Context->Registers.RegFlags = Value->Value.Qwords[0]; - } - // Handle reserved bits. - Context->Registers.RegFlags |= (1ULL << 1); - Context->Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15)); - Context->Registers.RegFlags &= 0x3FFFFF; - break; - - case ND_REG_CR: - switch (op->Info.Register.Reg) - { - case NDR_CR0: - Context->Registers.RegCr0 = Value->Value.Qwords[0]; - break; - case NDR_CR2: - Context->Registers.RegCr2 = Value->Value.Qwords[0]; - break; - case NDR_CR3: - Context->Registers.RegCr3 = Value->Value.Qwords[0]; - break; - case NDR_CR4: - Context->Registers.RegCr4 = Value->Value.Qwords[0]; - break; - case NDR_CR8: - Context->Registers.RegCr8 = Value->Value.Qwords[0]; - break; - default: - return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; - } - break; - - default: - return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; - } - } - else if (op->Type == ND_OP_MEM) - { - // Compute the GLA. - ND_UINT64 gla = ShemuComputeLinearAddress(Context, op); - - // Handle self-write. We store a 1 for each written byte inside the shellcode space. Once the modified bytes - // are executed, we can trigger the self-write detection. - if (ShemuIsShellcodePtr(Context, gla, op->Size)) - { - ShemuSetBits(SHELLBMP(Context), gla - Context->ShellcodeBase, op->Size, 1); - } - - // Handle RIP save on the stack. - if (ShemuIsStackPtr(Context, gla, MAX(op->Size, Context->Instruction.WordLength))) - { - ND_UINT8 stckstrlen = 0; - ND_UINT32 i; - - // Note: only Context->Instruction.WordLength bits are flagged as RIP, as that is the RIP size. - if (Context->Instruction.Instruction == ND_INS_CALLNR || - Context->Instruction.Instruction == ND_INS_CALLNI) - { - ShemuSetBits(STACKBMP(Context), gla - Context->StackBase, Context->Instruction.WordLength, 1); - } - else if (Context->Instruction.Instruction == ND_INS_FNSTENV) - { - // OK: op->Size will be the FPU state size. - ShemuSetBits(STACKBMP(Context), (gla + 0xC) - Context->StackBase, Context->Instruction.WordLength, 1); - } - else if (Context->Instruction.Instruction == ND_INS_FXSAVE || - Context->Instruction.Instruction == ND_INS_FXSAVE64) - { - // OK: op->Size will be the FXSAVE size. - ShemuSetBits(STACKBMP(Context), (gla + 0x8) - Context->StackBase, Context->Instruction.WordLength, 1); - } - else - { - // Something is written on a previously saved RIP; reset it. - ShemuSetBits(STACKBMP(Context), gla - Context->StackBase, op->Size, 0); - } - - // Check if a string is being saved on the stack. Typically used by shellcodes like this: - // PUSH str0 - // PUSH str1 - // ... - // PUSH strn - // Other variants may exist, but all we care about are stores on the stack, and all are checked. - // Note that we will ignore registers which have not been modified during emulation; those are considered - // input values for the emulated code, and may be pointers or other data. We are interested only in - // stack values built within the emulate code. - for (i = 0; i < Value->Size; i++) - { - unsigned char c = Value->Value.Bytes[i]; - - if ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9') || - c == '\\' || c == '/' || c == ':' || c == ' ') - { - stckstrlen++; - } - else - { - break; - } - } - - if (stckstrlen == Value->Size) - { - // Make sure the value is not present inside a non-dirty GPR. - for (i = 0; i < 16; i++) - { - if (ShemuCmpGprValue(Context, i, Value->Size, Value->Value.Qwords[0], ND_FALSE) && - (0 == (Context->DirtyGprBitmap & (1 << i)))) - { - // A register is saved on the stack, but that register wasn't written during the emulation. - stckstrlen = 0; - break; - } - } - } - - Context->StrLength += stckstrlen; - - if (Context->StrLength >= Context->StrThreshold) - { - Context->Flags |= SHEMU_FLAG_STACK_STR; - } - - if (stckstrlen != Value->Size) - { - // Not a full string stored on the stack, reset the counter. - Context->StrLength = 0; - } - } - - // Set the value. - status = ShemuSetMemValue(Context, gla, MIN(op->Size, Value->Size), Value->Value.Bytes); - if (SHEMU_SUCCESS != status) - { - return status; - } - - // If this is a stack access, we need to update the stack pointer. - if (op->Info.Memory.IsStack) - { - ND_UINT64 regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), ND_FALSE); - - regval -= op->Size; - - ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, ND_FALSE); - } - - // If this is a string operation, make sure we update RSI/RDI. - if (op->Info.Memory.IsString) - { - ND_UINT64 regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE); - - regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; - - ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE); - } - } - else - { - return SHEMU_ABORT_INVALID_INSTRUX; - } - - return SHEMU_SUCCESS; -} - - -// -// ShemuMultiply64Unsigned -// -static void -ShemuMultiply64Unsigned( - ND_UINT64 Operand1, - ND_UINT64 Operand2, - ND_UINT64 *ResHigh, - ND_UINT64 *ResLow - ) -{ - ND_UINT64 xLow = (ND_UINT64)(ND_UINT32)Operand1; - ND_UINT64 xHigh = Operand1 >> 32; - ND_UINT64 yLow = (ND_UINT64)(ND_UINT32)Operand2; - ND_UINT64 yHigh = Operand2 >> 32; - - ND_UINT64 p0 = xLow * yLow; - ND_UINT64 p1 = xLow * yHigh; - ND_UINT64 p2 = xHigh * yLow; - ND_UINT64 p3 = xHigh * yHigh; - - ND_UINT32 cy = (ND_UINT32)(((p0 >> 32) + (ND_UINT32)p1 + (ND_UINT32)p2) >> 32); - - *ResLow = p0 + (p1 << 32) + (p2 << 32); - *ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + cy; -} - - -// -// ShemuMultiply64Signed -// -static void -ShemuMultiply64Signed( - ND_SINT64 Operand1, - ND_SINT64 Operand2, - ND_SINT64 *ResHigh, - ND_SINT64 *ResLow - ) -{ - ShemuMultiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow); - if (Operand1 < 0LL) *ResHigh -= Operand2; - if (Operand2 < 0LL) *ResHigh -= Operand1; -} - - -// -// ShemuCheckDiv -// -static ND_BOOL -ShemuCheckDiv( - ND_UINT64 Divident, - ND_UINT64 Divider, - ND_UINT8 Size // The size of the Source (Divider). The Divident is twice as large. - ) -{ - // Returns ND_TRUE if all checks are OK, and Divident / Divider will not cause #DE. - - if (Divider == 0) - { - // Division by zero. - return ND_FALSE; - } - - // If the result won't fit in the destination, a #DE would be generated. - switch (Size) - { - case 1: - if (((Divident >> 8) & 0xFF) >= Divider) - { - return ND_FALSE; - } - break; - - case 2: - if (((Divident >> 16) & 0xFFFF) >= Divider) - { - return ND_FALSE; - } - break; - - case 4: - if (((Divident >> 32) & 0xFFFFFFFF) >= Divider) - { - return ND_FALSE; - } - break; - - default: - // 64 bit source division is not supported. - return ND_FALSE; - } - - return ND_TRUE; -} - - -// -// ShemuCheckIdiv -// -static ND_BOOL -ShemuCheckIdiv( - ND_SINT64 Divident, - ND_SINT64 Divider, - ND_UINT8 Size // The size of the Source (Divider). - ) -{ - ND_BOOL neg1, neg2; - ND_UINT64 quotient, max; - - neg1 = Divident < 0; - neg2 = Divider < 0; - - if (neg1) - { - Divident = -Divident; - } - - if (neg2) - { - Divider = -Divider; - } - - // Do checks when dividing positive values. - if (!ShemuCheckDiv(Divident, Divider, Size)) - { - return ND_FALSE; - } - - // Get the positive quotient. - quotient = (ND_UINT64)Divident / (ND_UINT64)Divider; - - max = (Size == 1) ? 0x80 : (Size == 2) ? 0x8000 : (Size == 4) ? 0x80000000 : 0x8000000000000000; - - if (neg1 ^ neg2) - { - // The Divident and the Divider have different signs, the quotient must be negative. If it's positive => #DE. - if (ND_GET_SIGN(Size, quotient) && quotient != max) - { - return ND_FALSE; - } - } - else - { - // Both the Divident and the Divider are positive/negative, so a positive result must be produced. If it's - // negative => #DE. - if (ND_GET_SIGN(Size, quotient)) - { - return ND_FALSE; - } - } - - return ND_TRUE; -} - - -// -// ShemuPrintContext -// -#ifndef BDDISASM_NO_FORMAT -static void -ShemuPrintContext( +void +ShemuFlushIcache( SHEMU_CONTEXT *Context ) { - char text[ND_MIN_BUF_SIZE] = { 0 }; - - NdToText(&Context->Instruction, Context->Registers.RegRip, ND_MIN_BUF_SIZE, text); - - shemu_printf(Context, " RAX = 0x%016llx RCX = 0x%016llx RDX = 0x%016llx RBX = 0x%016llx\n", - Context->Registers.RegRax, Context->Registers.RegRcx, Context->Registers.RegRdx, Context->Registers.RegRbx); - shemu_printf(Context, " RSP = 0x%016llx RBP = 0x%016llx RSI = 0x%016llx RDI = 0x%016llx\n", - Context->Registers.RegRsp, Context->Registers.RegRbp, Context->Registers.RegRsi, Context->Registers.RegRdi); - shemu_printf(Context, " R8 = 0x%016llx R9 = 0x%016llx R10 = 0x%016llx R11 = 0x%016llx\n", - Context->Registers.RegR8, Context->Registers.RegR9, Context->Registers.RegR10, Context->Registers.RegR11); - shemu_printf(Context, " R12 = 0x%016llx R13 = 0x%016llx R14 = 0x%016llx R15 = 0x%016llx\n", - Context->Registers.RegR12, Context->Registers.RegR13, Context->Registers.RegR14, Context->Registers.RegR15); - shemu_printf(Context, " RIP = 0x%016llx RFLAGS = 0x%016llx ", - Context->Registers.RegRip, Context->Registers.RegFlags); - shemu_printf(Context, " CF:%d PF:%d AF:%d ZF:%d SF:%d TF:%d IF:%d DF:%d OF:%d\n", - GET_FLAG(Context, NDR_RFLAG_CF), - GET_FLAG(Context, NDR_RFLAG_PF), - GET_FLAG(Context, NDR_RFLAG_AF), - GET_FLAG(Context, NDR_RFLAG_ZF), - GET_FLAG(Context, NDR_RFLAG_SF), - GET_FLAG(Context, NDR_RFLAG_TF), - GET_FLAG(Context, NDR_RFLAG_IF), - GET_FLAG(Context, NDR_RFLAG_DF), - GET_FLAG(Context, NDR_RFLAG_OF)); - - shemu_printf(Context, "Emulating: 0x%016llx %s\n", Context->Registers.RegRip, text); + Context->Icache.Address = 0; + Context->Icache.Size = 0; +} + + +// +// ShemuDisplayMemValue +// +void +ShemuDisplayMemValue( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Value, + ND_BOOL Load + ) +{ + char svalue[ND_MAX_REGISTER_SIZE * 2 + 2] = { 0 }; + + if (Size > ND_MAX_REGISTER_SIZE) + { + // Truncate the displayed value to 64 bytes. + Size = ND_MAX_REGISTER_SIZE; + } + + ShemuHexlify(Value, Size, svalue, sizeof(svalue)); + + shemu_printf(Context, " Memory %s, address 0x%016llx, size %lld, value %s\n", + Load ? "LOAD" : "STOR", Gla, Size, svalue); } -#else -#define ShemuPrintContext(Context) -#endif // !BDDISASM_NO_FORMAT // @@ -1746,1463 +555,12 @@ ShemuEmulate( SHEMU_CONTEXT *Context ) { - SHEMU_VALUE res = { 0 }, dst = { 0 }, src = { 0 }, rcx = { 0 }, aux = { 0 }; - ND_BOOL stop = ND_FALSE, cf; - ND_UINT16 cs = 0; - ND_UINT64 tsc = 0x1248fe7a5c30; - - if (ND_NULL == Context) + if (Context->ArchType == SHEMU_ARCH_TYPE_X86) + { + return ShemuX86Emulate(Context); + } + else { return SHEMU_ABORT_INVALID_PARAMETER; } - - if (ND_NULL == Context->Shellcode) - { - return SHEMU_ABORT_INVALID_PARAMETER; - } - - if (ND_NULL == Context->Stack) - { - return SHEMU_ABORT_INVALID_PARAMETER; - } - - if (ND_NULL == Context->Intbuf) - { - return SHEMU_ABORT_INVALID_PARAMETER; - } - - if (SHEMU_INTERNAL_BUFFER_SIZE(Context) > Context->IntbufSize) - { - return SHEMU_ABORT_INVALID_PARAMETER; - } - - if (Context->NopThreshold == 0) - { - Context->NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; - } - - if (Context->StrThreshold == 0) - { - Context->StrThreshold = SHEMU_DEFAULT_STR_THRESHOLD; - } - - while (Context->InstructionsCount++ < Context->MaxInstructionsCount) - { - NDSTATUS ndstatus; - ND_UINT64 rip; - ND_UINT32 i; - - tsc++; - - // Reset all the operands to 0. - nd_memzero(&dst, sizeof(dst)); - nd_memzero(&src, sizeof(src)); - nd_memzero(&res, sizeof(res)); - nd_memzero(&aux, sizeof(aux)); - nd_memzero(&rcx, sizeof(rcx)); - - // The stop flag has been set, this means we've reached a valid instruction, but that instruction cannot be - // emulated (for example, SYSCALL, INT, system instructions, etc). - if (stop) - { - return SHEMU_ABORT_CANT_EMULATE; - } - - // If we already have a detection and we wish to stop on detections, do so now. - if ((0 != Context->Flags) && (0 != (Context->Options & SHEMU_OPT_STOP_ON_EXPLOIT))) - { - return SHEMU_ABORT_SHELLCODE_DETECTED; - } - - // Make sure the RIP is pointing in the right area. We test only 1 byte - the decoder will make sure it can - // access as many bytes as needed and return error in case it can't. - if (!ShemuIsShellcodePtr(Context, Context->Registers.RegRip, 1)) - { - return SHEMU_ABORT_BRANCH_OUTSIDE; - } - - // Get the offset inside the shellcode buffer. - rip = Context->Registers.RegRip - Context->ShellcodeBase; - - // Decode the next instruction. - ndstatus = NdDecodeEx(&Context->Instruction, Context->Shellcode + rip, - Context->ShellcodeSize - (ND_SIZET)rip, Context->Mode, Context->Mode); - if (!ND_SUCCESS(ndstatus)) - { - if (ND_STATUS_BUFFER_TOO_SMALL == ndstatus) - { - return SHEMU_ABORT_BRANCH_OUTSIDE; - } - else - { - return SHEMU_ABORT_INVALID_INSTRUX; - } - } - - // Paranoid check... - if (!ShemuIsShellcodePtr(Context, Context->Registers.RegRip, Context->Instruction.Length)) - { - return SHEMU_ABORT_BRANCH_OUTSIDE; - } - - // Check if we just fetched an instruction from a previously written area, to raise self-write alert. - if (ShemuAnyBitsSet(SHELLBMP(Context), rip, Context->Instruction.Length)) - { - Context->Flags |= SHEMU_FLAG_WRITE_SELF; - } - - // Dump the context. - if (Context->Options & SHEMU_OPT_TRACE_EMULATION) - { - ShemuPrintContext(Context); - } - - // The RIP is incremented BEFORE actually emulating the instruction. This is what the CPU does as well. - Context->Registers.RegRip += Context->Instruction.Length; - - // FPU instructions are "pass-through", we just want to save the RIP, so we can emulate FNSTENV. - if ((Context->Instruction.IsaSet == ND_SET_X87) && (Context->Instruction.Instruction != ND_INS_FNSTENV)) - { - Context->Registers.FpuRip = Context->Registers.RegRip - Context->Instruction.Length; - continue; - } - - switch (Context->Instruction.Instruction) - { - case ND_INS_FNSTENV: - src.Size = Context->Instruction.Operands[0].Size; - src.Value.FpuEnvironment.FpuInstructionPointer = (ND_UINT32)Context->Registers.FpuRip; - SET_OP(Context, 0, &src); - break; - - case ND_INS_FXSAVE: - case ND_INS_FXSAVE64: - src.Size = MIN(Context->Instruction.Operands[0].Size, sizeof(src.Value.XsaveArea)); - src.Value.XsaveArea.FpuRip = Context->Registers.FpuRip; - SET_OP(Context, 0, &src); - break; - - case ND_INS_MOV_CR: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - // Fall through. - - case ND_INS_MOV: - case ND_INS_MOVZX: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_MOVSX: - case ND_INS_MOVSXD: - GET_OP(Context, 1, &src); - GET_OP(Context, 0, &dst); - dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); - SET_OP(Context, 0, &dst); - break; - - case ND_INS_CMOVcc: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - if (ShemuEvalCondition(Context, Context->Instruction.Condition)) - { - SET_OP(Context, 0, &src); - } - else - { - // Write back the same value that was already present in destination. This has the side-effect of - // clearing the upper 32 bit in the 64 bit destination register while in long mode. - SET_OP(Context, 0, &dst); - } - break; - - case ND_INS_SETcc: - if (ShemuEvalCondition(Context, Context->Instruction.Condition)) - { - src.Size = Context->Instruction.Operands[0].Size; - src.Value.Qwords[0] = 1; - } - else - { - src.Size = Context->Instruction.Operands[0].Size; - src.Value.Qwords[0] = 0; - } - SET_OP(Context, 0, &src); - break; - - case ND_INS_XLATB: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_XCHG: - GET_OP(Context, 1, &src); - GET_OP(Context, 0, &dst); - SET_OP(Context, 1, &dst); - SET_OP(Context, 0, &src); - break; - - case ND_INS_XADD: - GET_OP(Context, 1, &src); - GET_OP(Context, 0, &dst); - res.Size = dst.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; - SET_FLAGS(Context, res, dst, src, FM_ADD); - SET_OP(Context, 1, &dst); - SET_OP(Context, 0, &res); - break; - - case ND_INS_CMPXCHG: - GET_OP(Context, 2, &src); - GET_OP(Context, 0, &dst); - - res.Size = src.Size; - // Note: The accumulator is compared with the destination, not the other way around. - res.Value.Qwords[0] = src.Value.Qwords[0] - dst.Value.Qwords[0]; - - SET_FLAGS(Context, res, src, dst, FM_SUB); - - if (src.Value.Qwords[0] == dst.Value.Qwords[0]) - { - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - } - else - { - SET_OP(Context, 2, &dst); - } - break; - - case ND_INS_ADD: - case ND_INS_ADC: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - res.Size = src.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; - - if (ND_INS_ADC == Context->Instruction.Instruction) - { - res.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF); - } - - SET_FLAGS(Context, res, dst, src, FM_ADD); - SET_OP(Context, 0, &res); - - break; - - case ND_INS_SUB: - case ND_INS_SBB: - case ND_INS_CMP: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - res.Size = src.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; - - if (ND_INS_SBB == Context->Instruction.Instruction) - { - res.Value.Qwords[0] -= GET_FLAG(Context, NDR_RFLAG_CF); - } - - SET_FLAGS(Context, res, dst, src, FM_SUB); - - if (ND_INS_CMP != Context->Instruction.Instruction) - { - SET_OP(Context, 0, &res); - } - - break; - - case ND_INS_INC: - GET_OP(Context, 0, &dst); - src.Size = dst.Size; - src.Value.Qwords[0] = 1; - res.Size = src.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; - cf = GET_FLAG(Context, NDR_RFLAG_CF); - SET_FLAGS(Context, res, dst, src, FM_ADD); - SET_FLAG(Context, NDR_RFLAG_CF, cf); - SET_OP(Context, 0, &res); - break; - - case ND_INS_DEC: - GET_OP(Context, 0, &dst); - src.Size = dst.Size; - src.Value.Qwords[0] = 1; - res.Size = src.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; - cf = GET_FLAG(Context, NDR_RFLAG_CF); - SET_FLAGS(Context, res, dst, src, FM_SUB); - SET_FLAG(Context, NDR_RFLAG_CF, cf); - SET_OP(Context, 0, &res); - break; - - case ND_INS_PUSH: - case ND_INS_PUSHF: - GET_OP(Context, 0, &src); - SET_OP(Context, 1, &src); - break; - - case ND_INS_POP: - case ND_INS_POPF: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_PUSHA: - case ND_INS_PUSHAD: - src.Size = 32; - src.Value.Dwords[7] = (ND_UINT32)Context->Registers.RegRax; - src.Value.Dwords[6] = (ND_UINT32)Context->Registers.RegRcx; - src.Value.Dwords[5] = (ND_UINT32)Context->Registers.RegRdx; - src.Value.Dwords[4] = (ND_UINT32)Context->Registers.RegRbx; - src.Value.Dwords[3] = (ND_UINT32)Context->Registers.RegRsp; - src.Value.Dwords[2] = (ND_UINT32)Context->Registers.RegRbp; - src.Value.Dwords[1] = (ND_UINT32)Context->Registers.RegRsi; - src.Value.Dwords[0] = (ND_UINT32)Context->Registers.RegRdi; - SET_OP(Context, 1, &src); - break; - - case ND_INS_POPA: - case ND_INS_POPAD: - GET_OP(Context, 1, &src); - Context->Registers.RegRax = src.Value.Dwords[7]; - Context->Registers.RegRcx = src.Value.Dwords[6]; - Context->Registers.RegRdx = src.Value.Dwords[5]; - Context->Registers.RegRbx = src.Value.Dwords[4]; - Context->Registers.RegRsp = src.Value.Dwords[3]; - Context->Registers.RegRbp = src.Value.Dwords[2]; - Context->Registers.RegRsi = src.Value.Dwords[1]; - Context->Registers.RegRdi = src.Value.Dwords[0]; - break; - - case ND_INS_LEA: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_SHL: - case ND_INS_SAL: - case ND_INS_SHR: - case ND_INS_SAR: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - if (dst.Size == 8) - { - src.Value.Qwords[0] &= 0x3f; - } - else - { - src.Value.Qwords[0] &= 0x1f; - } - - res.Size = dst.Size; - - if (ND_INS_SHL == Context->Instruction.Instruction || - ND_INS_SAL == Context->Instruction.Instruction) - { - res.Value.Qwords[0] = dst.Value.Qwords[0] << src.Value.Qwords[0]; - } - else if (ND_INS_SHR == Context->Instruction.Instruction) - { - res.Value.Qwords[0] = dst.Value.Qwords[0] >> src.Value.Qwords[0]; - } - else - { - ND_SINT64 val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]); - val = val >> src.Value.Qwords[0]; - res.Value.Qwords[0] = (ND_UINT64)val; - } - - if (src.Value.Qwords[0] != 0) - { - // 0 bit shifts do not affect the flags. - if (ND_INS_SHL == Context->Instruction.Instruction || - ND_INS_SAL == Context->Instruction.Instruction) - { - SET_FLAGS(Context, res, dst, src, FM_SHL); - } - else if (ND_INS_SHR == Context->Instruction.Instruction) - { - SET_FLAGS(Context, res, dst, src, FM_SHR); - } - else - { - SET_FLAGS(Context, res, dst, src, FM_SAR); - } - } - - SET_OP(Context, 0, &res); - break; - - case ND_INS_RCL: - case ND_INS_RCR: - case ND_INS_ROL: - case ND_INS_ROR: - { - ND_UINT32 cnt, tempcnt, cntmask, bitwidth; - ND_UINT8 tempCF = 0; - - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - cnt = (ND_UINT32)src.Value.Qwords[0]; - cntmask = ((dst.Size == 8) ? 0x3F : 0x1F); - tempcnt = (cnt & cntmask); - bitwidth = (ND_UINT32)dst.Size * 8; - - if (ND_INS_RCL == Context->Instruction.Instruction || - ND_INS_RCR == Context->Instruction.Instruction) - { - if (dst.Size == 1) - { - tempcnt %= 9; - } - else if (dst.Size == 2) - { - tempcnt %= 17; - } - } - else - { - tempcnt %= (dst.Size * 8); - } - - if (ND_INS_RCL == Context->Instruction.Instruction) - { - tempCF = GET_FLAG(Context, NDR_RFLAG_CF); - - if (tempcnt != 0) - { - // tempcnt is in range [1, dst bit width]. - ND_UINT64 left = (tempcnt == bitwidth) ? 0 : (dst.Value.Qwords[0] << tempcnt); - ND_UINT64 right = (tempcnt == 1) ? 0 : (dst.Value.Qwords[0] >> (bitwidth - tempcnt + 1)); - - SET_FLAG(Context, NDR_RFLAG_CF, ND_GET_BIT(bitwidth - tempcnt, dst.Value.Qwords[0])); - - dst.Value.Qwords[0] = left | ((ND_UINT64)tempCF << (tempcnt - 1)) | right; - } - - if ((cnt & cntmask) == 1) - { - SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, NDR_RFLAG_CF)); - } - } - else if (ND_INS_RCR == Context->Instruction.Instruction) - { - tempCF = GET_FLAG(Context, NDR_RFLAG_CF); - - if ((cnt & cntmask) == 1) - { - SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, NDR_RFLAG_CF)); - } - - if (tempcnt != 0) - { - // tempcnt is in range [1, dst bit width]. - ND_UINT64 left = (tempcnt == bitwidth) ? 0 : (dst.Value.Qwords[0] >> tempcnt); - ND_UINT64 right = (tempcnt == 1) ? 0 : (dst.Value.Qwords[0] << (bitwidth - tempcnt + 1)); - - SET_FLAG(Context, NDR_RFLAG_CF, ND_GET_BIT(tempcnt - 1, dst.Value.Qwords[0])); - - dst.Value.Qwords[0] = left | ((ND_UINT64)tempCF << (bitwidth - tempcnt)) | right; - } - } - else if (ND_INS_ROL == Context->Instruction.Instruction) - { - if (tempcnt != 0) - { - // tempcnt is in range [1, dst bit width - 1]. - ND_UINT64 left = dst.Value.Qwords[0] << tempcnt; - ND_UINT64 right = dst.Value.Qwords[0] >> (bitwidth - tempcnt); - - dst.Value.Qwords[0] = left | right; - } - - if ((cnt & cntmask) != 0) - { - SET_FLAG(Context, NDR_RFLAG_CF, ND_LSB(dst.Size, dst.Value.Qwords[0])); - } - - if ((cnt & cntmask) == 1) - { - SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - GET_FLAG(Context, NDR_RFLAG_CF)); - } - } - else // ND_INS_ROR - { - if (tempcnt != 0) - { - // tempcnt is in range [1, dst bit width - 1]. - ND_UINT64 left = (dst.Value.Qwords[0] >> tempcnt); - ND_UINT64 right = (dst.Value.Qwords[0] << (bitwidth - tempcnt)); - - dst.Value.Qwords[0] = left | right; - } - - if ((cnt & cntmask) != 0) - { - SET_FLAG(Context, NDR_RFLAG_CF, ND_MSB(dst.Size, dst.Value.Qwords[0])); - } - - if ((cnt & cntmask) == 1) - { - SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ - ND_GET_BIT(dst.Size * 8ULL - 2, dst.Value.Qwords[0])); - } - } - - SET_OP(Context, 0, &dst); - } - break; - - case ND_INS_OR: - case ND_INS_XOR: - case ND_INS_AND: - case ND_INS_TEST: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - res.Size = dst.Size; - - if (ND_INS_OR == Context->Instruction.Instruction) - { - res.Value.Qwords[0] = dst.Value.Qwords[0] | src.Value.Qwords[0]; - } - else if (ND_INS_XOR == Context->Instruction.Instruction) - { - res.Value.Qwords[0] = dst.Value.Qwords[0] ^ src.Value.Qwords[0]; - } - else - { - res.Value.Qwords[0] = dst.Value.Qwords[0] & src.Value.Qwords[0]; - } - - if (ND_INS_TEST != Context->Instruction.Instruction) - { - SET_OP(Context, 0, &res); - } - - SET_FLAGS(Context, res, dst, src, FM_LOGIC); - break; - - case ND_INS_NOT: - GET_OP(Context, 0, &dst); - dst.Value.Qwords[0] = ~dst.Value.Qwords[0]; - SET_OP(Context, 0, &dst); - break; - - case ND_INS_NEG: - GET_OP(Context, 0, &src); - dst.Size = src.Size; - dst.Value.Qwords[0] = 0; - res.Size = src.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; - SET_OP(Context, 0, &res); - SET_FLAGS(Context, res, dst, src, FM_SUB); - SET_FLAG(Context, NDR_RFLAG_CF, src.Value.Qwords[0] != 0); - break; - - case ND_INS_BT: - case ND_INS_BTS: - case ND_INS_BTR: - case ND_INS_BTC: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - src.Value.Qwords[0] %= dst.Size * 8ULL; - - // Store the bit inside CF. - SET_FLAG(Context, NDR_RFLAG_CF, (dst.Value.Qwords[0] >> src.Value.Qwords[0]) & 1); - - if (ND_INS_BTS == Context->Instruction.Instruction) - { - dst.Value.Qwords[0] |= (1ULL << src.Value.Qwords[0]); - } - else if (ND_INS_BTR == Context->Instruction.Instruction) - { - dst.Value.Qwords[0] &= ~(1ULL << src.Value.Qwords[0]); - } - else if (ND_INS_BTC == Context->Instruction.Instruction) - { - dst.Value.Qwords[0] ^= (1ULL << src.Value.Qwords[0]); - } - - if (ND_INS_BT != Context->Instruction.Instruction) - { - SET_OP(Context, 0, &dst); - } - - break; - - case ND_INS_Jcc: - if (ShemuEvalCondition(Context, Context->Instruction.Condition)) - { - // Modify the RIP if the branch is taken. - GET_OP(Context, 1, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; - SET_OP(Context, 1, &aux); - } - break; - - case ND_INS_JrCXZ: - // Fetch the rCX value. It could be CX, ECX or RCX, depending on address size. - GET_OP(Context, 1, &rcx); - if (rcx.Value.Qwords[0] == 0) - { - // Modify the RIP if the branch is taken. - GET_OP(Context, 2, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; - SET_OP(Context, 2, &aux); - } - break; - - case ND_INS_LOOP: - case ND_INS_LOOPNZ: - case ND_INS_LOOPZ: - // rCX is decremented first. Note that the size depends on address size. - GET_OP(Context, 1, &rcx); - rcx.Value.Qwords[0]--; - SET_OP(Context, 1, &rcx); - if (rcx.Value.Qwords[0] > 0) - { - if (((ND_INS_LOOPNZ == Context->Instruction.Instruction) && (0 == GET_FLAG(Context, NDR_RFLAG_ZF))) || - ((ND_INS_LOOPZ == Context->Instruction.Instruction) && (0 != GET_FLAG(Context, NDR_RFLAG_ZF))) || - (ND_INS_LOOP == Context->Instruction.Instruction)) - { - // Modify the RIP if the branch is taken. - GET_OP(Context, 2, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; - SET_OP(Context, 2, &aux); - } - } - break; - - case ND_INS_JMPNR: - GET_OP(Context, 1, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; - SET_OP(Context, 1, &aux); - break; - - case ND_INS_JMPNI: - GET_OP(Context, 0, &src); - SET_OP(Context, 1, &src); // Set the RIP to the new value. - break; - - case ND_INS_CALLNR: - // Save the EIP on the stack. - GET_OP(Context, 1, &aux); - SET_OP(Context, 2, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.RelativeOffset.Rel; - SET_OP(Context, 1, &aux); - break; - - case ND_INS_CALLNI: - GET_OP(Context, 0, &src); - GET_OP(Context, 1, &dst); // The RIP - SET_OP(Context, 2, &dst); // Save the RIP on the stack. - SET_OP(Context, 1, &src); // Set the RIP to the new value. - break; - - case ND_INS_RETN: - if (!Context->Instruction.HasImm1) - { - // The simple RET form, 0xC3 - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - } - else - { - // The RET Imm16 form, 0xC2 - GET_OP(Context, 3, &src); - SET_OP(Context, 1, &src); - - // Patch the RSP register. - GET_OP(Context, 2, &aux); - aux.Value.Qwords[0] += Context->Instruction.Operands[0].Info.Immediate.Imm; - SET_OP(Context, 2, &aux); - } - break; - - case ND_INS_JMPFD: - case ND_INS_CALLFD: - cs = (ND_UINT16)Context->Instruction.Operands[0].Info.Address.BaseSeg; - goto check_far_branch; - - case ND_INS_JMPFI: - case ND_INS_CALLFI: - case ND_INS_IRET: - case ND_INS_RETF: - if (Context->Instruction.Instruction == ND_INS_RETF) - { - if (Context->Instruction.Operands[0].Type == ND_OP_IMM) - { - // RETF imm - GET_OP(Context, 3, &src); - } - else - { - // RETF - GET_OP(Context, 2, &src); - } - } - else if (Context->Instruction.Instruction == ND_INS_IRET) - { - // IRET - GET_OP(Context, 2, &src); - } - else - { - // JMP/CALL far - GET_OP(Context, 0, &src); - } - - // The destination code segment is the second WORD/DWORD/QWORD. - switch (Context->Instruction.WordLength) - { - case 2: - cs = (ND_UINT16)src.Value.Words[1]; - break; - case 4: - cs = (ND_UINT16)src.Value.Dwords[1]; - break; - case 8: - cs = (ND_UINT16)src.Value.Qwords[1]; - break; - default: - cs = 0; - break; - } - -check_far_branch: - if (Context->Mode == ND_CODE_32 && cs == 0x33) - { - Context->Flags |= SHEMU_FLAG_HEAVENS_GATE; - } - - // We may, in the future, emulate far branches, but they imply some tricky context switches (including - // the default TEB), so it may not be as straight forward as it seems. For now, all we wish to achieve - // is detection of far branches in long-mode, from Wow 64. - stop = ND_TRUE; - break; - - case ND_INS_LODS: - case ND_INS_STOS: - case ND_INS_MOVS: - // Fetch the rCX register, which is the third operand in case of repeated instructions. - while (Context->InstructionsCount < Context->MaxInstructionsCount) - { - GET_OP(Context, 2, &rcx); - - if (Context->Instruction.IsRepeated && (rcx.Value.Qwords[0] == 0)) - { - break; - } - - // Load the source into the destination. - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - - if (Context->Instruction.IsRepeated) - { - // Decrement RCX. - rcx.Value.Qwords[0]--; - SET_OP(Context, 2, &rcx); - } - else - { - break; - } - - Context->InstructionsCount++; - } - break; - - case ND_INS_SCAS: - case ND_INS_CMPS: - while (Context->InstructionsCount < Context->MaxInstructionsCount) - { - GET_OP(Context, 2, &rcx); - - if (Context->Instruction.IsRepeated && (rcx.Value.Qwords[0] == 0)) - { - break; - } - - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - res.Size = dst.Size; - res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; - - ShemuSetFlags(Context, res.Value.Qwords[0], dst.Value.Qwords[0], src.Value.Qwords[0], res.Size, FM_SUB); - - if (Context->Instruction.IsRepeated) - { - // Decrement RCX. - rcx.Value.Qwords[0]--; - SET_OP(Context, 2, &rcx); - - if (Context->Instruction.HasRepRepzXrelease && !GET_FLAG(Context, NDR_RFLAG_ZF)) - { - break; - } - - if (Context->Instruction.HasRepnzXacquireBnd && GET_FLAG(Context, NDR_RFLAG_ZF)) - { - break; - } - } - else - { - break; - } - - Context->InstructionsCount++; - } - break; - - case ND_INS_MUL: - case ND_INS_IMUL: - if (Context->Instruction.ExpOperandsCount == 1) - { - // MUL or IMUL with a single explicit operand. - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - res.Size = dst.Size * 2; - } - else if (Context->Instruction.ExpOperandsCount == 2) - { - // IMUL with 2 explicit operands. - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - res.Size = dst.Size; - } - else - { - // IMUL with 3 operands. The first operand is the write-only destination. - GET_OP(Context, 1, &dst); - GET_OP(Context, 2, &src); - res.Size = dst.Size; - } - - - if (dst.Size == 1) - { - if (ND_INS_MUL == Context->Instruction.Instruction) - { - res.Value.Words[0] = dst.Value.Bytes[0] * src.Value.Bytes[0]; - } - else - { - res.Value.Words[0] = (ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0]; - } - } - else if (dst.Size == 2) - { - if (ND_INS_MUL == Context->Instruction.Instruction) - { - res.Value.Dwords[0] = dst.Value.Words[0] * src.Value.Words[0]; - } - else - { - res.Value.Dwords[0] = (ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0]; - } - } - else if (dst.Size == 4) - { - if (ND_INS_MUL == Context->Instruction.Instruction) - { - res.Value.Qwords[0] = dst.Value.Qwords[0] * src.Value.Qwords[0]; - } - else - { - res.Value.Qwords[0] = (ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0]; - } - } - else - { - if (ND_INS_MUL == Context->Instruction.Instruction) - { - ShemuMultiply64Unsigned(dst.Value.Qwords[0], src.Value.Qwords[0], - &res.Value.Qwords[1], &res.Value.Qwords[0]); - } - else - { - ShemuMultiply64Signed(dst.Value.Qwords[0], src.Value.Qwords[0], - (ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]); - } - } - - if (Context->Instruction.ExpOperandsCount == 1) - { - // The result is stored in AX, DX:AX, EDX:EAX or RDX:RAX for the single-operand form. - switch (dst.Size) - { - case 1: - *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0]; - break; - case 2: - *((ND_UINT16*)&Context->Registers.RegRdx) = res.Value.Words[1]; - *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0]; - break; - case 4: - Context->Registers.RegRdx = res.Value.Dwords[1]; - Context->Registers.RegRax = res.Value.Dwords[0]; - break; - case 8: - Context->Registers.RegRdx = res.Value.Qwords[1]; - Context->Registers.RegRax = res.Value.Qwords[0]; - break; - } - } - else - { - // The result is truncated and stored in the destination operand for the 2 & 3 operands forms. - SET_OP(Context, 0, &res); - } - - // Set the flags. - if (ND_INS_MUL == Context->Instruction.Instruction) - { - ND_UINT8 cfof = 0; - - // CF and OF are set to 0 if the high part of the result is 0, otherwise they are set to 1. - switch (dst.Size) - { - case 1: - cfof = (0 == res.Value.Bytes[1]) ? 0 : 1; - break; - case 2: - cfof = (0 == res.Value.Words[1]) ? 0 : 1; - break; - case 4: - cfof = (0 == res.Value.Dwords[1]) ? 0 : 1; - break; - case 8: - cfof = (0 == res.Value.Qwords[1]) ? 0 : 1; - break; - } - - SET_FLAG(Context, NDR_RFLAG_CF, cfof); - SET_FLAG(Context, NDR_RFLAG_OF, cfof); - } - else - { - // The CF and OF flags are set when the signed integer value of the intermediate product differs from - // the sign extended operand - size - truncated product, otherwise the CF and OF flags are cleared. - ND_UINT8 cfof = 0, sign = 0; - - sign = ND_MSB(dst.Size, res.Value.Qwords[0]); - - switch (dst.Size) - { - case 1: - cfof = (0 == res.Value.Bytes[1] && 0 == sign) || - ((ND_UINT8)-1 == res.Value.Bytes[1] && 1 == sign) ? 0 : 1; - break; - case 2: - cfof = (0 == res.Value.Words[1] && 0 == sign) || - ((ND_UINT16)-1 == res.Value.Words[1] && 1 == sign) ? 0 : 1; - break; - case 4: - cfof = (0 == res.Value.Dwords[1] && 0 == sign) || - ((ND_UINT32)-1 == res.Value.Dwords[1] && 1 == sign) ? 0 : 1; - break; - case 8: - cfof = (0 == res.Value.Qwords[1] && 0 == sign) || - ((ND_UINT64)-1 == res.Value.Qwords[1] && 1 == sign) ? 0 : 1; - break; - } - - SET_FLAG(Context, NDR_RFLAG_CF, cfof); - SET_FLAG(Context, NDR_RFLAG_OF, cfof); - } - - break; - - case ND_INS_DIV: - case ND_INS_IDIV: - // DIV and IDIV only exist with a single explicit operand encoding. All flags are undefined. - GET_OP(Context, 0, &src); - - if (src.Size == 1) - { - ND_UINT16 divident; - - divident = (ND_UINT16)Context->Registers.RegRax; - - if (ND_INS_DIV == Context->Instruction.Instruction) - { - if (!ShemuCheckDiv(divident, src.Value.Bytes[0], 1)) - { - stop = ND_TRUE; - break; - } - - res.Value.Bytes[0] = (ND_UINT8)(divident / src.Value.Bytes[0]); - res.Value.Bytes[1] = (ND_UINT8)(divident % src.Value.Bytes[0]); - } - else - { - if (!ShemuCheckIdiv((ND_SINT64)(ND_SINT16)divident, (ND_SINT64)(ND_SINT8)src.Value.Bytes[0], 1)) - { - stop = ND_TRUE; - break; - } - - res.Value.Bytes[0] = (ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]); - res.Value.Bytes[1] = (ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]); - } - - // Result in AX (AL - quotient, AH - reminder). - *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0]; - } - else if (src.Size == 2) - { - ND_UINT32 divident; - - divident = ((ND_UINT32)(ND_UINT16)Context->Registers.RegRdx << 16) | - (ND_UINT32)(ND_UINT16)Context->Registers.RegRax; - - if (ND_INS_DIV == Context->Instruction.Instruction) - { - if (!ShemuCheckDiv(divident, src.Value.Words[0], 2)) - { - stop = ND_TRUE; - break; - } - - res.Value.Words[0] = (ND_UINT16)(divident / src.Value.Words[0]); - res.Value.Words[1] = (ND_UINT16)(divident % src.Value.Words[0]); - } - else - { - if (!ShemuCheckIdiv((ND_SINT64)(ND_SINT32)divident, (ND_SINT64)(ND_SINT16)src.Value.Words[0], 2)) - { - stop = ND_TRUE; - break; - } - - res.Value.Words[0] = (ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]); - res.Value.Words[1] = (ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]); - } - - *((ND_UINT16*)&Context->Registers.RegRdx) = res.Value.Words[1]; - *((ND_UINT16*)&Context->Registers.RegRax) = res.Value.Words[0]; - } - else if (src.Size == 4) - { - ND_UINT64 divident; - - divident = ((ND_UINT64)(ND_UINT32)Context->Registers.RegRdx << 32) | - (ND_UINT64)(ND_UINT32)Context->Registers.RegRax; - - if (ND_INS_DIV == Context->Instruction.Instruction) - { - if (!ShemuCheckDiv(divident, src.Value.Dwords[0], 4)) - { - stop = ND_TRUE; - break; - } - - res.Value.Dwords[0] = (ND_UINT32)(divident / src.Value.Dwords[0]); - res.Value.Dwords[1] = (ND_UINT32)(divident % src.Value.Dwords[0]); - } - else - { - if (!ShemuCheckIdiv((ND_SINT64)divident, (ND_SINT64)(ND_SINT32)src.Value.Dwords[0], 4)) - { - stop = ND_TRUE; - break; - } - - res.Value.Dwords[0] = (ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]); - res.Value.Dwords[1] = (ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]); - } - - Context->Registers.RegRdx = res.Value.Dwords[1]; - Context->Registers.RegRax = res.Value.Dwords[0]; - } - else if (src.Size == 8) - { - /// Not implemented! - } - - break; - - case ND_INS_CLD: - SET_FLAG(Context, NDR_RFLAG_DF, 0); - break; - - case ND_INS_STD: - SET_FLAG(Context, NDR_RFLAG_DF, 1); - break; - - case ND_INS_CLC: - SET_FLAG(Context, NDR_RFLAG_CF, 0); - break; - - case ND_INS_STC: - SET_FLAG(Context, NDR_RFLAG_CF, 1); - break; - - case ND_INS_CMC: - Context->Registers.RegFlags ^= NDR_RFLAG_CF; - break; - - case ND_INS_STI: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - SET_FLAG(Context, NDR_RFLAG_IF, 1); - break; - - case ND_INS_CLI: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - SET_FLAG(Context, NDR_RFLAG_IF, 0); - break; - - case ND_INS_SAHF: - { - ND_UINT8 ah = (Context->Registers.RegRax >> 8) & 0xFF; - // Handle reserved bits. - ah |= (1 << 1); - ah &= ~((1 << 3) | (1 << 5)); - ((ND_UINT8 *)&Context->Registers.RegFlags)[0] = ah; - } - break; - - case ND_INS_LAHF: - { - ND_UINT8 ah = ((ND_UINT8 *)&Context->Registers.RegFlags)[0]; - ((ND_UINT8 *)&Context->Registers.RegRax)[1] = ah; - } - break; - - case ND_INS_SALC: - if (GET_FLAG(Context, NDR_RFLAG_CF)) - { - *((ND_UINT8 *)&Context->Registers.RegRax) = 0xFF; - } - else - { - *((ND_UINT8 *)&Context->Registers.RegRax) = 0x0; - } - break; - - case ND_INS_NOP: - Context->NopCount++; - break; - - case ND_INS_WAIT: - break; - - case ND_INS_CBW: - case ND_INS_CWDE: - case ND_INS_CDQE: - GET_OP(Context, 1, &src); - dst.Size = src.Size * 2; - dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); - SET_OP(Context, 0, &dst); - break; - - case ND_INS_CWD: - case ND_INS_CDQ: - case ND_INS_CQO: - GET_OP(Context, 1, &src); - dst.Size = src.Size; - if (ND_GET_SIGN(src.Size, src.Value.Qwords[0])) - { - dst.Value.Qwords[0] = 0xFFFFFFFFFFFFFFFF; - } - else - { - dst.Value.Qwords[0] = 0; - } - SET_OP(Context, 0, &dst); - break; - - case ND_INS_AAA: - case ND_INS_AAD: - case ND_INS_AAM: - case ND_INS_AAS: - case ND_INS_DAA: - case ND_INS_DAS: - // Ignore these for now. - break; - - case ND_INS_ENDBR: - // Acts as a NOP, it's just a hint to the decoder. - break; - - case ND_INS_LFENCE: - case ND_INS_SFENCE: - case ND_INS_MFENCE: - // Nothing can be done for them, really. - break; - - case ND_INS_CPUID: - // OK; EAX, EBX, ECX and EDX are modified, which also zeroes the high 32 bit. - Context->Registers.RegRax = 0; - Context->Registers.RegRbx = 0; - Context->Registers.RegRcx = 0; - Context->Registers.RegRdx = 0; - break; - - // Some basic MMX/SSE instructions supported. - case ND_INS_EMMS: - nd_memzero(Context->MmxRegisters, sizeof(Context->MmxRegisters)); - break; - - case ND_INS_MOVD: - case ND_INS_MOVQ: - case ND_INS_MOVDQU: - case ND_INS_MOVDQA: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_PUNPCKLBW: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - if (dst.Size == 8) - { - // Operating on MMX register. - dst.Value.Bytes[7] = src.Value.Bytes[3]; - dst.Value.Bytes[6] = dst.Value.Bytes[3]; - dst.Value.Bytes[5] = src.Value.Bytes[2]; - dst.Value.Bytes[4] = dst.Value.Bytes[2]; - dst.Value.Bytes[3] = src.Value.Bytes[1]; - dst.Value.Bytes[2] = dst.Value.Bytes[1]; - dst.Value.Bytes[1] = src.Value.Bytes[0]; - } - else - { - // Operating on XMM register. - dst.Value.Bytes[15] = src.Value.Bytes[7]; - dst.Value.Bytes[14] = dst.Value.Bytes[7]; - dst.Value.Bytes[13] = src.Value.Bytes[6]; - dst.Value.Bytes[12] = dst.Value.Bytes[6]; - dst.Value.Bytes[11] = src.Value.Bytes[5]; - dst.Value.Bytes[10] = dst.Value.Bytes[5]; - dst.Value.Bytes[9] = src.Value.Bytes[4]; - dst.Value.Bytes[8] = dst.Value.Bytes[4]; - dst.Value.Bytes[7] = src.Value.Bytes[3]; - dst.Value.Bytes[6] = dst.Value.Bytes[3]; - dst.Value.Bytes[5] = src.Value.Bytes[2]; - dst.Value.Bytes[4] = dst.Value.Bytes[2]; - dst.Value.Bytes[3] = src.Value.Bytes[1]; - dst.Value.Bytes[2] = dst.Value.Bytes[1]; - dst.Value.Bytes[1] = src.Value.Bytes[0]; - } - SET_OP(Context, 0, &dst); - break; - - case ND_INS_PXOR: - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - for (i = 0; i < dst.Size; i++) - { - dst.Value.Bytes[i] ^= src.Value.Bytes[i]; - } - SET_OP(Context, 0, &dst); - break; - - // Some basic AVX/AVX2 instructions support. - case ND_INS_VMOVD: - case ND_INS_VMOVQ: - case ND_INS_VMOVDQU: - case ND_INS_VMOVDQA: - GET_OP(Context, 1, &src); - SET_OP(Context, 0, &src); - break; - - case ND_INS_VPBROADCASTB: - case ND_INS_VPBROADCASTW: - case ND_INS_VPBROADCASTD: - case ND_INS_VPBROADCASTQ: - GET_OP(Context, 1, &src); - dst.Size = Context->Instruction.Operands[0].Size; - for (i = 0; i < dst.Size / src.Size; i++) - { - switch (src.Size) - { - case 1: - dst.Value.Bytes[i] = src.Value.Bytes[0]; - break; - case 2: - dst.Value.Words[i] = src.Value.Words[0]; - break; - case 4: - dst.Value.Dwords[i] = src.Value.Dwords[0]; - break; - default: - dst.Value.Qwords[i] = src.Value.Qwords[0]; - break; - } - } - SET_OP(Context, 0, &dst); - break; - - case ND_INS_VPXOR: - GET_OP(Context, 1, &dst); - GET_OP(Context, 2, &src); - for (i = 0; i < dst.Size; i++) - { - dst.Value.Bytes[i] ^= src.Value.Bytes[i]; - } - SET_OP(Context, 0, &dst); - break; - - // Software interrupt/SYSCALL/SYSENTER. - case ND_INS_INT: - if (Context->Instruction.Immediate1 == 0x80 || - Context->Instruction.Immediate1 == 0x2E) - { - Context->Flags |= SHEMU_FLAG_SYSCALL; - } - - stop = ND_TRUE; - break; - - case ND_INS_SYSCALL: - case ND_INS_SYSENTER: - Context->Flags |= SHEMU_FLAG_SYSCALL; - stop = ND_TRUE; - break; - - // Some basic privileged instructions supported, specific to kernel-mode shellcodes. - case ND_INS_SWAPGS: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - Context->Flags |= SHEMU_FLAG_SWAPGS; - stop = ND_TRUE; - break; - - case ND_INS_RDMSR: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - if ((Context->Registers.RegRcx == 0xC0000082 && ND_CODE_64 == Context->Mode) || - (Context->Registers.RegRcx == 0x00000176 && ND_CODE_32 == Context->Mode)) - { - Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_READ; - } - - stop = ND_TRUE; - break; - - case ND_INS_WRMSR: - if (Context->Ring != 0) - { - return SHEMU_ABORT_NO_PRIVILEGE; - } - - if ((Context->Registers.RegRcx == 0xC0000082 && ND_CODE_64 == Context->Mode) || - (Context->Registers.RegRcx == 0x00000176 && ND_CODE_32 == Context->Mode)) - { - Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_WRITE; - } - - stop = ND_TRUE; - break; - - case ND_INS_SIDT: - if (Context->Ring == 0) - { - // Flag this only in ring0, as we treat the SHEMU_FLAG_SIDT as a ring0 specific indicator - it can be - // used to locate the kernel image. - Context->Flags |= SHEMU_FLAG_SIDT; - } - - stop = ND_TRUE; - break; - -#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86) - case ND_INS_AESIMC: - case ND_INS_AESDEC: - case ND_INS_AESDECLAST: - { - __m128i val, key; - - // Make sure AES support is present, and we can emulate AES decryption using AES instructions. - if (0 == (Context->Options & SHEMU_OPT_SUPPORT_AES)) - { - stop = ND_TRUE; - break; - } - - GET_OP(Context, 0, &dst); - GET_OP(Context, 1, &src); - - shemu_memcpy(&val, &dst, 16); - shemu_memcpy(&key, &src, 16); - - if (Context->Instruction.Instruction == ND_INS_AESDEC) - { - val = _mm_aesdec_si128(val, key); - } - else if (Context->Instruction.Instruction == ND_INS_AESDECLAST) - { - val = _mm_aesdeclast_si128(val, key); - } - else if (Context->Instruction.Instruction == ND_INS_AESIMC) - { - val = _mm_aesimc_si128(key); - } - - shemu_memcpy(&dst, &val, 16); - - SET_OP(Context, 0, &dst); - break; - } -#endif - - case ND_INS_RDTSC: - src.Size = 4; - // Set EAX to lower 32 bits. - src.Value.Dwords[0] = tsc & 0xFFFFFFFF; - SET_OP(Context, 0, &src); - // Set EDX to upper 32 bits. - src.Value.Dwords[0] = tsc >> 32; - SET_OP(Context, 1, &src); - break; - - - default: - return SHEMU_ABORT_UNSUPPORTED_INSTRUX; - } - } - - // Minimum percent of the instructions were NOPs => consider we have a NOP sled. Note that we get here only if - // the maximum number of instructions has been emulated successfully; if the emulation is aborted for any reason, - // this code will have no effect. - if ((Context->InstructionsCount >= Context->MaxInstructionsCount / 2) && - (Context->NopCount >= Context->InstructionsCount * Context->NopThreshold / 100)) - { - Context->Flags |= SHEMU_FLAG_NOP_SLED; - return SHEMU_ABORT_SHELLCODE_DETECTED; - } - - return SHEMU_SUCCESS; -} +} \ No newline at end of file diff --git a/bdshemu/bdshemu.vcxproj b/bdshemu/bdshemu.vcxproj index 86ae440..a979c47 100644 --- a/bdshemu/bdshemu.vcxproj +++ b/bdshemu/bdshemu.vcxproj @@ -643,10 +643,13 @@ + + - + + diff --git a/bdshemu/bdshemu.vcxproj.filters b/bdshemu/bdshemu.vcxproj.filters index 1402533..8959696 100644 --- a/bdshemu/bdshemu.vcxproj.filters +++ b/bdshemu/bdshemu.vcxproj.filters @@ -16,18 +16,36 @@ {e9031566-ae16-49a2-807a-b33729f7b1d4} - - - - Source Files - + + {d95202e3-5db7-4437-aaee-b42dd317eb1b} + + + {b37ad850-b053-4c49-a61c-81abc50c144e} + + + {ca0d8798-3c56-489f-8cc5-fe315397c76a} + Header Files\public - + + Header Files\public\x86 + + + Header Files\private + + Header Files\public + + + Source Files + + + Source Files\x86 + + \ No newline at end of file diff --git a/bdshemu/bdshemu_x86.c b/bdshemu/bdshemu_x86.c new file mode 100644 index 0000000..8072105 --- /dev/null +++ b/bdshemu/bdshemu_x86.c @@ -0,0 +1,3568 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +// +// bdshemu.c +// + +#include "../inc/bdshemu.h" +#include "../bddisasm/include/bddisasm_crt.h" +#include "include/bdshemu_common.h" + +#ifdef __clang__ +#include +#else +#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86) +#include +#endif // defined(ND_ARCH_X64) || defined(ND_ARCH_X86) +#endif // __clang__ + +// +// A generic emulator value. +// +typedef struct _SHEMU_VALUE +{ + union + { + ND_UINT8 Bytes[ND_MAX_REGISTER_SIZE]; + ND_UINT16 Words[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT16)]; + ND_UINT32 Dwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT32)]; + ND_UINT64 Qwords[ND_MAX_REGISTER_SIZE / sizeof(ND_UINT64)]; + + struct + { + ND_UINT16 FpuControlWord; + ND_UINT16 FpuStatusWord; + ND_UINT16 FpuTagWord; + ND_UINT16 Rsvd; + ND_UINT32 FpuDataPointer; + ND_UINT32 FpuInstructionPointer; + ND_UINT32 FpuLastInstructionOpcode; + } FpuEnvironment; + + struct + { + ND_UINT16 FpuControlWord; + ND_UINT16 FpuStatuwsWord; + ND_UINT16 FpuTagWord; + ND_UINT16 FpuOpcode; + ND_UINT64 FpuRip; + ND_UINT64 FpuDataPointer; + ND_UINT32 Mxcsr; + ND_UINT32 MxcsrMask; + } XsaveArea; + + struct + { + ND_UINT16 Limit; + ND_UINT64 Base; + } Descriptor; + + } Value; + + ND_OPERAND_SIZE Size; +} SHEMU_VALUE, *PSHEMU_VALUE; + + +enum +{ + FM_LOGIC, + FM_SHL, + FM_SHR, + FM_SAR, + FM_SUB, + FM_ADD, +} FLAGS_MODE; + + +#define GET_OP(ctx, op, val) { \ + SHEMU_STATUS status = ShemuX86GetOperandValue(ctx, op, val); \ + if (SHEMU_SUCCESS != status) \ + { \ + return status; \ + } \ +} + +#define SET_OP(ctx, op, val) { \ + SHEMU_STATUS status = ShemuX86SetOperandValue(ctx, op, val); \ + if (SHEMU_SUCCESS != status) \ + { \ + return status; \ + } \ +} + +#define GET_FLAG(ctx, flg) (!!((ctx)->Arch.X86.Registers.RegFlags & (flg))) +#define SET_FLAG(ctx, flg, val) ShemuX86SetFlag(ctx, flg, val) +#define SET_FLAGS(ctx, dst, src1, src2, fm) ShemuX86SetFlags(ctx, dst.Value.Qwords[0], src1.Value.Qwords[0], \ + src2.Value.Qwords[0], dst.Size, fm) + + +// +// ShemuX86SetFlag +// +static void +ShemuX86SetFlag( + SHEMU_CONTEXT *Context, + ND_UINT64 Flag, + ND_UINT64 Value + ) +{ + // {NF} present for instruction, no flags will be modified. + if (Context->Arch.X86.Instruction.HasNf) + { + return; + } + + if (Value) + { + Context->Arch.X86.Registers.RegFlags |= Flag; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~Flag; + } +} + + +// +// ShemuX86SetFlags +// +static void +ShemuX86SetFlags( + SHEMU_CONTEXT *Context, + ND_UINT64 Dst, + ND_UINT64 Src1, + ND_UINT64 Src2, + ND_OPERAND_SIZE Size, + ND_UINT8 FlagsMode + ) +{ + ND_UINT8 pfArr[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + + // {NF} present for instruction, no flags will be modified. + if (Context->Arch.X86.Instruction.HasNf) + { + return; + } + + // Mask the operands with their respective size. + Dst = ND_TRIM(Size, Dst); + Src1 = ND_TRIM(Size, Src1); + Src2 = ND_TRIM(Size, Src2); + + if (FlagsMode == FM_SHL || FlagsMode == FM_SHR || FlagsMode == FM_SAR) + { + // Shift with 0 count does not affect flags. + if (Src2 == 0) + { + return; + } + } + + // PF set if the first bytes has an even number of 1 bits. + if ((pfArr[Dst & 0xF] + pfArr[(Dst >> 4) & 0xF]) % 2 == 0) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_PF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_PF; + } + + // ZF set if the result is zero. + if (Dst == 0) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_ZF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_ZF; + } + + // SF is set if the sign flag is set. + if (ND_GET_SIGN(Size, Dst) != 0) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_SF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_SF; + } + + // OF and CF are handled differently for some instructions. + if (FM_LOGIC == FlagsMode) + { + // OF and CF are cleared on logic instructions. + Context->Arch.X86.Registers.RegFlags &= ~(NDR_RFLAG_OF | NDR_RFLAG_CF); + } + else if (FM_SHL == FlagsMode) + { + // CF is the last bit shifted out of the destination. + if ((Src2 <= Size * 8ULL) && ND_GET_BIT((Size * 8ULL) - Src2, Src1)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_CF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_CF; + } + + if (Src2 == 1) + { + if (ND_GET_BIT(Size * 8ULL - 1, Src1) ^ ND_GET_BIT(Size * 8ULL - 2, Src1)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_OF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_OF; + } + } + } + else if (FM_SHR == FlagsMode) + { + // CF is the last bit shifted out of the destination. + // Src2 - 1 is ok - this function does not get called if Src2 is 0. + if (ND_GET_BIT(Src2 - 1, Src1)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_CF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_CF; + } + + if (Src2 == 1) + { + if (ND_GET_BIT(Size * 8ULL - 1, Src1)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_OF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_OF; + } + } + } + else if (FM_SAR == FlagsMode) + { + // CF is the last bit shifted out of the destination. In case of SAR, if the shift ammount exceeds the operand + // size, CF will be 1 if the result is -1, or 0 if the result is 0. + // Src2 - 1 is ok - this function does not get called if Src2 is 0. + if (ND_GET_BIT(Src2 - 1, Src1) || ((Src2 >= (ND_UINT64)Size * 8) && Dst != 0)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_CF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_CF; + } + + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_OF; + } + else + { + // Set CF. + if ((FM_SUB == FlagsMode) && ((Src1 < Src2) || (Src1 == Src2 && Dst != 0))) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_CF; + } + else if ((FM_ADD == FlagsMode) && ((Dst < Src1) || (Dst == Src1 && Src2 != 0))) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_CF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_CF; + } + + // Set OF. + if (FM_SUB == FlagsMode) + { + if ((ND_GET_SIGN(Size, Src1) && !ND_GET_SIGN(Size, Src2) && !ND_GET_SIGN(Size, Dst)) || + (!ND_GET_SIGN(Size, Src1) && ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Dst))) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_OF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_OF; + } + } + else if (FM_ADD == FlagsMode) + { + if (ND_GET_SIGN(Size, Src1) == ND_GET_SIGN(Size, Src2) && + ND_GET_SIGN(Size, Src1) != ND_GET_SIGN(Size, Dst)) + { + Context->Arch.X86.Registers.RegFlags |= NDR_RFLAG_OF; + } + else + { + Context->Arch.X86.Registers.RegFlags &= ~NDR_RFLAG_OF; + } + } + } +} + + +// +// ShemuX86EvalCondition +// +static ND_BOOL +ShemuX86EvalCondition( + SHEMU_CONTEXT *Context, + ND_UINT8 ConditionCode + ) +{ + switch (ConditionCode) + { + case ND_COND_OVERFLOW: // O + if (GET_FLAG(Context, NDR_RFLAG_OF) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_OVERFLOW): // NO + if (GET_FLAG(Context, NDR_RFLAG_OF) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_CARRY: // C/B/NAE + if (GET_FLAG(Context, NDR_RFLAG_CF) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE + if (GET_FLAG(Context, NDR_RFLAG_CF) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_ZERO: // E/Z + if (GET_FLAG(Context, NDR_RFLAG_ZF) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_ZERO): // NE/NZ + if (GET_FLAG(Context, NDR_RFLAG_ZF) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_BELOW_OR_EQUAL: // BE/NA + if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE + if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_SIGN: // S + if (GET_FLAG(Context, NDR_RFLAG_SF) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_SIGN): // NS + if (GET_FLAG(Context, NDR_RFLAG_SF) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_PARITY: // P + if (GET_FLAG(Context, NDR_RFLAG_PF) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_PARITY): // NP + if (GET_FLAG(Context, NDR_RFLAG_PF) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_LESS: // L/NGE + if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_LESS): // NL/GE + if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 0) + { + return ND_TRUE; + } + break; + case ND_COND_LESS_OR_EQUAL: // LE/NG + if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | + (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1) + { + return ND_TRUE; + } + break; + case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G + if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) | + (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0) + { + return ND_TRUE; + } + break; + } + + return ND_FALSE; +} + + +// +// ShemuX86GetGprValue +// +static ND_UINT64 +ShemuX86GetGprValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg, + ND_UINT32 Size, + ND_BOOL High8 + ) +{ + if (High8 && Reg >= 4) + { + Reg = Reg - 4; + } + + // Any read of the GPR, before being modified, counts as being "saved". The reason here is that we cannot + // easily track a proper save in memory, as the register may be copied in another register, and only then + // saved. + if (!(Context->Arch.X86.GprTracker[Reg] & GPR_TRACK_DIRTY)) + { + Context->Arch.X86.GprTracker[Reg] |= GPR_TRACK_READ; + } + + switch (Size) + { + case 1: + if (High8) + { + // AH, CH, DH or BH accessed. + return (*(&Context->Arch.X86.Registers.RegRax + Reg) >> 8) & 0xff; + } + else + { + return *(&Context->Arch.X86.Registers.RegRax + Reg) & 0xff; + } + + case 2: + return *(&Context->Arch.X86.Registers.RegRax + Reg) & 0xffff; + + case 4: + return *(&Context->Arch.X86.Registers.RegRax + Reg) & 0xffffffff; + + default: + return *(&Context->Arch.X86.Registers.RegRax + Reg); + } +} + + +// +// ShemuX86GetGprValue +// +static void +ShemuX86SetGprValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg, + ND_UINT32 Size, + ND_UINT64 Value, + ND_BOOL High8 + ) +{ + if (High8 && Reg >= 4) + { + Reg = Reg - 4; + } + + // If ZeroUpper semantic is enabled for APX instruction, make sure to zero out the destination. + // {ZU} can be either explicit (example: IMUL), or implicit (example: any {ND} instruction). + if (Context->Arch.X86.Instruction.HasZu || Context->Arch.X86.Instruction.HasNd) + { + *(&Context->Arch.X86.Registers.RegRax + Reg) = 0; + } + + switch (Size) + { + case 1: + if (High8) + { + // AH, CH, DH or BH accessed. + *((ND_UINT8 *)(&Context->Arch.X86.Registers.RegRax + Reg) + 1) = Value & 0xFF; + } + else + { + *((ND_UINT8 *)(&Context->Arch.X86.Registers.RegRax + Reg)) = Value & 0xff; + } + break; + + case 2: + *((ND_UINT16 *)(&Context->Arch.X86.Registers.RegRax + Reg)) = Value & 0xffff; + break; + + case 4: + // Higher ND_UINT32 is always set to zero. + *(&Context->Arch.X86.Registers.RegRax + Reg) = Value & 0xffffffff; + break; + + default: + *(&Context->Arch.X86.Registers.RegRax + Reg) = Value; + break; + } + + // Mark the GPR as being dirty/written. + if (!(Context->Arch.X86.GprTracker[Reg] & GPR_TRACK_READ)) + { + Context->Arch.X86.GprTracker[Reg] |= GPR_TRACK_DIRTY; + } +} + + +// +// ShemuX86GetSegValue +// +static ND_UINT64 +ShemuX86GetSegValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg + ) +{ + switch (Reg) + { + case NDR_ES: + return Context->Arch.X86.Segments.Es.Selector; + case NDR_CS: + return Context->Arch.X86.Segments.Cs.Selector; + case NDR_SS: + return Context->Arch.X86.Segments.Ss.Selector; + case NDR_DS: + return Context->Arch.X86.Segments.Ds.Selector; + case NDR_FS: + return Context->Arch.X86.Segments.Fs.Selector; + case NDR_GS: + return Context->Arch.X86.Segments.Gs.Selector; + } + + return 0; +} + + +// +// ShemuX86SetSegValue +// +static void +ShemuX86SetSegValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg, + ND_UINT16 Value + ) +{ + switch (Reg) + { + case NDR_ES: + Context->Arch.X86.Segments.Es.Selector = Value; + break; + case NDR_CS: + Context->Arch.X86.Segments.Cs.Selector = Value; + break; + case NDR_SS: + Context->Arch.X86.Segments.Ss.Selector = Value; + break; + case NDR_DS: + Context->Arch.X86.Segments.Ds.Selector = Value; + break; + case NDR_FS: + Context->Arch.X86.Segments.Fs.Selector = Value; + break; + case NDR_GS: + Context->Arch.X86.Segments.Gs.Selector = Value; + break; + } +} + + +// +// ShemuX86GetSegBase +// +static ND_UINT64 +ShemuX86GetSegBase( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg + ) +{ + switch (Reg) + { + case NDR_ES: + return Context->Arch.X86.Segments.Es.Base; + case NDR_CS: + return Context->Arch.X86.Segments.Cs.Base; + case NDR_SS: + return Context->Arch.X86.Segments.Ss.Base; + case NDR_DS: + return Context->Arch.X86.Segments.Ds.Base; + case NDR_FS: + return Context->Arch.X86.Segments.Fs.Base; + case NDR_GS: + return Context->Arch.X86.Segments.Gs.Base; + } + + return 0; +} + + +// +// ShemuX86IsSelectorValid +// +static ND_BOOL +ShemuX86IsSelectorValid( + SHEMU_CONTEXT *Context, + ND_UINT32 Reg, + ND_UINT16 Value + ) +{ + // Allow NULL selectors in 64 bit mode inside ES, DS, FS, GS. + if ((Value == 0) && (Context->Arch.X86.Mode == ND_CODE_64) && (Reg != NDR_SS)) + { + return ND_TRUE; + } + + if ((Value & 0xFFF8) >= 0x80) + { + // Too large value. + return ND_FALSE; + } + + if ((Value & 4) != 0) + { + // LDT selector. + return ND_FALSE; + } + + if ((Context->Arch.X86.Ring == 0) && ((Value & 3) != 0)) + { + // Ring 0 selector, with RPL != 0. + return ND_FALSE; + } + + if ((Context->Arch.X86.Ring == 3) && ((Value & 3) != 3)) + { + // Ring 3 selector, with RPL != 3. + return ND_FALSE; + } + + return ND_TRUE; +} + + +// +// ShemuX86IsAddressAligned +// +static ND_BOOL +ShemuX86IsAddressAligned( + SHEMU_CONTEXT *Context, + ND_UINT64 Address + ) +{ + if (Context->Arch.X86.Mode == ND_CODE_64) + { + return Address % 8 == 0; + } + else + { + return Address % 4 == 0; + } +} + + +// +// ShemuX86TrackLoopStart +// +static void +ShemuX86TrackLoopStart( + SHEMU_CONTEXT *Context, + ND_UINT64 Rip, + ND_UINT64 Target + ) +{ + if (Context->LoopTrack.Active) + { + return; + } + + Context->LoopTrack.Active = ND_TRUE; + Context->LoopTrack.Iteration = 1; + Context->LoopTrack.Address = Rip; + Context->LoopTrack.Target = Target; + + if (!!(Context->Options & SHEMU_OPT_TRACE_LOOPS)) + { + shemu_printf(Context, " Loop BEGIN from RIP 0x%016llx, TARGET 0x%016llx, ITER %llu\n", + Context->LoopTrack.Address, Context->LoopTrack.Target, Context->LoopTrack.Iteration); + } +} + + +// +// ShemuX86TrackLoopStop +// +static void +ShemuX86TrackLoopStop( + SHEMU_CONTEXT *Context + ) +{ + if (!Context->LoopTrack.Active) + { + return; + } + + if (!!(Context->Options & SHEMU_OPT_TRACE_LOOPS)) + { + shemu_printf(Context, " Loop BREAK from RIP 0x%016llx, TARGET 0x%016llx, ITER %llu\n", + Context->LoopTrack.Address, Context->LoopTrack.Target, Context->LoopTrack.Iteration); + } + + Context->LoopTrack.Active = ND_FALSE; + Context->LoopTrack.Address = 0; + Context->LoopTrack.Target = 0; + Context->LoopTrack.Iteration = 0; +} + + +// +// ShemuX86TrackLoop +// +static ND_BOOL +ShemuX86TrackLoop( + SHEMU_CONTEXT *Context, + ND_BOOL Taken + ) +{ + ND_UINT64 rip, target; + + // The address of the loop instruction itself, not the next instruction. + rip = Context->Arch.X86.Registers.RegRip - Context->Arch.X86.Instruction.Length; + + // The branches we monitor always have a relative offset, which is the first operand. + target = Context->Arch.X86.Registers.RegRip + Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + + if (target < rip) + { + // Case 1: Backward branch. + if (Taken) + { + // Taken backward branch instruction. + if (rip == Context->LoopTrack.Address) + { + // Current active loop, this is a new iteration. Example: + // label1: <--+ + // ... | + // loop label1 ---+ + // ... + // Update loop information. + Context->LoopTrack.Iteration++; + } + else + { + // New loop, or loop within our current loop. Always track the inner most loop. Example: + // label1: <--+ + // ... | + // label2: <--+ | + // ... | | + // loop label2 ---+ | + // ... | + // loop label1 ---+ + // ... + // Start tracking the (potentially new) loop. + ShemuX86TrackLoopStop(Context); + + ShemuX86TrackLoopStart(Context, rip, target); + } + } + else + { + // Not taken backward branch instruction. + if (rip == Context->LoopTrack.Address) + { + // Current loop ends, the loop instruction is no longer taken. Example: + // label1: + // ... + // loop label1 ---+ + // ... <--+ + // Stop tracking. + ShemuX86TrackLoopStop(Context); + } + else + { + // Not taken backward branch, but not our current loop. + // Nothing to do. + } + } + } + else + { + // Case 2: Forward branch. + if (Taken) + { + // Taken forward branch instruction. + if (target < Context->LoopTrack.Target || target > Context->LoopTrack.Address) + { + // Break instruction. Example: + // label1: + // ... + // jnz label2 ---+ + // ... | + // loop label1 | + // ... | + // label2: <--+ + // ... + // Stop tracking. + ShemuX86TrackLoopStop(Context); + } + else + { + // If instruction. Example: + // label1: + // ... + // jnz label2 ---+ + // ... | + // label2: <--+ + // ... + // loop label1 + // ... + // Nothing to do. + } + } + else + { + // Not taken forward branch instruction. + // Nothing to do. + } + } + + // In theory, we can override whether the branch is taken or not, but for now, this is not used. + return Taken; +} + + +// +// ShemuX86ComputeLinearAddress +// +static ND_UINT64 +ShemuX86ComputeLinearAddress( + SHEMU_CONTEXT *Context, + PND_OPERAND Operand + ) +{ + ND_UINT64 gla = 0; + + if (Operand->Info.Memory.HasBase) + { + gla += ShemuX86GetGprValue(Context, Operand->Info.Memory.Base, Operand->Info.Memory.BaseSize, ND_FALSE); + } + + if (Operand->Info.Memory.HasIndex) + { + gla += ShemuX86GetGprValue(Context, Operand->Info.Memory.Index, Operand->Info.Memory.IndexSize, ND_FALSE) * + Operand->Info.Memory.Scale; + } + + // Note that this also handles the case where moffset (absolute addressing) is used, as HasDisp will be set when + // IsDirect is also set. + if (Operand->Info.Memory.HasDisp) + { + gla += Operand->Info.Memory.Disp; + } + + if (Operand->Info.Memory.IsRipRel) + { + gla += Context->Arch.X86.Registers.RegRip; + } + + // Special handling for BT, BTR, BTS, BTC instructions with bitbase addressing. + if (Operand->Info.Memory.IsBitbase) + { + ND_UINT64 bitbase, op1size, op2size, reg; + + op1size = Context->Arch.X86.Instruction.Operands[0].Size; + op2size = Context->Arch.X86.Instruction.Operands[1].Size; + + reg = ((ND_UINT64*)&Context->Arch.X86.Registers.RegRax)[Context->Arch.X86.Instruction.Operands[1].Info.Register.Reg]; + + // Note: only BT* with register source (NOT immediate) support bitbase addressing. + bitbase = ND_SIGN_EX(op2size, reg); + + if (bitbase & (1ULL << 63)) + { + gla -= ((~bitbase >> 3) & ~(op1size - 1)) + op1size; + } + else + { + gla += (bitbase >> 3) & ~(op1size - 1); + } + } + + // Special handling for stack operations: if we have a PUSH, we have to subtract the accessed size, as, in fact, + // [RSP - size] is accessed, not [RSP]. + if (Operand->Info.Memory.IsStack) + { + if (Operand->Access.Write || Operand->Access.CondWrite) + { + gla -= Operand->Size; + } + } + + // Make sure we truncate the linear address to the address size. + switch (Context->Arch.X86.Instruction.AddrMode) + { + case ND_ADDR_32: + gla &= 0xFFFFFFFF; + break; + case ND_ADDR_16: + gla &= 0xFFFF; + default: + break; + } + + // Memory operands usually have a segment. Note that we don't care about any segment checks, since we're most + // likely be provided with flat segments. If checks should be needed, dedicated callbacks should be added. + if (Operand->Info.Memory.HasSeg) + { + gla += ShemuX86GetSegBase(Context, Operand->Info.Memory.Seg); + + if (Context->Arch.X86.Mode != ND_CODE_64) + { + // Truncate to 32 bit outside 64 bit. + gla &= 0xFFFFFFFF; + } + } + + return gla; +} + + + +// +// ShemuX86GetOperandValue +// +static SHEMU_STATUS +ShemuX86GetOperandValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Operand, + SHEMU_VALUE *Value + ) +{ + SHEMU_STATUS status; + PND_OPERAND op = &Context->Arch.X86.Instruction.Operands[Operand]; + + Value->Size = op->Size; + if (Value->Size > sizeof(Value->Value)) + { + return SHEMU_ABORT_OPERAND_NOT_SUPPORTED; + } + + if (op->Type == ND_OP_REG) + { + switch (op->Info.Register.Type) + { + case ND_REG_GPR: + Value->Value.Qwords[0] = ShemuX86GetGprValue(Context, op->Info.Register.Reg, op->Size, + op->Info.Register.IsHigh8); + break; + + case ND_REG_SEG: + Value->Value.Qwords[0] = ShemuX86GetSegValue(Context, op->Info.Register.Reg); + break; + + case ND_REG_MMX: + Value->Value.Qwords[0] = Context->Arch.X86.MmxRegisters[op->Info.Register.Reg]; + break; + + case ND_REG_SSE: + shemu_memcpy(Value->Value.Bytes, + &Context->Arch.X86.SseRegisters[op->Info.Register.Reg], + op->Size); + break; + + case ND_REG_RIP: + Value->Value.Qwords[0] = ND_TRIM(Value->Size, Context->Arch.X86.Registers.RegRip); + break; + + case ND_REG_FLG: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegFlags; + break; + + case ND_REG_CR: + switch (op->Info.Register.Reg) + { + case NDR_CR0: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegCr0; + break; + case NDR_CR2: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegCr2; + break; + case NDR_CR3: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegCr3; + break; + case NDR_CR4: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegCr4; + break; + case NDR_CR8: + Value->Value.Qwords[0] = Context->Arch.X86.Registers.RegCr8; + break; + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + break; + + + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + } + else if (op->Type == ND_OP_MEM) + { + ND_UINT64 gla = ShemuX86ComputeLinearAddress(Context, op); + ND_UINT32 offsetPeb; + ND_UINT8 seg; + + if (op->Info.Memory.IsAG) + { + // Address generation instruction, the result is the linear address itself. + Value->Value.Qwords[0] = gla; + goto done_gla; + } + + if (Context->Arch.X86.Ring == 3) + { + // User-mode TIB offset that contains the PEB address. + offsetPeb = Context->Arch.X86.Mode == ND_CODE_32 ? 0x30 : 0x60; + seg = Context->Arch.X86.Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; + } + else + { + // Kernel-mode KPCR offset that contains the current KTHREAD address. + offsetPeb = Context->Arch.X86.Mode == ND_CODE_32 ? 0x124 : 0x188; + seg = Context->Arch.X86.Mode == ND_CODE_32 ? ND_PREFIX_G2_SEG_FS : ND_PREFIX_G2_SEG_GS; + } + + // Check if this is a TIB/PCR access. Make sure the FS/GS register is used for the access, in order to avoid + // FALSE positives where legitimate code accesses a linear TIB directly. + // Note that this covers accesses to the PEB field inside the TIB. + if (Context->Arch.X86.Ring == 3) + { + if (Context->Arch.X86.Instruction.Seg == seg && + gla == Context->TibBase + offsetPeb) + { + Context->Flags |= SHEMU_FLAG_TIB_ACCESS_PEB; + } + } + + // Note that this covers accesses to the Wow32Reserved in Wow64 mode. That field can be used to issue + // syscalls. + if (gla == Context->TibBase + 0xC0 && Context->Arch.X86.Instruction.Seg == seg && + Context->Arch.X86.Mode == ND_CODE_32) + { + Context->Flags |= SHEMU_FLAG_TIB_ACCESS_WOW32; + } + + // Check for accesses inside the KUSER_SHARED_DATA (SharedUserData). This page contains some + // global system information, it may host shellcodes, and is hard-coded at this address. We + // only consider accesses to some SUD fields, in order to avoid false-positives. + if ((gla >= 0x7FFE02D4 && gla < 0x7FFE02D5) || // KdDebuggerEnabled + (gla >= 0x7FFE0308 && gla < 0x7FFE1310) || // SystemCall + (gla >= 0x7FFE0330 && gla < 0x7FFE1338)) // Cookie + { + Context->Flags |= SHEMU_FLAG_SUD_ACCESS; + } + + // Check if we are reading a previously saved RIP. Ignore RET instructions, which naturally access the + // saved RIP. + if (Context->Arch.X86.Instruction.Category != ND_CAT_RET && + ShemuIsStackPtr(Context, gla, op->Size) && + ShemuStackBmpStateCheck(Context, gla - Context->StackBase, op->Size, STACK_BYTE_RIP)) + { + PND_OPERAND dst = ND_NULL; + + for (ND_UINT32 i = 0; i < Context->Arch.X86.Instruction.OperandsCount; i++) + { + // We fetch the first destination, if any. We ignore the current operand. + if ((i != Operand) && (Context->Arch.X86.Instruction.Operands[i].Access.Access & ND_ACCESS_ANY_WRITE)) + { + dst = &Context->Arch.X86.Instruction.Operands[i]; + break; + } + } + + // We consider a LOAD_RIP detection only if the RIP value is loaded in: + // - Another memory location; + // - A register, which is not (excluding bank register access, such as PPOPA): + // - A segment register; + // - The RIP register; + // - The Flags register; + // Loads which are propagated to other operand types (RIP, segment register, etc.) or which are not + // propagated at all (RMW instructions) are not considered, since they don't store the RIP anywehere. + if ((dst != ND_NULL) && + ((dst->Type == ND_OP_BANK) || + (dst->Type == ND_OP_MEM) || + (dst->Type == ND_OP_REG && + dst->Info.Register.Type != ND_REG_SEG && + dst->Info.Register.Type != ND_REG_RIP && + dst->Info.Register.Type != ND_REG_FLG))) + { + Context->Flags |= SHEMU_FLAG_LOAD_RIP; + } + } + + // Get the memory value. + status = ShemuMemLoad(Context, gla, Value->Size, Value->Value.Bytes); + if (SHEMU_SUCCESS != status) + { + return status; + } + + if (Context->Options & SHEMU_OPT_TRACE_MEMORY) + { + ShemuDisplayMemValue(Context, gla, Value->Size, Value->Value.Bytes, ND_TRUE); + } + + // If this is a stack access, we need to update the stack pointer. + if (op->Info.Memory.IsStack) + { + ND_UINT64 regval = ShemuX86GetGprValue(Context, NDR_RSP, (2 << Context->Arch.X86.Instruction.DefStack), ND_FALSE); + + regval += op->Size; + + ShemuX86SetGprValue(Context, NDR_RSP, (2 << Context->Arch.X86.Instruction.DefStack), regval, ND_FALSE); + } + + // If this is a string operation, make sure we update RSI/RDI. + if (op->Info.Memory.IsString) + { + ND_UINT64 regval = ShemuX86GetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE); + + regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; + + ShemuX86SetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE); + } + +done_gla:; + } + else if (op->Type == ND_OP_IMM) + { + Value->Value.Qwords[0] = op->Info.Immediate.Imm; + } + else if (op->Type == ND_OP_CONST) + { + Value->Value.Qwords[0] = op->Info.Constant.Const; + } + else if (op->Type == ND_OP_OFFS) + { + Value->Value.Qwords[0] = op->Info.RelativeOffset.Rel; + } + else + { + return SHEMU_ABORT_OPERAND_NOT_SUPPORTED; + } + + return SHEMU_SUCCESS; +} + + +// +// ShemuX86SetOperandValue +// +static SHEMU_STATUS +ShemuX86SetOperandValue( + SHEMU_CONTEXT *Context, + ND_UINT32 Operand, + SHEMU_VALUE *Value + ) +{ + SHEMU_STATUS status; + PND_OPERAND op = &Context->Arch.X86.Instruction.Operands[Operand]; + + // If a stack address is being loaded, check if it points to a string built on the stack. + if (ShemuIsStackPtr(Context, Value->Value.Qwords[0], Context->StrThreshold)) + { + ND_UINT64 sptr = Value->Value.Qwords[0]; + ND_UINT32 i, stckstrlen = 0; + + // Check if a string was saved on the stack. Typically used by shellcodes like this: + // PUSH str0 + // PUSH str1 + // ... + // PUSH strn + // Other variants may exist, but all we care about are stores on the stack, and all are checked. + + for (i = 0; i < Context->StrThreshold; i++) + { + unsigned char c; + + status = ShemuMemLoad(Context, sptr + i, 1, &c); + if (SHEMU_SUCCESS != status) + { + break; + } + + if ((c >= 'a' && c <= 'z') || (c >= 'A' && c <= 'Z') || (c >= '0' && c <= '9') || + c == '\\' || c == '/' || c == ':' || c == ' ') + { + stckstrlen++; + } + else + { + break; + } + } + + if (stckstrlen >= Context->StrThreshold) + { + Context->Flags |= SHEMU_FLAG_STACK_STR; + } + } + + + if (op->Type == ND_OP_REG) + { + switch (op->Info.Register.Type) + { + case ND_REG_GPR: + if (Context->Arch.X86.Instruction.Instruction == ND_INS_XCHG && + op->Info.Register.Reg == NDR_RSP && + ShemuX86IsAddressAligned(Context, Value->Value.Qwords[0])) + { + // Conditions for a STACK_PIVOT detection: + // 1. The instruction is XCHG + // 2. The value loaded in the RSP register is naturally aligned + // 3. The value points either inside the shellcode or the stack area, and at least 64 bytes are valid + if (ShemuIsShellcodePtr(Context, Value->Value.Qwords[0], 64) || + ShemuIsStackPtr(Context, Value->Value.Qwords[0], 64)) + { + Context->Flags |= SHEMU_FLAG_STACK_PIVOT; + } + } + + ShemuX86SetGprValue(Context, op->Info.Register.Reg, op->Size, Value->Value.Qwords[0], + op->Info.Register.IsHigh8); + break; + + case ND_REG_SEG: + if (!ShemuX86IsSelectorValid(Context, op->Info.Register.Reg, Value->Value.Words[0])) + { + return SHEMU_ABORT_INVALID_SELECTOR; + } + ShemuX86SetSegValue(Context, op->Info.Register.Reg, Value->Value.Words[0]); + break; + + case ND_REG_MMX: + Context->Arch.X86.MmxRegisters[op->Info.Register.Reg] = Value->Value.Qwords[0]; + // Only log these when they're written. + if (Context->Options & SHEMU_OPT_TRACE_EMULATION) + { + shemu_printf(Context, " MM%d = 0x%016llx\n", op->Info.Register.Reg, Value->Value.Qwords[0]); + } + break; + + case ND_REG_SSE: + if (Context->Arch.X86.Instruction.EncMode != ND_ENCM_LEGACY) + { + // Zero the entire register first, if we have a VEX/EVEX encoded instruction. + nd_memzero(&Context->Arch.X86.SseRegisters[op->Info.Register.Reg], ND_MAX_REGISTER_SIZE); + } + else + { + // Zero upper bits in the 128 bits register, if operand size is less than 16 bytes. + // Upper bits in the YMM/ZMM register are preserved. + nd_memzero(&Context->Arch.X86.SseRegisters[op->Info.Register.Reg], 16); + } + // Copy the value. + shemu_memcpy(&Context->Arch.X86.SseRegisters[op->Info.Register.Reg], + Value->Value.Bytes, + op->Size); + // Only log these when they're written. + if (Context->Options & SHEMU_OPT_TRACE_EMULATION) + { + shemu_printf(Context, + " %cMM%d (HI_32) = 0x%016llx%016llx%016llx%016llx\n", + op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, + Value->Value.Qwords[7], Value->Value.Qwords[6], + Value->Value.Qwords[5], Value->Value.Qwords[4]); + shemu_printf(Context, + " %cMM%d (LO_32) = 0x%016llx%016llx%016llx%016llx\n", + op->Size == 16 ? 'X' : op->Size == 32 ? 'Y' : 'Z', op->Info.Register.Reg, + Value->Value.Qwords[3], Value->Value.Qwords[2], + Value->Value.Qwords[1], Value->Value.Qwords[0]); + } + break; + + case ND_REG_RIP: + Context->Arch.X86.Registers.RegRip = ND_TRIM(Value->Size, Value->Value.Qwords[0]); + break; + + case ND_REG_FLG: + if (op->Size == 2) + { + *((ND_UINT16*)&Context->Arch.X86.Registers.RegFlags) = Value->Value.Words[0]; + } + else + { + Context->Arch.X86.Registers.RegFlags = Value->Value.Qwords[0]; + } + // Handle reserved bits. + Context->Arch.X86.Registers.RegFlags |= (1ULL << 1); + Context->Arch.X86.Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15)); + Context->Arch.X86.Registers.RegFlags &= 0x3FFFFF; + break; + + case ND_REG_CR: + switch (op->Info.Register.Reg) + { + case NDR_CR0: + Context->Arch.X86.Registers.RegCr0 = Value->Value.Qwords[0]; + break; + case NDR_CR2: + Context->Arch.X86.Registers.RegCr2 = Value->Value.Qwords[0]; + break; + case NDR_CR3: + Context->Arch.X86.Registers.RegCr3 = Value->Value.Qwords[0]; + break; + case NDR_CR4: + Context->Arch.X86.Registers.RegCr4 = Value->Value.Qwords[0]; + break; + case NDR_CR8: + Context->Arch.X86.Registers.RegCr8 = Value->Value.Qwords[0]; + break; + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + break; + + default: + return SHEMU_ABORT_REGISTER_NOT_SUPPORTED; + } + } + else if (op->Type == ND_OP_MEM) + { + // Compute the GLA. + ND_UINT64 gla = ShemuX86ComputeLinearAddress(Context, op); + + // Handle self-write. We store a 1 for each written byte inside the shellcode space. Once the modified bytes + // are executed, we can trigger the self-write detection. + if (ShemuIsShellcodePtr(Context, gla, op->Size)) + { + ShemuShellBmpStateSet(Context, gla - Context->ShellcodeBase, op->Size, SHELL_BYTE_DIRTY); + } + + // Handle RIP save on the stack. + if (ShemuIsStackPtr(Context, gla, MAX(op->Size, Context->Arch.X86.Instruction.WordLength))) + { + // Note: only Context->Arch.X86.Instruction.WordLength bits are flagged as RIP, as that is the RIP size. + if (Context->Arch.X86.Instruction.Instruction == ND_INS_CALLNR || + Context->Arch.X86.Instruction.Instruction == ND_INS_CALLNI) + { + ShemuStackBmpStateSet(Context, gla - Context->StackBase, + Context->Arch.X86.Instruction.WordLength, STACK_BYTE_RIP); + } + else if (Context->Arch.X86.Instruction.Instruction == ND_INS_FNSTENV) + { + // OK: op->Size will be the FPU state size (28 bytes); we only emulate 32 & 64 bit forms, the RIP is + // always 4 bytes. + ShemuStackBmpStateSet(Context, (gla + 0xC) - Context->StackBase, + MIN(Context->Arch.X86.Instruction.WordLength, 4), STACK_BYTE_RIP); + } + else if (Context->Arch.X86.Instruction.Instruction == ND_INS_FXSAVE || + Context->Arch.X86.Instruction.Instruction == ND_INS_FXSAVE64) + { + // OK: op->Size will be the FXSAVE size (512 bytes). + ShemuStackBmpStateSet(Context, (gla + 0x8) - Context->StackBase, + Context->Arch.X86.Instruction.WordLength, STACK_BYTE_RIP); + } + else + { + // Something is written on a previously saved RIP; reset it. + ShemuStackBmpStateClear(Context, gla - Context->StackBase, op->Size, STACK_BYTE_RIP); + } + } + + // Set the value. + status = ShemuMemStore(Context, gla, MIN(op->Size, Value->Size), Value->Value.Bytes); + if (SHEMU_SUCCESS != status) + { + return status; + } + + if (Context->Options & SHEMU_OPT_TRACE_MEMORY) + { + ShemuDisplayMemValue(Context, gla, Value->Size, Value->Value.Bytes, ND_FALSE); + } + + // If this is a stack access, we need to update the stack pointer. + if (op->Info.Memory.IsStack) + { + ND_UINT64 regval = ShemuX86GetGprValue(Context, NDR_RSP, (2 << Context->Arch.X86.Instruction.DefStack), ND_FALSE); + + regval -= op->Size; + + ShemuX86SetGprValue(Context, NDR_RSP, (2 << Context->Arch.X86.Instruction.DefStack), regval, ND_FALSE); + } + + // If this is a string operation, make sure we update RSI/RDI. + if (op->Info.Memory.IsString) + { + ND_UINT64 regval = ShemuX86GetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, ND_FALSE); + + regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size; + + ShemuX86SetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, ND_FALSE); + } + } + else + { + return SHEMU_ABORT_OPERAND_NOT_SUPPORTED; + } + + return SHEMU_SUCCESS; +} + + +// +// ShemuX86Multiply64Unsigned +// +static void +ShemuX86Multiply64Unsigned( + ND_UINT64 Operand1, + ND_UINT64 Operand2, + ND_UINT64 *ResHigh, + ND_UINT64 *ResLow + ) +{ + ND_UINT64 xLow = (ND_UINT64)(ND_UINT32)Operand1; + ND_UINT64 xHigh = Operand1 >> 32; + ND_UINT64 yLow = (ND_UINT64)(ND_UINT32)Operand2; + ND_UINT64 yHigh = Operand2 >> 32; + + ND_UINT64 p0 = xLow * yLow; + ND_UINT64 p1 = xLow * yHigh; + ND_UINT64 p2 = xHigh * yLow; + ND_UINT64 p3 = xHigh * yHigh; + + ND_UINT32 cy = (ND_UINT32)(((p0 >> 32) + (ND_UINT32)p1 + (ND_UINT32)p2) >> 32); + + *ResLow = p0 + (p1 << 32) + (p2 << 32); + *ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + cy; +} + + +// +// ShemuX86Multiply64Signed +// +static void +ShemuX86Multiply64Signed( + ND_SINT64 Operand1, + ND_SINT64 Operand2, + ND_SINT64 *ResHigh, + ND_SINT64 *ResLow + ) +{ + ShemuX86Multiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow); + if (Operand1 < 0LL) *ResHigh -= Operand2; + if (Operand2 < 0LL) *ResHigh -= Operand1; +} + + +// +// ShemuX86CheckDiv +// +static ND_BOOL +ShemuX86CheckDiv( + ND_UINT64 Divident, + ND_UINT64 Divider, + ND_UINT8 Size // The size of the Source (Divider). The Divident is twice as large. + ) +{ + // Returns ND_TRUE if all checks are OK, and Divident / Divider will not cause #DE. + + if (Divider == 0) + { + // Division by zero. + return ND_FALSE; + } + + // If the result won't fit in the destination, a #DE would be generated. + switch (Size) + { + case 1: + if (((Divident >> 8) & 0xFF) >= Divider) + { + return ND_FALSE; + } + break; + + case 2: + if (((Divident >> 16) & 0xFFFF) >= Divider) + { + return ND_FALSE; + } + break; + + case 4: + if (((Divident >> 32) & 0xFFFFFFFF) >= Divider) + { + return ND_FALSE; + } + break; + + default: + // 64 bit source division is not supported. + return ND_FALSE; + } + + return ND_TRUE; +} + + +// +// ShemuX86CheckIdiv +// +static ND_BOOL +ShemuX86CheckIdiv( + ND_SINT64 Divident, + ND_SINT64 Divider, + ND_UINT8 Size // The size of the Source (Divider). + ) +{ + ND_BOOL neg1, neg2; + ND_UINT64 quotient, max; + + neg1 = Divident < 0; + neg2 = Divider < 0; + + if (neg1) + { + Divident = -Divident; + } + + if (neg2) + { + Divider = -Divider; + } + + // Do checks when dividing positive values. + if (!ShemuX86CheckDiv(Divident, Divider, Size)) + { + return ND_FALSE; + } + + // Get the positive quotient. + quotient = (ND_UINT64)Divident / (ND_UINT64)Divider; + + max = (Size == 1) ? 0x80 : (Size == 2) ? 0x8000 : (Size == 4) ? 0x80000000 : 0x8000000000000000; + + if (neg1 ^ neg2) + { + // The Divident and the Divider have different signs, the quotient must be negative. If it's positive => #DE. + if (ND_GET_SIGN(Size, quotient) && quotient != max) + { + return ND_FALSE; + } + } + else + { + // Both the Divident and the Divider are positive/negative, so a positive result must be produced. If it's + // negative => #DE. + if (ND_GET_SIGN(Size, quotient)) + { + return ND_FALSE; + } + } + + return ND_TRUE; +} + + +// +// ShemuX86CountZeroBits +// +static ND_UINT8 +ShemuX86CountZeroBits( + ND_UINT64 Value, + ND_OPERAND_SIZE Size, + ND_BOOL Forward + ) +{ + ND_UINT8 cnt = 0; + + if (Forward) + { + for (ND_UINT32 i = 0; i < Size * 8 && ND_GET_BIT(i, Value) == 0; i++, cnt++); + } + else + { + for (ND_SINT32 i = Size * 8 - 1; i >= 0 && ND_GET_BIT(i, Value) == 0; i--, cnt++); + } + + return cnt; +} + + +// +// ShemuX86PrintContext +// +#ifndef BDDISASM_NO_FORMAT +static void +ShemuX86PrintContext( + SHEMU_CONTEXT *Context + ) +{ + char text[ND_MIN_BUF_SIZE] = { 0 }; + char ibytes[ND_MAX_INSTRUCTION_LENGTH * 2 + 2] = { 0 }; + + NdToText(&Context->Arch.X86.Instruction, Context->Arch.X86.Registers.RegRip, ND_MIN_BUF_SIZE, text); + + shemu_printf(Context, " RAX = 0x%016llx RCX = 0x%016llx RDX = 0x%016llx RBX = 0x%016llx\n", + Context->Arch.X86.Registers.RegRax, Context->Arch.X86.Registers.RegRcx, + Context->Arch.X86.Registers.RegRdx, Context->Arch.X86.Registers.RegRbx); + shemu_printf(Context, " RSP = 0x%016llx RBP = 0x%016llx RSI = 0x%016llx RDI = 0x%016llx\n", + Context->Arch.X86.Registers.RegRsp, Context->Arch.X86.Registers.RegRbp, + Context->Arch.X86.Registers.RegRsi, Context->Arch.X86.Registers.RegRdi); + shemu_printf(Context, " R8 = 0x%016llx R9 = 0x%016llx R10 = 0x%016llx R11 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR8, Context->Arch.X86.Registers.RegR9, + Context->Arch.X86.Registers.RegR10, Context->Arch.X86.Registers.RegR11); + shemu_printf(Context, " R12 = 0x%016llx R13 = 0x%016llx R14 = 0x%016llx R15 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR12, Context->Arch.X86.Registers.RegR13, + Context->Arch.X86.Registers.RegR14, Context->Arch.X86.Registers.RegR15); + + if (Context->Options & SHEMU_OPT_SUPPORT_APX) + { + shemu_printf(Context, " R16 = 0x%016llx R17 = 0x%016llx R18 = 0x%016llx R19 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR16, Context->Arch.X86.Registers.RegR17, + Context->Arch.X86.Registers.RegR18, Context->Arch.X86.Registers.RegR19); + shemu_printf(Context, " R20 = 0x%016llx R21 = 0x%016llx R22 = 0x%016llx R23 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR20, Context->Arch.X86.Registers.RegR21, + Context->Arch.X86.Registers.RegR22, Context->Arch.X86.Registers.RegR23); + shemu_printf(Context, " R24 = 0x%016llx R25 = 0x%016llx R26 = 0x%016llx R27 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR24, Context->Arch.X86.Registers.RegR25, + Context->Arch.X86.Registers.RegR26, Context->Arch.X86.Registers.RegR27); + shemu_printf(Context, " R28 = 0x%016llx R29 = 0x%016llx R30 = 0x%016llx R31 = 0x%016llx\n", + Context->Arch.X86.Registers.RegR28, Context->Arch.X86.Registers.RegR29, + Context->Arch.X86.Registers.RegR30, Context->Arch.X86.Registers.RegR31); + } + + shemu_printf(Context, " RIP = 0x%016llx RFLAGS = 0x%016llx ", + Context->Arch.X86.Registers.RegRip, Context->Arch.X86.Registers.RegFlags); + shemu_printf(Context, " CF:%d PF:%d AF:%d ZF:%d SF:%d TF:%d IF:%d DF:%d OF:%d\n", + GET_FLAG(Context, NDR_RFLAG_CF), + GET_FLAG(Context, NDR_RFLAG_PF), + GET_FLAG(Context, NDR_RFLAG_AF), + GET_FLAG(Context, NDR_RFLAG_ZF), + GET_FLAG(Context, NDR_RFLAG_SF), + GET_FLAG(Context, NDR_RFLAG_TF), + GET_FLAG(Context, NDR_RFLAG_IF), + GET_FLAG(Context, NDR_RFLAG_DF), + GET_FLAG(Context, NDR_RFLAG_OF)); + + ShemuHexlify(Context->Arch.X86.Instruction.InstructionBytes, Context->Arch.X86.Instruction.Length, + ibytes, sizeof(ibytes)); + + shemu_printf(Context, "IP: 0x%016llx %-30s %s\n", Context->Arch.X86.Registers.RegRip, ibytes, text); + +} +#else +#define ShemuX86PrintContext(Context) +#endif // !BDDISASM_NO_FORMAT + + +// +// ShemuX86Emulate +// +SHEMU_STATUS +ShemuX86Emulate( + SHEMU_CONTEXT *Context + ) +{ + ND_CONTEXT decodeCtx = { 0 }; + SHEMU_VALUE res, dst, src; + ND_BOOL stop = ND_FALSE, cf, sled = ND_TRUE, taken = ND_FALSE; + ND_UINT16 cs = 0; + ND_UINT64 tsc = 0x1248fe7a5c30; + + if (ND_NULL == Context) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (ND_NULL == Context->Shellcode) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (ND_NULL == Context->Stack) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (ND_NULL == Context->Intbuf) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (0 == (Context->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL)) + { + if (Context->StackSize + Context->ShellcodeSize > Context->IntbufSize) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + } + else + { + if (Context->StackSize > Context->IntbufSize) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (Context->AccessShellcode == ND_NULL) + { + // The AccessShellcode callback is mandatory when using the SHEMU_OPT_DIRECT_MAPPED_SHELL option. + return SHEMU_ABORT_INVALID_PARAMETER; + } + + // It is unsafe to allow self-writes to proceed, so this options is forced when using + // SHEMU_OPT_DIRECT_MAPPED_SHELL emulation. + Context->Options |= SHEMU_OPT_BYPASS_SELF_WRITES; + } + + if (Context->ArchType != SHEMU_ARCH_TYPE_X86) + { + return SHEMU_ABORT_INVALID_PARAMETER; + } + + if (Context->NopThreshold == 0) + { + Context->NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; + } + + if (Context->StrThreshold == 0) + { + Context->StrThreshold = SHEMU_DEFAULT_STR_THRESHOLD; + } + + decodeCtx.DefCode = Context->Arch.X86.Mode; + decodeCtx.DefData = Context->Arch.X86.Mode; + decodeCtx.DefStack = Context->Arch.X86.Mode; + decodeCtx.VendMode = ND_VEND_ANY; + decodeCtx.Options = 0; + decodeCtx.FeatMode = 0; + + // Enable APX support. + if (Context->Options & SHEMU_OPT_SUPPORT_APX) + { + decodeCtx.FeatMode |= ND_FEAT_APX; + } + + while (Context->InstructionsCount++ < Context->MaxInstructionsCount) + { + SHEMU_STATUS shstatus; + NDSTATUS ndstatus; + ND_UINT64 rip; // Offset, not actual linear address. + ND_UINT32 i, ilen; + ND_UINT8 ibytes[16]; + ND_BOOL hasNd = ND_FALSE; + + tsc++; + + // Reset all the operands to 0. + nd_memzero(&res, sizeof(res)); + nd_memzero(&dst, sizeof(dst)); + nd_memzero(&src, sizeof(src)); + + // The stop flag has been set, this means we've reached a valid instruction, but that instruction cannot be + // emulated (for example, SYSCALL, INT, system instructions, etc). + if (stop) + { + return SHEMU_ABORT_CANT_EMULATE; + } + + // If we already have a detection and we wish to stop on detections, do so now. + if ((0 != Context->Flags) && (0 != (Context->Options & SHEMU_OPT_STOP_ON_EXPLOIT))) + { + return SHEMU_ABORT_SHELLCODE_DETECTED; + } + + // Make sure the RIP is pointing in the right area. We test only 1 byte - the decoder will make sure it can + // access as many bytes as needed and return error in case it can't. + if (!ShemuIsShellcodePtr(Context, Context->Arch.X86.Registers.RegRip, 1)) + { + return SHEMU_ABORT_RIP_OUTSIDE; + } + + // Get the offset inside the shellcode buffer. + rip = Context->Arch.X86.Registers.RegRip - Context->ShellcodeBase; + + // Maximum number of bytes we can fetch. No more than 16 bytes. + ilen = (ND_UINT32)MIN(Context->ShellcodeSize - rip, sizeof(ibytes)); + + // Fetch instruction bytes. + shstatus = ShemuMemFetch(Context, Context->Arch.X86.Registers.RegRip, ilen, ibytes); + if (SHEMU_SUCCESS != shstatus) + { + return shstatus; + } + + // Decode the next instruction. + ndstatus = NdDecodeWithContext(&Context->Arch.X86.Instruction, ibytes, ilen, &decodeCtx); + if (!ND_SUCCESS(ndstatus)) + { + if (ND_STATUS_BUFFER_TOO_SMALL == ndstatus) + { + return SHEMU_ABORT_RIP_OUTSIDE; + } + else + { + return SHEMU_ABORT_DECODE_ERROR; + } + } + + // Paranoid check... + if (!ShemuIsShellcodePtr(Context, Context->Arch.X86.Registers.RegRip, Context->Arch.X86.Instruction.Length)) + { + return SHEMU_ABORT_RIP_OUTSIDE; + } + + // Check if this is a new, unique, address being executed. + if (!ShemuShellBmpStateCheck(Context, rip, 1, SHELL_BYTE_FETCHED)) + { + // If SHEMU_OPT_DIRECT_MAPPED_SHELL is not used, this will be incremented for each instruction. + Context->UniqueCount++; + + // Note: The first instruction byte is marked using SHELL_BYTE_FETCHED, and subsequent bytes using + // SHELL_BYTE_IBYTES. For example, if we have the instruction "33C0 (XOR eax, eax)" at address 0x1000, + // the flags will be set as follows: + // Shellcode state for 0x1000: SHELL_BYTE_FETCHED (0x33, the opcode) + // Shellcode state for 0x1001: SHELL_BYTE_IBYTES (0xC0, subsequent bytes) + // Normally, these two flags should never be set together. + + // Indicate that we've fetched an instruction from this address. + ShemuShellBmpStateSet(Context, rip, 1, SHELL_BYTE_FETCHED); + + // Indicate that subsequent bytes are part of a fetched & emulated instruction. + ShemuShellBmpStateSet(Context, rip + 1, Context->Arch.X86.Instruction.Length - 1, SHELL_BYTE_IBYTES); + } + + // Check if we just fetched an instruction from a previously written area, to raise self-write alert. + if (ShemuShellBmpStateCheck(Context, rip, Context->Arch.X86.Instruction.Length, SHELL_BYTE_DIRTY)) + { + Context->Flags |= SHEMU_FLAG_WRITE_SELF; + } + + // Dump the context. + if (Context->Options & SHEMU_OPT_TRACE_EMULATION) + { + ShemuX86PrintContext(Context); + } + + // The RIP is incremented BEFORE actually emulating the instruction. This is what the CPU does as well. + Context->Arch.X86.Registers.RegRip += Context->Arch.X86.Instruction.Length; + + // Bail out early if we encounter a privileged instruction. + if (Context->Arch.X86.Instruction.ValidModes.Ring3 == 0 && Context->Arch.X86.Ring == 3) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + // Some instruction types are unssuported. + if (Context->Arch.X86.Instruction.Category == ND_CAT_IO || + Context->Arch.X86.Instruction.Category == ND_CAT_IOSTRINGOP) + { + return SHEMU_ABORT_INSTRUX_NOT_SUPPORTED; + } + + // There are two important aspects of a NOP sled: + // 1. The NOPs must be at the beginning of the code; + // 2. The NOPs must be consecutive; + // We will only count consecutive NOPs if they're at the beginning of the code. + if (Context->Arch.X86.Instruction.Instruction != ND_INS_NOP) + { + sled = ND_FALSE; + } + + // Count the total number of '00 00' (ADD [rax], al) instructions. + if (Context->Arch.X86.Instruction.InstructionBytes[0] == 0 && + Context->Arch.X86.Instruction.InstructionBytes[1] == 0) + { + Context->NullCount++; + } + + // FPU instructions are "pass-through", we just want to save the RIP, so we can emulate FNSTENV. + if ((Context->Arch.X86.Instruction.IsaSet == ND_SET_X87) && + (Context->Arch.X86.Instruction.Instruction != ND_INS_FNSTENV)) + { + PND_OPERAND pMemOp = ND_NULL; + + Context->Arch.X86.Registers.FpuRip = Context->Arch.X86.Registers.RegRip - Context->Arch.X86.Instruction.Length; + + // If the instruction uses a memory operand, validate it, and bail out if it points outside + // shellcode or stack memory. + if (Context->Arch.X86.Instruction.OperandsCount >= 1 && + Context->Arch.X86.Instruction.Operands[0].Type == ND_OP_MEM) + { + pMemOp = &Context->Arch.X86.Instruction.Operands[0]; + } + else if (Context->Arch.X86.Instruction.OperandsCount >= 2 && + Context->Arch.X86.Instruction.Operands[1].Type == ND_OP_MEM) + { + pMemOp = &Context->Arch.X86.Instruction.Operands[1]; + } + + if (ND_NULL != pMemOp) + { + ND_UINT64 gla = ShemuX86ComputeLinearAddress(Context, pMemOp); + + if (!ShemuIsShellcodePtr(Context, gla, pMemOp->Size) && + !ShemuIsStackPtr(Context, gla, pMemOp->Size)) + { + stop = ND_TRUE; + } + } + + continue; + } + + // This flag can only be set for APX instructions. + hasNd = !!Context->Arch.X86.Instruction.HasNd; + + switch (Context->Arch.X86.Instruction.Instruction) + { + case ND_INS_FNSTENV: + if (Context->Arch.X86.Instruction.EfOpMode != ND_OPSZ_16) + { + src.Size = Context->Arch.X86.Instruction.Operands[0].Size; + src.Value.FpuEnvironment.FpuInstructionPointer = (ND_UINT32)Context->Arch.X86.Registers.FpuRip; + SET_OP(Context, 0, &src); + } + break; + + case ND_INS_FXSAVE: + case ND_INS_FXSAVE64: + src.Size = MIN(Context->Arch.X86.Instruction.Operands[0].Size, sizeof(src.Value.XsaveArea)); + src.Value.XsaveArea.FpuRip = Context->Arch.X86.Registers.FpuRip; + SET_OP(Context, 0, &src); + break; + + case ND_INS_MOV_CR: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + // Fall through. + + case ND_INS_MOV: + case ND_INS_MOVZX: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_MOVSX: + case ND_INS_MOVSXD: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); + SET_OP(Context, 0, &dst); + break; + + case ND_INS_CMOVcc: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + if (ShemuX86EvalCondition(Context, Context->Arch.X86.Instruction.Condition)) + { + SET_OP(Context, 0, &src); + } + else + { + // Write back the same value that was already present in destination. This has the side-effect of + // clearing the upper 32 bit in the 64 bit destination register while in long mode. + SET_OP(Context, 0, &dst); + } + break; + + case ND_INS_SETcc: + if (ShemuX86EvalCondition(Context, Context->Arch.X86.Instruction.Condition)) + { + src.Size = Context->Arch.X86.Instruction.Operands[0].Size; + src.Value.Qwords[0] = 1; + } + else + { + src.Size = Context->Arch.X86.Instruction.Operands[0].Size; + src.Value.Qwords[0] = 0; + } + SET_OP(Context, 0, &src); + break; + + case ND_INS_XLATB: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_XCHG: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + SET_OP(Context, 1, &dst); + SET_OP(Context, 0, &src); + break; + + case ND_INS_XADD: + GET_OP(Context, 1, &src); + GET_OP(Context, 0, &dst); + res.Size = dst.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_OP(Context, 1, &dst); + SET_OP(Context, 0, &res); + break; + + case ND_INS_CMPXCHG: + GET_OP(Context, 2, &src); + GET_OP(Context, 0, &dst); + + res.Size = src.Size; + // Note: The accumulator is compared with the destination, not the other way around. + res.Value.Qwords[0] = src.Value.Qwords[0] - dst.Value.Qwords[0]; + + SET_FLAGS(Context, res, src, dst, FM_SUB); + + if (src.Value.Qwords[0] == dst.Value.Qwords[0]) + { + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + } + else + { + SET_OP(Context, 2, &dst); + } + break; + + case ND_INS_ADD: + case ND_INS_ADC: + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + + if (ND_INS_ADC == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF); + } + + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_OP(Context, 0, &res); + + break; + + case ND_INS_SUB: + case ND_INS_SBB: + case ND_INS_CMP: + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + + if (ND_INS_SBB == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] -= GET_FLAG(Context, NDR_RFLAG_CF); + } + + SET_FLAGS(Context, res, dst, src, FM_SUB); + + if (ND_INS_CMP != Context->Arch.X86.Instruction.Instruction) + { + SET_OP(Context, 0, &res); + } + + break; + + case ND_INS_INC: + GET_OP(Context, hasNd ? 1 : 0, &dst); + src.Size = dst.Size; + src.Value.Qwords[0] = 1; + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] + src.Value.Qwords[0]; + cf = GET_FLAG(Context, NDR_RFLAG_CF); + SET_FLAGS(Context, res, dst, src, FM_ADD); + SET_FLAG(Context, NDR_RFLAG_CF, cf); + SET_OP(Context, 0, &res); + break; + + case ND_INS_DEC: + GET_OP(Context, hasNd ? 1 : 0, &dst); + src.Size = dst.Size; + src.Value.Qwords[0] = 1; + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + cf = GET_FLAG(Context, NDR_RFLAG_CF); + SET_FLAGS(Context, res, dst, src, FM_SUB); + SET_FLAG(Context, NDR_RFLAG_CF, cf); + SET_OP(Context, 0, &res); + break; + + case ND_INS_PUSH: + case ND_INS_PUSHP: + case ND_INS_PUSHF: + GET_OP(Context, 0, &src); + SET_OP(Context, 1, &src); + break; + + case ND_INS_POP: + case ND_INS_POPP: + case ND_INS_POPF: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_PUSH2: + case ND_INS_PUSH2P: + // APX extended EVEX can only be enabled in 64-bit mode, so it's safe to always assume 64-bit regs. + src.Size = 16; + src.Value.Qwords[0] = ShemuX86GetGprValue(Context, Context->Arch.X86.Instruction.Operands[1].Info.Register.Reg, 8, ND_FALSE); + src.Value.Qwords[1] = ShemuX86GetGprValue(Context, Context->Arch.X86.Instruction.Operands[0].Info.Register.Reg, 8, ND_FALSE); + SET_OP(Context, 2, &src); + break; + + case ND_INS_POP2: + case ND_INS_POP2P: + // I know this looks weird, and you would expect a PUSH2 r1, r2 to have a complementary POP2 r1, r2, but + // according to the current APX specification, this is not the case. The right pair for PUSH2 r1, r2 is, + // in fact, POP2 r2, r1 (the order of the popped operands must be reversed to match the PUSH2). + GET_OP(Context, 2, &src); + ShemuX86SetGprValue(Context, Context->Arch.X86.Instruction.Operands[0].Info.Register.Reg, 8, src.Value.Qwords[0], ND_FALSE); + ShemuX86SetGprValue(Context, Context->Arch.X86.Instruction.Operands[1].Info.Register.Reg, 8, src.Value.Qwords[1], ND_FALSE); + break; + + case ND_INS_PUSHA: + src.Size = 16; + src.Value.Words[7] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_AX, 2, ND_FALSE); + src.Value.Words[6] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_CX, 2, ND_FALSE); + src.Value.Words[5] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_DX, 2, ND_FALSE); + src.Value.Words[4] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_BX, 2, ND_FALSE); + src.Value.Words[3] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_SP, 2, ND_FALSE); + src.Value.Words[2] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_BP, 2, ND_FALSE); + src.Value.Words[1] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_SI, 2, ND_FALSE); + src.Value.Words[0] = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_DI, 2, ND_FALSE); + SET_OP(Context, 1, &src); // Operand 1 is the stack (destination). + break; + + case ND_INS_PUSHAD: + src.Size = 32; + src.Value.Dwords[7] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EAX, 4, ND_FALSE); + src.Value.Dwords[6] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_ECX, 4, ND_FALSE); + src.Value.Dwords[5] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EDX, 4, ND_FALSE); + src.Value.Dwords[4] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EBX, 4, ND_FALSE); + src.Value.Dwords[3] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_ESP, 4, ND_FALSE); + src.Value.Dwords[2] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EBP, 4, ND_FALSE); + src.Value.Dwords[1] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_ESI, 4, ND_FALSE); + src.Value.Dwords[0] = (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EDI, 4, ND_FALSE); + SET_OP(Context, 1, &src); // Operand 1 is the stack (destination). + break; + + case ND_INS_POPA: + GET_OP(Context, 1, &src); // Operand 1 is the stack (source). + ShemuX86SetGprValue(Context, NDR_AX, 2, src.Value.Words[7], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_CX, 2, src.Value.Words[6], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_DX, 2, src.Value.Words[5], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_BX, 2, src.Value.Words[4], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_BP, 2, src.Value.Words[2], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_SI, 2, src.Value.Words[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_DI, 2, src.Value.Words[0], ND_FALSE); + break; + + case ND_INS_POPAD: + GET_OP(Context, 1, &src); // Operand 1 is the stack (source). + ShemuX86SetGprValue(Context, NDR_EAX, 4, src.Value.Dwords[7], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_ECX, 4, src.Value.Dwords[6], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EDX, 4, src.Value.Dwords[5], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EBX, 4, src.Value.Dwords[4], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EBP, 4, src.Value.Dwords[2], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_ESI, 4, src.Value.Dwords[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EDI, 4, src.Value.Dwords[0], ND_FALSE); + break; + + case ND_INS_LEA: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_SHL: + case ND_INS_SAL: + case ND_INS_SHR: + case ND_INS_SAR: + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + + if (dst.Size == 8) + { + src.Value.Qwords[0] &= 0x3f; + } + else + { + src.Value.Qwords[0] &= 0x1f; + } + + res.Size = dst.Size; + + if (ND_INS_SHL == Context->Arch.X86.Instruction.Instruction || + ND_INS_SAL == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] << src.Value.Qwords[0]; + } + else if (ND_INS_SHR == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] >> src.Value.Qwords[0]; + } + else + { + ND_SINT64 val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]); + val = val >> src.Value.Qwords[0]; + res.Value.Qwords[0] = (ND_UINT64)val; + } + + if (src.Value.Qwords[0] != 0) + { + // 0 bit shifts do not affect the flags. + if (ND_INS_SHL == Context->Arch.X86.Instruction.Instruction || + ND_INS_SAL == Context->Arch.X86.Instruction.Instruction) + { + SET_FLAGS(Context, res, dst, src, FM_SHL); + } + else if (ND_INS_SHR == Context->Arch.X86.Instruction.Instruction) + { + SET_FLAGS(Context, res, dst, src, FM_SHR); + } + else + { + SET_FLAGS(Context, res, dst, src, FM_SAR); + } + } + + SET_OP(Context, 0, &res); + break; + + case ND_INS_RCL: + case ND_INS_RCR: + case ND_INS_ROL: + case ND_INS_ROR: + { + ND_UINT32 cnt, tempcnt, cntmask, bitwidth; + ND_UINT8 tempCF = 0; + + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + + cnt = (ND_UINT32)src.Value.Qwords[0]; + cntmask = ((dst.Size == 8) ? 0x3F : 0x1F); + tempcnt = (cnt & cntmask); + bitwidth = (ND_UINT32)dst.Size * 8; + + if (ND_INS_RCL == Context->Arch.X86.Instruction.Instruction || + ND_INS_RCR == Context->Arch.X86.Instruction.Instruction) + { + if (dst.Size == 1) + { + tempcnt %= 9; + } + else if (dst.Size == 2) + { + tempcnt %= 17; + } + } + else + { + tempcnt %= (dst.Size * 8); + } + + if (ND_INS_RCL == Context->Arch.X86.Instruction.Instruction) + { + tempCF = GET_FLAG(Context, NDR_RFLAG_CF); + + if (tempcnt != 0) + { + // tempcnt is in range [1, dst bit width]. + ND_UINT64 left = (tempcnt == bitwidth) ? 0 : (dst.Value.Qwords[0] << tempcnt); + ND_UINT64 right = (tempcnt == 1) ? 0 : (dst.Value.Qwords[0] >> (bitwidth - tempcnt + 1)); + + SET_FLAG(Context, NDR_RFLAG_CF, ND_GET_BIT(bitwidth - tempcnt, dst.Value.Qwords[0])); + + dst.Value.Qwords[0] = left | ((ND_UINT64)tempCF << (tempcnt - 1)) | right; + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); + } + } + else if (ND_INS_RCR == Context->Arch.X86.Instruction.Instruction) + { + tempCF = GET_FLAG(Context, NDR_RFLAG_CF); + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); + } + + if (tempcnt != 0) + { + // tempcnt is in range [1, dst bit width]. + ND_UINT64 left = (tempcnt == bitwidth) ? 0 : (dst.Value.Qwords[0] >> tempcnt); + ND_UINT64 right = (tempcnt == 1) ? 0 : (dst.Value.Qwords[0] << (bitwidth - tempcnt + 1)); + + SET_FLAG(Context, NDR_RFLAG_CF, ND_GET_BIT(tempcnt - 1, dst.Value.Qwords[0])); + + dst.Value.Qwords[0] = left | ((ND_UINT64)tempCF << (bitwidth - tempcnt)) | right; + } + } + else if (ND_INS_ROL == Context->Arch.X86.Instruction.Instruction) + { + if (tempcnt != 0) + { + // tempcnt is in range [1, dst bit width - 1]. + ND_UINT64 left = dst.Value.Qwords[0] << tempcnt; + ND_UINT64 right = dst.Value.Qwords[0] >> (bitwidth - tempcnt); + + dst.Value.Qwords[0] = left | right; + } + + if ((cnt & cntmask) != 0) + { + SET_FLAG(Context, NDR_RFLAG_CF, ND_LSB(dst.Size, dst.Value.Qwords[0])); + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + GET_FLAG(Context, NDR_RFLAG_CF)); + } + } + else // ND_INS_ROR + { + if (tempcnt != 0) + { + // tempcnt is in range [1, dst bit width - 1]. + ND_UINT64 left = (dst.Value.Qwords[0] >> tempcnt); + ND_UINT64 right = (dst.Value.Qwords[0] << (bitwidth - tempcnt)); + + dst.Value.Qwords[0] = left | right; + } + + if ((cnt & cntmask) != 0) + { + SET_FLAG(Context, NDR_RFLAG_CF, ND_MSB(dst.Size, dst.Value.Qwords[0])); + } + + if ((cnt & cntmask) == 1) + { + SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^ + ND_GET_BIT(dst.Size * 8ULL - 2, dst.Value.Qwords[0])); + } + } + + SET_OP(Context, 0, &dst); + } + break; + + case ND_INS_OR: + case ND_INS_XOR: + case ND_INS_AND: + case ND_INS_TEST: + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + + res.Size = dst.Size; + + if (ND_INS_OR == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] | src.Value.Qwords[0]; + } + else if (ND_INS_XOR == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] ^ src.Value.Qwords[0]; + } + else + { + res.Value.Qwords[0] = dst.Value.Qwords[0] & src.Value.Qwords[0]; + } + + if (ND_INS_TEST != Context->Arch.X86.Instruction.Instruction) + { + SET_OP(Context, 0, &res); + } + + SET_FLAGS(Context, res, dst, src, FM_LOGIC); + break; + + case ND_INS_NOT: + GET_OP(Context, hasNd ? 1 : 0, &dst); + dst.Value.Qwords[0] = ~dst.Value.Qwords[0]; + SET_OP(Context, 0, &dst); + break; + + case ND_INS_NEG: + GET_OP(Context, hasNd ? 1 : 0, &src); + dst.Size = src.Size; + dst.Value.Qwords[0] = 0; + res.Size = src.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + SET_OP(Context, 0, &res); + SET_FLAGS(Context, res, dst, src, FM_SUB); + SET_FLAG(Context, NDR_RFLAG_CF, src.Value.Qwords[0] != 0); + break; + + case ND_INS_BT: + case ND_INS_BTS: + case ND_INS_BTR: + case ND_INS_BTC: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + src.Value.Qwords[0] %= dst.Size * 8ULL; + + // Store the bit inside CF. + SET_FLAG(Context, NDR_RFLAG_CF, (dst.Value.Qwords[0] >> src.Value.Qwords[0]) & 1); + + if (ND_INS_BTS == Context->Arch.X86.Instruction.Instruction) + { + dst.Value.Qwords[0] |= (1ULL << src.Value.Qwords[0]); + } + else if (ND_INS_BTR == Context->Arch.X86.Instruction.Instruction) + { + dst.Value.Qwords[0] &= ~(1ULL << src.Value.Qwords[0]); + } + else if (ND_INS_BTC == Context->Arch.X86.Instruction.Instruction) + { + dst.Value.Qwords[0] ^= (1ULL << src.Value.Qwords[0]); + } + + if (ND_INS_BT != Context->Arch.X86.Instruction.Instruction) + { + SET_OP(Context, 0, &dst); + } + + break; + + case ND_INS_Jcc: + // Initial condition evaluation. + taken = ShemuX86EvalCondition(Context, Context->Arch.X86.Instruction.Condition); + + // Track the loop. This may override the taken/not taken state. + taken = ShemuX86TrackLoop(Context, taken); + + if (taken) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 1, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &res); + } + + break; + + case ND_INS_JrCXZ: + // Fetch the rCX value. It could be CX, ECX or RCX, depending on address size. + GET_OP(Context, 1, &dst); + + // Initial condition evaluation. + taken = dst.Value.Qwords[0] == 0; + + // Track the loop. This may override the taken/not taken state. + taken = ShemuX86TrackLoop(Context, taken); + + if (taken) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 2, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 2, &res); + } + + break; + + case ND_INS_LOOP: + case ND_INS_LOOPNZ: + case ND_INS_LOOPZ: + // rCX is decremented first. Note that the size depends on address size. + GET_OP(Context, 1, &dst); + dst.Value.Qwords[0]--; + SET_OP(Context, 1, &dst); + + // Initial condition evaluation. + taken = dst.Value.Qwords[0] > 0 && + (((ND_INS_LOOPNZ == Context->Arch.X86.Instruction.Instruction) && (0 == GET_FLAG(Context, NDR_RFLAG_ZF))) || + ((ND_INS_LOOPZ == Context->Arch.X86.Instruction.Instruction) && (0 != GET_FLAG(Context, NDR_RFLAG_ZF))) || + (ND_INS_LOOP == Context->Arch.X86.Instruction.Instruction)); + + // Track the loop. This may override the taken/not taken state. + taken = ShemuX86TrackLoop(Context, taken); + + if (taken) + { + // Modify the RIP if the branch is taken. + GET_OP(Context, 2, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 2, &res); + } + + break; + + case ND_INS_JMPNR: + // Track loops. + ShemuX86TrackLoop(Context, ND_TRUE); + + GET_OP(Context, 1, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &res); + break; + + case ND_INS_JMPNI: + GET_OP(Context, 0, &src); + SET_OP(Context, 1, &src); // Set the RIP to the new value. + break; + + case ND_INS_CALLNR: + // Save the EIP on the stack. + GET_OP(Context, 1, &res); + SET_OP(Context, 2, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.RelativeOffset.Rel; + SET_OP(Context, 1, &res); + break; + + case ND_INS_CALLNI: + GET_OP(Context, 0, &src); + GET_OP(Context, 1, &dst); // The RIP + SET_OP(Context, 2, &dst); // Save the RIP on the stack. + SET_OP(Context, 1, &src); // Set the RIP to the new value. + break; + + case ND_INS_RETN: + if (!Context->Arch.X86.Instruction.HasImm1) + { + // The simple RET form, 0xC3 + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + } + else + { + // The RET Imm16 form, 0xC2 + GET_OP(Context, 3, &src); + SET_OP(Context, 1, &src); + + // Patch the RSP register. + GET_OP(Context, 2, &res); + res.Value.Qwords[0] += Context->Arch.X86.Instruction.Operands[0].Info.Immediate.Imm; + SET_OP(Context, 2, &res); + } + break; + + case ND_INS_JMPFD: + case ND_INS_CALLFD: + cs = (ND_UINT16)Context->Arch.X86.Instruction.Operands[0].Info.Address.BaseSeg; + goto check_far_branch; + + case ND_INS_JMPFI: + case ND_INS_CALLFI: + case ND_INS_IRET: + case ND_INS_RETF: + if (Context->Arch.X86.Instruction.Instruction == ND_INS_RETF) + { + if (Context->Arch.X86.Instruction.Operands[0].Type == ND_OP_IMM) + { + // RETF imm + GET_OP(Context, 3, &src); + } + else + { + // RETF + GET_OP(Context, 2, &src); + } + } + else if (Context->Arch.X86.Instruction.Instruction == ND_INS_IRET) + { + // IRET + GET_OP(Context, 2, &src); + } + else + { + // JMP/CALL far + GET_OP(Context, 0, &src); + } + + // The destination code segment is the second WORD/DWORD/QWORD. + switch (Context->Arch.X86.Instruction.WordLength) + { + case 2: + cs = (ND_UINT16)src.Value.Words[1]; + break; + case 4: + cs = (ND_UINT16)src.Value.Dwords[1]; + break; + case 8: + cs = (ND_UINT16)src.Value.Qwords[1]; + break; + default: + cs = 0; + break; + } + +check_far_branch: + if (Context->Arch.X86.Mode == ND_CODE_32 && cs == 0x33) + { + Context->Flags |= SHEMU_FLAG_HEAVENS_GATE; + } + + // We may, in the future, emulate far branches, but they imply some tricky context switches (including + // the default TEB), so it may not be as straight forward as it seems. For now, all we wish to achieve + // is detection of far branches in long-mode, from Wow 64. + stop = ND_TRUE; + break; + + case ND_INS_LODS: + case ND_INS_STOS: + case ND_INS_MOVS: + // Fetch the rCX register, which is the third operand in case of repeated instructions. + while (Context->InstructionsCount < Context->MaxInstructionsCount) + { + // Get the RCX value. + GET_OP(Context, 2, &dst); + + if (Context->Arch.X86.Instruction.IsRepeated && (dst.Value.Qwords[0] == 0)) + { + break; + } + + // Load the source into the destination. + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + + if (Context->Arch.X86.Instruction.IsRepeated) + { + // Decrement RCX. + dst.Value.Qwords[0]--; + SET_OP(Context, 2, &dst); + } + else + { + break; + } + + Context->InstructionsCount++; + } + break; + + case ND_INS_SCAS: + case ND_INS_CMPS: + while (Context->InstructionsCount < Context->MaxInstructionsCount) + { + // Get the RCX value. + GET_OP(Context, 2, &dst); + + if (Context->Arch.X86.Instruction.IsRepeated && (dst.Value.Qwords[0] == 0)) + { + break; + } + + // Move on with the source & destination. + nd_memzero(&dst, sizeof(dst)); + + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + res.Size = dst.Size; + res.Value.Qwords[0] = dst.Value.Qwords[0] - src.Value.Qwords[0]; + + SET_FLAGS(Context, res, dst, src, FM_SUB); + + if (Context->Arch.X86.Instruction.IsRepeated) + { + // Read RCX again & decrement it. + nd_memzero(&dst, sizeof(dst)); + GET_OP(Context, 2, &dst); + dst.Value.Qwords[0]--; + SET_OP(Context, 2, &dst); + + if (Context->Arch.X86.Instruction.HasRepRepzXrelease && !GET_FLAG(Context, NDR_RFLAG_ZF)) + { + break; + } + + if (Context->Arch.X86.Instruction.HasRepnzXacquireBnd && GET_FLAG(Context, NDR_RFLAG_ZF)) + { + break; + } + } + else + { + break; + } + + Context->InstructionsCount++; + } + break; + + case ND_INS_MUL: + case ND_INS_IMUL: + if (Context->Arch.X86.Instruction.ExpOperandsCount == 1) + { + // MUL or IMUL with a single explicit operand. + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + res.Size = dst.Size * 2; + } + else if (Context->Arch.X86.Instruction.ExpOperandsCount == 2) + { + // IMUL with 2 explicit operands. + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + res.Size = dst.Size; + } + else + { + // IMUL with 3 operands. The first operand is the write-only destination. + // This also covers the {ND} form, which is equivalent to the 3 operand form. + GET_OP(Context, 1, &dst); + GET_OP(Context, 2, &src); + res.Size = dst.Size; + } + + + if (dst.Size == 1) + { + if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Words[0] = dst.Value.Bytes[0] * src.Value.Bytes[0]; + } + else + { + res.Value.Words[0] = (ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0]; + } + } + else if (dst.Size == 2) + { + if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Dwords[0] = dst.Value.Words[0] * src.Value.Words[0]; + } + else + { + res.Value.Dwords[0] = (ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0]; + } + } + else if (dst.Size == 4) + { + if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] * src.Value.Qwords[0]; + } + else + { + res.Value.Qwords[0] = (ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0]; + } + } + else + { + if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction) + { + ShemuX86Multiply64Unsigned(dst.Value.Qwords[0], src.Value.Qwords[0], + &res.Value.Qwords[1], &res.Value.Qwords[0]); + } + else + { + ShemuX86Multiply64Signed(dst.Value.Qwords[0], src.Value.Qwords[0], + (ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]); + } + } + + if (Context->Arch.X86.Instruction.ExpOperandsCount == 1) + { + // The result is stored in AX, DX:AX, EDX:EAX or RDX:RAX for the single-operand form. + switch (dst.Size) + { + case 1: + ShemuX86SetGprValue(Context, NDR_AX, 2, res.Value.Words[0], ND_FALSE); + break; + case 2: + ShemuX86SetGprValue(Context, NDR_DX, 2, res.Value.Words[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_AX, 2, res.Value.Words[0], ND_FALSE); + break; + case 4: + ShemuX86SetGprValue(Context, NDR_EDX, 4, res.Value.Dwords[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EAX, 4, res.Value.Dwords[0], ND_FALSE); + break; + case 8: + ShemuX86SetGprValue(Context, NDR_RDX, 8, res.Value.Qwords[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_RAX, 8, res.Value.Qwords[0], ND_FALSE); + break; + } + } + else + { + // The result is truncated and stored in the destination operand for the 2 & 3 operands forms. + SET_OP(Context, 0, &res); + } + + // Set the flags. + if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction) + { + ND_UINT8 cfof = 0; + + // CF and OF are set to 0 if the high part of the result is 0, otherwise they are set to 1. + switch (dst.Size) + { + case 1: + cfof = (0 == res.Value.Bytes[1]) ? 0 : 1; + break; + case 2: + cfof = (0 == res.Value.Words[1]) ? 0 : 1; + break; + case 4: + cfof = (0 == res.Value.Dwords[1]) ? 0 : 1; + break; + case 8: + cfof = (0 == res.Value.Qwords[1]) ? 0 : 1; + break; + } + + SET_FLAG(Context, NDR_RFLAG_CF, cfof); + SET_FLAG(Context, NDR_RFLAG_OF, cfof); + } + else + { + // The CF and OF flags are set when the signed integer value of the intermediate product differs from + // the sign extended operand - size - truncated product, otherwise the CF and OF flags are cleared. + ND_UINT8 cfof = 0, sign = 0; + + sign = ND_MSB(dst.Size, res.Value.Qwords[0]); + + switch (dst.Size) + { + case 1: + cfof = (0 == res.Value.Bytes[1] && 0 == sign) || + ((ND_UINT8)-1 == res.Value.Bytes[1] && 1 == sign) ? 0 : 1; + break; + case 2: + cfof = (0 == res.Value.Words[1] && 0 == sign) || + ((ND_UINT16)-1 == res.Value.Words[1] && 1 == sign) ? 0 : 1; + break; + case 4: + cfof = (0 == res.Value.Dwords[1] && 0 == sign) || + ((ND_UINT32)-1 == res.Value.Dwords[1] && 1 == sign) ? 0 : 1; + break; + case 8: + cfof = (0 == res.Value.Qwords[1] && 0 == sign) || + ((ND_UINT64)-1 == res.Value.Qwords[1] && 1 == sign) ? 0 : 1; + break; + } + + SET_FLAG(Context, NDR_RFLAG_CF, cfof); + SET_FLAG(Context, NDR_RFLAG_OF, cfof); + } + + break; + + case ND_INS_DIV: + case ND_INS_IDIV: + // DIV and IDIV only exist with a single explicit operand encoding. All flags are undefined. + // No {ND} form for DIV/IDIV. + GET_OP(Context, 0, &src); + + if (src.Size == 1) + { + ND_UINT16 divident; + + divident = (ND_UINT16)ShemuX86GetGprValue(Context, NDR_AX, 2, ND_FALSE); + + if (ND_INS_DIV == Context->Arch.X86.Instruction.Instruction) + { + if (!ShemuX86CheckDiv(divident, src.Value.Bytes[0], 1)) + { + stop = ND_TRUE; + break; + } + + res.Value.Bytes[0] = (ND_UINT8)(divident / src.Value.Bytes[0]); + res.Value.Bytes[1] = (ND_UINT8)(divident % src.Value.Bytes[0]); + } + else + { + if (!ShemuX86CheckIdiv((ND_SINT64)(ND_SINT16)divident, (ND_SINT64)(ND_SINT8)src.Value.Bytes[0], 1)) + { + stop = ND_TRUE; + break; + } + + res.Value.Bytes[0] = (ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]); + res.Value.Bytes[1] = (ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]); + } + + // Result in AX (AL - quotient, AH - reminder). + ShemuX86SetGprValue(Context, NDR_AX, 2, res.Value.Words[0], ND_FALSE); + } + else if (src.Size == 2) + { + ND_UINT32 divident; + + divident = ((ND_UINT32)ShemuX86GetGprValue(Context, NDR_EDX, 2, ND_FALSE) << 16) | + (ND_UINT32)ShemuX86GetGprValue(Context, NDR_EAX, 2, ND_FALSE); + + if (ND_INS_DIV == Context->Arch.X86.Instruction.Instruction) + { + if (!ShemuX86CheckDiv(divident, src.Value.Words[0], 2)) + { + stop = ND_TRUE; + break; + } + + res.Value.Words[0] = (ND_UINT16)(divident / src.Value.Words[0]); + res.Value.Words[1] = (ND_UINT16)(divident % src.Value.Words[0]); + } + else + { + if (!ShemuX86CheckIdiv((ND_SINT64)(ND_SINT32)divident, (ND_SINT64)(ND_SINT16)src.Value.Words[0], 2)) + { + stop = ND_TRUE; + break; + } + + res.Value.Words[0] = (ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]); + res.Value.Words[1] = (ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]); + } + + ShemuX86SetGprValue(Context, NDR_DX, 2, res.Value.Words[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_AX, 2, res.Value.Words[0], ND_FALSE); + } + else if (src.Size == 4) + { + ND_UINT64 divident; + + divident = ((ND_UINT64)ShemuX86GetGprValue(Context, NDR_EDX, 4, ND_FALSE) << 32) | + (ND_UINT64)ShemuX86GetGprValue(Context, NDR_EAX, 4, ND_FALSE); + + if (ND_INS_DIV == Context->Arch.X86.Instruction.Instruction) + { + if (!ShemuX86CheckDiv(divident, src.Value.Dwords[0], 4)) + { + stop = ND_TRUE; + break; + } + + res.Value.Dwords[0] = (ND_UINT32)(divident / src.Value.Dwords[0]); + res.Value.Dwords[1] = (ND_UINT32)(divident % src.Value.Dwords[0]); + } + else + { + if (!ShemuX86CheckIdiv((ND_SINT64)divident, (ND_SINT64)(ND_SINT32)src.Value.Dwords[0], 4)) + { + stop = ND_TRUE; + break; + } + + res.Value.Dwords[0] = (ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]); + res.Value.Dwords[1] = (ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]); + } + + ShemuX86SetGprValue(Context, NDR_EDX, 4, res.Value.Dwords[1], ND_FALSE); + ShemuX86SetGprValue(Context, NDR_EAX, 4, res.Value.Dwords[0], ND_FALSE); + } + else if (src.Size == 8) + { + /// Not implemented! + } + + break; + + case ND_INS_CLD: + SET_FLAG(Context, NDR_RFLAG_DF, 0); + break; + + case ND_INS_STD: + SET_FLAG(Context, NDR_RFLAG_DF, 1); + break; + + case ND_INS_CLC: + SET_FLAG(Context, NDR_RFLAG_CF, 0); + break; + + case ND_INS_STC: + SET_FLAG(Context, NDR_RFLAG_CF, 1); + break; + + case ND_INS_CMC: + Context->Arch.X86.Registers.RegFlags ^= NDR_RFLAG_CF; + break; + + case ND_INS_STI: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + SET_FLAG(Context, NDR_RFLAG_IF, 1); + break; + + case ND_INS_CLI: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + SET_FLAG(Context, NDR_RFLAG_IF, 0); + break; + + case ND_INS_SAHF: + { + ND_UINT8 ah = (ND_UINT8)ShemuX86GetGprValue(Context, NDR_AH, 1, ND_TRUE); + // Handle reserved bits. + ah |= (1 << 1); + ah &= ~((1 << 3) | (1 << 5)); + ((ND_UINT8 *)&Context->Arch.X86.Registers.RegFlags)[0] = ah; + } + break; + + case ND_INS_LAHF: + { + ND_UINT8 ah = ((ND_UINT8 *)&Context->Arch.X86.Registers.RegFlags)[0]; + ShemuX86SetGprValue(Context, NDR_AH, 1, ah, ND_TRUE); + } + break; + + case ND_INS_SALC: + if (GET_FLAG(Context, NDR_RFLAG_CF)) + { + ShemuX86SetGprValue(Context, NDR_AL, 1, 0xFF, ND_FALSE); + } + else + { + ShemuX86SetGprValue(Context, NDR_AL, 1, 0x00, ND_FALSE); + } + break; + + case ND_INS_NOP: + if (sled) + { + Context->NopCount++; + } + break; + + case ND_INS_WAIT: + break; + + case ND_INS_CBW: + case ND_INS_CWDE: + case ND_INS_CDQE: + GET_OP(Context, 1, &src); + dst.Size = src.Size * 2; + dst.Value.Qwords[0] = ND_SIGN_EX(src.Size, src.Value.Qwords[0]); + SET_OP(Context, 0, &dst); + break; + + case ND_INS_CWD: + case ND_INS_CDQ: + case ND_INS_CQO: + GET_OP(Context, 1, &src); + dst.Size = src.Size; + if (ND_GET_SIGN(src.Size, src.Value.Qwords[0])) + { + dst.Value.Qwords[0] = 0xFFFFFFFFFFFFFFFF; + } + else + { + dst.Value.Qwords[0] = 0; + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_BSWAP: + GET_OP(Context, 0, &src); + + dst.Size = src.Size; + + switch (src.Size) + { + case 2: + // Although undefined, when executing BSWAP with 16 bit operands, the result is set to 0. + dst.Value.Words[0] = 0; + break; + case 4: + dst.Value.Bytes[3] = src.Value.Bytes[0]; + dst.Value.Bytes[2] = src.Value.Bytes[1]; + dst.Value.Bytes[1] = src.Value.Bytes[2]; + dst.Value.Bytes[0] = src.Value.Bytes[3]; + break; + case 8: + dst.Value.Bytes[7] = src.Value.Bytes[0]; + dst.Value.Bytes[6] = src.Value.Bytes[1]; + dst.Value.Bytes[5] = src.Value.Bytes[2]; + dst.Value.Bytes[4] = src.Value.Bytes[3]; + dst.Value.Bytes[3] = src.Value.Bytes[4]; + dst.Value.Bytes[2] = src.Value.Bytes[5]; + dst.Value.Bytes[1] = src.Value.Bytes[6]; + dst.Value.Bytes[0] = src.Value.Bytes[7]; + default: + break; + } + + SET_OP(Context, 0, &dst); + break; + + case ND_INS_BSF: + case ND_INS_BSR: + // No APX form. + GET_OP(Context, 1, &src); + + if (src.Value.Qwords[0] == 0) + { + SET_FLAG(Context, NDR_RFLAG_ZF, 1); + } + else + { + SET_FLAG(Context, NDR_RFLAG_ZF, 0); + + dst.Size = src.Size; + dst.Value.Qwords[0] = ShemuX86CountZeroBits(src.Value.Qwords[0], + src.Size, + Context->Arch.X86.Instruction.Instruction == ND_INS_BSF); + + if (Context->Arch.X86.Instruction.Instruction == ND_INS_BSR) + { + dst.Value.Qwords[0] = src.Size * 8ULL - dst.Value.Qwords[0] - 1; + } + + SET_OP(Context, 0, &dst); + } + break; + + case ND_INS_POPCNT: + // No {ND} form. + GET_OP(Context, 1, &src); + + dst.Size = src.Size; + dst.Value.Qwords[0] = 0; + + for (ND_UINT32 bit = 0; bit < src.Size * 8; bit++) + { + if (ND_GET_BIT(bit, src.Value.Qwords[0])) + { + dst.Value.Qwords[0]++; + } + } + + SET_FLAG(Context, NDR_RFLAG_OF, 0); + SET_FLAG(Context, NDR_RFLAG_SF, 0); + SET_FLAG(Context, NDR_RFLAG_ZF, 0); + SET_FLAG(Context, NDR_RFLAG_CF, 0); + SET_FLAG(Context, NDR_RFLAG_PF, 0); + SET_FLAG(Context, NDR_RFLAG_ZF, src.Value.Qwords[0] == 0 ? 1 : 0); + + SET_OP(Context, 0, &dst); + break; + + case ND_INS_LZCNT: + case ND_INS_TZCNT: + // No {ND} form. + GET_OP(Context, 1, &src); + + dst.Size = src.Size; + dst.Value.Qwords[0] = ShemuX86CountZeroBits(src.Value.Qwords[0], + src.Size, + Context->Arch.X86.Instruction.Instruction == ND_INS_TZCNT); + + // Set CF. + if (dst.Value.Qwords[0] == src.Size * 8ULL) + { + SET_FLAG(Context, NDR_RFLAG_CF, 1); + } + else + { + SET_FLAG(Context, NDR_RFLAG_CF, 0); + } + + // Set ZF. + if (dst.Value.Qwords[0] == 0) + { + SET_FLAG(Context, NDR_RFLAG_ZF, 1); + } + else + { + SET_FLAG(Context, NDR_RFLAG_ZF, 0); + } + + // Set the result. + SET_OP(Context, 0, &dst); + break; + + case ND_INS_SHLD: + case ND_INS_SHRD: + { + SHEMU_VALUE cnt = { 0 }; + + GET_OP(Context, hasNd ? 1 : 0, &dst); + GET_OP(Context, hasNd ? 2 : 1, &src); + GET_OP(Context, hasNd ? 3 : 2, &cnt); + + res.Size = dst.Size; + + if (dst.Size == 8) + { + cnt.Value.Qwords[0] &= 0x3f; + } + else + { + cnt.Value.Qwords[0] &= 0x1f; + } + + if (cnt.Value.Qwords[0] == 0) + { + // 0-shift, destination & flags are not affected. + } + else if (cnt.Value.Qwords[0] > dst.Size * 8ull) + { + // Shift count larger that operand size, destination & flags are undefined. Store 0 in destination. + SET_OP(Context, 0, &res); + } + else + { + // Positive shift, count less than operand size. + if (ND_INS_SHLD == Context->Arch.X86.Instruction.Instruction) + { + res.Value.Qwords[0] = dst.Value.Qwords[0] << cnt.Value.Qwords[0]; + + res.Value.Qwords[0] |= src.Value.Qwords[0] >> (dst.Size * 8ull - cnt.Value.Qwords[0]); + + SET_FLAGS(Context, res, dst, cnt, FM_SHL); + } + else + { + res.Value.Qwords[0] = dst.Value.Qwords[0] >> cnt.Value.Qwords[0]; + + res.Value.Qwords[0] |= src.Value.Qwords[0] << (dst.Size * 8ull - cnt.Value.Qwords[0]); + + SET_FLAGS(Context, res, dst, cnt, FM_SHR); + } + + SET_OP(Context, 0, &res); + } + } + break; + + case ND_INS_PREFETCH: + case ND_INS_PREFETCHE: + case ND_INS_PREFETCHM: + case ND_INS_PREFETCHNTA: + case ND_INS_PREFETCHT0: + case ND_INS_PREFETCHT1: + case ND_INS_PREFETCHT2: + case ND_INS_PREFETCHW: + case ND_INS_PREFETCHWT1: + // Act as NOPs, they're just hints to the hardware prefetchers. + break; + + case ND_INS_ENDBR: + // Acts as a NOP, it's just a hint to the decoder. + break; + + case ND_INS_LFENCE: + case ND_INS_SFENCE: + case ND_INS_MFENCE: + // Nothing can be done for them, really. + break; + + case ND_INS_CPUID: + // OK; EAX, EBX, ECX and EDX are modified, which also zeroes the high 32 bit. + ShemuX86SetGprValue(Context, NDR_RAX, 8, 0, ND_FALSE); + ShemuX86SetGprValue(Context, NDR_RCX, 8, 0, ND_FALSE); + ShemuX86SetGprValue(Context, NDR_RDX, 8, 0, ND_FALSE); + ShemuX86SetGprValue(Context, NDR_RBX, 8, 0, ND_FALSE); + break; + + // Some basic MMX/SSE instructions supported. + case ND_INS_EMMS: + nd_memzero(Context->Arch.X86.MmxRegisters, sizeof(Context->Arch.X86.MmxRegisters)); + break; + + case ND_INS_MOVD: + case ND_INS_MOVQ: + case ND_INS_MOVDQU: + case ND_INS_MOVDQA: + // If the source size is less than the destination size, the upper bits will be zero. + // Note that we don't really care about #GP on unaligned MOVDQA accesses... + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_PUNPCKLBW: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + if (dst.Size == 8) + { + // Operating on MMX register. + dst.Value.Bytes[7] = src.Value.Bytes[3]; + dst.Value.Bytes[6] = dst.Value.Bytes[3]; + dst.Value.Bytes[5] = src.Value.Bytes[2]; + dst.Value.Bytes[4] = dst.Value.Bytes[2]; + dst.Value.Bytes[3] = src.Value.Bytes[1]; + dst.Value.Bytes[2] = dst.Value.Bytes[1]; + dst.Value.Bytes[1] = src.Value.Bytes[0]; + } + else + { + // Operating on XMM register. + dst.Value.Bytes[15] = src.Value.Bytes[7]; + dst.Value.Bytes[14] = dst.Value.Bytes[7]; + dst.Value.Bytes[13] = src.Value.Bytes[6]; + dst.Value.Bytes[12] = dst.Value.Bytes[6]; + dst.Value.Bytes[11] = src.Value.Bytes[5]; + dst.Value.Bytes[10] = dst.Value.Bytes[5]; + dst.Value.Bytes[9] = src.Value.Bytes[4]; + dst.Value.Bytes[8] = dst.Value.Bytes[4]; + dst.Value.Bytes[7] = src.Value.Bytes[3]; + dst.Value.Bytes[6] = dst.Value.Bytes[3]; + dst.Value.Bytes[5] = src.Value.Bytes[2]; + dst.Value.Bytes[4] = dst.Value.Bytes[2]; + dst.Value.Bytes[3] = src.Value.Bytes[1]; + dst.Value.Bytes[2] = dst.Value.Bytes[1]; + dst.Value.Bytes[1] = src.Value.Bytes[0]; + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_PXOR: + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + for (i = 0; i < dst.Size; i++) + { + dst.Value.Bytes[i] ^= src.Value.Bytes[i]; + } + SET_OP(Context, 0, &dst); + break; + + // Some basic AVX/AVX2 instructions support. + case ND_INS_VMOVD: + case ND_INS_VMOVQ: + case ND_INS_VMOVDQU: + case ND_INS_VMOVDQA: + GET_OP(Context, 1, &src); + SET_OP(Context, 0, &src); + break; + + case ND_INS_VPBROADCASTB: + case ND_INS_VPBROADCASTW: + case ND_INS_VPBROADCASTD: + case ND_INS_VPBROADCASTQ: + GET_OP(Context, 1, &src); + dst.Size = Context->Arch.X86.Instruction.Operands[0].Size; + for (i = 0; i < dst.Size / src.Size; i++) + { + switch (src.Size) + { + case 1: + dst.Value.Bytes[i] = src.Value.Bytes[0]; + break; + case 2: + dst.Value.Words[i] = src.Value.Words[0]; + break; + case 4: + dst.Value.Dwords[i] = src.Value.Dwords[0]; + break; + default: + dst.Value.Qwords[i] = src.Value.Qwords[0]; + break; + } + } + SET_OP(Context, 0, &dst); + break; + + case ND_INS_VPXOR: + GET_OP(Context, 1, &dst); + GET_OP(Context, 2, &src); + for (i = 0; i < dst.Size; i++) + { + dst.Value.Bytes[i] ^= src.Value.Bytes[i]; + } + SET_OP(Context, 0, &dst); + break; + + // Software interrupt/SYSCALL/SYSENTER. + case ND_INS_INT: + if ((Context->Arch.X86.Instruction.Immediate1 == 0x80 || + Context->Arch.X86.Instruction.Immediate1 == 0x2E) && + Context->Arch.X86.Registers.RegRax < 0x1000) + { + Context->Flags |= SHEMU_FLAG_SYSCALL; + } + + // Fall through + case ND_INS_INT1: + case ND_INS_INT3: + case ND_INS_INTO: + stop = ND_TRUE; + break; + + case ND_INS_SYSCALL: + case ND_INS_SYSENTER: + if (Context->Arch.X86.Registers.RegRax < 0x1000) + { + Context->Flags |= SHEMU_FLAG_SYSCALL; + } + stop = ND_TRUE; + break; + + // Some basic privileged instructions supported, specific to kernel-mode shellcodes. + case ND_INS_SWAPGS: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + Context->Flags |= SHEMU_FLAG_SWAPGS; + stop = ND_TRUE; + break; + + case ND_INS_RDMSR: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + // Fetch ECX value. + GET_OP(Context, 2, &src); + + if ((src.Value.Dwords[0] == 0xC0000082 && ND_CODE_64 == Context->Arch.X86.Mode) || + (src.Value.Dwords[0] == 0x00000176 && ND_CODE_32 == Context->Arch.X86.Mode)) + { + Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_READ; + } + + stop = ND_TRUE; + break; + + case ND_INS_WRMSR: + if (Context->Arch.X86.Ring != 0) + { + return SHEMU_ABORT_NO_PRIVILEGE; + } + + // Fetch ECX value. + GET_OP(Context, 2, &src); + + if ((src.Value.Dwords[0] == 0xC0000082 && ND_CODE_64 == Context->Arch.X86.Mode) || + (src.Value.Dwords[0] == 0x00000176 && ND_CODE_32 == Context->Arch.X86.Mode)) + { + Context->Flags |= SHEMU_FLAG_SYSCALL_MSR_WRITE; + } + + stop = ND_TRUE; + break; + + case ND_INS_SIDT: + if (Context->Arch.X86.Ring == 0) + { + // Flag this only in ring0, as we treat the SHEMU_FLAG_SIDT as a ring0 specific indicator - it can be + // used to locate the kernel image. + Context->Flags |= SHEMU_FLAG_SIDT; + } + + stop = ND_TRUE; + break; + +#if defined(ND_ARCH_X64) || defined(ND_ARCH_X86) + case ND_INS_AESIMC: + case ND_INS_AESDEC: + case ND_INS_AESDECLAST: + { + __m128i val, key; + + // Make sure AES support is present, and we can emulate AES decryption using AES instructions. + if (0 == (Context->Options & SHEMU_OPT_SUPPORT_AES)) + { + break; + } + + GET_OP(Context, 0, &dst); + GET_OP(Context, 1, &src); + + shemu_memcpy(&val, &dst, 16); + shemu_memcpy(&key, &src, 16); + + if (Context->Arch.X86.Instruction.Instruction == ND_INS_AESDEC) + { + val = _mm_aesdec_si128(val, key); + } + else if (Context->Arch.X86.Instruction.Instruction == ND_INS_AESDECLAST) + { + val = _mm_aesdeclast_si128(val, key); + } + else if (Context->Arch.X86.Instruction.Instruction == ND_INS_AESIMC) + { + val = _mm_aesimc_si128(key); + } + + shemu_memcpy(&dst, &val, 16); + + SET_OP(Context, 0, &dst); + break; + } +#endif + + case ND_INS_RDTSC: + src.Size = 4; + // Set EAX to lower 32 bits. + src.Value.Dwords[0] = tsc & 0xFFFFFFFF; + SET_OP(Context, 0, &src); + // Set EDX to upper 32 bits. + src.Value.Dwords[0] = tsc >> 32; + SET_OP(Context, 1, &src); + break; + + case ND_INS_RDFSBASE: + case ND_INS_RDGSBASE: + src.Size = Context->Arch.X86.Instruction.Operands[0].Size; + src.Value.Qwords[0] = Context->TibBase; + SET_OP(Context, 0, &src); + break; + + case ND_INS_UD0: + case ND_INS_UD1: + case ND_INS_UD2: + stop = ND_TRUE; + break; + + default: + return SHEMU_ABORT_INSTRUX_NOT_SUPPORTED; + + break; + } + } + + // Minimum percent of the instructions were NOPs => consider we have a NOP sled. Note that we get here only if + // the maximum number of instructions has been emulated successfully; if the emulation is aborted for any reason, + // this code will have no effect. + if ((Context->InstructionsCount >= Context->MaxInstructionsCount / 2) && + (Context->NopCount >= Context->InstructionsCount * Context->NopThreshold / 100)) + { + Context->Flags |= SHEMU_FLAG_NOP_SLED; + } + + return SHEMU_SUCCESS; +} diff --git a/bdshemu/include/bdshemu_common.h b/bdshemu/include/bdshemu_common.h new file mode 100644 index 0000000..b7f77a4 --- /dev/null +++ b/bdshemu/include/bdshemu_common.h @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BDSHEMU_COMMON_H_ +#define BDSHEMU_COMMON_H_ + +#if defined(_MSC_VER) +#include +#else +#define _Analysis_assume_(x) +#endif + + +// The SHELLBMP and STACKBMP are two bitmaps which hold the state of each shellcode byte and each stack byte. +// Inside SHELLBMP, we store whether a shellcode byte has been fetched for execution or not, and whether it was +// modified or not. +// Inside STACKBMP, we store whether a stack byte is part of a previously saved RIP value or not. +#define STACKBMP(ctx) ((ctx)->Intbuf) +#define STACKBMP_SIZE(ctx) ((ctx)->StackSize) +#define SHELLBMP(ctx) (!((ctx)->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL) ? (ctx)->Intbuf + (ctx)->StackSize : ND_NULL) +#define SHELLBMP_SIZE(ctx) (!((ctx)->Options & SHEMU_OPT_DIRECT_MAPPED_SHELL) ? (ctx)->ShellcodeSize : 0) +#define MAX(a, b) ((a) < (b) ? (b) : (a)) +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + + +// Flags used for the shellcode. These are set inside SHELLBMP. Each byte at index X inside SHELLBMP indicates the state +// of the shellcode byte at index X. +#define SHELL_BYTE_DIRTY (0x01) // The location inside the shellcode has been written. +#define SHELL_BYTE_FETCHED (0x02) // The location inside the shellcode has been fetched for execution. +#define SHELL_BYTE_IBYTES (0x04) // The location inside the shellcode represents executed instruction + // bytes. Does not include the first instruction byte, which is marked + // using the SHELL_BYTE_FETCHED flag. + +// Flags used for the stack. These are set inside STACKBMP. Each byte at index X inside STACKBMP indicates the state +// of the stack byte at index X. +#define STACK_BYTE_RIP (0x01) // The location inside the stack contains a RIP portion. + +// Flags used for the GPR tracking mechanism. Each byte X inside the GPR tracker array indicates the state of said GPR. +#define GPR_TRACK_READ (0x01) // The GPR has been read, by any instruction (including RMW). +#define GPR_TRACK_DIRTY (0x02) // The GPR has been modified. + + +#define GET_BITS(val, start, stop) (((val) >> (start)) & ((1ULL << ((stop) - (start) + 1)) - 1)) + +#define ShemuShellBmpStateSet(Context, Start, Count, Flags) \ + ShemuBmpStateUpdate(SHELLBMP(Context), SHELLBMP_SIZE(Context), Start, Count, Flags, ND_FALSE) + +#define ShemuShellBmpStateClear(Context, Start, Count, Flags) \ + ShemuBmpStateUpdate(SHELLBMP(Context), SHELLBMP_SIZE(Context), Start, Count, Flags, ND_TRUE) + +#define ShemuShellBmpStateCheck(Context, Start, Count, Flags) \ + ShemuBmpStateCheck(SHELLBMP(Context), SHELLBMP_SIZE(Context), Start, Count, Flags) + +#define ShemuStackBmpStateSet(Contxt, Start, Count, Flags) \ + ShemuBmpStateUpdate(STACKBMP(Context), STACKBMP_SIZE(Context), Start, Count, Flags, ND_FALSE) + +#define ShemuStackBmpStateClear(Context, Start, Count, Flags) \ + ShemuBmpStateUpdate(STACKBMP(Context), STACKBMP_SIZE(Context), Start, Count, Flags, ND_TRUE) + +#define ShemuStackBmpStateCheck(Context, Start, Count, Flags) \ + ShemuBmpStateCheck(STACKBMP(Context), STACKBMP_SIZE(Context), Start, Count, Flags) + + + + +void +shemu_printf( + SHEMU_CONTEXT *Context, + char *formatstring, + ... + ); + +void * +shemu_memcpy( + void *Dest, + const void *Source, + ND_SIZET Size + ); + +void +ShemuHexlify( + ND_UINT8 *Value, + ND_UINT64 ValueSize, + char *Hex, + ND_UINT64 HexSize + ); + +void +ShemuBmpStateUpdate( + ND_UINT8 *Bitmap, + ND_UINT64 Size, + ND_UINT64 Start, + ND_UINT64 Count, + ND_UINT8 Flags, + ND_BOOL Clear + ); + +ND_BOOL +ShemuBmpStateCheck( + ND_UINT8 *Bitmap, + ND_UINT64 Size, + ND_UINT64 Start, + ND_UINT64 Count, + ND_UINT8 Flags + ); + +ND_BOOL +ShemuIsShellcodePtr( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size + ); + +ND_BOOL +ShemuIsStackPtr( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size + ); + +ND_BOOL +ShemuIsIcachePtr( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size + ); + +SHEMU_STATUS +ShemuMemLoad( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Value + ); + +SHEMU_STATUS +ShemuMemStore( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Value + ); + +SHEMU_STATUS +ShemuMemFetch( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Bytes + ); + +void +ShemuFlushIcache( + SHEMU_CONTEXT *Context + ); + +void +ShemuDisplayMemValue( + SHEMU_CONTEXT *Context, + ND_UINT64 Gla, + ND_UINT64 Size, + ND_UINT8 *Value, + ND_BOOL Load + ); + +ND_BOOL +ShemuIsImmMetasploitHash( + ND_UINT64 Value + ); + +#endif // BDSHEMU_COMMON_H_ \ No newline at end of file diff --git a/bdshemu_fuzz/CMakeLists.txt b/bdshemu_fuzz/CMakeLists.txt index 46a4885..1a26bec 100644 --- a/bdshemu_fuzz/CMakeLists.txt +++ b/bdshemu_fuzz/CMakeLists.txt @@ -1,6 +1,7 @@ cmake_minimum_required(VERSION 3.16) option(BDD_FUZZ_WITH_LOGS "Enable logging for the fuzzer" OFF) +option(BDD_FUZZ_DIRECT_MAP "Enable direct SHEMU_OPT_DIRECT_MAPPED_SHELL" OFF) project(bdshemu_fuzzer LANGUAGES C) @@ -17,4 +18,23 @@ if (BDD_FUZZ_WITH_LOGS) target_compile_definitions(shfuzzx64 PRIVATE ENABLE_LOGGING) endif (BDD_FUZZ_WITH_LOGS) +if (BDD_FUZZ_DIRECT_MAP) + target_compile_definitions(shfuzzx86 PRIVATE DIRECT_MAP) + target_compile_definitions(shfuzzx64 PRIVATE DIRECT_MAP) +endif (BDD_FUZZ_DIRECT_MAP) + +# Using CMAKE_C_COMPILER_ID to check for this will not work because afl-gcc is reported as gcc, while afl-clang and +# afl-clang-fast are reported as clang. +# We also don't want to use libfuzzer with AFL because it seems to have some build issues. +# TODO: but it should work, see https://chromium.googlesource.com/chromium/src/+/master/testing/libfuzzer/AFL_integration.md#how +if ("${CMAKE_C_COMPILER_ID}" STREQUAL "Clang" AND NOT "${CMAKE_C_COMPILER}" MATCHES "afl-.*") + message(STATUS "Will use libfuzzer") + + target_compile_options(shfuzzx86 PRIVATE -fsanitize=fuzzer) + target_link_libraries(shfuzzx86 PRIVATE -fsanitize=fuzzer) + + target_compile_options(shfuzzx64 PRIVATE -fsanitize=fuzzer) + target_link_libraries(shfuzzx64 PRIVATE -fsanitize=fuzzer) +endif () + add_custom_target(shfuzz DEPENDS shfuzzx86 shfuzzx64) diff --git a/bdshemu_fuzz/README.md b/bdshemu_fuzz/README.md deleted file mode 100644 index 66d0235..0000000 --- a/bdshemu_fuzz/README.md +++ /dev/null @@ -1,49 +0,0 @@ -# Bitdefender Shellocde Emulator Fuzzer - -This assumes that you have [AFL](https://github.com/google/AFL) in your path. - -It collects the `bddisasm` and `bdshemu` sources into a single executable, built with AFL instrumentation. - -## Getting started - -Build it with `make shfuzz`. - -Start fuzzing with `make fuzz32` (for 32-bit mode samples) or `make fuzz64` (for 64-bit mode samples). - -If you're in a hurry you can fuzz in the quick and dirty mode with `DIRTY=y`: `make fuzz32 DIRTY=y` or `make fuzz64 DIRTY=y`. - -Activate support for [address sanitizer](https://github.com/google/sanitizers/wiki/AddressSanitizer) with `AFL_USE_ASAN=1 make shfuzz`. This can uncover more bugs, but it is a lot slower and requires more memory. - -Input files are in the `in-32` and `in-64` directories, crashes will be in `out-32/crashes` or `out-64/crashes`, hangs will be in `out-32/hangs` or `out-64/hangs`. - -## Details - -If the `AFL_COMPILER` variable is not set, the build process looks for `afl-clang-fast` and if it is available, the tool is compiled with that. If not, it tries to choose between `afl-clang` and `afl-gcc`. -If you want to use a certain compiler simply set `AFL_COMPILER` before invoking make: `AFL_COMPILER=afl-gcc make`. -Note that `afl-clang-fast` is not compiled by default when compiling AFL. See [llvm mode](https://github.com/google/AFL/tree/master/llvm_mode) in the AFL repository. - -Run the fuzzer in 32-bit mode with `make fuzz32`, or in 64-bit mode with `make fuzz64`. - -If you want to take advantage of multiple cores see [parallel fuzzing](https://github.com/google/AFL/blob/master/docs/parallel_fuzzing.txt). - -If `afl-clang-fast` is used, we try to use AFL in persistent mode, which should provide better performance. - -Note that both `fuzz32` and `fuzz64` assume that the tool was compiled with `afl-clang-fast`, `afl-clang`, or `afl-gcc`. - -ASAN builds will have increased memory requirements. You may need to tweak the `-m` parameter (or set `AFL_MEMORY`) for `afl-fuzz` (see [notes for ASAN](https://github.com/google/AFL/blob/master/docs/notes_for_asan.txt)). - -By default, all logging is disabled, as it is already not visible while AFL is running. Compile with `LOG=y` in order to enable some minimal logging. - -## Using the tool - -The `shfuzz` tool is a simplified version of `disasmtool`. It takes 3 positional arguments: - -```bash -shfuzz file mode use_logging -``` - -- file - the path to a input file that contains instructions to be disassembled and emulated; -- mode - the mode in which to run: `32` for 32-bit instructions, `64` for 64-bit instruction; -- use_logging - if present, will actually log everything that `bdshemu` wants to log; even if absent, the `ShemuLog` implementation will still try to access every character in the string it should normally print, so if you want to find bugs related to logging you can still do, but it is a lot faster when the strings don't get printed. This is ignored if you compile `shfuzz` without `LOG=y`. - -Any errors encountered while parsing the arguments, trying to open the input file, or allocate memory are handled by calling `abort()`. This makes it easier to detect these problems. diff --git a/bdshemu_fuzz/bdshemu_fuzzer.c b/bdshemu_fuzz/bdshemu_fuzzer.c index a29fde9..1208e68 100644 --- a/bdshemu_fuzz/bdshemu_fuzzer.c +++ b/bdshemu_fuzz/bdshemu_fuzzer.c @@ -25,11 +25,37 @@ #define LOG(fmt, ...) #endif // ENABLE_LOGGING -void ShemuLog(char *data) +#define DEFAULT_OPTIONS (SHEMU_OPT_TRACE_EMULATION |\ + SHEMU_OPT_SUPPORT_AES |\ + SHEMU_OPT_SUPPORT_APX) + +void ShemuLog(char *data, void *ctx) { + (void)(ctx); LOG("%s", data); } +ND_BOOL +access_shellcode(void *Ctx, ND_UINT64 Gla, ND_SIZET Size, ND_UINT8 *Buffer, ND_BOOL Store) +{ + SHEMU_CONTEXT *ctx = Ctx; + ND_UINT32 offset; + + offset = (ND_UINT32)(Gla - ctx->ShellcodeBase); + + if (Store) + { + memcpy(ctx->Shellcode + offset, Buffer, Size); + } + else + { + memcpy(Buffer, ctx->Shellcode + offset, Size); + } + + return true; +} + +#if defined(FUZZ_X86) || defined(FUZZ_X64) #ifdef FUZZ_X86 #define DEF_CODE ND_CODE_32 #define FUZZER_TYPE "x86" @@ -45,6 +71,13 @@ void run_shemu(uint8_t *Data, size_t Size) SHEMU_CONTEXT ctx = { 0 }; SHEMU_STATUS shs; +#if defined(DIRECT_MAP) + ctx.AccessShellcode = access_shellcode; + ctx.Options |= SHEMU_OPT_DIRECT_MAPPED_SHELL; +#endif + + ctx.ArchType = SHEMU_ARCH_TYPE_X86; + ctx.Shellcode = Data; ctx.Stack = calloc(1, 0x2000); @@ -65,28 +98,28 @@ void run_shemu(uint8_t *Data, size_t Size) ctx.ShellcodeSize = (uint32_t)Size; ctx.StackBase = 0x100000; ctx.StackSize = 0x2000; - ctx.Registers.RegRsp = 0x101000; + ctx.Arch.X86.Registers.RegRsp = 0x101000; ctx.IntbufSize = (uint32_t)Size + 0x2000; - ctx.Registers.RegFlags = NDR_RFLAG_IF | 2; - ctx.Registers.RegRip = ctx.ShellcodeBase; + ctx.Arch.X86.Registers.RegFlags = NDR_RFLAG_IF | 2; + ctx.Arch.X86.Registers.RegRip = ctx.ShellcodeBase; - ctx.Segments.Cs.Selector = 0x10; - ctx.Segments.Ds.Selector = 0x28; - ctx.Segments.Es.Selector = 0x28; - ctx.Segments.Ss.Selector = 0x28; - ctx.Segments.Fs.Selector = 0x30; - ctx.Segments.Fs.Base = 0x7FFF0000; - ctx.Segments.Gs.Selector = 0x30; - ctx.Segments.Gs.Base = 0x7FFF0000; + ctx.Arch.X86.Segments.Cs.Selector = 0x10; + ctx.Arch.X86.Segments.Ds.Selector = 0x28; + ctx.Arch.X86.Segments.Es.Selector = 0x28; + ctx.Arch.X86.Segments.Ss.Selector = 0x28; + ctx.Arch.X86.Segments.Fs.Selector = 0x30; + ctx.Arch.X86.Segments.Fs.Base = 0x7FFF0000; + ctx.Arch.X86.Segments.Gs.Selector = 0x30; + ctx.Arch.X86.Segments.Gs.Base = 0x7FFF0000; - ctx.Mode = DEF_CODE; - ctx.Ring = 3; - ctx.TibBase = ctx.Mode == ND_CODE_32 ? ctx.Segments.Fs.Base : ctx.Segments.Gs.Base; + ctx.Arch.X86.Mode = DEF_CODE; + ctx.Arch.X86.Ring = 3; + ctx.TibBase = ctx.Arch.X86.Mode == ND_CODE_32 ? ctx.Arch.X86.Segments.Fs.Base : ctx.Arch.X86.Segments.Gs.Base; ctx.MaxInstructionsCount = 4096; ctx.Log = &ShemuLog; ctx.Flags = 0; - ctx.Options = SHEMU_OPT_TRACE_EMULATION; + ctx.Options |= DEFAULT_OPTIONS; shs = ShemuEmulate(&ctx); LOG("[+] Shemu returned: 0x%08x\n", shs); @@ -94,10 +127,11 @@ void run_shemu(uint8_t *Data, size_t Size) free(ctx.Intbuf); free(ctx.Stack); } +#else +#error "Do not know what to fuzz, define one of FUZZ_X86, FUZZ_X64" +#endif #if defined(__AFL_FUZZ_TESTCASE_LEN) -#include - // See https://github.com/AFLplusplus/AFLplusplus/blob/stable/instrumentation/README.persistent_mode.md __AFL_FUZZ_INIT(); diff --git a/bdshemu_fuzz/fuzzing_image_entrypoint.sh b/bdshemu_fuzz/fuzzing_image_entrypoint.sh new file mode 100644 index 0000000..c4a17bc --- /dev/null +++ b/bdshemu_fuzz/fuzzing_image_entrypoint.sh @@ -0,0 +1,21 @@ +#!/bin/bash +set -e + +# Check if the -it flag is provided +if [ -t 0 ] && [ -t 1 ]; then + echo "Running in interactive mode" +else + echo "Error: This container requires an interactive shell (-it flag)." + exit 1 +fi + +# Check if the volume directory is present +if [ ! -d "${SHARE_DIR}" ]; then + echo "Warning: Volume directory '${SHARE_DIR}' is missing." + echo "Please use the -v flag to specify a host directory." + echo "For example 'podman run -v /host/path:${SHARE_DIR}'" + echo "You will need to manually copy fuzzing inputs/outputs from/to the host" +fi + +# Continue with the original command +exec "$@" diff --git a/bdshemu_test/README.md b/bdshemu_test/README.md index c0d0352..98f0327 100644 --- a/bdshemu_test/README.md +++ b/bdshemu_test/README.md @@ -1,7 +1,7 @@ # Shellcode Emulator Tests These tests are used to validate basic bdshemu functionality. Each test consists of up to three files: -* The binary test file. The name format for this type of file is `name_32|64[_r0]`. No extension must be provided; 32 indicates 32 bit test file, 64 indicates 64 bit test file, and r0 indicates kernel payload +* The binary test file. The name format for this type of file is `name_32|64[_r0].test`. 32 indicates 32 bit test file, 64 indicates 64 bit test file, and r0 indicates kernel payload * The output result file. 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zhaT-rsi(7mo^3eo_uwmUhH#>%9#cvtf%QO|IMFVd0rMbE^pIpqt$TE}n8k@6k4&j& zvXGu_I5^c_2hhPe*;AsY22)CAEy7B|GlUVpWMJS1$BF34zmzJgMDbNH2pLd<9*Lf< zOQ~cfMnehPv^Dj@>A;&DX`^SHQi`ccV#Jtzy&OFil~RO^FTyN3^rTcup$Zy8SaSLa zyBH#e9zjZ})hdNY4sE`4ePObC&_hcpMF`+^460B8s%QKN)Boz;*fUHig`8;!Vaa{< zk7kG*dL$^NR=5nFQU785JV_2cM3hn_A76wSpTnLhN-4xDi)#%|s2dE9qd|_19cGoA Q!9QhSM;DJANN*GV4{tpwPXGV_ diff --git a/bdshemu_test/test_all.py b/bdshemu_test/test_all.py index f50dec1..3441c4a 100644 --- a/bdshemu_test/test_all.py +++ b/bdshemu_test/test_all.py @@ -5,87 +5,175 @@ import os import sys import glob +import shutil from zipfile import ZipFile from pathlib import Path -total_tests = 0 -failed_tests = 0 +TEMP_PATH = "!temp" -def test_dir(dir): - global total_tests - global failed_tests +# A test file-name contains some indicators as to how the emulation should be done: +# - If '_16' is present in the name, emulation will be done on 16 bit +# - If '_32' is present in the name, emulation will be done on 32 bit +# - If '_64' is present in the name, emulation will be done on 64 bit +# - If '_r0' is present in the name, emulation will be done as kernel code +# A test case consists of minimum two files: +# - An '.test' file, containing the binary code to be emulated +# - An '.result' file, containing the emulation output +# A test is considered passed if the output produced during emulation is identical to the +# output containted in the '.result' file. + +# +# test_dir +# +# Runs the tests inside the provided directory. +# Returns a tuplecontaining the total number of tests run and the number of failed tests. +# +def test_dir(dir, arch='x86'): + total_tests = 0 + failed_tests = 0 - for f in glob.glob('%s\\*' % dir): - if -1 == f.find('.'): - if 0 < f.find('_16'): - mod = '-b16' - elif 0 < f.find('_32'): - mod = '-b32' - else: - mod = '-b64' - if 0 < f.find('_r0'): - mod += ' -k' - - print(' * Running test case %s...' % f) - os.system('disasm shemu %s -f %s >%s.temp' % (mod, f, f)) - try: - res = open('%s.result' % f).read() - except: - print(' ! No result file provided for test %s!' % f) - - try: - tmp = open('%s.temp' % f).read() - except: - print(' ! No result produced by test %s!' % f) - - total_tests += 1 - if res != tmp: - print(' **** FAILED! ****') - failed_tests += 1 - else: - print(' * Passed.') - - for f in glob.glob('%s\\*_decoded.bin' % dir): - os.remove(f) - for f in glob.glob('%s\\*.temp' % dir): - os.remove(f) + for f in glob.glob('%s\\*.test' % dir): + base, _ = os.path.splitext(f) -def regenerate(dir): - for f in glob.glob('%s\\*' % dir): - if -1 == f.find('.'): - if 0 < f.find('_16'): - mod = '-b16' - elif 0 < f.find('_32'): - mod = '-b32' - else: - mod = '-b64' - if 0 < f.find('_r0'): - mod += ' -k' + tst_file = f + res_file = base + '.result' + tmp_file = base + '.temp' + + if 0 < tst_file.find('_16'): + mod = '-b16' + elif 0 < tst_file.find('_32'): + mod = '-b32' + else: + mod = '-b64' + + if 0 < tst_file.find('_r0'): + mod += ' -k' + + print(' * Running test case %s...' % tst_file) + os.system('disasm shemu %s -f %s >%s' % (mod, tst_file, tmp_file)) + try: + res = open(res_file).read() + except: + print(' ! No result file provided for test %s!' % tst_file) + + try: + tmp = open(tmp_file).read() + except: + print(' ! No result produced by test %s!' % tst_file) + + total_tests += 1 + if res != tmp: + print(' **** FAILED! ****') + failed_tests += 1 + else: + print(' * Passed.') + + # Cleanup. + os.remove(tmp_file) + os.remove(tst_file + "_decoded.bin") + + return (total_tests, failed_tests) + +# +# regenerate +# +def regenerate(dir, arch='x86'): + for f in glob.glob('%s\\*.test' % dir): + base, _ = os.path.splitext(f) + + tst_file = f + res_file = base + '.result' + + if 0 < f.find('_16'): + mod = '-b16' + elif 0 < f.find('_32'): + mod = '-b32' + else: + mod = '-b64' + + if 0 < f.find('_r0'): + mod += ' -k' - print(' * Regenerating test case %s...' % f) - os.system('disasm -exi shemu %s -f %s >%s.result' % (mod, f, f)) - - for f in glob.glob('%s\\*_decoded.bin' % dir): - os.remove(f) + print(' * Regenerating test case %s...' % tst_file) + os.system('disasm -exi shemu %s -f %s >%s' % (mod, tst_file, res_file)) + + # Cleanup. + os.remove(tst_file + "_decoded.bin") + +# +# parse_dir_rec +# +def parse_dir_rec(dir, arch, handler): + for f in glob.glob(dir + "\\*"): + path, name = os.path.split(f) + if name in ['.', '..']: + continue + if os.path.isdir(f): + parse_dir_rec(f, arch, handler) + handler(f, arch) -cleanup_files = [] -print("Extracting test archive...\n") -with ZipFile('bdshemu_test.zip') as zf: - cleanup_files = zf.namelist() - zf.extractall() -print("Done!\n") +# +# test_archive +# +def test_archive(filename, arch='x86'): + cleanup_files = [] -for dn in glob.glob("*"): - if not os.path.isdir(dn): - continue - print('Testing %s...' % dn) - test_dir(dn) -print("Ran %d tests, %d failed" % (total_tests, failed_tests)) + # Run the x86 test. + print("Extracting test archive...") + with ZipFile(filename) as zf: + cleanup_files = zf.namelist() + zf.extractall(path=TEMP_PATH) + zf.close() -print("Cleaning up test files...\n") -for f in cleanup_files: - p = Path(os.getcwd()) / f - if p.is_file(): - p.unlink() -print("Done!\n") + print("Running tests...") + total_tests, failed_tests = 0, 0 + for dn in glob.glob(os.path.join(TEMP_PATH, "*")): + if not os.path.isdir(dn): + continue + print('Testing %s...' % dn) + cnt_tests, cnt_failed = test_dir(dn, arch) + + total_tests += cnt_tests + failed_tests += cnt_failed + + print("========================================================================") + print("Summary:") + print("Ran %d tests, %d failed" % (total_tests, failed_tests)) + print("========================================================================") + print() + + shutil.rmtree(TEMP_PATH) + + +if __name__ == "__main__": + # No arguments provided, auto-run all tests. + if len(sys.argv) == 1: + print("Running x86 tests...") + test_archive("x86\\bdshemu_test_x86.zip") + + sys.exit(0) + + opt_dir = "" + opt_regen = False + opt_arch = 'x86' + + for arg in sys.argv[1:]: + if os.path.isdir(arg): + print("Will test directory", arg) + opt_dir = arg + if arg == "regenerate": + print("Will regenerate tests...") + opt_regen = True + + print("Identified architecture: ", opt_arch) + + # Single directory test. + if not opt_dir: + print("A directory containing tests must be supplied!") + sys.exit(-1) + + if opt_regen: + parse_dir_rec(opt_dir, opt_arch, regenerate) + else: + parse_dir_rec(opt_dir, opt_arch, test_dir) \ No newline at end of file diff --git a/bdshemu_test/x86/bdshemu_test_x86.zip b/bdshemu_test/x86/bdshemu_test_x86.zip new file mode 100644 index 0000000000000000000000000000000000000000..0fcd70ff613b239eba11c47692c74560d1afeb62 GIT binary patch literal 164049 zcma%@1zc3=*T;wMMmh$>0i=eMk_G_>1nKS$X(XgO6s1!dNePisx;q3Z1*97UC5876 z?ykD)?)&F{o<|(!-aEtdJ?H$+InSVU7YUgd1pm@|qM~{A%^wpg@UO9vvy};l(jU)3 z2c0{Tsf536&twOF1_cJ$U(azdb9OP{<}xrbvb8nmWH)lQyU|sF0|KL?jAR5+llkun z)hM$N39^wHpuenLN@6HIC~Nkt_o}};0tyMSGCuur4{hLeln1zc;Y0v|+K@pY%743u zlbN%ttxNDT1^YlKe(;g(tPyTZu-#`QS-o0hLWYz~{=y>rnDJ*M;rP5{)m<;sbEWgh zJxJOnpU(+%bLpD2J)g(zCM8FFr8IOU7gZ-@E&N1HTx!H6uiHr z|D=_WBvCw&yf+)9cL5f0sa74YKv2uTRlBZsg84k&GgMt}y!vepRZC;SgVMU7dop5% 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a/bindings/pybddisasm/pybddisasm/pybddisasm.c +++ b/bindings/pybddisasm/pybddisasm/pybddisasm.c @@ -15,7 +15,7 @@ #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) -#if _MSC_VER +#ifdef _MSC_VER int nd_vsnprintf_s(char *buffer, size_t size, size_t count, const char *format, va_list argptr) { return vsnprintf(buffer, size, format, argptr); diff --git a/bindings/pybddisasm/pybddisasm/pybddisasm.i b/bindings/pybddisasm/pybddisasm/pybddisasm.i index 6308397..b1c1ce0 100644 --- a/bindings/pybddisasm/pybddisasm/pybddisasm.i +++ b/bindings/pybddisasm/pybddisasm/pybddisasm.i @@ -165,13 +165,10 @@ %define __x86_64__ %enddef - %include "bddisasm.h" -%include "constants.h" -%include "cpuidflags.h" -%include "disasmstatus.h" -%include "disasmtypes.h" -%include "registers.h" -%include "version.h" - -%include "pybddisasm.h" +%include "bdx86_constants.h" +%include "bdx86_cpuidflags.h" +%include "bddisasm_status.h" +%include "bddisasm_types.h" +%include "bdx86_registers.h" +%include "bdx86_core.h" diff --git a/bindings/pybddisasm/setup.py b/bindings/pybddisasm/setup.py index 2e7ef9e..4792547 100644 --- a/bindings/pybddisasm/setup.py +++ b/bindings/pybddisasm/setup.py @@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution from codecs import open VERSION = (0, 3, 0) -LIBRARY_VERSION = (1, 38, 0) +LIBRARY_VERSION = (2, 1, 0) DIR_INCLUDE = '../../inc' here = os.path.abspath(os.path.dirname(__file__)) @@ -25,7 +25,6 @@ __library_dirs = ['../../build', '../../bin/x64/Release'] __packages = ['pybddisasm'] __requires = ['setuptools'] - class BinaryDistribution(Distribution): def has_ext_modules(arg): return True @@ -33,10 +32,8 @@ class BinaryDistribution(Distribution): def is_pure(self): return False - def __fn_validate_compatibility(): - print(os.getcwd()) - version_header = '%s/version.h' % (DIR_INCLUDE) + version_header = '%s/bddisasm_version.h' % (DIR_INCLUDE) with open(version_header, 'r') as file: data = file.read() @@ -62,10 +59,9 @@ def __fn_validate_compatibility(): if int(major) != LIBRARY_VERSION[0] or int(minor) != LIBRARY_VERSION[1] or int(revision) != LIBRARY_VERSION[2]: print('error: The version of the library is not compatible with the pybddisasm!') print('error: Library : %s.%s.%s - pybddisasm : %d.%d.%d' % (major, minor, revision, LIBRARY_VERSION[0], - LIBRARY_VERSION[1], LIBRARY_VERSION[2])) + LIBRARY_VERSION[1], LIBRARY_VERSION[2])) sys.exit(1) - __fn_validate_compatibility() with open('README.md', 'r', 'utf-8') as f: @@ -91,11 +87,12 @@ setup( install_requires=__requires, zip_safe=False, classifiers=[ + 'Programming Language :: Python :: 3.5', + 'Programming Language :: Python :: 3.6', 'Programming Language :: Python :: 3.7', 'Programming Language :: Python :: 3.8', 'Programming Language :: Python :: 3.9', 'Programming Language :: Python :: 3.10', - 'Programming Language :: Python :: 3.11', 'License :: OSI Approved :: Apache Software License', 'Operating System :: Microsoft :: Windows', 'Operating System :: POSIX :: Linux' diff --git a/bindings/rsbddisasm/Cargo.toml b/bindings/rsbddisasm/Cargo.toml index 46a2f49..f519e99 100644 --- a/bindings/rsbddisasm/Cargo.toml +++ b/bindings/rsbddisasm/Cargo.toml @@ -4,3 +4,6 @@ members = [ "bddisasm-sys", "bddisasm", ] + +[workspace.package] +version = "0.2.3" diff --git a/bindings/rsbddisasm/bddisasm-sys/Cargo.toml b/bindings/rsbddisasm/bddisasm-sys/Cargo.toml index 79a4c00..afb586c 100644 --- a/bindings/rsbddisasm/bddisasm-sys/Cargo.toml +++ b/bindings/rsbddisasm/bddisasm-sys/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "bddisasm-sys" -version = "0.4.0" +version.workspace = true authors = ["Cristi Anichitei "] edition = "2018" links = "bddisasm" diff --git a/bindings/rsbddisasm/bddisasm-sys/build.rs b/bindings/rsbddisasm/bddisasm-sys/build.rs index cbf0b13..66bbe9e 100644 --- a/bindings/rsbddisasm/bddisasm-sys/build.rs +++ b/bindings/rsbddisasm/bddisasm-sys/build.rs @@ -9,10 +9,10 @@ fn main() { println!("cargo:rerun-if-changed=csrc"); cc::Build::new() - .file("csrc/bddisasm/bddisasm.c") - .file("csrc/bddisasm/bdformat.c") - .file("csrc/bddisasm/bdhelpers.c") - .file("csrc/bddisasm/crt.c") + .file("csrc/bddisasm/bddisasm_crt.c") + .file("csrc/bddisasm/bdx86_decoder.c") + .file("csrc/bddisasm/bdx86_formatter.c") + .file("csrc/bddisasm/bdx86_helpers.c") .include("csrc/bddisasm/include") .include("csrc/inc") .define("BDDISASM_HAS_VSNPRINTF", Some("1")) diff --git a/bindings/rsbddisasm/bddisasm-sys/src/lib.rs b/bindings/rsbddisasm/bddisasm-sys/src/lib.rs index b988f80..05f68f0 100644 --- a/bindings/rsbddisasm/bddisasm-sys/src/lib.rs +++ b/bindings/rsbddisasm/bddisasm-sys/src/lib.rs @@ -30,8 +30,8 @@ mod tests { let mut major: u32 = 0; let mut minor: u32 = 0; let mut revision: u32 = 0; - let mut build_date: *mut c_char = std::ptr::null_mut(); - let mut build_time: *mut c_char = std::ptr::null_mut(); + let mut build_date: *const c_char = std::ptr::null(); + let mut build_time: *const c_char = std::ptr::null(); unsafe { NdGetVersion( @@ -53,7 +53,7 @@ mod tests { // There are no other asserts in this test. Enforcing a known minor version is not worth it, we mainly want to // see that `NdGetVersion` works. - assert_eq!(major, 1); + assert_eq!(major, 2); } fn do_decode(code: &[u8]) -> (INSTRUX, NDSTATUS) { @@ -79,10 +79,7 @@ mod tests { let (instrux, status) = do_decode(&code); assert_eq!(status, 0, "Failed to decode instruction {:#x?}", code); - assert_eq!( - unsafe { instrux.__bindgen_anon_2.Instruction }, - _ND_INS_CLASS::ND_INS_NOP - ); + assert_eq!(instrux.Instruction, _ND_INS_CLASS::ND_INS_NOP); } #[test] diff --git a/bindings/rsbddisasm/bddisasm/CHANGELOG.md b/bindings/rsbddisasm/bddisasm/CHANGELOG.md index b130b65..409fdf0 100644 --- a/bindings/rsbddisasm/bddisasm/CHANGELOG.md +++ b/bindings/rsbddisasm/bddisasm/CHANGELOG.md @@ -2,19 +2,13 @@ ## 0.3.1 -### Added +### Removed -- support for new Intel ISA, per Intel Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE. - -### Changed - -- `Mnemonic`, `IsaSet`, and `Category` use all caps for the enum variants - -## 0.3.0 - -### Fixed - -- #84: handle 0 sizes in `OpSize::from_raw` +- the `ExceptionClass` enum +- `sse_cond`, `has_mvex`, `has_drex`, `has_imm3`, `immediate3`, `sign_disp`, `imm3_length`, `imm3_offset`, `bhint` from `DecodedInstruction` +- multiple variants from `Category`, `IsaSet`, `Mnemonic` in accordance with the changes in `bddisasm` +- `raw_size`, `decorator` from `Operand` +- the `Operand` struct ## 0.2.1 diff --git a/bindings/rsbddisasm/bddisasm/Cargo.toml b/bindings/rsbddisasm/bddisasm/Cargo.toml index c90fb1b..e5bb113 100644 --- a/bindings/rsbddisasm/bddisasm/Cargo.toml +++ b/bindings/rsbddisasm/bddisasm/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "bddisasm" -version = "0.3.0" +version.workspace = true authors = ["Cristi Anichitei "] edition = "2018" license = "Apache-2.0" @@ -14,7 +14,7 @@ categories = ["api-bindings", "hardware-support"] keywords = ["disassembler", "decoder", "x86", "amd64", "x86_64"] [dependencies] -bddisasm-sys = { version = "0.4.0", path = "../bddisasm-sys" } +bddisasm-sys = { version = "0.2.3", path = "../bddisasm-sys" } [features] std = [] @@ -23,5 +23,5 @@ std = [] all-features = true [dev-dependencies] -anyhow = "1.0" +anyhow = "1.0.0" clap = "2.34.0" diff --git a/bindings/rsbddisasm/bddisasm/src/cpu_modes.rs b/bindings/rsbddisasm/bddisasm/src/cpu_modes.rs index 23bf710..94c92cc 100644 --- a/bindings/rsbddisasm/bddisasm/src/cpu_modes.rs +++ b/bindings/rsbddisasm/bddisasm/src/cpu_modes.rs @@ -29,6 +29,7 @@ // TODO: maybe use something like the `bitflags` crate and have all these as flags? /// Privilege levels (rings) in which an instruction is supported. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct PrivilegeLevel { /// Instruction is valid in ring 0. @@ -45,6 +46,7 @@ pub struct PrivilegeLevel { } /// Operating modes in which an instruction is supported. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct OperatingMode { /// The instruction is valid in real mode. @@ -64,6 +66,7 @@ pub struct OperatingMode { } /// Special modes - these may be active inside other modes (example: `TSX` in `Long mode`). +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct SpecialModes { /// The instruction is valid in System Management Mode. @@ -86,6 +89,7 @@ pub struct SpecialModes { } /// VMX mode - they engulf all the other modes. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct VmxMode { /// The instruction is valid in VMX root mode. diff --git a/bindings/rsbddisasm/bddisasm/src/decode_error.rs b/bindings/rsbddisasm/bddisasm/src/decode_error.rs index a40f416..5937324 100644 --- a/bindings/rsbddisasm/bddisasm/src/decode_error.rs +++ b/bindings/rsbddisasm/bddisasm/src/decode_error.rs @@ -7,7 +7,7 @@ //! //! # Notes //! -//! All error codes that can be returned by `bddisasm-sys` are encapsulated in the [`DecodeError`](DecodeError) enum. +//! All error codes that can be returned by `bddisasm-sys` are encapsulated in the [`DecodeError`] enum. //! However, some of these are unlikely to be encountered when using this crate (for example, //! [`BufferOverflow`](DecodeError::BufferOverflow)) which indicates that a buffer passed to the `bddisasm` C library is //! not large enough. @@ -117,6 +117,9 @@ pub enum DecodeError { /// Not enough space is available. BufferOverflow, + /// EVEX payload byte 3 is invalid. + InvalidEvexByte3, + /// Internal library error. InternalError(u64), } @@ -181,6 +184,9 @@ impl fmt::Display for DecodeError { DecodeError::BufferOverflow => { write!(f, "not enough space is available to format instruction") } + DecodeError::InvalidEvexByte3 => { + write!(f, "EVEX payload byte 3 is invalid.") + } DecodeError::InternalError(e) => write!(f, "internal error: {}", e), } } @@ -232,6 +238,7 @@ pub(crate) fn status_to_error(status: ffi::NDSTATUS) -> Result<(), DecodeError> ffi::ND_STATUS_INVALID_PARAMETER => Err(DecodeError::InvalidParameter), ffi::ND_STATUS_INVALID_INSTRUX => Err(DecodeError::InvalidInstrux), ffi::ND_STATUS_BUFFER_OVERFLOW => Err(DecodeError::BufferOverflow), + ffi::ND_STATUS_INVALID_EVEX_BYTE3 => Err(DecodeError::InvalidEvexByte3), ffi::ND_STATUS_INTERNAL_ERROR => Err(DecodeError::InternalError(0)), _ => panic!("Unexpected status: {:#x}", status), } diff --git a/bindings/rsbddisasm/bddisasm/src/decoded_instruction.rs b/bindings/rsbddisasm/bddisasm/src/decoded_instruction.rs index d4d25c6..2e1e397 100644 --- a/bindings/rsbddisasm/bddisasm/src/decoded_instruction.rs +++ b/bindings/rsbddisasm/bddisasm/src/decoded_instruction.rs @@ -12,7 +12,7 @@ use crate::instruction_category::Category; use crate::isa_set::IsaSet; use crate::mnemonic::Mnemonic; use crate::operand; -use crate::operand::{OpAccess, OpAddr, Operands, OperandsLookup}; +use crate::operand::{OpAccess, Operands, OperandsLookup}; use crate::rflags::flags_raw; use crate::tuple::Tuple; @@ -168,45 +168,6 @@ impl VectorSize { } } -/// Exception classes. -/// -/// Different instruction sets or encodings are covered by different exception classes. -#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] -pub enum ExceptionClass { - None, - - /// SSE/AVX exception class (for legacy encoded SSE instructions and VEX instructions). - SseAvx, - - /// EVEX exception class (for EVEX encoded AVX* instructions). - Evex, - - /// Opmask instructions exception class. - Opmask, - - /// AMX exception class type (for VEX encoded AMX instructions). - Amx, -} - -#[doc(hidden)] -impl ExceptionClass { - pub(crate) fn from_raw(value: u8) -> Result { - if value == ffi::_ND_EX_CLASS::ND_EXC_None as u8 { - Ok(ExceptionClass::None) - } else if value == ffi::_ND_EX_CLASS::ND_EXC_SSE_AVX as u8 { - Ok(ExceptionClass::SseAvx) - } else if value == ffi::_ND_EX_CLASS::ND_EXC_EVEX as u8 { - Ok(ExceptionClass::Evex) - } else if value == ffi::_ND_EX_CLASS::ND_EXC_OPMASK as u8 { - Ok(ExceptionClass::Opmask) - } else if value == ffi::_ND_EX_CLASS::ND_EXC_AMX as u8 { - Ok(ExceptionClass::Amx) - } else { - Err(DecodeError::InternalError(value.into())) - } - } -} - /// Describes the way an instruction accesses the flags register. /// /// Individual bits can be checked using the [rflags](crate::rflags) module. @@ -262,6 +223,7 @@ impl EvexRounding { } /// Indicates which prefixes are valid for an instruction. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct ValidPrefixes { /// The instruction supports REP prefix. @@ -306,6 +268,7 @@ impl ValidPrefixes { } /// Indicates which decorators are valid for an instruction. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct ValidDecorators { /// The instruction supports embedded rounding mode. @@ -348,7 +311,7 @@ impl DecodedInstruction { /// /// # Arguments /// - /// * `code` - An [u8](u8) slice that holds the code to be decoded. Note that decoding is attempted only from offset + /// * `code` - An [`u8`] slice that holds the code to be decoded. Note that decoding is attempted only from offset /// 0 inside this code chunk. /// * `mode` - The mode in which to decode the instruction. /// * `ip` - The instruction pointer value to use when formatting the decoded instruction. Does not affect the @@ -403,8 +366,7 @@ impl DecodedInstruction { Ok(DecodedInstruction { inner: instrux, ip, - instruction: Mnemonic::try_from(unsafe { instrux.__bindgen_anon_2.Instruction }) - .unwrap(), + instruction: Mnemonic::try_from(instrux.Instruction).unwrap(), length: instrux.Length as usize, }) } @@ -428,6 +390,7 @@ impl DecodedInstruction { /// Get the mnemonic of the instruction. #[inline] + #[must_use] pub fn mnemonic(&self) -> Mnemonic { self.instruction } @@ -436,6 +399,7 @@ impl DecodedInstruction { /// /// It is guaranteed that no instruction will exceed a length of 15 bytes. #[inline] + #[must_use] pub fn length(&self) -> usize { self.length } @@ -476,22 +440,24 @@ impl DecodedInstruction { /// /// This function will panic if the operand returned by the C library is invalid. This can not happen under normal /// circumstances. + #[must_use] pub fn operands(&self) -> Operands { let mut operands = Operands::default(); - for op_index in 0..self.inner.OperandsCount { + let op_count = self.inner.OperandsCount(); + for op_index in 0..op_count { operands.operands[op_index as usize] = operand::Operand::from_raw(self.inner.Operands[op_index as usize]).unwrap(); } - operands.actual_count = self.inner.OperandsCount as usize; + operands.actual_count = op_count as usize; operands } /// Returns the CPUID support flag. /// - /// If [None](None), the instruction is supported on any CPU, and no CPUID flag exists. + /// If [`None`], the instruction is supported on any CPU, and no CPUID flag exists. /// /// # Examples /// @@ -517,6 +483,7 @@ impl DecodedInstruction { /// # Ok(()) /// # } /// ``` + #[must_use] pub fn cpuid(&self) -> Option { let cpuid = unsafe { self.inner.CpuidFlag.__bindgen_anon_1 }; let leaf = cpuid.Leaf; @@ -548,6 +515,7 @@ impl DecodedInstruction { /// /// This function will panic if the encoding mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn encoding_mode(&self) -> EncodingMode { EncodingMode::from_raw(u32::from(self.inner.EncMode())).unwrap() } @@ -558,6 +526,7 @@ impl DecodedInstruction { /// /// This function will panic if the VEX mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn vex_mode(&self) -> Option { if self.has_vex() { Some(VexMode::from_raw(u32::from(self.inner.VexMode())).unwrap()) @@ -572,13 +541,14 @@ impl DecodedInstruction { /// /// This function will panic if the addressing mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn addr_mode(&self) -> AddressingMode { AddressingMode::from_raw(u32::from(self.inner.AddrMode())).unwrap() } /// Get the operand mode/size. /// - /// This is computed based on the passed-in [DecodeMode](DecodeMode) and instruction prefixes. + /// This is computed based on the passed-in [`DecodeMode`] and instruction prefixes. /// /// # Remarks /// @@ -586,7 +556,7 @@ impl DecodedInstruction { /// /// # Examples /// - /// Using [DecodeMode::Bits64](DecodeMode::Bits64), `0x50` encodes a `PUSH rax` instruction with an operand size of + /// Using [`DecodeMode::Bits64`], `0x50` encodes a `PUSH rax` instruction with an operand size of /// 32 because it has no prefix that promotes it, but the effective size is 64 because the instruction always /// operates on 64 bits. /// @@ -615,6 +585,7 @@ impl DecodedInstruction { /// /// This function will panic if the operand size is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn op_mode(&self) -> OperandSize { OperandSize::from_raw(u32::from(self.inner.OpMode())).unwrap() } @@ -627,13 +598,14 @@ impl DecodedInstruction { /// /// This function will panic if the operand size is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn effective_op_mode(&self) -> OperandSize { OperandSize::from_raw(u32::from(self.inner.EfOpMode())).unwrap() } /// Get the Vector mode/size, if any. /// - /// This is computed based on the passed-in [DecodeMode](DecodeMode) and instruction prefixes. + /// This is computed based on the passed-in [`DecodeMode`] and instruction prefixes. /// /// # Remarks /// @@ -643,6 +615,7 @@ impl DecodedInstruction { /// /// This function will panic if the vector mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn vec_mode(&self) -> Option { if self.has_vector() { Some(VectorSize::from_raw(u32::from(self.inner.VecMode())).unwrap()) @@ -659,6 +632,7 @@ impl DecodedInstruction { /// /// This function will panic if the vector mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn effective_vec_mode(&self) -> Option { if self.has_vector() { Some(VectorSize::from_raw(u32::from(self.inner.EfVecMode())).unwrap()) @@ -669,234 +643,245 @@ impl DecodedInstruction { /// `true` if REX is present. #[inline] + #[must_use] pub fn has_rex(&self) -> bool { self.inner.HasRex() != 0 } /// `true` if VEX is present. #[inline] + #[must_use] pub fn has_vex(&self) -> bool { self.inner.HasVex() != 0 } /// `true` if XOP is present. #[inline] + #[must_use] pub fn has_xop(&self) -> bool { self.inner.HasXop() != 0 } /// `true` if EVEX is present. #[inline] + #[must_use] pub fn has_evex(&self) -> bool { self.inner.HasEvex() != 0 } - /// `true` if MVEX is present. - #[inline] - pub fn has_mvex(&self) -> bool { - self.inner.HasMvex() != 0 - } - /// `true` if 0x66 is present. #[inline] + #[must_use] pub fn has_op_size(&self) -> bool { self.inner.HasOpSize() != 0 } /// `true` if 0x67 is present. #[inline] + #[must_use] pub fn has_addr_size(&self) -> bool { self.inner.HasAddrSize() != 0 } /// `true` if 0xF0 is present. #[inline] + #[must_use] pub fn has_lock(&self) -> bool { self.inner.HasLock() != 0 } /// `true` if 0xF2 is present. #[inline] + #[must_use] pub fn has_repnz_xacquire_bnd(&self) -> bool { self.inner.HasRepnzXacquireBnd() != 0 } /// `true` if 0xF3 is present. #[inline] + #[must_use] pub fn has_rep_repz_xrelease(&self) -> bool { self.inner.HasRepRepzXrelease() != 0 } /// `true` if segment override is present. #[inline] + #[must_use] pub fn has_seg(&self) -> bool { self.inner.HasSeg() != 0 } /// `true` if the instruction is repeated up to `RCX` times. #[inline] + #[must_use] pub fn is_repeated(&self) -> bool { self.inner.IsRepeated() != 0 } /// `true` if the instruction is XACQUIRE enabled. #[inline] + #[must_use] pub fn is_xacquire_enabled(&self) -> bool { self.inner.IsXacquireEnabled() != 0 } /// `true` if the instruction is XRELEASE enabled. #[inline] + #[must_use] pub fn is_xrelease_enabled(&self) -> bool { self.inner.IsXreleaseEnabled() != 0 } /// `true` if the instruction uses RIP relative addressing. #[inline] + #[must_use] pub fn is_rip_relative(&self) -> bool { self.inner.IsRipRelative() != 0 } /// `true` if this is an indirect CALL/JMP that is CET tracked. #[inline] + #[must_use] pub fn is_cet_tracked(&self) -> bool { self.inner.IsCetTracked() != 0 } /// `true` if we have valid MODRM. #[inline] + #[must_use] pub fn has_mod_rm(&self) -> bool { self.inner.HasModRm() != 0 } /// `true` if we have valid SIB. #[inline] + #[must_use] pub fn has_sib(&self) -> bool { self.inner.HasSib() != 0 } - /// `true` if we have valid DREX. - #[inline] - pub fn has_drex(&self) -> bool { - self.inner.HasDrex() != 0 - } - /// `true` if the instruction has displacement. #[inline] + #[must_use] pub fn has_disp(&self) -> bool { self.inner.HasDisp() != 0 } /// `true` if the instruction contains a direct address (ie, `CALL far 0x9A`). #[inline] + #[must_use] pub fn has_addr(&self) -> bool { self.inner.HasAddr() != 0 } /// `true` if the instruction contains a moffset (ie, `MOV al, [mem], 0xA0`). #[inline] + #[must_use] pub fn has_moffset(&self) -> bool { self.inner.HasMoffset() != 0 } /// `true` if immediate is present. #[inline] + #[must_use] pub fn has_imm1(&self) -> bool { self.inner.HasImm1() != 0 } /// `true` if second immediate is present. #[inline] + #[must_use] pub fn has_imm2(&self) -> bool { self.inner.HasImm2() != 0 } - /// `true` if third immediate is present. - #[inline] - pub fn has_imm3(&self) -> bool { - self.inner.HasImm3() != 0 - } - /// `true` if the instruction contains a relative offset (ie, `Jcc 0x7x`). #[inline] + #[must_use] pub fn has_rel_offs(&self) -> bool { self.inner.HasRelOffs() != 0 } /// `true` if SSE immediate that encodes additional registers is present. #[inline] + #[must_use] pub fn has_sse_imm(&self) -> bool { self.inner.HasSseImm() != 0 } /// `true` if the instruction uses compressed displacement. #[inline] + #[must_use] pub fn has_comp_disp(&self) -> bool { self.inner.HasCompDisp() != 0 } /// `true` if the instruction uses broadcast addressing. #[inline] + #[must_use] pub fn has_broadcast(&self) -> bool { self.inner.HasBroadcast() != 0 } /// `true` if the instruction has mask. #[inline] + #[must_use] pub fn has_mask(&self) -> bool { self.inner.HasMask() != 0 } /// `true` if the instruction uses zeroing. #[inline] + #[must_use] pub fn has_zero(&self) -> bool { self.inner.HasZero() != 0 } /// `true` if the instruction has embedded rounding. #[inline] + #[must_use] pub fn has_er(&self) -> bool { self.inner.HasEr() != 0 } /// `true` if the instruction has SAE. #[inline] + #[must_use] pub fn has_sae(&self) -> bool { self.inner.HasSae() != 0 } /// `true` if the instruction ignores embedded rounding. #[inline] + #[must_use] pub fn has_ign_er(&self) -> bool { self.inner.HasIgnEr() != 0 } - /// Displacement sign. `false` if positive, `true` if negative. - #[inline] - pub fn sign_disp(&self) -> bool { - self.inner.SignDisp() != 0 - } - /// `true` if changing prefix. #[inline] + #[must_use] pub fn has_mandatory_66(&self) -> bool { self.inner.HasMandatory66() != 0 } /// 0x66 is mandatory prefix. Does not behave as REP prefix. #[inline] + #[must_use] pub fn has_mandatory_f2(&self) -> bool { self.inner.HasMandatoryF2() != 0 } /// 0x66 is mandatory prefix. Does not behave as REP prefix. #[inline] + #[must_use] pub fn has_mandatory_f3(&self) -> bool { self.inner.HasMandatoryF3() != 0 } /// The length of the instruction word. 2, 4 or 8. #[inline] + #[must_use] pub fn word_length(&self) -> usize { self.inner.WordLength() as usize } @@ -905,72 +890,77 @@ impl DecodedInstruction { /// /// This will also be the offset to the first opcode. The primary opcode will always be the last one. #[inline] + #[must_use] pub fn pref_length(&self) -> usize { self.inner.PrefLength() as usize } /// Number of opcode bytes. Max 3. #[inline] + #[must_use] pub fn op_length(&self) -> usize { self.inner.OpLength() as usize } /// Displacement length, in bytes. Maximum 4. #[inline] + #[must_use] pub fn disp_length(&self) -> usize { self.inner.DispLength() as usize } /// Absolute address length, in bytes. Maximum 8 bytes. #[inline] + #[must_use] pub fn addr_length(&self) -> usize { self.inner.AddrLength() as usize } /// Memory offset length, in bytes. Maximum 8 bytes. #[inline] + #[must_use] pub fn moffset_length(&self) -> usize { self.inner.MoffsetLength() as usize } /// First immediate length, in bytes. Maximum 8 bytes. #[inline] + #[must_use] pub fn imm1_length(&self) -> usize { self.inner.Imm1Length() as usize } /// Second immediate length, in bytes. Maximum 8 bytes. #[inline] + #[must_use] pub fn imm2_length(&self) -> usize { self.inner.Imm2Length() as usize } - /// Third immediate length, in bytes. Maximum 8 bytes. - #[inline] - pub fn imm3_length(&self) -> usize { - self.inner.Imm3Length() as usize - } - /// Relative offset length, in bytes. Maximum 4 bytes. #[inline] + #[must_use] pub fn rel_offs_length(&self) -> usize { self.inner.RelOffsLength() as usize } /// The offset of the first opcode, inside the instruction. #[inline] + #[must_use] pub fn op_offset(&self) -> usize { self.inner.OpOffset() as usize } /// The offset of the nominal opcode, inside the instruction. #[inline] + #[must_use] pub fn main_op_offset(&self) -> usize { self.inner.MainOpOffset() as usize } - #[inline] /// The offset of the displacement, inside the instruction. + #[inline] + #[must_use] pub fn disp_offset(&self) -> Option { let value = self.inner.DispOffset() as usize; if value == 0 { @@ -980,8 +970,9 @@ impl DecodedInstruction { } } - #[inline] /// The offset of the hard-coded address. + #[inline] + #[must_use] pub fn addr_offset(&self) -> Option { let value = self.inner.AddrOffset() as usize; if value == 0 { @@ -993,6 +984,7 @@ impl DecodedInstruction { /// The offset of the absolute address, inside the instruction. #[inline] + #[must_use] pub fn moffset_offset(&self) -> Option { let value = self.inner.MoffsetOffset() as usize; if value == 0 { @@ -1004,6 +996,7 @@ impl DecodedInstruction { /// The offset of the immediate, inside the instruction. #[inline] + #[must_use] pub fn imm1_offset(&self) -> Option { let value = self.inner.Imm1Offset() as usize; if value == 0 { @@ -1015,6 +1008,7 @@ impl DecodedInstruction { /// The offset of the second immediate, if any, inside the instruction. #[inline] + #[must_use] pub fn imm2_offset(&self) -> Option { let value = self.inner.Imm2Offset() as usize; if value == 0 { @@ -1024,19 +1018,9 @@ impl DecodedInstruction { } } - /// The offset of the third immediate, if any, inside the instruction. - #[inline] - pub fn imm3_offset(&self) -> Option { - let value = self.inner.Imm3Offset() as usize; - if value == 0 { - None - } else { - Some(value) - } - } - /// The offset of the relative offset used in instruction. #[inline] + #[must_use] pub fn rel_offs_offset(&self) -> Option { let value = self.inner.RelOffsOffset() as usize; if value == 0 { @@ -1048,6 +1032,7 @@ impl DecodedInstruction { /// The offset of the SSE immediate, if any, inside the instruction. #[inline] + #[must_use] pub fn sse_imm_offset(&self) -> Option { let value = self.inner.SseImmOffset() as usize; if value == 0 { @@ -1059,6 +1044,7 @@ impl DecodedInstruction { /// The offset of the mod rm byte inside the instruction, if any. #[inline] + #[must_use] pub fn mod_rm_offset(&self) -> Option { let value = self.inner.ModRmOffset() as usize; if value == 0 { @@ -1070,12 +1056,14 @@ impl DecodedInstruction { /// Number of words accessed on/from the stack. #[inline] + #[must_use] pub fn stack_words(&self) -> usize { - self.inner.StackWords as usize + self.inner.StackWords() as usize } /// The last rep/repz/repnz prefix. if any. #[inline] + #[must_use] pub fn rep(&self) -> Option { let value = self.inner.Rep; if value == 0 { @@ -1087,6 +1075,7 @@ impl DecodedInstruction { /// The last segment override prefix. if none. `FS`/`GS` if 64 bit. #[inline] + #[must_use] pub fn seg(&self) -> Option { let value = self.inner.Seg; if value == 0 { @@ -1096,24 +1085,9 @@ impl DecodedInstruction { } } - /// The last segment override indicating a branch hint. - #[inline] - pub fn bhint(&self) -> u8 { - self.inner.Bhint - } - - /// Get the REX prefix. - #[inline] - pub fn rex(&self) -> Option { - if self.has_rex() { - Some(unsafe { self.inner.Rex.Rex }) - } else { - None - } - } - /// Get the `ModRM` byte. #[inline] + #[must_use] pub fn mod_rm(&self) -> Option { if self.has_mod_rm() { Some(unsafe { self.inner.ModRm.ModRm }) @@ -1124,6 +1098,7 @@ impl DecodedInstruction { /// Get the `SIB` byte. #[inline] + #[must_use] pub fn sib(&self) -> Option { if self.has_sib() { Some(unsafe { self.inner.Sib.Sib }) @@ -1134,6 +1109,7 @@ impl DecodedInstruction { /// Get the 2-bytes `VEX` prefix. #[inline] + #[must_use] pub fn vex2(&self) -> Option<(u8, u8)> { if matches!(self.vex_mode(), Some(VexMode::Vex2b)) { let vex2 = self.inner.__bindgen_anon_1; @@ -1147,6 +1123,7 @@ impl DecodedInstruction { /// Get the 3-bytes `VEX` prefix. #[inline] + #[must_use] pub fn vex3(&self) -> Option<(u8, u8, u8)> { if matches!(self.vex_mode(), Some(VexMode::Vex3b)) { let vex3 = self.inner.__bindgen_anon_1; @@ -1160,6 +1137,7 @@ impl DecodedInstruction { /// Get the `XOP` bytes. #[inline] + #[must_use] pub fn xop(&self) -> Option<(u8, u8, u8)> { if self.has_xop() { let xop = self.inner.__bindgen_anon_1; @@ -1173,6 +1151,7 @@ impl DecodedInstruction { /// Get the `EVEX` bytes. #[inline] + #[must_use] pub fn evex(&self) -> Option<(u8, u8, u8, u8)> { if self.has_evex() { let evex = self.inner.__bindgen_anon_1; @@ -1184,24 +1163,12 @@ impl DecodedInstruction { } } - /// Get the `segment:offset` address accessed by the instruction, if any. - #[inline] - pub fn address(&self) -> Option { - if self.has_addr() { - let raw = self.inner.Address; - let raw = unsafe { raw.__bindgen_anon_1 }; - - Some(OpAddr::new(raw.Cs, u64::from(raw.Ip))) - } else { - None - } - } - /// Get the absolute offset, if any. #[inline] + #[must_use] pub fn moffset(&self) -> Option { if self.has_moffset() { - Some(self.inner.Moffset) + Some(unsafe { self.inner.__bindgen_anon_2.Moffset }) } else { None } @@ -1209,9 +1176,10 @@ impl DecodedInstruction { /// Get the displacement. Max 4 bytes. Used in `ModRM` instructions. #[inline] + #[must_use] pub fn disp(&self) -> Option { if self.has_disp() { - Some(self.inner.Displacement) + Some(unsafe { self.inner.__bindgen_anon_2.Displacement }) } else { None } @@ -1219,9 +1187,10 @@ impl DecodedInstruction { /// Get the relative offset, used for branches. Max 4 bytes. #[inline] + #[must_use] pub fn rel_offset(&self) -> Option { if self.has_rel_offs() { - Some(self.inner.RelativeOffset) + Some(unsafe { self.inner.__bindgen_anon_2.RelativeOffset }) } else { None } @@ -1229,6 +1198,7 @@ impl DecodedInstruction { /// Get the first immediate. #[inline] + #[must_use] pub fn immediate1(&self) -> Option { if self.has_imm1() { Some(self.inner.Immediate1) @@ -1237,21 +1207,12 @@ impl DecodedInstruction { } } - /// Get the second immediate. Used mainly for [`Mnemonic::ENTER`](Mnemonic::ENTER). + /// Get the second immediate. Used mainly for [`Mnemonic::ENTER`]. #[inline] + #[must_use] pub fn immediate2(&self) -> Option { if self.has_imm2() { - Some(self.inner.Immediate2) - } else { - None - } - } - - /// Get the third additional immediate. - #[inline] - pub fn immediate3(&self) -> Option { - if self.has_imm3() { - Some(self.inner.Immediate3) + Some(unsafe { self.inner.__bindgen_anon_3.Immediate2 }) } else { None } @@ -1259,19 +1220,10 @@ impl DecodedInstruction { /// Get the SSE immediate. It is used to select a register. #[inline] + #[must_use] pub fn sse_immediate(&self) -> Option { if self.has_sse_imm() { - Some(self.inner.SseImmediate) - } else { - None - } - } - - /// Get the `SSE` condition byte. - #[inline] - pub fn sse_cond(&self) -> Option { - if (self.inner.Attributes & ffi::ND_FLAG_SSE_CONDB) != 0 { - Some(self.inner.SseCondition) + Some(unsafe { self.inner.__bindgen_anon_3.SseImmediate }) } else { None } @@ -1279,9 +1231,10 @@ impl DecodedInstruction { /// Get the condition byte. #[inline] + #[must_use] pub fn cond(&self) -> Option { - if (self.inner.Attributes & ffi::ND_FLAG_COND) != 0 { - Some(self.inner.Condition) + if (self.inner.Attributes & ffi::ND_FLAG_COND as u64) != 0 { + Some(self.inner.__bindgen_anon_4.Condition()) } else { None } @@ -1291,26 +1244,30 @@ impl DecodedInstruction { /// /// The opcode is the last byte. #[inline] + #[must_use] pub fn is_3d_now(&self) -> bool { - (self.inner.Attributes & ffi::ND_FLAG_3DNOW) != 0 + (self.inner.Attributes & ffi::ND_FLAG_3DNOW as u64) != 0 } /// Get the number of operands. #[inline] + #[must_use] pub fn operands_count(&self) -> usize { - self.inner.OperandsCount as usize + self.inner.OperandsCount() as usize } /// Number of explicit operands. /// /// Use this if you want to ignore implicit operands such as stack, flags, etc. #[inline] + #[must_use] pub fn exp_operands_count(&self) -> usize { - self.inner.ExpOperandsCount as usize + self.inner.ExpOperandsCount() as usize } /// Get the `CS` access mode. #[inline] + #[must_use] pub fn cs_access(&self) -> OpAccess { OpAccess::from_raw(ffi::ND_OPERAND_ACCESS { Access: self.inner.CsAccess, @@ -1319,6 +1276,7 @@ impl DecodedInstruction { /// Get the `RIP` access mode. #[inline] + #[must_use] pub fn rip_access(&self) -> OpAccess { OpAccess::from_raw(ffi::ND_OPERAND_ACCESS { Access: self.inner.RipAccess, @@ -1327,6 +1285,7 @@ impl DecodedInstruction { /// Get the stack access mode. #[inline] + #[must_use] pub fn stack_access(&self) -> OpAccess { OpAccess::from_raw(ffi::ND_OPERAND_ACCESS { Access: self.inner.StackAccess, @@ -1337,6 +1296,7 @@ impl DecodedInstruction { /// /// This includes the stack or shadow stack access. #[inline] + #[must_use] pub fn memory_access(&self) -> OpAccess { OpAccess::from_raw(ffi::ND_OPERAND_ACCESS { Access: self.inner.MemoryAccess, @@ -1345,34 +1305,39 @@ impl DecodedInstruction { /// `true` if the instruction is a branch. #[inline] + #[must_use] pub fn is_branch(&self) -> bool { self.inner.BranchInfo.IsBranch() != 0 } /// `true` if the instruction is a conditional branch. #[inline] + #[must_use] pub fn is_conditional_branch(&self) -> bool { self.inner.BranchInfo.IsConditional() != 0 } /// `true` if the instruction is a indirect branch. #[inline] + #[must_use] pub fn is_indirect_branch(&self) -> bool { self.inner.BranchInfo.IsIndirect() != 0 } /// `true` if the instruction is a far branch. #[inline] + #[must_use] pub fn is_far_branch(&self) -> bool { self.inner.BranchInfo.IsFar() != 0 } /// Get the rflags access. + #[must_use] pub fn flags_access(&self) -> FlagsAccess { let facc = self.inner.FlagsAccess; let mode = OpAccess::from_raw(ffi::ND_OPERAND_ACCESS { - Access: facc.RegAccess, + Access: self.inner.RflAccess, }); FlagsAccess { @@ -1391,26 +1356,18 @@ impl DecodedInstruction { /// /// This function will panic if the access mode is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn fpu_flags_access(&self) -> FpuFlags { FpuFlags::from_raw(self.inner.FpuFlagsAccess).unwrap() } - /// The exception class. - /// - /// # Panics - /// - /// This function will panic if the exception class is unrecognized. This can not happen under normal circumstances. - #[inline] - pub fn exception_class(&self) -> ExceptionClass { - ExceptionClass::from_raw(self.inner.ExceptionClass).unwrap() - } - /// `EVEX` tuple type. /// /// # Panics /// /// This function will panic if the EVEX tuple type is unrecognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn evex_tuple(&self) -> Option { if self.has_evex() { Some(Tuple::from_raw(u32::from(self.inner.TupleType)).unwrap()) @@ -1426,9 +1383,10 @@ impl DecodedInstruction { /// This function will panic if the EVEX rounding mode is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn evex_rounding(&self) -> Option { if self.has_er() { - Some(EvexRounding::from_raw(self.inner.RoundingMode).unwrap()) + Some(EvexRounding::from_raw(self.inner.RoundingMode()).unwrap()) } else { None } @@ -1440,6 +1398,7 @@ impl DecodedInstruction { /// /// This function will panic if the cateogory not recognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn category(&self) -> Category { Category::try_from(self.inner.Category).unwrap() } @@ -1450,6 +1409,7 @@ impl DecodedInstruction { /// /// This function will panic if the ISA set not recognized. This can not happen under normal circumstances. #[inline] + #[must_use] pub fn isa_set(&self) -> IsaSet { IsaSet::try_from(self.inner.IsaSet).unwrap() } @@ -1460,44 +1420,51 @@ impl DecodedInstruction { /// /// See [`cpu_modes`](crate::cpu_modes) for examples. #[inline] + #[must_use] pub fn valid_cpu_modes(&self) -> CpuModes { CpuModes::from_raw(self.inner.ValidModes) } /// Get the valid prefixes for this instruction. #[inline] + #[must_use] pub fn valid_prefixes(&self) -> ValidPrefixes { ValidPrefixes::from_raw(self.inner.ValidPrefixes) } /// Get the decorators accepted by the instruction. #[inline] + #[must_use] pub fn valid_decorators(&self) -> ValidDecorators { ValidDecorators::from_raw(self.inner.ValidDecorators) } /// Get the main/nominal opcode. #[inline] + #[must_use] pub fn primary_op_code(&self) -> u8 { - self.inner.PrimaryOpCode + unsafe { self.inner.__bindgen_anon_4.PrimaryOpCode } } /// `true` if the instruction is a SIMD instruction that operates on vector regs. #[inline] + #[must_use] pub fn has_vector(&self) -> bool { - self.inner.Attributes & ffi::ND_FLAG_VECTOR != 0 + self.inner.Attributes & ffi::ND_FLAG_VECTOR as u64 != 0 } } impl<'a> DecodedInstruction { /// Get the instruction bytes. #[inline] + #[must_use] pub fn bytes(&'a self) -> &'a [u8] { &self.inner.InstructionBytes[..self.inner.Length as usize] } /// Get the opcode bytes (escape codes and main op code). #[inline] + #[must_use] pub fn op_code_bytes(&'a self) -> &'a [u8] { &self.inner.OpCodeBytes[..self.op_length()] } @@ -1510,12 +1477,14 @@ impl<'a> DecodedInstruction { /// /// # Examples /// - /// See [`OperandsLookup`](OperandsLookup) for examples. + /// See [`OperandsLookup`] for examples. /// /// # Panics /// /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. + #[inline] + #[must_use] pub fn operand_lookup(&'a self) -> OperandsLookup { OperandsLookup::from_raw(&self.inner) } @@ -1586,7 +1555,6 @@ mod tests { // implementations at every build, but these tests should be enough to catch the unlikely situation in which // a new constant is added. let bindings = include_str!("../../bddisasm-sys/csrc/inc/bddisasm.h"); - let mut exc_count: u8 = 0; let mut shadow_stack_count: u8 = 0; let mut tuple_count: u32 = 0; let mut evex_rounding: u8 = 0; @@ -1601,9 +1569,6 @@ mod tests { assert!(OperandSize::from_raw(get_tokens(line, 2)).is_ok()); } else if line.starts_with("#define ND_VECM_") { assert!(VectorSize::from_raw(get_tokens(line, 2)).is_ok()); - } else if line.starts_with(" ND_EXC_") { - assert!(ExceptionClass::from_raw(exc_count).is_ok()); - exc_count += 1; } else if line.starts_with("#define ND_SIZE_") && !line.starts_with("#define ND_SIZE_TO_MASK(sz)") { @@ -1633,14 +1598,11 @@ mod tests { evex_rounding += 1; } } - - // There is no `ND_SIZE_*` macro for 0, but the size 0 is valid, so test it here. - assert_eq!(operand::OpSize::from_raw(0), Ok(operand::OpSize::Bytes(0))); } #[test] fn status() { - let status = include_str!("../../bddisasm-sys/csrc/inc/disasmstatus.h"); + let status = include_str!("../../bddisasm-sys/csrc/inc/bddisasm_status.h"); for line in status.lines() { if line.starts_with("#define ND_STATUS_SUCCESS") || line.starts_with("#define ND_STATUS_HINT_OPERAND_NOT_USED") @@ -1652,20 +1614,6 @@ mod tests { } } - #[test] - fn check_all_exception_classes() { - // This is a really contrieved way of making sure that we check all variants of `ffi::_ND_EX_CLASS`. If a new - // one is added, this will fail to build. We do this because `ExceptionClass::from_raw` takes an `u8`. - // NOTE: When a new variant is added, `ExceptionClass::from_raw` must be updated. - match ffi::_ND_EX_CLASS::ND_EXC_None { - ffi::_ND_EX_CLASS::ND_EXC_None => {} - ffi::_ND_EX_CLASS::ND_EXC_SSE_AVX => {} - ffi::_ND_EX_CLASS::ND_EXC_EVEX => {} - ffi::_ND_EX_CLASS::ND_EXC_OPMASK => {} - ffi::_ND_EX_CLASS::ND_EXC_AMX => {} - } - } - #[test] fn check_all_evex_roundings() { // This is a really contrieved way of making sure that we check all variants of `ffi::_ND_ROUNDING`. If a new diff --git a/bindings/rsbddisasm/bddisasm/src/decoder.rs b/bindings/rsbddisasm/bddisasm/src/decoder.rs index eeaf994..fefe531 100644 --- a/bindings/rsbddisasm/bddisasm/src/decoder.rs +++ b/bindings/rsbddisasm/bddisasm/src/decoder.rs @@ -20,10 +20,11 @@ impl<'a> Decoder<'a> { /// /// # Arguments /// - /// * `code` - An [u8](u8) slice that holds the code to be decoded. + /// * `code` - An [`u8`] slice that holds the code to be decoded. /// * `mode` - The mode in which to decode the instruction. /// * `ip` - The instruction pointer value to use when formatting the decoded instruction. Does not affect the /// decoding process in any way. + #[must_use] pub fn new(code: &'a [u8], mode: DecodeMode, ip: u64) -> Self { Self { code, @@ -82,15 +83,12 @@ impl<'a> Decoder<'a> { } else { let result = DecodedInstruction::decode_with_ip(&self.code[self.offset..], self.mode, self.ip); - match result { - Ok(ins) => { - self.offset += ins.length() as usize; - self.ip += ins.length() as u64; - } - Err(_) => { - self.offset += 1; - self.ip += 1; - } + if let Ok(ins) = result { + self.offset += ins.length(); + self.ip += ins.length() as u64; + } else { + self.offset += 1; + self.ip += 1; }; Some(result) @@ -99,7 +97,7 @@ impl<'a> Decoder<'a> { /// Attempts to decode the next instruction from the given code chunk. /// - /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`](DecodeResult) it + /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`] it /// will also return the offset from which decoding was attempted, as well as the corresponding instruction pointer. /// /// # Examples @@ -134,7 +132,7 @@ impl<'a> Decoder<'a> { /// Attempts to decode the next instruction from the given code chunk. /// - /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`](DecodeResult) it + /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`] it /// will also return the offset from which decoding was attempted. /// /// # Examples @@ -168,7 +166,7 @@ impl<'a> Decoder<'a> { /// Attempts to decode the next instruction from the given code chunk. /// - /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`](DecodeResult) it + /// Behaves like [`decode_next`](Decoder::decode_next), but in addition to the [`DecodeResult`] it /// will also return the corresponding instruction pointer. /// /// # Examples diff --git a/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs b/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs index 564b25d..f0f24ef 100644 --- a/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs +++ b/bindings/rsbddisasm/bddisasm/src/fpu_flags.rs @@ -4,6 +4,8 @@ */ //! Offers information about how an instructions accesses the FPU status registers. +#![allow(clippy::module_name_repetitions)] + use super::decode_error::DecodeError; /// The mode in which a FPU status flag is accessed. diff --git a/bindings/rsbddisasm/bddisasm/src/instruction_category.rs b/bindings/rsbddisasm/bddisasm/src/instruction_category.rs index d477105..03672e1 100644 --- a/bindings/rsbddisasm/bddisasm/src/instruction_category.rs +++ b/bindings/rsbddisasm/bddisasm/src/instruction_category.rs @@ -15,6 +15,7 @@ pub enum Category { AES, AESKL, AMX, + APX, ARITH, AVX, AVX2, @@ -72,7 +73,6 @@ pub enum Category { MOVDIRI, MPX, NOP, - PADLOCK, PCLMULQDQ, PCONFIG, POP, @@ -108,6 +108,7 @@ pub enum Category { UINTR, UNCOND_BR, UNKNOWN, + USER_MSR, VAES, VFMA, VFMAPS, @@ -129,6 +130,7 @@ pub enum Category { impl TryFrom for Category { type Error = DecodeError; + #[allow(clippy::too_many_lines)] fn try_from(value: ffi::ND_INS_CATEGORY) -> Result { match value { ffi::_ND_INS_TYPE::ND_CAT_INVALID => Err(DecodeError::InternalError(value as u64)), @@ -136,6 +138,7 @@ impl TryFrom for Category { ffi::_ND_INS_TYPE::ND_CAT_AES => Ok(Category::AES), ffi::_ND_INS_TYPE::ND_CAT_AESKL => Ok(Category::AESKL), ffi::_ND_INS_TYPE::ND_CAT_AMX => Ok(Category::AMX), + ffi::_ND_INS_TYPE::ND_CAT_APX => Ok(Category::APX), ffi::_ND_INS_TYPE::ND_CAT_ARITH => Ok(Category::ARITH), ffi::_ND_INS_TYPE::ND_CAT_AVX => Ok(Category::AVX), ffi::_ND_INS_TYPE::ND_CAT_AVX2 => Ok(Category::AVX2), @@ -193,7 +196,6 @@ impl TryFrom for Category { ffi::_ND_INS_TYPE::ND_CAT_MOVDIRI => Ok(Category::MOVDIRI), ffi::_ND_INS_TYPE::ND_CAT_MPX => Ok(Category::MPX), ffi::_ND_INS_TYPE::ND_CAT_NOP => Ok(Category::NOP), - ffi::_ND_INS_TYPE::ND_CAT_PADLOCK => Ok(Category::PADLOCK), ffi::_ND_INS_TYPE::ND_CAT_PCLMULQDQ => Ok(Category::PCLMULQDQ), ffi::_ND_INS_TYPE::ND_CAT_PCONFIG => Ok(Category::PCONFIG), ffi::_ND_INS_TYPE::ND_CAT_POP => Ok(Category::POP), @@ -229,6 +231,7 @@ impl TryFrom for Category { ffi::_ND_INS_TYPE::ND_CAT_UINTR => Ok(Category::UINTR), ffi::_ND_INS_TYPE::ND_CAT_UNCOND_BR => Ok(Category::UNCOND_BR), ffi::_ND_INS_TYPE::ND_CAT_UNKNOWN => Ok(Category::UNKNOWN), + ffi::_ND_INS_TYPE::ND_CAT_USER_MSR => Ok(Category::USER_MSR), ffi::_ND_INS_TYPE::ND_CAT_VAES => Ok(Category::VAES), ffi::_ND_INS_TYPE::ND_CAT_VFMA => Ok(Category::VFMA), ffi::_ND_INS_TYPE::ND_CAT_VFMAPS => Ok(Category::VFMAPS), diff --git a/bindings/rsbddisasm/bddisasm/src/isa_set.rs b/bindings/rsbddisasm/bddisasm/src/isa_set.rs index f836cd2..a5abcea 100644 --- a/bindings/rsbddisasm/bddisasm/src/isa_set.rs +++ b/bindings/rsbddisasm/bddisasm/src/isa_set.rs @@ -20,6 +20,7 @@ pub enum IsaSet { AMXFP16, AMXINT8, AMXTILE, + APX_F, AVX, AVX2, AVX2GATHER, @@ -56,8 +57,6 @@ pub enum IsaSet { CLZERO, CMPCCXADD, CMPXCHG16B, - CYRIX, - CYRIX_SMM, ENQCMD, F16C, FMA, @@ -132,6 +131,7 @@ pub enum IsaSet { UD, UINTR, UNKNOWN, + USER_MSR, VAES, VPCLMULQDQ, VTX, @@ -149,6 +149,7 @@ pub enum IsaSet { impl TryFrom for IsaSet { type Error = DecodeError; + #[allow(clippy::too_many_lines)] fn try_from(value: ffi::ND_INS_SET) -> Result { match value { ffi::_ND_INS_SET::ND_SET_INVALID => Err(DecodeError::InternalError(value as u64)), @@ -161,6 +162,7 @@ impl TryFrom for IsaSet { ffi::_ND_INS_SET::ND_SET_AMXFP16 => Ok(IsaSet::AMXFP16), ffi::_ND_INS_SET::ND_SET_AMXINT8 => Ok(IsaSet::AMXINT8), ffi::_ND_INS_SET::ND_SET_AMXTILE => Ok(IsaSet::AMXTILE), + ffi::_ND_INS_SET::ND_SET_APX_F => Ok(IsaSet::APX_F), ffi::_ND_INS_SET::ND_SET_AVX => Ok(IsaSet::AVX), ffi::_ND_INS_SET::ND_SET_AVX2 => Ok(IsaSet::AVX2), ffi::_ND_INS_SET::ND_SET_AVX2GATHER => Ok(IsaSet::AVX2GATHER), @@ -197,8 +199,6 @@ impl TryFrom for IsaSet { ffi::_ND_INS_SET::ND_SET_CLZERO => Ok(IsaSet::CLZERO), ffi::_ND_INS_SET::ND_SET_CMPCCXADD => Ok(IsaSet::CMPCCXADD), ffi::_ND_INS_SET::ND_SET_CMPXCHG16B => Ok(IsaSet::CMPXCHG16B), - ffi::_ND_INS_SET::ND_SET_CYRIX => Ok(IsaSet::CYRIX), - ffi::_ND_INS_SET::ND_SET_CYRIX_SMM => Ok(IsaSet::CYRIX_SMM), ffi::_ND_INS_SET::ND_SET_ENQCMD => Ok(IsaSet::ENQCMD), ffi::_ND_INS_SET::ND_SET_F16C => Ok(IsaSet::F16C), ffi::_ND_INS_SET::ND_SET_FMA => Ok(IsaSet::FMA), @@ -273,6 +273,7 @@ impl TryFrom for IsaSet { ffi::_ND_INS_SET::ND_SET_UD => Ok(IsaSet::UD), ffi::_ND_INS_SET::ND_SET_UINTR => Ok(IsaSet::UINTR), ffi::_ND_INS_SET::ND_SET_UNKNOWN => Ok(IsaSet::UNKNOWN), + ffi::_ND_INS_SET::ND_SET_USER_MSR => Ok(IsaSet::USER_MSR), ffi::_ND_INS_SET::ND_SET_VAES => Ok(IsaSet::VAES), ffi::_ND_INS_SET::ND_SET_VPCLMULQDQ => Ok(IsaSet::VPCLMULQDQ), ffi::_ND_INS_SET::ND_SET_VTX => Ok(IsaSet::VTX), diff --git a/bindings/rsbddisasm/bddisasm/src/lib.rs b/bindings/rsbddisasm/bddisasm/src/lib.rs index 6aba95d..be0793a 100644 --- a/bindings/rsbddisasm/bddisasm/src/lib.rs +++ b/bindings/rsbddisasm/bddisasm/src/lib.rs @@ -22,7 +22,7 @@ //! //! ```toml //! [dependencies] -//! bddisasm = "0.1.0" +//! bddisasm = "0.2" //! ``` //! //! # Examples @@ -47,7 +47,7 @@ //! //! ## Decoding multiple instructions //! -//! Use [`Decoder`](crate::decoder::Decoder) to decode multiple instructions from a chunk of code. +//! Use [`Decoder`] to decode multiple instructions from a chunk of code. //! //! ``` //! use bddisasm::{Decoder, DecodeMode}; @@ -120,7 +120,7 @@ //! //! ## Working with instruction operands //! -//! Instruction operands can be analyzed using the [operand](crate::operand) module. Rich informaion is offered for +//! Instruction operands can be analyzed using the [`operand`] module. Rich informaion is offered for //! each type of operand. Bellow is a minimal example that looks at a memory operand. //! //! ``` @@ -190,6 +190,7 @@ //! #![cfg_attr(all(not(test), not(feature = "std")), no_std)] +#![allow(clippy::if_not_else)] pub extern crate bddisasm_sys as ffi; diff --git a/bindings/rsbddisasm/bddisasm/src/mnemonic.rs b/bindings/rsbddisasm/bddisasm/src/mnemonic.rs index 0ca6569..1f5e157 100644 --- a/bindings/rsbddisasm/bddisasm/src/mnemonic.rs +++ b/bindings/rsbddisasm/bddisasm/src/mnemonic.rs @@ -41,7 +41,6 @@ pub enum Mnemonic { AESENCWIDE256KL, AESIMC, AESKEYGENASSIST, - ALTINST, AND, ANDN, ANDNPD, @@ -87,8 +86,10 @@ pub enum Mnemonic { CALLNI, CALLNR, CBW, + CCMP, CDQ, CDQE, + CFCMOV, CLAC, CLC, CLD, @@ -134,10 +135,9 @@ pub enum Mnemonic { COMISD, COMISS, CPUID, - CPU_READ, - CPU_WRITE, CQO, CRC32, + CTEST, CVTDQ2PD, CVTDQ2PS, CVTPD2DQ, @@ -171,7 +171,6 @@ pub enum Mnemonic { DIVPS, DIVSD, DIVSS, - DMINT, DPPD, DPPS, EMMS, @@ -315,6 +314,7 @@ pub enum Mnemonic { INVPCID, INVVPID, IRET, + JMPABS, JMPE, JMPFD, JMPFI, @@ -382,7 +382,6 @@ pub enum Mnemonic { MINSS, MONITOR, MONITORX, - MONTMUL, MOV, MOVAPD, MOVAPS, @@ -557,10 +556,13 @@ pub enum Mnemonic { PMULLW, PMULUDQ, POP, + POP2, + POP2P, POPA, POPAD, POPCNT, POPF, + POPP, POR, PREFETCH, PREFETCHE, @@ -613,9 +615,12 @@ pub enum Mnemonic { PUNPCKLQDQ, PUNPCKLWD, PUSH, + PUSH2, + PUSH2P, PUSHA, PUSHAD, PUSHF, + PUSHP, PVALIDATE, PXOR, RCL, @@ -632,7 +637,6 @@ pub enum Mnemonic { RDPRU, RDRAND, RDSEED, - RDSHR, RDTSC, RDTSCP, RETF, @@ -647,14 +651,11 @@ pub enum Mnemonic { ROUNDPS, ROUNDSD, ROUNDSS, - RSDC, - RSLDT, RSM, RSQRTPS, RSQRTSS, RSSSP, RSTORSSP, - RSTS, SAHF, SAL, SALC, @@ -691,7 +692,6 @@ pub enum Mnemonic { SKINIT, SLDT, SLWPCB, - SMINT, SMSW, SPFLT, SQRTPD, @@ -713,9 +713,6 @@ pub enum Mnemonic { SUBPS, SUBSD, SUBSS, - SVDC, - SVLDT, - SVTS, SWAPGS, SYSCALL, SYSENTER, @@ -754,6 +751,8 @@ pub enum Mnemonic { UNPCKHPS, UNPCKLPD, UNPCKLPS, + URDMSR, + UWRMSR, V4FMADDPS, V4FMADDSS, V4FNMADDPS, @@ -1621,18 +1620,12 @@ pub enum Mnemonic { WRMSRLIST, WRMSRNS, WRPKRU, - WRSHR, WRSS, WRUSS, XABORT, XADD, XBEGIN, XCHG, - XCRYPTCBC, - XCRYPTCFB, - XCRYPTCTR, - XCRYPTECB, - XCRYPTOFB, XEND, XGETBV, XLATB, @@ -1647,9 +1640,6 @@ pub enum Mnemonic { XSAVEOPT, XSAVES, XSETBV, - XSHA1, - XSHA256, - XSTORE, XSUSLDTRK, XTEST, } @@ -1658,6 +1648,7 @@ pub enum Mnemonic { impl TryFrom for Mnemonic { type Error = DecodeError; + #[allow(clippy::too_many_lines)] fn try_from(value: ffi::ND_INS_CLASS) -> Result { match value { ffi::_ND_INS_CLASS::ND_INS_INVALID => Err(DecodeError::InternalError(value as u64)), @@ -1691,7 +1682,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_AESENCWIDE256KL => Ok(Mnemonic::AESENCWIDE256KL), ffi::_ND_INS_CLASS::ND_INS_AESIMC => Ok(Mnemonic::AESIMC), ffi::_ND_INS_CLASS::ND_INS_AESKEYGENASSIST => Ok(Mnemonic::AESKEYGENASSIST), - ffi::_ND_INS_CLASS::ND_INS_ALTINST => Ok(Mnemonic::ALTINST), ffi::_ND_INS_CLASS::ND_INS_AND => Ok(Mnemonic::AND), ffi::_ND_INS_CLASS::ND_INS_ANDN => Ok(Mnemonic::ANDN), ffi::_ND_INS_CLASS::ND_INS_ANDNPD => Ok(Mnemonic::ANDNPD), @@ -1737,8 +1727,10 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_CALLNI => Ok(Mnemonic::CALLNI), ffi::_ND_INS_CLASS::ND_INS_CALLNR => Ok(Mnemonic::CALLNR), ffi::_ND_INS_CLASS::ND_INS_CBW => Ok(Mnemonic::CBW), + ffi::_ND_INS_CLASS::ND_INS_CCMP => Ok(Mnemonic::CCMP), ffi::_ND_INS_CLASS::ND_INS_CDQ => Ok(Mnemonic::CDQ), ffi::_ND_INS_CLASS::ND_INS_CDQE => Ok(Mnemonic::CDQE), + ffi::_ND_INS_CLASS::ND_INS_CFCMOV => Ok(Mnemonic::CFCMOV), ffi::_ND_INS_CLASS::ND_INS_CLAC => Ok(Mnemonic::CLAC), ffi::_ND_INS_CLASS::ND_INS_CLC => Ok(Mnemonic::CLC), ffi::_ND_INS_CLASS::ND_INS_CLD => Ok(Mnemonic::CLD), @@ -1784,10 +1776,9 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_COMISD => Ok(Mnemonic::COMISD), ffi::_ND_INS_CLASS::ND_INS_COMISS => Ok(Mnemonic::COMISS), ffi::_ND_INS_CLASS::ND_INS_CPUID => Ok(Mnemonic::CPUID), - ffi::_ND_INS_CLASS::ND_INS_CPU_READ => Ok(Mnemonic::CPU_READ), - ffi::_ND_INS_CLASS::ND_INS_CPU_WRITE => Ok(Mnemonic::CPU_WRITE), ffi::_ND_INS_CLASS::ND_INS_CQO => Ok(Mnemonic::CQO), ffi::_ND_INS_CLASS::ND_INS_CRC32 => Ok(Mnemonic::CRC32), + ffi::_ND_INS_CLASS::ND_INS_CTEST => Ok(Mnemonic::CTEST), ffi::_ND_INS_CLASS::ND_INS_CVTDQ2PD => Ok(Mnemonic::CVTDQ2PD), ffi::_ND_INS_CLASS::ND_INS_CVTDQ2PS => Ok(Mnemonic::CVTDQ2PS), ffi::_ND_INS_CLASS::ND_INS_CVTPD2DQ => Ok(Mnemonic::CVTPD2DQ), @@ -1821,7 +1812,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_DIVPS => Ok(Mnemonic::DIVPS), ffi::_ND_INS_CLASS::ND_INS_DIVSD => Ok(Mnemonic::DIVSD), ffi::_ND_INS_CLASS::ND_INS_DIVSS => Ok(Mnemonic::DIVSS), - ffi::_ND_INS_CLASS::ND_INS_DMINT => Ok(Mnemonic::DMINT), ffi::_ND_INS_CLASS::ND_INS_DPPD => Ok(Mnemonic::DPPD), ffi::_ND_INS_CLASS::ND_INS_DPPS => Ok(Mnemonic::DPPS), ffi::_ND_INS_CLASS::ND_INS_EMMS => Ok(Mnemonic::EMMS), @@ -1965,6 +1955,7 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_INVPCID => Ok(Mnemonic::INVPCID), ffi::_ND_INS_CLASS::ND_INS_INVVPID => Ok(Mnemonic::INVVPID), ffi::_ND_INS_CLASS::ND_INS_IRET => Ok(Mnemonic::IRET), + ffi::_ND_INS_CLASS::ND_INS_JMPABS => Ok(Mnemonic::JMPABS), ffi::_ND_INS_CLASS::ND_INS_JMPE => Ok(Mnemonic::JMPE), ffi::_ND_INS_CLASS::ND_INS_JMPFD => Ok(Mnemonic::JMPFD), ffi::_ND_INS_CLASS::ND_INS_JMPFI => Ok(Mnemonic::JMPFI), @@ -2032,7 +2023,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_MINSS => Ok(Mnemonic::MINSS), ffi::_ND_INS_CLASS::ND_INS_MONITOR => Ok(Mnemonic::MONITOR), ffi::_ND_INS_CLASS::ND_INS_MONITORX => Ok(Mnemonic::MONITORX), - ffi::_ND_INS_CLASS::ND_INS_MONTMUL => Ok(Mnemonic::MONTMUL), ffi::_ND_INS_CLASS::ND_INS_MOV => Ok(Mnemonic::MOV), ffi::_ND_INS_CLASS::ND_INS_MOVAPD => Ok(Mnemonic::MOVAPD), ffi::_ND_INS_CLASS::ND_INS_MOVAPS => Ok(Mnemonic::MOVAPS), @@ -2207,10 +2197,13 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_PMULLW => Ok(Mnemonic::PMULLW), ffi::_ND_INS_CLASS::ND_INS_PMULUDQ => Ok(Mnemonic::PMULUDQ), ffi::_ND_INS_CLASS::ND_INS_POP => Ok(Mnemonic::POP), + ffi::_ND_INS_CLASS::ND_INS_POP2 => Ok(Mnemonic::POP2), + ffi::_ND_INS_CLASS::ND_INS_POP2P => Ok(Mnemonic::POP2P), ffi::_ND_INS_CLASS::ND_INS_POPA => Ok(Mnemonic::POPA), ffi::_ND_INS_CLASS::ND_INS_POPAD => Ok(Mnemonic::POPAD), ffi::_ND_INS_CLASS::ND_INS_POPCNT => Ok(Mnemonic::POPCNT), ffi::_ND_INS_CLASS::ND_INS_POPF => Ok(Mnemonic::POPF), + ffi::_ND_INS_CLASS::ND_INS_POPP => Ok(Mnemonic::POPP), ffi::_ND_INS_CLASS::ND_INS_POR => Ok(Mnemonic::POR), ffi::_ND_INS_CLASS::ND_INS_PREFETCH => Ok(Mnemonic::PREFETCH), ffi::_ND_INS_CLASS::ND_INS_PREFETCHE => Ok(Mnemonic::PREFETCHE), @@ -2263,9 +2256,12 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_PUNPCKLQDQ => Ok(Mnemonic::PUNPCKLQDQ), ffi::_ND_INS_CLASS::ND_INS_PUNPCKLWD => Ok(Mnemonic::PUNPCKLWD), ffi::_ND_INS_CLASS::ND_INS_PUSH => Ok(Mnemonic::PUSH), + ffi::_ND_INS_CLASS::ND_INS_PUSH2 => Ok(Mnemonic::PUSH2), + ffi::_ND_INS_CLASS::ND_INS_PUSH2P => Ok(Mnemonic::PUSH2P), ffi::_ND_INS_CLASS::ND_INS_PUSHA => Ok(Mnemonic::PUSHA), ffi::_ND_INS_CLASS::ND_INS_PUSHAD => Ok(Mnemonic::PUSHAD), ffi::_ND_INS_CLASS::ND_INS_PUSHF => Ok(Mnemonic::PUSHF), + ffi::_ND_INS_CLASS::ND_INS_PUSHP => Ok(Mnemonic::PUSHP), ffi::_ND_INS_CLASS::ND_INS_PVALIDATE => Ok(Mnemonic::PVALIDATE), ffi::_ND_INS_CLASS::ND_INS_PXOR => Ok(Mnemonic::PXOR), ffi::_ND_INS_CLASS::ND_INS_RCL => Ok(Mnemonic::RCL), @@ -2282,7 +2278,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_RDPRU => Ok(Mnemonic::RDPRU), ffi::_ND_INS_CLASS::ND_INS_RDRAND => Ok(Mnemonic::RDRAND), ffi::_ND_INS_CLASS::ND_INS_RDSEED => Ok(Mnemonic::RDSEED), - ffi::_ND_INS_CLASS::ND_INS_RDSHR => Ok(Mnemonic::RDSHR), ffi::_ND_INS_CLASS::ND_INS_RDTSC => Ok(Mnemonic::RDTSC), ffi::_ND_INS_CLASS::ND_INS_RDTSCP => Ok(Mnemonic::RDTSCP), ffi::_ND_INS_CLASS::ND_INS_RETF => Ok(Mnemonic::RETF), @@ -2297,14 +2292,11 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_ROUNDPS => Ok(Mnemonic::ROUNDPS), ffi::_ND_INS_CLASS::ND_INS_ROUNDSD => Ok(Mnemonic::ROUNDSD), ffi::_ND_INS_CLASS::ND_INS_ROUNDSS => Ok(Mnemonic::ROUNDSS), - ffi::_ND_INS_CLASS::ND_INS_RSDC => Ok(Mnemonic::RSDC), - ffi::_ND_INS_CLASS::ND_INS_RSLDT => Ok(Mnemonic::RSLDT), ffi::_ND_INS_CLASS::ND_INS_RSM => Ok(Mnemonic::RSM), ffi::_ND_INS_CLASS::ND_INS_RSQRTPS => Ok(Mnemonic::RSQRTPS), ffi::_ND_INS_CLASS::ND_INS_RSQRTSS => Ok(Mnemonic::RSQRTSS), ffi::_ND_INS_CLASS::ND_INS_RSSSP => Ok(Mnemonic::RSSSP), ffi::_ND_INS_CLASS::ND_INS_RSTORSSP => Ok(Mnemonic::RSTORSSP), - ffi::_ND_INS_CLASS::ND_INS_RSTS => Ok(Mnemonic::RSTS), ffi::_ND_INS_CLASS::ND_INS_SAHF => Ok(Mnemonic::SAHF), ffi::_ND_INS_CLASS::ND_INS_SAL => Ok(Mnemonic::SAL), ffi::_ND_INS_CLASS::ND_INS_SALC => Ok(Mnemonic::SALC), @@ -2341,7 +2333,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_SKINIT => Ok(Mnemonic::SKINIT), ffi::_ND_INS_CLASS::ND_INS_SLDT => Ok(Mnemonic::SLDT), ffi::_ND_INS_CLASS::ND_INS_SLWPCB => Ok(Mnemonic::SLWPCB), - ffi::_ND_INS_CLASS::ND_INS_SMINT => Ok(Mnemonic::SMINT), ffi::_ND_INS_CLASS::ND_INS_SMSW => Ok(Mnemonic::SMSW), ffi::_ND_INS_CLASS::ND_INS_SPFLT => Ok(Mnemonic::SPFLT), ffi::_ND_INS_CLASS::ND_INS_SQRTPD => Ok(Mnemonic::SQRTPD), @@ -2363,9 +2354,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_SUBPS => Ok(Mnemonic::SUBPS), ffi::_ND_INS_CLASS::ND_INS_SUBSD => Ok(Mnemonic::SUBSD), ffi::_ND_INS_CLASS::ND_INS_SUBSS => Ok(Mnemonic::SUBSS), - ffi::_ND_INS_CLASS::ND_INS_SVDC => Ok(Mnemonic::SVDC), - ffi::_ND_INS_CLASS::ND_INS_SVLDT => Ok(Mnemonic::SVLDT), - ffi::_ND_INS_CLASS::ND_INS_SVTS => Ok(Mnemonic::SVTS), ffi::_ND_INS_CLASS::ND_INS_SWAPGS => Ok(Mnemonic::SWAPGS), ffi::_ND_INS_CLASS::ND_INS_SYSCALL => Ok(Mnemonic::SYSCALL), ffi::_ND_INS_CLASS::ND_INS_SYSENTER => Ok(Mnemonic::SYSENTER), @@ -2404,6 +2392,8 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_UNPCKHPS => Ok(Mnemonic::UNPCKHPS), ffi::_ND_INS_CLASS::ND_INS_UNPCKLPD => Ok(Mnemonic::UNPCKLPD), ffi::_ND_INS_CLASS::ND_INS_UNPCKLPS => Ok(Mnemonic::UNPCKLPS), + ffi::_ND_INS_CLASS::ND_INS_URDMSR => Ok(Mnemonic::URDMSR), + ffi::_ND_INS_CLASS::ND_INS_UWRMSR => Ok(Mnemonic::UWRMSR), ffi::_ND_INS_CLASS::ND_INS_V4FMADDPS => Ok(Mnemonic::V4FMADDPS), ffi::_ND_INS_CLASS::ND_INS_V4FMADDSS => Ok(Mnemonic::V4FMADDSS), ffi::_ND_INS_CLASS::ND_INS_V4FNMADDPS => Ok(Mnemonic::V4FNMADDPS), @@ -3271,18 +3261,12 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_WRMSRLIST => Ok(Mnemonic::WRMSRLIST), ffi::_ND_INS_CLASS::ND_INS_WRMSRNS => Ok(Mnemonic::WRMSRNS), ffi::_ND_INS_CLASS::ND_INS_WRPKRU => Ok(Mnemonic::WRPKRU), - ffi::_ND_INS_CLASS::ND_INS_WRSHR => Ok(Mnemonic::WRSHR), ffi::_ND_INS_CLASS::ND_INS_WRSS => Ok(Mnemonic::WRSS), ffi::_ND_INS_CLASS::ND_INS_WRUSS => Ok(Mnemonic::WRUSS), ffi::_ND_INS_CLASS::ND_INS_XABORT => Ok(Mnemonic::XABORT), ffi::_ND_INS_CLASS::ND_INS_XADD => Ok(Mnemonic::XADD), ffi::_ND_INS_CLASS::ND_INS_XBEGIN => Ok(Mnemonic::XBEGIN), ffi::_ND_INS_CLASS::ND_INS_XCHG => Ok(Mnemonic::XCHG), - ffi::_ND_INS_CLASS::ND_INS_XCRYPTCBC => Ok(Mnemonic::XCRYPTCBC), - ffi::_ND_INS_CLASS::ND_INS_XCRYPTCFB => Ok(Mnemonic::XCRYPTCFB), - ffi::_ND_INS_CLASS::ND_INS_XCRYPTCTR => Ok(Mnemonic::XCRYPTCTR), - ffi::_ND_INS_CLASS::ND_INS_XCRYPTECB => Ok(Mnemonic::XCRYPTECB), - ffi::_ND_INS_CLASS::ND_INS_XCRYPTOFB => Ok(Mnemonic::XCRYPTOFB), ffi::_ND_INS_CLASS::ND_INS_XEND => Ok(Mnemonic::XEND), ffi::_ND_INS_CLASS::ND_INS_XGETBV => Ok(Mnemonic::XGETBV), ffi::_ND_INS_CLASS::ND_INS_XLATB => Ok(Mnemonic::XLATB), @@ -3297,9 +3281,6 @@ impl TryFrom for Mnemonic { ffi::_ND_INS_CLASS::ND_INS_XSAVEOPT => Ok(Mnemonic::XSAVEOPT), ffi::_ND_INS_CLASS::ND_INS_XSAVES => Ok(Mnemonic::XSAVES), ffi::_ND_INS_CLASS::ND_INS_XSETBV => Ok(Mnemonic::XSETBV), - ffi::_ND_INS_CLASS::ND_INS_XSHA1 => Ok(Mnemonic::XSHA1), - ffi::_ND_INS_CLASS::ND_INS_XSHA256 => Ok(Mnemonic::XSHA256), - ffi::_ND_INS_CLASS::ND_INS_XSTORE => Ok(Mnemonic::XSTORE), ffi::_ND_INS_CLASS::ND_INS_XSUSLDTRK => Ok(Mnemonic::XSUSLDTRK), ffi::_ND_INS_CLASS::ND_INS_XTEST => Ok(Mnemonic::XTEST), } diff --git a/bindings/rsbddisasm/bddisasm/src/operand.rs b/bindings/rsbddisasm/bddisasm/src/operand.rs index 049faac..446750b 100644 --- a/bindings/rsbddisasm/bddisasm/src/operand.rs +++ b/bindings/rsbddisasm/bddisasm/src/operand.rs @@ -29,10 +29,6 @@ impl OpAddr { offset: raw.Offset, } } - - pub(crate) fn new(base_seg: u16, offset: u64) -> Self { - Self { base_seg, offset } - } } /// The type of a register. @@ -188,7 +184,7 @@ pub struct OpReg { /// /// # Remarks /// - /// If [kind](OpReg::kind) is [OpRegType::Gpr](OpRegType::Gpr), the high and low part of 16-bit registers will have + /// If [kind](OpReg::kind) is [`OpRegType::Gpr`], the high and low part of 16-bit registers will have /// the same index (for example, `AH` and `AL`). To differentiate between them use [is_high8](OpReg::is_high8). pub index: usize, @@ -223,7 +219,7 @@ impl OpReg { kind, size: raw.Size, index, - count: raw.Count, + count: raw.Count as u32, is_high8, is_block: raw.IsBlock() != 0, }) @@ -279,6 +275,7 @@ impl ShadowStackAccess { } /// Describes a memory operand. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] pub struct OpMem { /// `true` if the memory operand is a broadcast operand. @@ -353,19 +350,23 @@ pub struct OpMem { impl OpMem { pub(crate) fn from_raw(raw: ffi::ND_OPDESC_MEMORY) -> Result { let seg = if raw.HasSeg() != 0 { - Some(raw.Seg) + Some(raw.Seg()) } else { None }; let (base, base_size) = if raw.HasBase() != 0 { - (Some(raw.Base), Some(raw.BaseSize)) + (Some(raw.Base()), Some(raw.BaseSize as u32)) } else { (None, None) }; let (index, index_size, scale) = if raw.HasIndex() != 0 { - (Some(raw.Index), Some(raw.IndexSize), Some(raw.Scale)) + ( + Some(raw.Index), + Some(raw.IndexSize as u32), + Some(raw.Scale()), + ) } else { (None, None, None) }; @@ -385,10 +386,10 @@ impl OpMem { let (vsib, index_size) = if raw.IsVsib() != 0 { ( Some(Vsib { - vsib_element_size: raw.Vsib.ElemSize, - vsib_element_count: raw.Vsib.ElemCount, + vsib_element_size: unsafe { raw.__bindgen_anon_1.Vsib.ElemSize }, + vsib_element_count: unsafe { raw.__bindgen_anon_1.Vsib.ElemCount }, }), - Some(raw.Vsib.IndexSize.into()), + Some(unsafe { raw.__bindgen_anon_1.Vsib.IndexSize.into() }), ) } else { (None, index_size) @@ -460,7 +461,9 @@ impl Default for OpInfo { } impl OpInfo { - /// Returns the associated [OpReg](OpReg) for register operands. Returns [`None`] otherwise. + /// Returns the associated [`OpReg`] for register operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_reg(&self) -> Option<&OpReg> { if let OpInfo::Reg(o) = self { Some(o) @@ -469,7 +472,9 @@ impl OpInfo { } } - /// Returns the associated [OpMem](OpMem) for memory operands. Returns [`None`] otherwise. + /// Returns the associated [`OpMem`] for memory operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_mem(&self) -> Option<&OpMem> { if let OpInfo::Mem(o) = self { Some(o) @@ -479,6 +484,8 @@ impl OpInfo { } /// Returns the associated immediate value for immediate operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_imm(&self) -> Option { if let OpInfo::Imm(o) = self { Some(*o) @@ -487,7 +494,9 @@ impl OpInfo { } } - /// Returns the associated [OpAddr](OpAddr) for absolute address operands. Returns [`None`] otherwise. + /// Returns the associated [`OpAddr`] for absolute address operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_addr(&self) -> Option<&OpAddr> { if let OpInfo::Addr(o) = self { Some(o) @@ -497,6 +506,8 @@ impl OpInfo { } /// Returns the associated constant value for constant operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_const(&self) -> Option { if let OpInfo::Const(o) = self { Some(*o) @@ -506,6 +517,8 @@ impl OpInfo { } /// Returns `Some` for bank operands. Returns [`None`] otherwise. + #[inline] + #[must_use] pub fn as_bank(&self) -> Option<()> { if let OpInfo::Bank = self { Some(()) @@ -515,31 +528,43 @@ impl OpInfo { } /// Returns `true` for register operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_reg(&self) -> bool { self.as_reg().is_some() } /// Returns `true` for memory operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_mem(&self) -> bool { self.as_mem().is_some() } /// Returns `true` for immediate operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_imm(&self) -> bool { self.as_imm().is_some() } /// Returns `true` for absolute address operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_addr(&self) -> bool { self.as_addr().is_some() } /// Returns `true` for constant operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_const(&self) -> bool { self.as_const().is_some() } /// Returns `true` for bank operands. Returns `false` otherwise. + #[inline] + #[must_use] pub fn is_bank(&self) -> bool { self.as_bank().is_some() } @@ -548,25 +573,26 @@ impl OpInfo { #[doc(hidden)] impl OpInfo { pub(crate) fn from_raw(raw: ffi::ND_OPERAND) -> Result { - match raw.Type { - ffi::_ND_OPERAND_TYPE::ND_OP_NOT_PRESENT => Ok(OpInfo::None), - ffi::_ND_OPERAND_TYPE::ND_OP_REG => { - Ok(OpInfo::Reg(OpReg::from_raw(unsafe { raw.Info.Register })?)) - } - ffi::_ND_OPERAND_TYPE::ND_OP_MEM => { - Ok(OpInfo::Mem(OpMem::from_raw(unsafe { raw.Info.Memory })?)) - } - ffi::_ND_OPERAND_TYPE::ND_OP_IMM => Ok(OpInfo::Imm(unsafe { raw.Info.Immediate }.Imm)), - ffi::_ND_OPERAND_TYPE::ND_OP_OFFS => { - Ok(OpInfo::Offs(unsafe { raw.Info.RelativeOffset }.Rel)) - } - ffi::_ND_OPERAND_TYPE::ND_OP_ADDR => { - Ok(OpInfo::Addr(OpAddr::from_raw(unsafe { raw.Info.Address }))) - } - ffi::_ND_OPERAND_TYPE::ND_OP_CONST => { - Ok(OpInfo::Const(unsafe { raw.Info.Constant }.Const)) - } - ffi::_ND_OPERAND_TYPE::ND_OP_BANK => Ok(OpInfo::Bank), + let typ = raw.Type() as i32; + + if typ == ffi::_ND_OPERAND_TYPE::ND_OP_NOT_PRESENT as i32 { + Ok(OpInfo::None) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_REG as i32 { + Ok(OpInfo::Reg(OpReg::from_raw(unsafe { raw.Info.Register })?)) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_MEM as i32 { + Ok(OpInfo::Mem(OpMem::from_raw(unsafe { raw.Info.Memory })?)) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_IMM as i32 { + Ok(OpInfo::Imm(unsafe { raw.Info.Immediate }.Imm)) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_OFFS as i32 { + Ok(OpInfo::Offs(unsafe { raw.Info.RelativeOffset }.Rel)) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_ADDR as i32 { + Ok(OpInfo::Addr(OpAddr::from_raw(unsafe { raw.Info.Address }))) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_CONST as i32 { + Ok(OpInfo::Const(unsafe { raw.Info.Constant }.Const)) + } else if typ == ffi::_ND_OPERAND_TYPE::ND_OP_BANK as i32 { + Ok(OpInfo::Bank) + } else { + Err(DecodeError::InternalError(0)) } } } @@ -620,7 +646,6 @@ impl fmt::Display for OpSize { impl OpSize { pub(crate) fn from_raw(value: ffi::ND_OPERAND_SIZE) -> Result { match value { - 0 => Ok(OpSize::Bytes(0)), ffi::ND_SIZE_8BIT => Ok(OpSize::Bytes(1)), ffi::ND_SIZE_16BIT => Ok(OpSize::Bytes(2)), ffi::ND_SIZE_32BIT => Ok(OpSize::Bytes(4)), @@ -645,6 +670,7 @@ impl OpSize { } /// Operand access mode. +#[allow(clippy::struct_excessive_bools)] #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)] pub struct OpAccess { /// The operand is read. @@ -701,32 +727,6 @@ pub struct Decorator { pub broadcast: Option, } -#[doc(hidden)] -impl Decorator { - pub(crate) fn from_raw(raw: ffi::ND_OPERAND_DECORATOR) -> Decorator { - let mask_register = if raw.HasMask() != 0 { - Some(raw.Mask.Msk) - } else { - None - }; - - let broadcast = if raw.HasBroadcast() != 0 { - Some(Broadcast { - count: raw.Broadcast.Count, - size: raw.Broadcast.Size, - }) - } else { - None - }; - - Self { - mask_register, - has_zero: raw.HasZero() != 0, - broadcast, - } - } -} - /// Describes an instruction operand. /// /// Each operand type encodes different information. See [`OpInfo`] for details. @@ -775,23 +775,11 @@ pub struct Operand { /// cases. pub size: OpSize, - /// Raw size inside the instruction. - /// - /// This will usually be identical to [size](Operand::size), however, some instructions force the actual size of - /// their operands to 64 bit (`PUSH`/`POP` or branches are good examples). - /// - /// Although the raw size of the relative offset or the immediate will be [raw_size](Operand::raw_size), internally, - /// the CPU will use [size](Operand::size) (usually sign-extended). - pub raw_size: OpSize, - /// Access mode. pub access: OpAccess, /// `true` if the operand is default. This also applies to implicit operands. pub is_default: bool, - - /// Decorator information. - pub decorator: Decorator, } #[doc(hidden)] @@ -800,10 +788,8 @@ impl Operand { Ok(Self { info: OpInfo::from_raw(raw)?, size: OpSize::from_raw(raw.Size)?, - raw_size: OpSize::from_raw(raw.RawSize)?, access: OpAccess::from_raw(raw.Access), is_default: unsafe { raw.Flags.__bindgen_anon_1 }.IsDefault() != 0, - decorator: Decorator::from_raw(raw.Decorator), }) } } @@ -932,6 +918,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn dest(&self, index: usize) -> Option { let op = match index { 0 => unsafe { self.op_rlut.Dst1.as_ref() }, @@ -961,6 +948,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn src(&self, index: usize) -> Option { let op = match index { 0 => unsafe { self.op_rlut.Src1.as_ref() }, @@ -991,6 +979,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn mem(&self, index: usize) -> Option { let op = match index { 0 => unsafe { self.op_rlut.Mem1.as_ref() }, @@ -1013,6 +1002,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn stack(&self) -> Option { let op = unsafe { self.op_rlut.Stack.as_ref() }; @@ -1031,6 +1021,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn flags(&self) -> Option { let op = unsafe { self.op_rlut.Flags.as_ref() }; @@ -1049,6 +1040,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rip(&self) -> Option { let op = unsafe { self.op_rlut.Rip.as_ref() }; @@ -1067,6 +1059,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn cs(&self) -> Option { let op = unsafe { self.op_rlut.Cs.as_ref() }; @@ -1085,6 +1078,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn ss(&self) -> Option { let op = unsafe { self.op_rlut.Ss.as_ref() }; @@ -1103,6 +1097,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rax(&self) -> Option { let op = unsafe { self.op_rlut.Rax.as_ref() }; @@ -1121,6 +1116,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rcx(&self) -> Option { let op = unsafe { self.op_rlut.Rcx.as_ref() }; @@ -1139,6 +1135,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rdx(&self) -> Option { let op = unsafe { self.op_rlut.Rdx.as_ref() }; @@ -1157,6 +1154,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rbx(&self) -> Option { let op = unsafe { self.op_rlut.Rbx.as_ref() }; @@ -1175,6 +1173,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rsp(&self) -> Option { let op = unsafe { self.op_rlut.Rsp.as_ref() }; @@ -1193,6 +1192,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rbp(&self) -> Option { let op = unsafe { self.op_rlut.Rbp.as_ref() }; @@ -1211,6 +1211,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rsi(&self) -> Option { let op = unsafe { self.op_rlut.Rsi.as_ref() }; @@ -1229,6 +1230,7 @@ impl<'a> OperandsLookup<'a> { /// This function will panic if the result of the C library is unrecognized. This can not happen under normal /// circumstances. #[inline] + #[must_use] pub fn rdi(&self) -> Option { let op = unsafe { self.op_rlut.Rdi.as_ref() }; @@ -1236,7 +1238,7 @@ impl<'a> OperandsLookup<'a> { } } -/// A collection of [Operand](Operand)s. +/// A collection of [`Operand`]s. #[derive(Copy, Clone, Eq, PartialEq, Hash, Debug, Default)] pub struct Operands { pub(crate) operands: [Operand; 10], @@ -1266,7 +1268,6 @@ mod tests { let dest = operands[0]; assert_eq!(dest.size, OpSize::Bytes(1)); - assert_eq!(dest.raw_size, OpSize::Bytes(1)); assert_eq!(dest.is_default, false); assert!(dest.access.write); @@ -1281,7 +1282,6 @@ mod tests { let src = operands[1]; assert_eq!(src.size, OpSize::Bytes(1)); - assert_eq!(src.raw_size, OpSize::Bytes(1)); assert_eq!(src.is_default, false); assert!(src.access.read); diff --git a/bindings/rsbddisasm/update_ins.py b/bindings/rsbddisasm/update_ins.py new file mode 100644 index 0000000..928ed84 --- /dev/null +++ b/bindings/rsbddisasm/update_ins.py @@ -0,0 +1,198 @@ +import os +import subprocess +import sys +from pathlib import Path + +from git import Repo + +repo = Repo(search_parent_directories=True) +root = Path(repo.working_tree_dir) + +print(f"Repo root: {root}") + +hdr_dirs = root / "inc" +x86_constants = hdr_dirs / "bdx86_constants.h" + +print(f"Looking for enums in {x86_constants}") + +with open(x86_constants, "r") as data: + nd_ins = [] + nd_ins_set = [] + nd_ins_type = [] + + for line in data: + if "INVALID" in line: + continue + + if line.startswith(" ND_CAT_"): + token = line.replace(',', '').strip() + nd_ins_type.append(token) + continue + + if line.startswith(" ND_SET_"): + token = line.replace(',', '').strip() + nd_ins_set.append(token) + continue + + if line.startswith(" ND_INS_"): + token = line.replace(',', '').strip() + nd_ins.append(token) + continue + +print(f"ND_INS_: {len(nd_ins)} ND_SET_: {len(nd_ins_set)} ND_CAT_: {len(nd_ins_type)}") + +bindings = root / "bindings/rsbddisasm/bddisasm/src" +mnemonic = bindings / "mnemonic.rs" +ins_cat = bindings / "instruction_category.rs" +isa_set = bindings / "isa_set.rs" + +license_header = """ +/* + * Copyright (c) 2021 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +""" + +print(f"Generating {mnemonic}") + +with open(mnemonic, "w") as fmnemonic: + fmnemonic.write(license_header) + fmnemonic.write("//! Mnemonics.\n") + fmnemonic.write("\n") + fmnemonic.write("use super::decode_error::DecodeError;\n") + fmnemonic.write("use core::convert::TryFrom;\n") + + mnemonic_enum_def = """ +/// Uniquely identifies an instruction. +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +#[allow(non_camel_case_types)] +pub enum Mnemonic { + """ + fmnemonic.write(mnemonic_enum_def) + for ins in nd_ins: + line = ins.replace("ND_INS_", "") + fmnemonic.write(f"{line},\n") + + fmnemonic.write("}\n") + + try_from = """ +#[doc(hidden)] +impl TryFrom for Mnemonic { + type Error = DecodeError; + + #[allow(clippy::too_many_lines)] + fn try_from(value: ffi::ND_INS_CLASS) -> Result { + match value { + ffi::_ND_INS_CLASS::ND_INS_INVALID => Err(DecodeError::InternalError(value as u64)), + """ + fmnemonic.write(try_from) + for ins in nd_ins: + line = f"ffi::_ND_INS_CLASS::{ins} => Ok(Mnemonic::{ins.replace('ND_INS_', '')}),\n" + fmnemonic.write(line) + + end = """ + } + } +} + """ + fmnemonic.write(end) + +print(f"Generating {ins_cat}") + +with open(ins_cat, "w") as finscat: + finscat.write(license_header) + finscat.write("//! Instruction categories.\n") + finscat.write("\n") + finscat.write("use super::decode_error::DecodeError;\n") + finscat.write("use core::convert::TryFrom;\n") + + ins_cat_enum_def = """ +/// Instruction category. +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +#[allow(non_camel_case_types)] +pub enum Category { + """ + finscat.write(ins_cat_enum_def) + for ins in nd_ins_type: + line = ins.replace("ND_CAT_", "") + if line[0].isdigit(): + line = f"I{line}" + finscat.write(f"{line},\n") + + finscat.write("}\n") + + try_from = """ +#[doc(hidden)] +impl TryFrom for Category { + type Error = DecodeError; + + #[allow(clippy::too_many_lines)] + fn try_from(value: ffi::ND_INS_CATEGORY) -> Result { + match value { + ffi::_ND_INS_TYPE::ND_CAT_INVALID => Err(DecodeError::InternalError(value as u64)), + """ + finscat.write(try_from) + for ins in nd_ins_type: + ok = ins.replace('ND_CAT_', '') + if ok[0].isdigit(): + ok = f"I{ok}" + line = f"ffi::_ND_INS_TYPE::{ins} => Ok(Category::{ok}),\n" + finscat.write(line) + + end = """ + } + } +} + """ + finscat.write(end) + +print(f"Generating {isa_set}") + +with open(isa_set, "w") as fset: + fset.write(license_header) + fset.write("//! Instruction sets.\n") + fset.write("\n") + fset.write("use super::decode_error::DecodeError;\n") + fset.write("use core::convert::TryFrom;\n") + + ins_set_enum_def = """ +/// ISA set. +#[derive(Copy, Clone, Eq, PartialEq, Hash, Debug)] +#[allow(non_camel_case_types)] +pub enum IsaSet { + """ + fset.write(ins_set_enum_def) + for ins in nd_ins_set: + line = ins.replace("ND_SET_", "") + if line[0].isdigit(): + line = f"I{line}" + fset.write(f"{line},\n") + + fset.write("}\n") + + try_from = """ +#[doc(hidden)] +impl TryFrom for IsaSet { + type Error = DecodeError; + + #[allow(clippy::too_many_lines)] + fn try_from(value: ffi::ND_INS_SET) -> Result { + match value { + ffi::_ND_INS_SET::ND_SET_INVALID => Err(DecodeError::InternalError(value as u64)), + """ + fset.write(try_from) + for ins in nd_ins_set: + ok = ins.replace('ND_SET_', '') + if ok[0].isdigit(): + ok = f"I{ok}" + line = f"ffi::_ND_INS_SET::{ins} => Ok(IsaSet::{ok}),\n" + fset.write(line) + + end = """ + } + } +} + """ + fset.write(end) + +subprocess.check_output(["cargo", "fmt"]) diff --git a/disasmtool/CMakeLists.txt b/disasmtool/CMakeLists.txt index 0e471e2..8f13151 100644 --- a/disasmtool/CMakeLists.txt +++ b/disasmtool/CMakeLists.txt @@ -50,9 +50,7 @@ else () -Wno-unused-function -Wno-multichar -Wno-incompatible-pointer-types - -Wno-discarded-qualifiers -Wnull-dereference - -Wduplicated-cond -Werror=implicit-function-declaration -pipe -fwrapv @@ -65,4 +63,10 @@ else () -gdwarf-4 -grecord-gcc-switches -march=westmere) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_compile_options( + disasmtool + PRIVATE -Wno-discarded-qualifiers + -Wduplicated-cond) + endif () endif () diff --git a/disasmtool/disasmtool.c b/disasmtool/disasmtool.c index 5073c42..e27e93c 100644 --- a/disasmtool/disasmtool.c +++ b/disasmtool/disasmtool.c @@ -2,12 +2,20 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ +#ifdef WIN32 +#define _CRT_SECURE_NO_WARNINGS #include -#include -#include -#include -#include #include +#else +#include +#endif // WIN32 + +#include +#include +#include +#include +#include +#include // Main disasm header file. #include "bdshemu.h" @@ -62,21 +70,58 @@ nd_memset(void *s, int c, size_t n) } #endif // !defined(BDDISASM_HAS_MEMSET) + +#ifdef WIN32 +#define cpuid __cpuid +#else +#define _stricmp strcasecmp +#define __rdtsc __builtin_ia32_rdtsc + +void cpuid(int cpuInfo[4], int function_id) +{ + unsigned int *cpuinfo = (unsigned int *)cpuInfo; + __get_cpuid(function_id, &cpuinfo[0], &cpuinfo[1], &cpuinfo[2], &cpuinfo[3]); +} +#endif //WIN32 + + +#define FG_Black "\033[1;30m" +#define FG_Red "\033[1;31m" +#define FG_Green "\033[1;32m" +#define FG_Yellow "\033[1;33m" +#define FG_Blue "\033[1;34m" +#define FG_Magenta "\033[1;35m" +#define FG_Cyan "\033[1;36m" +#define FG_White "\033[1;37m" + +void set_bold_fg_color(const char *Color) +{ + printf(Color); +} + +void reset_fg_color(void) +{ + printf("\033[0m"); +} + + void ShemuLog( - __in PCHAR Data + _In_ PCHAR Data, + _In_ void *Context ) { + UNREFERENCED_PARAMETER(Context); printf("%s", Data); } bool ShemuAccessMem( - __in PSHEMU_CONTEXT Ctx, - __in uint64_t Gla, - __in size_t Size, - __inout uint8_t *Buffer, - __in bool Store + _In_ PSHEMU_CONTEXT Ctx, + _In_ uint64_t Gla, + _In_ size_t Size, + _Inout_ uint8_t *Buffer, + _In_ bool Store ) { UNREFERENCED_PARAMETER(Ctx); @@ -95,10 +140,36 @@ ShemuAccessMem( return true; } +bool +ShemuAccessShellcode( + _In_ PSHEMU_CONTEXT Ctx, + _In_ uint64_t Gla, + _In_ size_t Size, + _Inout_ uint8_t *Buffer, + _In_ bool Store + ) +{ + ND_UINT32 offset; + + offset = (ND_UINT32)(Gla - Ctx->ShellcodeBase); + + if (Store) + { + memcpy(Ctx->Shellcode + offset, Buffer, Size); + } + else + { + memcpy(Buffer, Ctx->Shellcode + offset, Size); + } + + return true; +} + + const char* set_to_string( - __in ND_INS_SET Set + _In_ ND_INS_SET Set ) { switch (Set) @@ -106,6 +177,7 @@ set_to_string( case ND_SET_3DNOW: return "3DNOW"; case ND_SET_ADX: return "ADX"; case ND_SET_AES: return "AES"; + case ND_SET_APX_F: return "APX_F"; case ND_SET_AMD: return "AMD"; case ND_SET_AMXBF16: return "AMX-BF16"; case ND_SET_AMXFP16: return "AMX-FP16"; @@ -148,8 +220,6 @@ set_to_string( case ND_SET_CLZERO: return "CLZERO"; case ND_SET_CMPCCXADD: return "CMPCCXADD"; case ND_SET_CMPXCHG16B: return "CMPXCHG16B"; - case ND_SET_CYRIX: return "CYRIX"; - case ND_SET_CYRIX_SMM: return "CYRIX_SMM"; case ND_SET_ENQCMD: return "ENQCMD"; case ND_SET_F16C: return "F16C"; case ND_SET_FMA: return "FMA"; @@ -224,6 +294,7 @@ set_to_string( case ND_SET_UD: return "UD"; case ND_SET_UINTR: return "UINTR"; case ND_SET_UNKNOWN: return "UNKNOWN"; + case ND_SET_USER_MSR: return "USER_MSR"; case ND_SET_VAES: return "VAES"; case ND_SET_VPCLMULQDQ: return "VPCLMULQDQ"; case ND_SET_VTX: return "VTX"; @@ -242,7 +313,7 @@ set_to_string( const char* category_to_string( - __in ND_INS_CATEGORY Category + _In_ ND_INS_CATEGORY Category ) { switch (Category) @@ -252,6 +323,7 @@ category_to_string( case ND_CAT_AESKL: return "AESKL"; case ND_CAT_ARITH: return "ARITH"; case ND_CAT_AMX: return "AMX"; + case ND_CAT_APX: return "APX"; case ND_CAT_AVX: return "AVX"; case ND_CAT_AVX2: return "AVX2"; case ND_CAT_AVX2GATHER: return "AVX2GATHER"; @@ -308,7 +380,6 @@ category_to_string( case ND_CAT_MOVDIRI: return "MOVDIRI"; case ND_CAT_MPX: return "MPX"; case ND_CAT_NOP: return "NOP"; - case ND_CAT_PADLOCK: return "PADLOCK"; case ND_CAT_PCLMULQDQ: return "PCLMULQDQ"; case ND_CAT_PCONFIG: return "PCONFIG"; case ND_CAT_POP: return "POP"; @@ -344,6 +415,7 @@ category_to_string( case ND_CAT_UINTR: return "UINTR"; case ND_CAT_UNCOND_BR: return "UNCOND_BR"; case ND_CAT_UNKNOWN: return "UNKNOWN"; + case ND_CAT_USER_MSR: return "USER_MSR"; case ND_CAT_VAES: return "VAES"; case ND_CAT_VFMA: return "VFMA"; case ND_CAT_VFMAPS: return "VFMAPS"; @@ -366,7 +438,7 @@ category_to_string( const char* optype_to_string( - __in ND_OPERAND_TYPE OpType + _In_ ND_OPERAND_TYPE OpType ) { switch (OpType) @@ -376,8 +448,10 @@ optype_to_string( case ND_OP_CONST: return "Constant"; case ND_OP_MEM: return "Memory"; case ND_OP_ADDR: return "Address"; + case ND_OP_ADDR_NEAR: return "Address"; case ND_OP_OFFS: return "Offset"; case ND_OP_BANK: return "Bank"; + case ND_OP_DFV: return "Default flags"; default: return "???"; } } @@ -385,7 +459,7 @@ optype_to_string( const char* regtype_to_string( - __in ND_REG_TYPE RegType + _In_ ND_REG_TYPE RegType ) { switch (RegType) @@ -417,7 +491,7 @@ regtype_to_string( const char* encoding_to_string( - __in ND_OPERAND_ENCODING Encoding + _In_ ND_OPERAND_ENCODING Encoding ) { switch (Encoding) @@ -441,7 +515,7 @@ encoding_to_string( const char* tuple_to_string( - __in ND_TUPLE Tuple + _In_ ND_TUPLE Tuple ) { switch (Tuple) @@ -468,12 +542,30 @@ tuple_to_string( const char* -exception_evex_to_string( - __in ND_EX_TYPE_EVEX ExClass +exception_type_to_string( + _In_ ND_EX_TYPE ExType ) { - switch (ExClass) + switch (ExType) { + case ND_EXT_1: return "1"; + case ND_EXT_2: return "2"; + case ND_EXT_3: return "3"; + case ND_EXT_4: return "4"; + case ND_EXT_5: return "5"; + case ND_EXT_6: return "6"; + case ND_EXT_7: return "7"; + case ND_EXT_8: return "8"; + case ND_EXT_9: return "9"; + case ND_EXT_10: return "10"; + case ND_EXT_11: return "11"; + case ND_EXT_12: return "12"; + case ND_EXT_13: return "13"; + case ND_EXT_14: return "14"; + + case ND_EXT_K20: return "K20"; + case ND_EXT_K21: return "K21"; + case ND_EXT_E1: return "E1"; case ND_EXT_E1NF: return "E1NF"; case ND_EXT_E2: return "E2"; @@ -495,14 +587,55 @@ exception_evex_to_string( case ND_EXT_E11: return "E11"; case ND_EXT_E12: return "E12"; case ND_EXT_E12NP: return "E12NP"; + + case ND_EXT_AMX_E1: return "AMX-E1"; + case ND_EXT_AMX_E2: return "AMX-E2"; + case ND_EXT_AMX_E3: return "AMX-E3"; + case ND_EXT_AMX_E4: return "AMX-E4"; + case ND_EXT_AMX_E5: return "AMX-E5"; + case ND_EXT_AMX_E6: return "AMX-E6"; + + case ND_EXT_AMX_EVEX_E1: return "AMX-EVEX-E1"; + case ND_EXT_AMX_EVEX_E2: return "AMX-EVEX-E2"; + case ND_EXT_AMX_EVEX_E3: return "AMX-EVEX-E3"; + + case ND_EXT_APX_EVEX_BMI: return "APX-EVEX-BMI"; + case ND_EXT_APX_EVEX_CCMP: return "APX-EVEX-CCMP"; + case ND_EXT_APX_EVEX_WRSS: return "APX-EVEX-WRSS"; + case ND_EXT_APX_EVEX_WRUSS: return "APX-EVEX-WRUSS"; + case ND_EXT_APX_EVEX_CFCMOV: return "APX-EVEX-CFCMOV"; + case ND_EXT_APX_EVEX_CMPCCXADD: return "APX-EVEX-CMPCCXADD"; + case ND_EXT_APX_EVEX_ENQCMD: return "APX-EVEX-ENQCMD"; + case ND_EXT_APX_EVEX_INT: return "APX-EVEX-INT"; + case ND_EXT_APX_EVEX_INVEPT: return "APX-EVEX-INVEPT"; + case ND_EXT_APX_EVEX_INVPCID: return "APX-EVEX-INVPCID"; + case ND_EXT_APX_EVEX_INVVPID: return "APX-EVEX-INVVPID"; + case ND_EXT_APX_EVEX_KEYLOCKER: return "APX-EVEX-KEYLOCKER"; + case ND_EXT_APX_EVEX_KMOV: return "APX-EVEX-KMOV"; + case ND_EXT_APX_EVEX_PP2: return "APX-EVEX-PP2"; + case ND_EXT_APX_EVEX_SHA: return "APX-EVEX-SHA"; + case ND_EXT_APX_EVEX_RAOINT: return "APX-EVEX-RAO-INT"; + case ND_EXT_APX_EVEX_USER_MSR: return "APX-EVEX-USER-MSR"; + default: return "None"; } } +ND_BOOL +is_hex_digit( + _In_ char Digit + ) +{ + return (Digit >= '0' && Digit <= '9') || + (Digit >= 'A' && Digit <= 'F') || + (Digit >= 'a' && Digit <= 'f'); +} + + BYTE hex_to_bin( - __in char HexByte + _In_ char HexByte ) { // Transforms one hex-digit to a number. @@ -525,10 +658,10 @@ hex_to_bin( INT32 regstr_to_idx( - __in const char* Reg + _In_ const char *Reg ) { - static const char* reg64[] = + static const char *reg64[] = { "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" @@ -547,10 +680,10 @@ regstr_to_idx( _Success_(return) -BOOLEAN +bool match_gpr( - __in const char* Arg, - __out DWORD* Index + _In_ const char *Arg, + _Out_ DWORD *Index ) { // Check if the provided argument is a register. @@ -560,92 +693,103 @@ match_gpr( if (idx >= 0) { *Index = idx; - return TRUE; + return true; } } - return FALSE; + return false; } void print_instruction( - __in SIZE_T Rip, - __in PINSTRUX Instrux, - __in PDISASM_OPTIONS Options + _In_ size_t Rip, + _In_ PINSTRUX Instrux, + _In_ PDISASM_OPTIONS Options ) { char instruxText[ND_MIN_BUF_SIZE]; DWORD k = 0, idx = 0, i = 0; - printf("%p ", (void*)(Rip)); + printf("%016zX ", Rip); if (Options->Highlight) { + +#ifdef WIN32 + // Enable virtual terminal processing on Windows, so we can display colors. + HANDLE consoleHandle = GetStdHandle(STD_OUTPUT_HANDLE); + DWORD consoleMode; + + if (consoleHandle == INVALID_HANDLE_VALUE) + { + return; + } + + if (!GetConsoleMode(consoleHandle, &consoleMode)) + { + return; + } + + SetConsoleMode(consoleHandle, consoleMode | ENABLE_VIRTUAL_TERMINAL_PROCESSING); +#endif + // Display prefixes. - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_INTENSITY); + set_bold_fg_color(FG_White); for (idx = 0; idx < Instrux->PrefLength; idx++, k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); // Display opcodes. - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_GREEN | FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Green); for (idx = 0; idx < (DWORD)(ND_IS_3DNOW(Instrux) ? Instrux->OpLength - 1 : Instrux->OpLength); idx++, k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); // Display modrm and sib. - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_GREEN | FOREGROUND_RED | FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Yellow); for (idx = 0; idx < (DWORD)(Instrux->HasModRm + Instrux->HasSib); idx++, k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); // Display displacement. - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_INTENSITY); - + set_bold_fg_color(FG_Blue); for (idx = 0; idx < (DWORD)(Instrux->DispLength); idx++, k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); // Display relative offset/moffset/immediates. - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_RED | FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Red); for (idx = 0; idx < (DWORD)(Instrux->Imm1Length + Instrux->Imm2Length + Instrux->RelOffsLength + Instrux->MoffsetLength + Instrux->HasSseImm + Instrux->AddrLength); idx++, k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); if (ND_IS_3DNOW(Instrux)) { - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_GREEN | FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Green); for (; k < Instrux->Length; k++) { printf("%02x", Instrux->InstructionBytes[k]); } - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED); + reset_fg_color(); } + +#ifdef WIN32 + // Reset console mode on Windows. + SetConsoleMode(consoleHandle, consoleMode); +#endif } for (; k < Instrux->Length; k++) @@ -700,38 +844,22 @@ print_instruction( tuple_to_string((ND_TUPLE)Instrux->TupleType)); } - if (Instrux->ExceptionClass != ND_EXC_None) + if (Instrux->ExceptionType != ND_EXT_None) { printf(" Exception class: %s, ", - Instrux->ExceptionClass == ND_EXC_SSE_AVX ? "SSE/VEX" : - Instrux->ExceptionClass == ND_EXC_EVEX ? "EVEX" : - Instrux->ExceptionClass == ND_EXC_OPMASK ? "Opmask" : - Instrux->ExceptionClass == ND_EXC_AMX ? "AMX" : "???"); + Instrux->ExceptionType >= ND_EXT_1 && Instrux->ExceptionType <= ND_EXT_14 ? "SSE/VEX" : + Instrux->ExceptionType >= ND_EXT_E1 && Instrux->ExceptionType <= ND_EXT_E12NP ? "EVEX" : + Instrux->ExceptionType >= ND_EXT_K20 && Instrux->ExceptionType <= ND_EXT_K21 ? "Opmask" : + Instrux->ExceptionType >= ND_EXT_AMX_E1 && Instrux->ExceptionType <= ND_EXT_AMX_E6 ? "AMX" : + Instrux->ExceptionType >= ND_EXT_AMX_EVEX_E1 && Instrux->ExceptionType <= ND_EXT_APX_EVEX_USER_MSR ? "APX" : "???"); - switch (Instrux->ExceptionClass) - { - case ND_EXC_SSE_AVX: - printf("exception type: %d\n", Instrux->ExceptionType); - break; - case ND_EXC_EVEX: - printf("exception type: %s\n", exception_evex_to_string((ND_EX_TYPE_EVEX)Instrux->ExceptionType)); - break; - case ND_EXC_OPMASK: - printf("exception type: K%d\n", Instrux->ExceptionType + 19); - break; - case ND_EXC_AMX: - printf("exception type: AMX-E%d\n", Instrux->ExceptionType); - break; - default: - printf("exception type: ???\n"); - break; - } + printf("exception type: %s\n", exception_type_to_string(Instrux->ExceptionType)); } - if (Instrux->FlagsAccess.RegAccess != 0) + if (Instrux->RflAccess != 0) { DWORD fidx, all; - BOOLEAN individual = FALSE; + bool individual = false; char *flags[22] = { "CF", NULL, "PF", NULL, "AF", NULL, "ZF", "SF", "TF", "IF", "DF", "OF", "IOPL",NULL, "NT", NULL, "RF", "VM", "AC", "VIF", "VIP", "ID" }; @@ -748,7 +876,7 @@ print_instruction( continue; } - individual = TRUE; + individual = true; printf("%s: ", flags[fidx]); @@ -854,7 +982,10 @@ print_instruction( Instrux->Operands[i].Access.Access == (ND_ACCESS_COND_READ|ND_ACCESS_WRITE) ? "CRW" : Instrux->Operands[i].Access.Access == ND_ACCESS_PREFETCH ? "P" : "--", optype_to_string(Instrux->Operands[i].Type), (int)Instrux->Operands[i].Size, - (int)Instrux->Operands[i].RawSize, encoding_to_string(Instrux->Operands[i].Encoding) + Instrux->Operands[i].Type == ND_OP_IMM ? Instrux->Operands[i].Info.Immediate.RawSize : + Instrux->Operands[i].Type == ND_OP_OFFS ? Instrux->Operands[i].Info.RelativeOffset.RawSize : + Instrux->Operands[i].Size, + encoding_to_string(Instrux->Operands[i].Encoding) ); if (ND_OP_MEM == Instrux->Operands[i].Type) @@ -975,13 +1106,13 @@ print_instruction( if (Instrux->Operands[i].Decorator.HasBroadcast) { printf(" Decorator: Broadcast %d bytes element %d times\n", - Instrux->Operands[i].Decorator.Broadcast.Size, - Instrux->Operands[i].Decorator.Broadcast.Count); + Instrux->Operands[i].Info.Memory.Broadcast.Size, + Instrux->Operands[i].Info.Memory.Broadcast.Count); } if (Instrux->Operands[i].Decorator.HasMask) { - printf(" Decorator: Mask k%d\n", Instrux->Operands[i].Decorator.Mask.Msk); + printf(" Decorator: Mask k%d\n", Instrux->Operands[i].Decorator.Msk); } if (Instrux->Operands[i].Decorator.HasZero) @@ -1053,13 +1184,13 @@ print_instruction( void handle_disasm( - __in PDISASM_OPTIONS Options + _In_ PDISASM_OPTIONS Options ) { INSTRUX instrux; ND_CONTEXT ctx = { 0 }; unsigned long long icount = 0, istart, iend, start, end, itotal = 0, tilen = 0, ticount = 0; - SIZE_T rip, fsize = Options->Size; + size_t rip, fsize = Options->Size; PBYTE buffer = Options->Buffer; start = clock(); @@ -1099,7 +1230,7 @@ handle_disasm( { if (Options->Print) { - printf("%p ", (void*)(rip + Options->Rip)); + printf("%016zX ", rip + Options->Rip); printf("%02x", buffer[rip]); @@ -1112,6 +1243,7 @@ handle_disasm( { rip += 16; } + else { rip++; @@ -1131,6 +1263,10 @@ handle_disasm( { rip += 16; } + else if (Options->Skip1) + { + rip++; + } else { rip += instrux.Length; @@ -1156,9 +1292,7 @@ handle_shemu( SHEMU_CONTEXT ctx; SHEMU_STATUS shstatus; char *fileName; - HANDLE hFile; - DWORD outSize; - SIZE_T rip = 0, fsize = Options->Size, offset = 0, decFileNameLength = 0, shellSize; + size_t rip = 0, fsize = Options->Size, offset = 0, decFileNameLength = 0, shellSize; char *fNameDecoded; PBYTE buffer = Options->Buffer; @@ -1168,29 +1302,15 @@ handle_shemu( if (fileName == NULL) { - decFileNameLength = sizeof("hex_string_decoded.bin"); - fNameDecoded = (char *)malloc(sizeof(char) * decFileNameLength); + fNameDecoded = "hex_string_decoded.bin"; } else { decFileNameLength = strlen(fileName) + sizeof("_decoded.bin"); - fNameDecoded = (char *)malloc(sizeof(char) * decFileNameLength); - } - - if (NULL == fNameDecoded) - { - printf("Could not allocate file name.\n"); - } - else - { - if (fileName == NULL) - { - sprintf_s(fNameDecoded, decFileNameLength, "hex_string_decoded.bin"); - } - else - { - sprintf_s(fNameDecoded, decFileNameLength, "%s_decoded.bin", fileName); - } + fNameDecoded = malloc(sizeof(char) * decFileNameLength); + + // This is safe, we allocated enough space. + sprintf(fNameDecoded, "%s_decoded.bin", fileName); } if (Options->Offset < PAGE_SIZE) @@ -1202,99 +1322,84 @@ handle_shemu( shellSize = fsize + 0x100; // Allocate the shellcode, stack, shell bitmap and stack bitmaps. - ctx.Shellcode = (uint8_t *)malloc(shellSize); - if (NULL == ctx.Shellcode) - { - printf("Memory error: couldn't allocated %zu bytes!\n", fsize); - goto cleanup_and_exit; - } + ctx.Shellcode = malloc(shellSize); -#define STACK_SIZE 0x2000 - - ctx.Stack = (uint8_t *)malloc(STACK_SIZE); - if (NULL == ctx.Stack) - { - printf("Memory error: couldn't allocated %zu bytes!\n", fsize); - goto cleanup_and_exit; - } - - ctx.Intbuf = (uint8_t *)malloc(shellSize + STACK_SIZE); - if (NULL == ctx.Intbuf) - { - printf("Memory error: couldn't allocated %zu bytes!\n", fsize); - goto cleanup_and_exit; - } +#define STACK_SIZE 0x2000ull + ctx.Stack = malloc(STACK_SIZE); + ctx.Intbuf = malloc(shellSize + STACK_SIZE); memset(ctx.Shellcode, 0, shellSize); memset(ctx.Stack, 0, STACK_SIZE); - memcpy((BYTE *)ctx.Shellcode, (BYTE *)buffer, fsize); + memcpy(ctx.Shellcode, buffer, fsize); memset(ctx.Intbuf, 0, shellSize + STACK_SIZE); // Use the provided RIP, if any. Otherwise, use a hard-coded value. ctx.ShellcodeBase = (rip != 0 ? rip & PAGE_MASK : 0x200000); - ctx.ShellcodeSize = (DWORD)shellSize; + ctx.ShellcodeSize = shellSize; ctx.StackBase = (ctx.ShellcodeBase & PAGE_MASK) - STACK_SIZE - 0x1000; ctx.StackSize = STACK_SIZE; - ctx.IntbufSize = (DWORD)shellSize + STACK_SIZE; + ctx.IntbufSize = shellSize + STACK_SIZE; - ctx.Mode = Options->Mode; - ctx.Ring = Options->Ring; + ctx.ArchType = SHEMU_ARCH_TYPE_X86; - ctx.Registers.RegFlags = NDR_RFLAG_IF | 2; - ctx.Registers.RegRip = ctx.ShellcodeBase + offset; - ctx.Registers.RegRsp = ctx.StackBase + STACK_SIZE / 2; + ctx.Arch.X86.Mode = Options->Mode; + ctx.Arch.X86.Ring = Options->Ring; - if (ctx.Mode == ND_CODE_64) + ctx.Arch.X86.Registers.RegFlags = NDR_RFLAG_IF | 2; + ctx.Arch.X86.Registers.RegRip = ctx.ShellcodeBase + offset; + ctx.Arch.X86.Registers.RegRsp = ctx.StackBase + STACK_SIZE / 2; + + if (ctx.Arch.X86.Mode == ND_CODE_64) { - ctx.Segments.Cs.Selector = (ctx.Ring == 3) ? 0x33 : 0x10; - ctx.Segments.Ds.Selector = (ctx.Ring == 3) ? 0x2b : 0x18; - ctx.Segments.Es.Selector = (ctx.Ring == 3) ? 0x2b : 0x18; - ctx.Segments.Ss.Selector = (ctx.Ring == 3) ? 0x2b : 0x18; - ctx.Segments.Fs.Selector = (ctx.Ring == 3) ? 0x2b : 0x00; - ctx.Segments.Gs.Selector = (ctx.Ring == 3) ? 0x53 : 0x00; + ctx.Arch.X86.Segments.Cs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x33 : 0x10; + ctx.Arch.X86.Segments.Ds.Selector = (ctx.Arch.X86.Ring == 3) ? 0x2b : 0x18; + ctx.Arch.X86.Segments.Es.Selector = (ctx.Arch.X86.Ring == 3) ? 0x2b : 0x18; + ctx.Arch.X86.Segments.Ss.Selector = (ctx.Arch.X86.Ring == 3) ? 0x2b : 0x18; + ctx.Arch.X86.Segments.Fs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x2b : 0x00; + ctx.Arch.X86.Segments.Gs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x53 : 0x00; - ctx.Segments.Fs.Base = 0; - ctx.Segments.Gs.Base = 0x7FFF0000; + ctx.Arch.X86.Segments.Fs.Base = 0; + ctx.Arch.X86.Segments.Gs.Base = 0x7FFF0000; } else { - ctx.Segments.Cs.Selector = (ctx.Ring == 3) ? 0x1b : 0x08; - ctx.Segments.Ds.Selector = (ctx.Ring == 3) ? 0x23 : 0x10; - ctx.Segments.Es.Selector = (ctx.Ring == 3) ? 0x23 : 0x10; - ctx.Segments.Ss.Selector = (ctx.Ring == 3) ? 0x23 : 0x10; - ctx.Segments.Fs.Selector = (ctx.Ring == 3) ? 0x3b : 0x30; - ctx.Segments.Gs.Selector = (ctx.Ring == 3) ? 0x23 : 0x00; + ctx.Arch.X86.Segments.Cs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x1b : 0x08; + ctx.Arch.X86.Segments.Ds.Selector = (ctx.Arch.X86.Ring == 3) ? 0x23 : 0x10; + ctx.Arch.X86.Segments.Es.Selector = (ctx.Arch.X86.Ring == 3) ? 0x23 : 0x10; + ctx.Arch.X86.Segments.Ss.Selector = (ctx.Arch.X86.Ring == 3) ? 0x23 : 0x10; + ctx.Arch.X86.Segments.Fs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x3b : 0x30; + ctx.Arch.X86.Segments.Gs.Selector = (ctx.Arch.X86.Ring == 3) ? 0x23 : 0x00; - ctx.Segments.Fs.Base = 0x7FFF0000; - ctx.Segments.Gs.Base = 0; + ctx.Arch.X86.Segments.Fs.Base = 0x7FFF0000; + ctx.Arch.X86.Segments.Gs.Base = 0; } // Dummy values, to resemble regular CR0/CR4 values. - ctx.Registers.RegCr0 = 0x0000000080050031; - ctx.Registers.RegCr4 = 0x0000000000170678; + ctx.Arch.X86.Registers.RegCr0 = 0x0000000080050031; + ctx.Arch.X86.Registers.RegCr4 = 0x0000000000170678; if (Options->UseShemuRegs) { // Copy the new GPRs - memcpy(&ctx.Registers.RegRax, Options->ShemuRegs, sizeof(Options->ShemuRegs)); + memcpy(&ctx.Arch.X86.Registers.RegRax, Options->ShemuRegs, sizeof(Options->ShemuRegs)); // Update the stack to point to the new RSP, if one exists - if (ctx.Registers.RegRsp != 0) + if (ctx.Arch.X86.Registers.RegRsp != 0) { // Consider the stack base at least with a page before the current RSP. In case of pushes or operations - // which decrease the RSP, we will always give SHEMU_ABORT_BRANCH_OUTSIDE otherwise. - ctx.StackBase = ctx.Registers.RegRsp - 0x1000; + // which decrease the RSP, we will always give SHEMU_ABORT_RIP_OUTSIDE otherwise. + ctx.StackBase = ctx.Arch.X86.Registers.RegRsp - 0x1000; } } - ctx.TibBase = 0x7FFF0000; - ctx.MaxInstructionsCount = 4096; + ctx.MaxInstructionsCount = 10000; ctx.Flags = 0; - ctx.Options = SHEMU_OPT_TRACE_EMULATION; + ctx.Options = SHEMU_OPT_TRACE_EMULATION | SHEMU_OPT_TRACE_MEMORY | SHEMU_OPT_TRACE_STRINGS | SHEMU_OPT_TRACE_LOOPS; ctx.Log = &ShemuLog; ctx.AccessMemory = (ShemuMemAccess)&ShemuAccessMem; + ctx.AccessShellcode = (ShemuMemAccess)&ShemuAccessShellcode; // Configurable thresholds. ctx.NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; @@ -1305,7 +1410,7 @@ handle_shemu( int regs[4] = { 0 }; #if defined(ND_ARCH_X86) || defined(ND_ARCH_X64) - __cpuid(regs, 1); + cpuid(regs, 1); #endif // CPUID leaf function 1, register ECX, bit 25 indicates AES-NI support. @@ -1319,90 +1424,68 @@ handle_shemu( ctx.Options |= SHEMU_OPT_BYPASS_SELF_WRITES; } - shstatus = ShemuEmulate(&ctx); + ctx.Options |= SHEMU_OPT_SUPPORT_APX; - printf("Emulation terminated with status 0x%08x, flags: 0x%llx, %u NOPs, %u total instructions\n", - shstatus, (unsigned long long)ctx.Flags, ctx.NopCount, ctx.InstructionsCount); - if (ctx.Flags & SHEMU_FLAG_NOP_SLED) + shstatus = ShemuX86Emulate(&ctx); + + // Print each set flag after emulation. + printf("Emulation terminated with status 0x%08x, flags: 0x%llx, %llu NOPs, %llu NULLs, %llu total instructions, %llu unique instructions\n", + shstatus, (unsigned long long)ctx.Flags, ctx.NopCount, ctx.NullCount, ctx.InstructionsCount, ctx.UniqueCount); + + struct { - printf(" SHEMU_FLAG_NOP_SLED\n"); - } - if (ctx.Flags & SHEMU_FLAG_LOAD_RIP) + ND_UINT64 Flag; + const char* Name; + } const shemuFlags[] = { +#define FLAGENTRY(f) { .Flag = f, .Name = #f } + FLAGENTRY(SHEMU_FLAG_NOP_SLED), + FLAGENTRY(SHEMU_FLAG_LOAD_RIP), + FLAGENTRY(SHEMU_FLAG_WRITE_SELF), + FLAGENTRY(SHEMU_FLAG_TIB_ACCESS_PEB), + FLAGENTRY(SHEMU_FLAG_SYSCALL), + FLAGENTRY(SHEMU_FLAG_STACK_STR), + FLAGENTRY(SHEMU_FLAG_TIB_ACCESS_WOW32), + FLAGENTRY(SHEMU_FLAG_HEAVENS_GATE), + FLAGENTRY(SHEMU_FLAG_STACK_PIVOT), + FLAGENTRY(SHEMU_FLAG_SUD_ACCESS), + FLAGENTRY(SHEMU_FLAG_KPCR_ACCESS), + FLAGENTRY(SHEMU_FLAG_SWAPGS), + FLAGENTRY(SHEMU_FLAG_SYSCALL_MSR_READ), + FLAGENTRY(SHEMU_FLAG_SYSCALL_MSR_WRITE), + FLAGENTRY(SHEMU_FLAG_SIDT), +#undef FLAGENTRY + }; + + for (uint32_t fli = 0; fli < ARRAYSIZE(shemuFlags); fli++) { - printf(" SHEMU_FLAG_LOAD_RIP\n"); - } - if (ctx.Flags & SHEMU_FLAG_WRITE_SELF) - { - printf(" SHEMU_FLAG_WRITE_SELF\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL) - { - printf(" SHEMU_FLAG_SYSCALL\n"); - } - if (ctx.Flags & SHEMU_FLAG_STACK_STR) - { - printf(" SHEMU_FLAG_STACK_STR\n"); - } - if (ctx.Flags & SHEMU_FLAG_TIB_ACCESS_WOW32) - { - printf(" SHEMU_FLAG_TIB_ACCESS_WOW32\n"); - } - if (ctx.Flags & SHEMU_FLAG_HEAVENS_GATE) - { - printf(" SHEMU_FLAG_HEAVENS_GATE\n"); - } - if (ctx.Flags & SHEMU_FLAG_STACK_PIVOT) - { - printf(" SHEMU_FLAG_STACK_PIVOT\n"); - } - if (ctx.Flags & SHEMU_FLAG_SUD_ACCESS) - { - printf(" SHEMU_FLAG_SUD_ACCESS\n"); - } - if (ctx.Flags & SHEMU_FLAG_KPCR_ACCESS) - { - printf(" SHEMU_FLAG_KPCR_ACCESS\n"); - } - if (ctx.Flags & SHEMU_FLAG_SWAPGS) - { - printf(" SHEMU_FLAG_SWAPGS\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_READ) - { - printf(" SHEMU_FLAG_SYSCALL_MSR_READ\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_WRITE) - { - printf(" SHEMU_FLAG_SYSCALL_MSR_WRITE\n"); - } - if (ctx.Flags & SHEMU_FLAG_SIDT) - { - printf(" SHEMU_FLAG_SIDT\n"); + if (ctx.Flags & shemuFlags[fli].Flag) + { + printf(" %s\n", shemuFlags[fli].Name); + } } if (fNameDecoded != NULL) { - // If a decoded file name is present, dump the code, as it look after emulation, on disk. - // If the shellcode decrypted itself, the decoded file will contain the plain-text version. - hFile = CreateFileA(fNameDecoded, GENERIC_WRITE, FILE_SHARE_READ, NULL, - CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); - if (INVALID_HANDLE_VALUE == hFile) + size_t outSize; + FILE *file = fopen(fNameDecoded, "wb"); + if (file == NULL) { - printf("Could not open the file %s : 0x%08x\n", fNameDecoded, GetLastError()); + printf("Could not create the file %s\n", fNameDecoded); goto cleanup_and_exit; } - WriteFile(hFile, (BYTE *)ctx.Shellcode, (DWORD)fsize, &outSize, NULL); + outSize = fwrite(ctx.Shellcode, 1, fsize, file); + if (outSize == 0) { printf("No bytes written to %s!\n", fNameDecoded); } - CloseHandle(hFile); + fclose(file); } cleanup_and_exit: - if (NULL != fNameDecoded) + if (NULL != fileName && NULL != fNameDecoded) { free(fNameDecoded); } @@ -1424,7 +1507,7 @@ cleanup_and_exit: } -void print_help() +void print_help(void) { uint32_t major, minor, revision; char *date, *time; @@ -1463,30 +1546,32 @@ void print_help() printf(" -o offset - Start processing from the indicated `offset` (default is 0).\n"); printf(" -r rip - Use the indicated `rip` for disassembly (default is 0).\n"); printf(" -v vendor - Set prefered vendor (default is any). The following are valid `vendor` values:\n"); - printf(" intel, amd, cyrix, mpx, any\n"); + printf(" intel, amd, any\n"); printf(" -t feature - Set prefered feature mode (default is all). The following are valid `feature` values (multiple can be used):\n"); printf(" none, all, mpx, cet, cldm, piti\n"); printf("\n"); printf("OPTIONS valid only with decode command:\n"); printf(" -hl - Highlight instruction parts. The colors used are:\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), - FOREGROUND_BLUE|FOREGROUND_GREEN|FOREGROUND_RED|FOREGROUND_INTENSITY); + + set_bold_fg_color(FG_White); printf(" light white prefixes\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_GREEN|FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Green); printf(" light green opcodes\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_GREEN|FOREGROUND_RED|FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Yellow); printf(" light yellow modrm and sib\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_BLUE|FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Blue); printf(" light blue displacement\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_RED|FOREGROUND_INTENSITY); + set_bold_fg_color(FG_Red); printf(" light red relative offset, immediate, address\n"); - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), FOREGROUND_BLUE|FOREGROUND_GREEN|FOREGROUND_RED); + reset_fg_color(); + printf(" -nv - Don't print disassembly. Use this only for performance tests.\n"); printf(" -iv - Print performance statistics.\n"); printf(" -exi - Print extended info about instructions.\n"); printf(" -bits - Print the instruction bit fields.\n"); printf(" -skip16 - Skip 16 bytes after each decoded instruction. Useful when decoding invalid instructions.\n"); + printf(" -skip1 - Skip a single byte after each decoded instruction. Useful when decoding every possible offset.\n"); printf("\n"); printf("OPTIONS valid only with shemu command:\n"); printf(" -reg val - Set register `reg` to value `val` for emulation. `reg` must be the plain 64-bit register name (ie: rax).\n"); @@ -1515,33 +1600,52 @@ void print_help() void cleanup_context( - __inout DISASM_OPTIONS *Options + _Inout_ DISASM_OPTIONS *Options ) { if (Options->InputMode == inputFile) { if (NULL != Options->Buffer) { - UnmapViewOfFile(Options->Buffer); - } - - if (NULL != Options->HandleMapping && INVALID_HANDLE_VALUE != Options->HandleMapping) - { - CloseHandle(Options->HandleMapping); - } - - if (NULL != Options->HandleFile && INVALID_HANDLE_VALUE != Options->HandleFile) - { - CloseHandle(Options->HandleFile); + free(Options->Buffer); } } } +void *read_file(const char *Path, size_t *Size) +{ + void *buffer; + FILE *fd = fopen(Path, "rb"); + if (fd == NULL) + { + printf("fopen failed for \"%s\"\n", Path); + return NULL; + } + + fseek(fd, 0ull, SEEK_END); + *Size = ftell(fd); + rewind(fd); + + buffer = malloc(*Size); + if (buffer != NULL) + { + size_t readCount = fread(buffer, 1, *Size, fd); + if (readCount != *Size) + { + printf("Only %zx bytes were read! Expected %zx\n", readCount, *Size); + *Size = readCount; + } + } + + fclose(fd); + return buffer; +} + _Success_(return) -BOOLEAN +bool parse_input( - __inout DISASM_OPTIONS* Options + _Inout_ DISASM_OPTIONS* Options ) { static BYTE hexbuf[4096]; @@ -1549,102 +1653,85 @@ parse_input( if (inputNone == Options->InputMode) { printf("Expecting an input mode: either -f or -h!\n"); - return FALSE; + return false; } if (inputFile == Options->InputMode) { - // Open the file. - Options->HandleFile = CreateFileA(Options->FileName, GENERIC_READ|GENERIC_WRITE, FILE_SHARE_READ|FILE_SHARE_WRITE, NULL, - OPEN_EXISTING, FILE_ATTRIBUTE_NORMAL, NULL); - if (INVALID_HANDLE_VALUE == Options->HandleFile) + Options->Buffer = read_file(Options->FileName, &Options->Size); + if (Options->Buffer == NULL) { - printf("Couldn't open file '%s': 0x%08x\n", Options->FileName, GetLastError()); + printf("Couldn't read '%s'\n", Options->FileName); cleanup_context(Options); - return FALSE; + return false; } - // Create a file mapping. - Options->HandleMapping = CreateFileMappingA(Options->HandleFile, NULL, PAGE_READWRITE, 0, 0, "DisasmFile"); - if (NULL == Options->HandleMapping) + if (Options->Size == 0) { - printf("Couldn't create file mapping for '%s': 0x%08x\n", Options->FileName, GetLastError()); + printf("The input file '%s' is empty\n", Options->FileName); cleanup_context(Options); - return FALSE; + return false; } - - // Map the file. - Options->Buffer = (BYTE *)MapViewOfFile(Options->HandleMapping, FILE_MAP_ALL_ACCESS, 0, 0, 0); - if (NULL == Options->Buffer) - { - printf("Couldn't map the view for '%s': 0x%08x\n", Options->FileName, GetLastError()); - cleanup_context(Options); - return FALSE; - } - - Options->Size = GetFileSize(Options->HandleFile, NULL); } else { - DWORD idx, sx = 0, mx, of; + DWORD idx = 0; - Options->Size = (DWORD)strlen(Options->FileName); + Options->Size = strlen(Options->FileName); if (Options->Size < 2) { printf("Min 1-byte buffer needed!\n"); - return FALSE; - } - - // Since we expect a hex string, the buffer must be even-sized. - if (Options->Size % 2 == 1) - { - printf("Even-sized hex buffer expected!\n"); - return FALSE; - } - - // If the buffer starts with \x, assume it's escaped format. Note that we only check - // the first two characters for \x - afterwards, we will only look after the hex-digits - // at offsets 2 & 3 inside each 4-characters chunk. - if (Options->FileName[0] == '\\' && Options->FileName[1] == 'x') - { - sx = 1; - } - - // If escaped format is used, buffer must be at least 4 characters long (1 byte). - if (sx && Options->Size < 4) - { - printf("Min 1-byte buffer needed!\n"); - return FALSE; - } - - if (sx) - { - mx = 4; - of = 2; - } - else - { - mx = 2; - of = 0; - } - - // Check for maximum size. - if (Options->Size / mx > sizeof(hexbuf)) - { - printf("Max %zu bytes buffer accepted!\n", sizeof(hexbuf)); - return FALSE; + return false; } // Extract each byte from the provided hex input. - for (idx = 0; idx < Options->Size / mx; idx++) + for (size_t bidx = 0; bidx < Options->Size - 1; ) { - hexbuf[idx] = ((hex_to_bin(Options->FileName[idx * mx + of]) << 4) | - (hex_to_bin(Options->FileName[idx * mx + of + 1]))) & 0xFF; + // '\x' + if (Options->FileName[bidx] == '\\' && Options->FileName[bidx + 1] == 'x') + { + bidx += 2; + continue; + } + + // '0x' + if (Options->FileName[bidx] == '0' && Options->FileName[bidx + 1] == 'x') + { + bidx += 2; + continue; + } + + // '0x' + if (Options->FileName[bidx] == '0' && Options->FileName[bidx + 1] == 'X') + { + bidx += 2; + continue; + } + + // ' ' + // '0x' + if (Options->FileName[bidx] == ' ') + { + bidx += 1; + continue; + } + + if (is_hex_digit(Options->FileName[bidx]) && + is_hex_digit(Options->FileName[bidx + 1])) + { + hexbuf[idx++] = ((hex_to_bin(Options->FileName[bidx]) << 4) | + (hex_to_bin(Options->FileName[bidx + 1]))) & 0xFF; + bidx += 2; + continue; + } + + printf("Unexpected hex-character encountered: %c!\n", Options->FileName[bidx]); + return false; } Options->FileName = NULL; - Options->Size /= sx ? 4 : 2; + Options->Size = idx; Options->Buffer = hexbuf; } @@ -1653,19 +1740,19 @@ parse_input( { printf("The offset exceeds the buffer size!\n"); cleanup_context(Options); - return FALSE; + return false; } - return TRUE; + return true; } _Success_(return) -BOOLEAN +bool parse_arguments( - __in int argc, - __in char* argv[], - __out DISASM_OPTIONS *Options + _In_ int argc, + _In_ char* argv[], + _Out_ DISASM_OPTIONS *Options ) { int i; @@ -1673,7 +1760,7 @@ parse_arguments( if (argc < 2 || NULL == argv) { print_help(); - return FALSE; + return false; } memset(Options, 0, sizeof(*Options)); @@ -1682,7 +1769,7 @@ parse_arguments( Options->Command = commandDecode; Options->Mode = ND_CODE_64; Options->Ring = 3; - Options->Print = TRUE; + Options->Print = true; Options->Vendor = ND_VEND_ANY; Options->Feature = ND_FEAT_ALL; @@ -1701,7 +1788,7 @@ parse_arguments( else { Options->ShemuRegs[gprIdx] = (size_t)strtoull(argv[i + 1], NULL, 0); - Options->UseShemuRegs = TRUE; + Options->UseShemuRegs = true; i++; } } @@ -1735,7 +1822,7 @@ parse_arguments( // Offset inside the provided buffer. if (i + 1 < argc) { - sscanf_s(argv[i + 1], "%zx", &Options->Offset); + Options->Offset = (size_t)strtoull(argv[i + 1], NULL, 0); i++; } } @@ -1744,7 +1831,7 @@ parse_arguments( // Rip. Can be any value, as it's used only for disassembly. if (i + 1 < argc) { - sscanf_s(argv[i + 1], "%zx", &Options->Rip); + Options->Rip = (size_t)strtoull(argv[i + 1], NULL, 0); i++; } } @@ -1756,7 +1843,7 @@ parse_arguments( else if (argv[i][0] == '-' && argv[i][1] == 'b' && argv[i][2] == 'w' && argv[i][3] == 0) { // Bypass self writes in shemu. - Options->BypassSelfWrites = TRUE; + Options->BypassSelfWrites = true; } else if (0 == strcmp(argv[i], "-b16")) { @@ -1783,16 +1870,6 @@ parse_arguments( // Prefer AMD instructions. Options->Vendor = ND_VEND_AMD; } - else if (0 == strcmp(argv[i], "-v geode")) - { - // Prefer Geode instructions. - Options->Vendor = ND_VEND_GEODE; - } - else if (0 == strcmp(argv[i], "-v cyrix")) - { - // Prefer Cyrix instructions. - Options->Vendor = ND_VEND_CYRIX; - } else if (0 == strcmp(argv[i], "-v any")) { // Try to decode everything. @@ -1851,32 +1928,37 @@ parse_arguments( else if (0 == strcmp(argv[i], "-nv")) { // Do not print anything. - Options->Print = FALSE; + Options->Print = false; } else if (0 == strcmp(argv[i], "-hl")) { // Highlight instruction components. - Options->Highlight = TRUE; + Options->Highlight = true; } else if (0 == strcmp(argv[i], "-iv")) { // Print statistics. - Options->Stats = TRUE; + Options->Stats = true; } else if (0 == strcmp(argv[i], "-exi")) { // Print extended instruction information. - Options->ExtendedInfo = TRUE; + Options->ExtendedInfo = true; } else if (0 == strcmp(argv[i], "-bits")) { // Print instruction bitfields. - Options->BitFields = TRUE; + Options->BitFields = true; } else if (0 == strcmp(argv[i], "-skip16")) { // Skip 16 bytes after each decoded instruction. - Options->Skip16 = TRUE; + Options->Skip16 = true; + } + else if (0 == strcmp(argv[i], "-skip1")) + { + // Skip a single byte after each decoded instruction. + Options->Skip1 = true; } else { @@ -1890,17 +1972,16 @@ parse_arguments( if (!parse_input(Options)) { printf("Could not find a valid input!\n"); - return FALSE; + return false; } - return TRUE; + return true; } - int main( - __in int argc, - __in char* argv[] + _In_ int argc, + _In_ char* argv[] ) { DISASM_OPTIONS options = { 0 }; diff --git a/disasmtool/disasmtool.h b/disasmtool/disasmtool.h index 9104155..b1019d3 100644 --- a/disasmtool/disasmtool.h +++ b/disasmtool/disasmtool.h @@ -5,6 +5,24 @@ #ifndef DISASMTOOL_H #define DISASMTOOL_H +#include +#include + +#ifndef WIN32 +#define _In_ +#define _Inout_ +#define _Out_ +#define _Success_(x) + +typedef char CHAR, *PCHAR; +typedef unsigned char BYTE, *PBYTE; + +typedef int32_t INT32; +typedef uint32_t DWORD; + +#define UNREFERENCED_PARAMETER(P) (void)(P) +#define ARRAYSIZE(A) (sizeof(A)/sizeof((A)[0])) +#endif // !WIN32 typedef enum _DISASM_COMMAND { @@ -29,26 +47,24 @@ typedef struct _DISASM_OPTIONS size_t Size; // Buffer size. size_t Offset; // Offset inside the buffer. size_t Rip; // Virtual RIP. - BOOLEAN Highlight; // Highlight instruction components, if true. - BOOLEAN ExtendedInfo; // Display extended instruction info, if true. - BOOLEAN BitFields; // Display the various bitfields inside the instruction, if true. - BOOLEAN Skip16; // Automatically jump over 16 bytes after each instruction. - BOOLEAN Stats; // Display disassembly stats (clocks / instruction, instructions / second), if true. - BOOLEAN Print; // Print instruction disassembly, if true. + bool Highlight; // Highlight instruction components, if true. + bool ExtendedInfo; // Display extended instruction info, if true. + bool BitFields; // Display the various bitfields inside the instruction, if true. + bool Skip16; // Automatically jump over 16 bytes after each instruction. + bool Skip1; // Automatically jump over one single byte after each instruction. + bool Stats; // Display disassembly stats (clocks / instruction, instructions / second), if true. + bool Print; // Print instruction disassembly, if true. uint8_t Mode; // Mode - 16, 32 or 64-bit mode. uint8_t Ring; // Ring - 0, 1, 2 or 3. uint8_t Vendor; // Preffered vendor. uint8_t Feature; // Used features. char *FileName; // Input file, if any. size_t ShemuRegs[ND_MAX_GPR_REGS]; - BOOLEAN UseShemuRegs; // If truue, the registers in ShemuRegs will be used for shemu input. - BOOLEAN BypassSelfWrites; // If true, shemu emulation will ignore self-modifications made by the shellcode. + bool UseShemuRegs; // If truue, the registers in ShemuRegs will be used for shemu input. + bool BypassSelfWrites; // If true, shemu emulation will ignore self-modifications made by the shellcode. // Internal. INPUT_MODE InputMode; - HANDLE HandleFile; - HANDLE HandleMapping; - } DISASM_OPTIONS, *PDISASM_OPTIONS; diff --git a/disasmtool_lix/CMakeLists.txt b/disasmtool_lix/CMakeLists.txt deleted file mode 100644 index 2c2b059..0000000 --- a/disasmtool_lix/CMakeLists.txt +++ /dev/null @@ -1,65 +0,0 @@ -cmake_minimum_required(VERSION 3.16) - -project(disasmtool LANGUAGES CXX) - -# Use Release as the build type if no build type was specified and we're not using a multi-config generator . -if (NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) - message(STATUS "No build type given. Will use 'Release'") - set(CMAKE_BUILD_TYPE - "Release" - CACHE STRING "Choose the type of build." FORCE) - # Set the possible values of build type for cmake-gui. - set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release") -endif () - -add_executable(disasmtool disasmtool.cpp dumpers.cpp rapidjson.cpp) - -target_compile_options( - disasmtool - PRIVATE "$<$:-U_FORTIFY_SOURCE>" - "$<$:-D_FORTIFY_SOURCE=2>" - -Wall - -Wextra - -Wshadow - -Wformat-security - -Wstrict-overflow=2 - -Wno-unused-function - -Wno-multichar - -Werror=format-security - -pipe - -fpie - -fwrapv - -fno-strict-aliasing - -fstack-protector-strong - -ffunction-sections - -fdata-sections - -g3 - -gdwarf-4 - -grecord-gcc-switches - -march=nehalem - -fno-omit-frame-pointer) - -if (NOT TARGET bddisasm) - find_package(bddisasm REQUIRED) -endif () - -find_package(RapidJSON QUIET REQUIRED) - -target_link_libraries(disasmtool PRIVATE bddisasm::bddisasm bddisasm::bdshemu) -# :( https://github.com/satishbabariya/modern-cmake#good-boys-export-their-targets -target_include_directories(disasmtool PRIVATE ${RapidJSON_INCLUDE_DIRS}) - -if ("${CMAKE_BUILD_TYPE}" STREQUAL "Release") - include(CheckIPOSupported) - check_ipo_supported(RESULT USE_IPO) - if (USE_IPO) - set_target_properties(disasmtool PROPERTIES INTERPROCEDURAL_OPTIMIZATION True) - endif () -endif () - -set_target_properties( - disasmtool - PROPERTIES POSITION_INDEPENDENT_CODE ON - CXX_STANDARD 17 - CXX_STANDARD_REQUIRED ON - CXX_EXTENSIONS ON) diff --git a/disasmtool_lix/Makefile b/disasmtool_lix/Makefile deleted file mode 100644 index 17b8709..0000000 --- a/disasmtool_lix/Makefile +++ /dev/null @@ -1,39 +0,0 @@ -.PHONY: all last_build debug release - -CMAKE_BUILD_DIR = build - -CPUCOUNT := $(shell grep -c "^processor" /proc/cpuinfo) - -ifneq (,$(CPUCOUNT)) -EXTRA_MAKE_ARGS := -j$(CPUCOUNT) -endif - -# NINJA := $(shell which ninja 2>/dev/null) - -ifneq (,$(NINJA)) -GENERATOR := "Ninja" -else -GENERATOR := "Unix Makefiles" -endif - -$(shell if [ ! -d $(CMAKE_BUILD_DIR) ]; then mkdir $(CMAKE_BUILD_DIR); fi) - -all: last_build - -last_build: - @cmake -H. -G$(GENERATOR) -B$(CMAKE_BUILD_DIR) -DCMAKE_EXPORT_COMPILE_COMMANDS=ON - @cmake --build $(CMAKE_BUILD_DIR) -- $(EXTRA_MAKE_ARGS) - -debug: CMAKE_BUILD_TYPE := Debug -debug: build - -release: CMAKE_BUILD_TYPE := Release -release: build - -clean: - @if [ -d $(CMAKE_BUILD_DIR) ]; then cmake --build $(CMAKE_BUILD_DIR) --target clean; fi - -reset: - @if [ -d $(CMAKE_BUILD_DIR) ]; then rm -r $(CMAKE_BUILD_DIR); fi - - diff --git a/disasmtool_lix/disasm.hpp b/disasmtool_lix/disasm.hpp deleted file mode 100644 index 96e8c8d..0000000 --- a/disasmtool_lix/disasm.hpp +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#include - -#include -using StringBuffer = rapidjson::StringBuffer; - - -extern "C" -{ - - // On windows, simply include Windows.h -#ifndef _WIN32 -typedef void VOID, *PVOID; -typedef unsigned char BOOLEAN, *PBOOLEAN; -typedef char CHAR, *PCHAR; -typedef unsigned char BYTE, *PBYTE; -typedef unsigned short WORD, *PWORD; -typedef unsigned int DWORD, *PDWORD; -typedef unsigned long long QWORD, *PQWORD; -typedef size_t SIZE_T; -#endif - -#ifndef FALSE -#define FALSE 0 -#endif - -#ifndef TRUE -#define TRUE 1 -#endif - -#ifndef MAX_PATH -#define MAX_PATH 255 -#endif - -// Main disasm header file. -#include "bdshemu.h" -#include "bddisasm.h" - -#include -#include -} - - -#include - - -std::string enc_mode_to_str(const uint8_t enc_mode); -std::string op_type_to_str(const ND_OPERAND_TYPE type); -std::string op_enc_to_str(const ND_OPERAND_ENCODING Encoding); -std::string ins_class_to_str(const ND_INS_CLASS cls); -std::string ins_cat_to_str(ND_INS_CATEGORY category); -std::string ins_set_to_str(ND_INS_SET ins_set); -std::string reg_to_str(const int reg, const ND_REG_TYPE type); -std::string reg_type_to_str(const ND_REG_TYPE type); - -StringBuffer instrux_to_json(INSTRUX *instrux, size_t rip, bool text_only = false); -StringBuffer byte_to_json(uint8_t byte, size_t rip); -StringBuffer disassemble_one(uint8_t *bytes, size_t size, size_t rip, uint8_t bits, uint8_t vendor = ND_VEND_INTEL); - -bool regs_from_json(const std::string &str, SHEMU_GPR_REGS ®s, bool &update_rsp); diff --git a/disasmtool_lix/disasmtool.cpp b/disasmtool_lix/disasmtool.cpp deleted file mode 100644 index 2359dcf..0000000 --- a/disasmtool_lix/disasmtool.cpp +++ /dev/null @@ -1,927 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#include -#include -#include -#include -#include -#include - -#include "external/argparse.h" - -#include "disasm.hpp" - -#define STACK_SIZE 0x2000 -#define PAGE_MASK 0xFFFFFFFFFFFFF000 - -static const long NSEC_PER_SEC = (1000ULL * 1000ULL * 1000ULL); - -static const char *gSpaces[16] = -{ - "", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", - " ", -}; - - -struct options { - size_t rip; - size_t offset; - size_t size; - size_t count; - - uint8_t bits; - - uint8_t vendor; - bool no_color; - bool verbose; - bool dump_stats; - bool interactive; - bool comm; - bool json_output; - bool extended; - - bool shemu; - std::string shctx; - bool kernel; - - std::string in_file; - std::string hex_string; - std::string hex_file; - std::string shctx_file; - std::string shdec_file; - - // From here on, these are set internally - std::unique_ptr bytes; - size_t actual_size; - int address_size; - - bool output_redirected; -}; - - -extern "C" -{ -#if !defined(BDDISASM_HAS_VSNPRINTF) - int nd_vsnprintf_s(char *buffer, size_t sizeOfBuffer, [[maybe_unused]] size_t count, const char *format, va_list argptr) - { - return vsnprintf(buffer, sizeOfBuffer, format, argptr); - } -#endif // !defined(BDDISASM_HAS_VSNPRINTF) - -#if !defined(BDDISASM_HAS_MEMSET) - void * - nd_memset(void *s, int c, size_t n) - { - return memset(s, c, n); - } -#endif // !defined(BDDISASM_HAS_MEMSET) -} - -static bool _hexstring_to_bytes(options &opts) -{ - if (!opts.hex_file.empty()) { - auto f = std::ifstream(opts.hex_file, std::ios::in); - - if (!f.is_open()) { - std::cerr << "Failed to open file " << opts.hex_file << std::endl; - return false; - } - - f.seekg(0, std::ios::end); - opts.hex_string.reserve(f.tellg()); - f.seekg(0, std::ios::beg); - - opts.hex_string.assign((std::istreambuf_iterator(f)), std::istreambuf_iterator()); - } - - if (opts.hex_string.empty()) - return false; - - opts.actual_size = 0; - opts.hex_string.erase(std::remove_if(opts.hex_string.begin(), opts.hex_string.end(), isspace), opts.hex_string.end()); - - // This is the maximum size, not the actual size - auto initial_size = opts.hex_string.length() / 2 + 1; - - opts.bytes = std::make_unique(initial_size); - auto bytes = opts.bytes.get(); - - for (size_t i = 0; i < opts.hex_string.length(); i += 2) { - auto pair = opts.hex_string.substr(i, 2); - char *end_ptr; - - if (pair == "0x" || pair == "0X" || pair == "\\x") - continue; - - auto b = static_cast(std::strtoul(pair.c_str(), &end_ptr, 16)); - - size_t conv_size = static_cast(end_ptr - pair.c_str()); - - if (conv_size != pair.length()) { - std::cerr << "Trying to convert invalid hex number: " << pair << std::endl; - return false; - } - - bytes[opts.actual_size++] = b; - } - - return true; -} - -static bool _load_shctx(options &opts) -{ - if (opts.shctx_file.empty()) - return false; - - auto f = std::ifstream(opts.shctx_file, std::ios::in); - if (!f.is_open()) { - std::cout << "Failed to open file " << opts.shctx_file << std::endl; - return false; - } - - f.seekg(0, std::ios::end); - opts.shctx.reserve(f.tellg()); - f.seekg(0, std::ios::beg); - - opts.shctx.assign((std::istreambuf_iterator(f)), std::istreambuf_iterator()); - - return true; -} - -static bool _file_to_bytes(options &opts) -{ - auto f = std::ifstream(opts.in_file, std::ios::in | std::ios::binary); - - if (!f.is_open()) { - std::cerr << "Failed to open file " << opts.in_file << std::endl; - return false; - } - - f.seekg(0, std::ios::end); - - opts.actual_size = f.tellg(); - - if (opts.offset >= opts.actual_size) { - std::cerr << "Offset bigger than file size" << std::endl; - return false; - } - - f.seekg(0, std::ios::beg); - - opts.bytes = std::make_unique(opts.actual_size); - - f.read(reinterpret_cast(opts.bytes.get()), opts.actual_size); - - return true; -} - -// Don't change the order (on linux these values are color codes) -enum Colors { - Reset = 0, -#if defined(_WIN32) - Red = FOREGROUND_INTENSITY | FOREGROUND_RED, - Green = FOREGROUND_INTENSITY | FOREGROUND_GREEN, - Yellow = FOREGROUND_INTENSITY | FOREGROUND_RED | FOREGROUND_GREEN, - Blue = FOREGROUND_INTENSITY | FOREGROUND_BLUE, - Magenta = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_RED, - Cyan = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_GREEN, - White = FOREGROUND_INTENSITY | FOREGROUND_BLUE | FOREGROUND_GREEN | FOREGROUND_RED, -#elif defined(__unix__) - Red, - Green, - Yellow, - Blue, - Magenta, - Cyan, - White, -#endif -}; - - -static void _set_text_color(Colors color) -{ -#if defined(_WIN32) - static WORD old_attrs = -1; - - if (old_attrs == -1) { - CONSOLE_SCREEN_BUFFER_INFO buffer_info; - GetConsoleScreenBufferInfo(GetStdHandle(STD_OUTPUT_HANDLE), &buffer_info); - old_attrs = buffer_info.wAttributes; - } - - if (color == Reset) - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), old_attrs); - else - SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE), color); -#elif defined(__unix__) - if (color == Reset) - std::cout << "\033[m"; - else - std::cout << "\033[0;3" << color << "m"; -#endif -} - - -static struct timespec diff_time(struct timespec const &end, struct timespec const &start) -{ - struct timespec result; - - if (end.tv_nsec > start.tv_nsec) { - result.tv_sec = end.tv_sec - start.tv_sec; - result.tv_nsec = end.tv_nsec - start.tv_nsec; - } else { - result.tv_sec = end.tv_sec - start.tv_sec - 1; - result.tv_nsec = NSEC_PER_SEC + end.tv_nsec - start.tv_nsec; - } - - return result; -} - - -void print_instruction(const size_t rip, INSTRUX *instrux, const options &opts) -{ - char instruxText[ND_MIN_BUF_SIZE]; - uint32_t k = 0; - - printf("%*zx ", opts.address_size, rip); - - if (!opts.no_color) - { - _set_text_color(Magenta); - for (uint32_t idx = 0; idx < instrux->PrefLength; idx++, k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - _set_text_color(Green); - for (uint32_t idx = 0; idx < (DWORD)(ND_IS_3DNOW(instrux) ? instrux->OpLength - 1 : instrux->OpLength); idx++, k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - _set_text_color(Yellow); - for (uint32_t idx = 0; idx < (DWORD)(instrux->HasModRm + instrux->HasSib); idx++, k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - _set_text_color(Blue); - for (uint32_t idx = 0; idx < (DWORD)(instrux->DispLength); idx++, k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - _set_text_color(Red); - for (uint32_t idx = 0; idx < (DWORD)(instrux->Imm1Length + instrux->Imm2Length + - instrux->RelOffsLength + instrux->MoffsetLength + - instrux->HasSseImm + instrux->AddrLength); idx++, k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - if (ND_IS_3DNOW(instrux)) - { - _set_text_color(Green); - for (; k < instrux->Length; k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - } - - _set_text_color(Reset); - } - - for (; k < instrux->Length; k++) - { - printf("%02x", instrux->InstructionBytes[k]); - } - - std::cout << gSpaces[16 - instrux->Length]; - - NdToText(instrux, rip, sizeof(instruxText), instruxText); - - std::cout << instruxText << std::endl; - - if (opts.extended) { - const uint8_t opsize[3] = { 2, 4, 8 }; - const uint8_t adsize[3] = { 2, 4, 8 }; - const uint8_t veclen[3] = { 16, 32, 64 }; - - printf(" DSIZE: %2d, ASIZE: %2d, VLEN: ", - opsize[instrux->EfOpMode] * 8, adsize[instrux->AddrMode] * 8); - - if (ND_HAS_VECTOR(instrux)) { - printf("%2d\n", veclen[instrux->VecMode] * 8); - } else { - printf("-\n"); - } - - printf(" ISA Set: %s, Ins cat: %s, Ins class: %d, CET tracked: %s\n", - ins_set_to_str(instrux->IsaSet).c_str(), ins_cat_to_str(instrux->Category).c_str(), instrux->Instruction, - instrux->IsCetTracked ? "yes" : "no"); - - if (0 != instrux->CpuidFlag.Flag) { - const char *regs[4] = { "eax", "ecx", "edx", "ebx" }; - - printf(" CPUID leaf: 0x%08x", instrux->CpuidFlag.Leaf); - - if (instrux->CpuidFlag.SubLeaf != ND_CFF_NO_SUBLEAF) - { - printf(", sub-leaf: 0x%08x", instrux->CpuidFlag.SubLeaf); - } - - printf(", reg: %s, bit %u\n", regs[instrux->CpuidFlag.Reg], instrux->CpuidFlag.Bit); - } - - printf(" FLAGS access: "); - - uint32_t all = instrux->FlagsAccess.Tested.Raw | instrux->FlagsAccess.Modified.Raw | instrux->FlagsAccess.Set.Raw - | instrux->FlagsAccess.Cleared.Raw | instrux->FlagsAccess.Undefined.Raw; - const char *flags[22] = { "CF", nullptr, "PF", nullptr, "AF", nullptr, "ZF", "SF", "TF", "IF", "DF", "OF", "IOPL", nullptr, "NT", nullptr, "RF", "VM", "AC", "VIF", "VIP", "ID" }; - - for (uint32_t fidx = 0; fidx < 21; fidx++) { - if (flags[fidx] != nullptr) { - if (0 == (all & (1ULL << fidx))) { - continue; - } - - printf("%s: ", flags[fidx]); - - if (instrux->FlagsAccess.Tested.Raw & (1ULL << fidx)) { - printf("t"); - } - - if (instrux->FlagsAccess.Modified.Raw & (1ULL << fidx)) { - printf("m"); - } - - if (instrux->FlagsAccess.Set.Raw & (1ULL << fidx)) { - printf("1"); - } - - if (instrux->FlagsAccess.Cleared.Raw & (1ULL << fidx)) { - printf("0"); - } - - if (instrux->FlagsAccess.Undefined.Raw & (1ULL << fidx)) { - printf("u"); - } - - printf("; "); - } - } - - printf("\n"); - - printf(" Valid modes: R0: %s, R1: %s, R2: %s, R3: %s, Real: %s, V8086: %s, Prot: %s, Compat: %s, Long: %s, SMM: %s, SGX: %s, TSX: %s, VMXRoot: %s, VMXNonRoot: %s\n", - instrux->ValidModes.Ring0 ? "yes" : "no", - instrux->ValidModes.Ring1 ? "yes" : "no", - instrux->ValidModes.Ring2 ? "yes" : "no", - instrux->ValidModes.Ring3 ? "yes" : "no", - instrux->ValidModes.Real ? "yes" : "no", - instrux->ValidModes.V8086 ? "yes" : "no", - instrux->ValidModes.Protected ? "yes" : "no", - instrux->ValidModes.Compat ? "yes" : "no", - instrux->ValidModes.Long ? "yes" : "no", - instrux->ValidModes.Smm ? "yes" : "no", - instrux->ValidModes.Sgx ? "yes" : "no", - instrux->ValidModes.Tsx ? "yes" : "no", - instrux->ValidModes.VmxRoot ? "yes" : "no", - instrux->ValidModes.VmxNonRoot ? "yes" : "no"); - - for (uint8_t i = 0; i < instrux->OperandsCount; i++) { - printf(" Operand %d %s Type: %10s, Size: %2d, RawSize: %2d, Encoding: %s", i, - instrux->Operands[i].Access.Read && instrux->Operands[i].Access.Write ? "RW" : - instrux->Operands[i].Access.Write ? "-W" : instrux->Operands[i].Access.Read ? "R-" : "--", - op_type_to_str(instrux->Operands[i].Type).c_str(), (int)instrux->Operands[i].Size, - (int)instrux->Operands[i].RawSize, op_enc_to_str(instrux->Operands[i].Encoding).c_str()); - - if (ND_OP_MEM == instrux->Operands[i].Type) { - printf(", "); - - if (instrux->Operands[i].Info.Memory.IsAG) { - printf("Address Generator, "); - } - - if (instrux->Operands[i].Info.Memory.IsBitbase) { - printf("Bitbase Addressing, "); - } - - if (instrux->Operands[i].Info.Memory.IsMib) { - printf("MIB Addressing, "); - } - - if (instrux->Operands[i].Info.Memory.IsVsib) { - printf("VSIB Addressing, "); - } - - if (instrux->Operands[i].Info.Memory.IsStack) { - printf("Stack, "); - } - - if (instrux->Operands[i].Info.Memory.IsShadowStack) { - printf("Shadow Stack, "); - } - } - - if (ND_OP_REG == instrux->Operands[i].Type) { - printf(", RegType: %16s, RegSize: %2u, ", - reg_type_to_str(instrux->Operands[i].Info.Register.Type).c_str(), - instrux->Operands[i].Info.Register.Size); - if (instrux->Operands[i].Info.Register.Type == ND_REG_MSR) - { - printf("RegId: 0x%08x, RegCount: %u\n", - instrux->Operands[i].Info.Register.Reg, - instrux->Operands[i].Info.Register.Count); - } - else - { - printf("RegId: %u, RegCount: %u\n", - instrux->Operands[i].Info.Register.Reg, - instrux->Operands[i].Info.Register.Count); - } - } - - printf("\n"); - - if (instrux->Operands[i].Decorator.HasBroadcast) { - printf(" Decorator: Broadcast %d bytes element %d times\n", - instrux->Operands[i].Decorator.Broadcast.Size, - instrux->Operands[i].Decorator.Broadcast.Count); - } - - if (instrux->Operands[i].Decorator.HasMask) { - printf(" Decorator: Mask k%d\n", instrux->Operands[i].Decorator.Mask.Msk); - } - - if (instrux->Operands[i].Decorator.HasZero) { - printf(" Decorator: Zero (no merging)\n"); - } - } - - printf("\n"); - } -} - - -StringBuffer disassemble_one(uint8_t *bytes, size_t size, size_t rip, uint8_t bits, uint8_t vendor /* = ND_VEND_INTEL */) -{ - INSTRUX instrux; - - auto status = NdDecodeEx2(&instrux, bytes, size, bits, bits, bits, vendor); - if (!ND_SUCCESS(status)) - return byte_to_json(bytes[0], rip); - else - return instrux_to_json(&instrux, rip); -} - -void shemu_log(PCHAR msg) -{ - printf("%s", msg); -} - -ND_BOOL shemu_access_mem(void * /* Ctx */, uint64_t /* Gla */, size_t Size, uint8_t *Buffer, ND_BOOL Store) -{ - if (!Store) - { - memset(Buffer, 0, Size); - } - - return ND_TRUE; -} - -void shemu(options &opts) -{ - SHEMU_CONTEXT ctx = { }; - SHEMU_STATUS shstatus; - - auto stack = std::make_unique(STACK_SIZE); - auto intbuf = std::make_unique(opts.actual_size + STACK_SIZE); - auto shellcode = std::make_unique(opts.actual_size); - - ctx.Stack = stack.get(); - memset(ctx.Stack, 0, STACK_SIZE); - - ctx.Intbuf = intbuf.get(); - memset(ctx.Intbuf, 0, opts.actual_size + STACK_SIZE); - - ctx.Shellcode = shellcode.get(); - memcpy(ctx.Shellcode, opts.bytes.get(), opts.actual_size); - - ctx.ShellcodeSize = opts.actual_size; - ctx.StackSize = STACK_SIZE; - ctx.Registers.RegRsp = 0x101000; - ctx.IntbufSize = opts.actual_size + STACK_SIZE; - - ctx.Registers.RegFlags = NDR_RFLAG_IF | 2; - ctx.Registers.RegRip = opts.rip ? opts.rip : 0x200000; - ctx.Segments.Cs.Selector = 0x10; - ctx.Segments.Ds.Selector = 0x28; - ctx.Segments.Es.Selector = 0x28; - ctx.Segments.Ss.Selector = 0x28; - ctx.Segments.Fs.Selector = 0x30; - ctx.Segments.Fs.Base = 0x7FFF0000; - ctx.Segments.Gs.Selector = 0x30; - ctx.Segments.Gs.Base = 0x7FFF0000; - - // Dummy values, to resemble regular CR0/CR4 values. - ctx.Registers.RegCr0 = 0x0000000080050031; - ctx.Registers.RegCr4 = 0x0000000000170678; - - ctx.Mode = opts.bits; - ctx.Ring = opts.kernel ? 0 : 3; - ctx.TibBase = (opts.bits == ND_DATA_32 ? ctx.Segments.Fs.Base : ctx.Segments.Gs.Base); - ctx.MaxInstructionsCount = 4096; - ctx.Options = SHEMU_OPT_TRACE_EMULATION; - ctx.Log = shemu_log; - ctx.AccessMemory = shemu_access_mem; - - uint32_t eax, ebx, ecx, edx; - - eax = ebx = ecx = edx = 0; - - __get_cpuid(1, &eax, &ebx, &ecx, &edx); - - if (!!(ecx & (1UL << 25))) - { - ctx.Options |= SHEMU_OPT_SUPPORT_AES; - } - - // Configurable thresholds. - ctx.NopThreshold = SHEMU_DEFAULT_NOP_THRESHOLD; - ctx.StrThreshold = SHEMU_DEFAULT_STR_THRESHOLD; - ctx.MemThreshold = SHEMU_DEFAULT_MEM_THRESHOLD; - - bool update_rsp = false; - - if (!opts.shctx.empty() && !regs_from_json(opts.shctx, ctx.Registers, update_rsp)) { - std::cerr << "Failed to parse context file." << std::endl; - return; - } - - // Consider the stack base at least with a page before the current RSP. In case of pushes or operations - // which decrease the RSP, we will always give SHEMU_ABORT_BRANCH_OUTSIDE otherwise. - ctx.StackBase = ctx.Registers.RegRsp - 0x1000; - ctx.ShellcodeBase = (ctx.Registers.RegRip ? ctx.Registers.RegRip & PAGE_MASK : 0x200000); - - shstatus = ShemuEmulate(&ctx); - - printf("Emulation terminated with status 0x%08x, flags: 0x%llx, %u NOPs\n", - shstatus, (unsigned long long)ctx.Flags, ctx.NopCount); - if (ctx.Flags & SHEMU_FLAG_NOP_SLED) - { - printf(" SHEMU_FLAG_NOP_SLED\n"); - } - if (ctx.Flags & SHEMU_FLAG_LOAD_RIP) - { - printf(" SHEMU_FLAG_LOAD_RIP\n"); - } - if (ctx.Flags & SHEMU_FLAG_WRITE_SELF) - { - printf(" SHEMU_FLAG_WRITE_SELF\n"); - } - if (ctx.Flags & SHEMU_FLAG_TIB_ACCESS) - { - printf(" SHEMU_FLAG_TIB_ACCESS\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL) - { - printf(" SHEMU_FLAG_SYSCALL\n"); - } - if (ctx.Flags & SHEMU_FLAG_STACK_STR) - { - printf(" SHEMU_FLAG_STACK_STR\n"); - } - if (ctx.Flags & SHEMU_FLAG_KPCR_ACCESS) - { - printf(" SHEMU_FLAG_KPCR_ACCESS\n"); - } - if (ctx.Flags & SHEMU_FLAG_SWAPGS) - { - printf(" SHEMU_FLAG_SWAPGS\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_READ) - { - printf(" SHEMU_FLAG_SYSCALL_MSR_READ\n"); - } - if (ctx.Flags & SHEMU_FLAG_SYSCALL_MSR_WRITE) - { - printf(" SHEMU_FLAG_SYSCALL_MSR_WRITE\n"); - } - - if (!opts.shdec_file.empty()) { - auto f = std::ofstream(opts.shdec_file, std::ios::out | std::ios::binary); - - if (!f.is_open()) - std::cerr << "Failed to open file " << opts.shdec_file<< std::endl; - else - f.write(reinterpret_cast(ctx.Shellcode), ctx.ShellcodeSize); - } -} - -size_t disassemble(options &opts) -{ - struct timespec start; - clock_gettime(CLOCK_THREAD_CPUTIME_ID, &start); - - size_t icount = 0, miss_count = 0, ibytes = 0; - size_t rel_rip = opts.offset; - size_t total_disasm = 0; - auto bytes = opts.bytes.get(); - auto disasm_size = std::min(opts.actual_size - opts.offset, opts.size); - - opts.address_size = int(std::ceil(((8 * sizeof(opts.actual_size)) - __builtin_clzll(opts.actual_size)) / 4.0)); - - while ((total_disasm < disasm_size) && (icount < opts.count)) { - INSTRUX instrux; - - auto status = NdDecodeEx2(&instrux, - &bytes[rel_rip], - opts.actual_size - rel_rip, - opts.bits, - opts.bits, - opts.bits, - opts.vendor); - - if (!ND_SUCCESS(status)) { - if (!opts.dump_stats) { - - if (opts.json_output) { - auto j = byte_to_json(bytes[rel_rip], rel_rip + opts.rip); - std::cout << j.GetString() << std::endl; - } else { - printf("%*zx ", opts.address_size, rel_rip + opts.rip); - printf("%02x", bytes[rel_rip]); - printf("%s", gSpaces[16 - opts.address_size]); - printf("db 0x%02x\n", bytes[rel_rip]); - } - } - - rel_rip++; - total_disasm++; - - miss_count++; - } else { - icount++; - ibytes += instrux.Length; - - if (!opts.dump_stats) { - if (opts.json_output) { - auto j = instrux_to_json(&instrux, rel_rip + opts.rip); - std::cout << j.GetString() << std::endl; - } else - print_instruction(rel_rip + opts.rip, &instrux, opts); - } else if (opts.json_output) - instrux_to_json(&instrux, rel_rip + opts.rip); - - rel_rip += instrux.Length; - total_disasm += instrux.Length; - } - } - - struct timespec end; - clock_gettime(CLOCK_THREAD_CPUTIME_ID, &end); - - if (opts.dump_stats) - { - auto result = diff_time(end, start); - - long total_ns = result.tv_sec * NSEC_PER_SEC + result.tv_nsec; - - printf("Disassembled %zu instructions took %ld.%09ld seconds, %lu ns / instr.\n", - icount, result.tv_sec, result.tv_nsec, total_ns / icount); - printf("Invalid: %zu/%zu (%.2f) bytes\n", miss_count, ibytes, - (static_cast(miss_count) / static_cast(disasm_size)) * 100.0); - } - - opts.rip += rel_rip; - - return icount; -} - - -static bool _validate_and_fix_args(options& opts) -{ - if (!opts.interactive && !opts.comm) { - int total = 0; - - if (!opts.hex_string.empty()) - total++; - - if (!opts.hex_file.empty()) - total++; - - if (!opts.in_file.empty()) - total++; - - if (total == 0) { - std::cerr << "Give hex, file or hex-file..." << std::endl; - return false; - } else if (total > 1) { - std::cerr << "Only one of hex, file or hex-file can be present..." << std::endl; - return false; - } - } - - if (opts.interactive || opts.comm) { - if (!opts.in_file.empty() || !opts.hex_string.empty() || !opts.hex_file.empty()) { - std::cerr << "Interactive mode doesn't work with file, hex-string or hex-file" << std::endl; - return false; - } - - if (opts.size || opts.count || opts.offset) { - std::cerr << "Interactive mode doesn't work with size, count or offset" << std::endl; - return false; - } - } - - switch (opts.bits) { - case 64: - opts.bits = ND_DATA_64; - break; - - case 32: - opts.bits = ND_DATA_32; - break; - - case 16: - opts.bits = ND_DATA_16; - break; - - default: - std::cerr << "Please give --bits [64,32,16]" << std::endl; - return false; - } - - if (0 == opts.size) - opts.size = std::numeric_limits::max(); - - if (0 == opts.count) - opts.count = std::numeric_limits::max(); - - if (!isatty(fileno(stdout))) - opts.output_redirected = true; - - if (!opts.hex_file.empty()) - opts.shdec_file = opts.hex_file + "_decoded.bin"; - else if (!opts.in_file.empty()) - opts.shdec_file = opts.in_file + "_decoded.bin"; - else - opts.shdec_file = "hex_string_decoded.bin"; - - return true; -} - - -static size_t _get_hex_opt(argparse::ArgumentParser &parser, const std::string &field) -{ - return std::strtoul(parser.get(field).c_str(), nullptr, 0); -} - - -int main(int argc, const char **argv) -{ - auto opts = options{}; - - auto parser = argparse::ArgumentParser(argv[0], "Disassembler tool for Linux"); - - parser.add_argument("-i", "--interactive", "Interactive mode", false); - parser.add_argument("-c", "--comm", "Comm mode", false); - parser.add_argument("-r", "--rip", "Use this rip to disassemble", false); - parser.add_argument("-f", "--file", "Use this input file", false); - parser.add_argument("-x", "--hex", "Use this hex-string", false); - parser.add_argument("--hexfile", "Use this input file as a hex-string", false); - parser.add_argument("--no-color", "Don't use colors", false); - parser.add_argument("--offset", "Use this offset in file/hex-string", false); - parser.add_argument("--size", "Only disasemble this size from file/hex-string", false); - parser.add_argument("--count", "Only disasemble this many instructions", false); - parser.add_argument("--stats", "Dump statistics (time, count, etc.)", false); - parser.add_argument("-b", "--bits", "Use the arch [16, 32, 64]", false); - parser.add_argument("--verbose", "Verbose mode", false); - parser.add_argument("--json", "Output to json", false); - parser.add_argument("--extended", "Extended instruction info", false); - parser.add_argument("--shemu", "Emulate the input hexfile", false); - parser.add_argument("--kernel", "Kernel mode for shemu context", false); - parser.add_argument("--shctx", "Shemu context file. Must be a JSON file.", false); - - parser.enable_help(); - - auto err = parser.parse(argc, argv); - if (err) { - std::cout << err << std::endl; - return -1; - } - - if (parser.exists("help")) { - parser.print_help(); - return 0; - } - - opts.bits = parser.get("bits"); - opts.interactive = parser.exists("interactive"); - opts.comm = parser.exists("comm"); - opts.offset = _get_hex_opt(parser, "offset"); - opts.size = _get_hex_opt(parser, "size"); - opts.count = _get_hex_opt(parser, "count"); - opts.rip = _get_hex_opt(parser, "rip"); - opts.in_file = parser.get("file"); - opts.hex_string = parser.get("hex"); - opts.hex_file = parser.get("hexfile"); - opts.no_color = parser.exists("no-color"); - opts.dump_stats = parser.exists("stats"); - opts.verbose = parser.exists("verbose"); - opts.json_output = parser.exists("json"); - opts.extended = parser.exists("extended"); - opts.shemu = parser.exists("shemu"); - opts.kernel = parser.exists("kernel"); - opts.shctx_file = parser.get("shctx"); - - if (opts.verbose) { - std::cout << "interactive: " << opts.interactive << std::endl; - std::cout << "comm: " << opts.comm << std::endl; - std::cout << "rip: " << opts.rip << std::endl; - std::cout << "bits: " << static_cast(opts.bits) << std::endl; - std::cout << "offset: " << opts.offset << std::endl; - std::cout << "size: " << opts.offset << std::endl; - std::cout << "count: " << opts.count << std::endl; - std::cout << "in_file: " << opts.in_file << std::endl; - std::cout << "no-color: " << opts.no_color << std::endl; - std::cout << "stats: " << opts.dump_stats << std::endl; - std::cout << "hex: " << opts.hex_string << std::endl; - std::cout << "json: " << opts.json_output << std::endl; - std::cout << "extended: " << opts.extended << std::endl; - std::cout << "shemu:" << opts.shemu << std::endl; - std::cout << "kernel:" << opts.kernel << std::endl; - std::cout << "shctx:" << opts.shctx_file << std::endl; - } - - if (!_validate_and_fix_args(opts)) { - return 1; - } - - if (!opts.interactive && !opts.comm) { - if (!opts.hex_string.empty() || !opts.hex_file.empty()) { - if (!_hexstring_to_bytes(opts)) - return 1; - } else if (!opts.in_file.empty()) { - if (!_file_to_bytes(opts)) - return 1; - } - - if (opts.offset >= opts.actual_size) - return 1; - - if (!opts.shemu) { - disassemble(opts); - } - else { - _load_shctx(opts); - shemu(opts); - } - - } else { - while (true) { - opts.hex_string.clear(); - - if (!opts.comm) - std::cout << ">> "; - - std::getline(std::cin, opts.hex_string); - - if (opts.hex_string == "q" - || opts.hex_string == "quit" - || opts.hex_string == "exit" - || opts.hex_string.empty()) { - - if (!opts.comm) - std::cout << "Bye!" << std::endl; - - break; - } - - _hexstring_to_bytes(opts); - - disassemble(opts); - - std::cout.flush(); - } - } - - return 0; -} diff --git a/disasmtool_lix/dumpers.cpp b/disasmtool_lix/dumpers.cpp deleted file mode 100644 index abf94b6..0000000 --- a/disasmtool_lix/dumpers.cpp +++ /dev/null @@ -1,2119 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#include "disasm.hpp" - - -std::string enc_mode_to_str(const uint8_t enc_mode) -{ - switch (enc_mode) { - case ND_ENCM_LEGACY: return "legacy"; - case ND_ENCM_XOP: return "xop"; - case ND_ENCM_VEX: return "vex"; - case ND_ENCM_EVEX: return "evex"; - } - - return ""; -} - - -std::string op_enc_to_str(const ND_OPERAND_ENCODING Encoding) -{ - switch (Encoding) { - case ND_OPE_NP: return "NP"; - case ND_OPE_R: return "R"; - case ND_OPE_M: return "M"; - case ND_OPE_V: return "V"; - case ND_OPE_O: return "O"; - case ND_OPE_I: return "I"; - case ND_OPE_D: return "D"; - case ND_OPE_C: return "C"; - case ND_OPE_1: return "1"; - case ND_OPE_A: return "A"; - case ND_OPE_L: return "L"; - case ND_OPE_E: return "E"; - case ND_OPE_S: return "S"; - default: return ""; - } -} - - -std::string op_type_to_str(const ND_OPERAND_TYPE type) -{ - switch(type) { - case ND_OP_NOT_PRESENT: - return "not_present"; - case ND_OP_REG: - return "register"; - case ND_OP_MEM: - return "memory"; - case ND_OP_IMM: - return "immediate"; - case ND_OP_OFFS: - return "offset"; - case ND_OP_ADDR: - return "address"; - case ND_OP_CONST: - return "const"; - case ND_OP_BANK: - return "bank"; - } - - return ""; -} - - -std::string ins_class_to_str(const ND_INS_CLASS cls) -{ - switch (cls) { - case ND_INS_INVALID: return "invalid"; - case ND_INS_AAA: return "aaa"; - case ND_INS_AAD: return "aad"; - case ND_INS_AADD: return "aadd"; - case ND_INS_AAM: return "aam"; - case ND_INS_AAND: return "aand"; - case ND_INS_AAS: return "aas"; - case ND_INS_ADC: return "adc"; - case ND_INS_ADCX: return "adcx"; - case ND_INS_ADD: return "add"; - case ND_INS_ADDPD: return "addpd"; - case ND_INS_ADDPS: return "addps"; - case ND_INS_ADDSD: return "addsd"; - case ND_INS_ADDSS: return "addss"; - case ND_INS_ADDSUBPD: return "addsubpd"; - case ND_INS_ADDSUBPS: return "addsubps"; - case ND_INS_ADOX: return "adox"; - case ND_INS_AESDEC: return "aesdec"; - case ND_INS_AESDEC128KL: return "aesdec128kl"; - case ND_INS_AESDEC256KL: return "aesdec256kl"; - case ND_INS_AESDECLAST: return "aesdeclast"; - case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl"; - case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl"; - case ND_INS_AESENC: return "aesenc"; - case ND_INS_AESENC128KL: return "aesenc128kl"; - case ND_INS_AESENC256KL: return "aesenc256kl"; - case ND_INS_AESENCLAST: return "aesenclast"; - case ND_INS_AESENCWIDE128KL: return "aesencwide128kl"; - case ND_INS_AESENCWIDE256KL: return "aesencwide256kl"; - case ND_INS_AESIMC: return "aesimc"; - case ND_INS_AESKEYGENASSIST: return "aeskeygenassist"; - case ND_INS_ALTINST: return "altinst"; - case ND_INS_AND: return "and"; - case ND_INS_ANDN: return "andn"; - case ND_INS_ANDNPD: return "andnpd"; - case ND_INS_ANDNPS: return "andnps"; - case ND_INS_ANDPD: return "andpd"; - case ND_INS_ANDPS: return "andps"; - case ND_INS_AOR: return "aor"; - case ND_INS_ARPL: return "arpl"; - case ND_INS_AXOR: return "axor"; - case ND_INS_BEXTR: return "bextr"; - case ND_INS_BLCFILL: return "blcfill"; - case ND_INS_BLCI: return "blci"; - case ND_INS_BLCIC: return "blcic"; - case ND_INS_BLCMSK: return "blcmsk"; - case ND_INS_BLCS: return "blcs"; - case ND_INS_BLENDPD: return "blendpd"; - case ND_INS_BLENDPS: return "blendps"; - case ND_INS_BLENDVPD: return "blendvpd"; - case ND_INS_BLENDVPS: return "blendvps"; - case ND_INS_BLSFILL: return "blsfill"; - case ND_INS_BLSI: return "blsi"; - case ND_INS_BLSIC: return "blsic"; - case ND_INS_BLSMSK: return "blsmsk"; - case ND_INS_BLSR: return "blsr"; - case ND_INS_BNDCL: return "bndcl"; - case ND_INS_BNDCN: return "bndcn"; - case ND_INS_BNDCU: return "bndcu"; - case ND_INS_BNDLDX: return "bndldx"; - case ND_INS_BNDMK: return "bndmk"; - case ND_INS_BNDMOV: return "bndmov"; - case ND_INS_BNDSTX: return "bndstx"; - case ND_INS_BOUND: return "bound"; - case ND_INS_BSF: return "bsf"; - case ND_INS_BSR: return "bsr"; - case ND_INS_BSWAP: return "bswap"; - case ND_INS_BT: return "bt"; - case ND_INS_BTC: return "btc"; - case ND_INS_BTR: return "btr"; - case ND_INS_BTS: return "bts"; - case ND_INS_BZHI: return "bzhi"; - case ND_INS_CALLFD: return "callfd"; - case ND_INS_CALLFI: return "callfi"; - case ND_INS_CALLNI: return "callni"; - case ND_INS_CALLNR: return "callnr"; - case ND_INS_CBW: return "cbw"; - case ND_INS_CDQ: return "cdq"; - case ND_INS_CDQE: return "cdqe"; - case ND_INS_CLAC: return "clac"; - case ND_INS_CLC: return "clc"; - case ND_INS_CLD: return "cld"; - case ND_INS_CLDEMOTE: return "cldemote"; - case ND_INS_CLEVICT0: return "clevict0"; - case ND_INS_CLEVICT1: return "clevict1"; - case ND_INS_CLFLUSH: return "clflush"; - case ND_INS_CLFLUSHOPT: return "clflushopt"; - case ND_INS_CLGI: return "clgi"; - case ND_INS_CLI: return "cli"; - case ND_INS_CLRSSBSY: return "clrssbsy"; - case ND_INS_CLTS: return "clts"; - case ND_INS_CLUI: return "clui"; - case ND_INS_CLWB: return "clwb"; - case ND_INS_CLZERO: return "clzero"; - case ND_INS_CMC: return "cmc"; - case ND_INS_CMOVcc: return "cmovcc"; - case ND_INS_CMP: return "cmp"; - case ND_INS_CMPBEXADD: return "cmpbexadd"; - case ND_INS_CMPCXADD: return "cmpcxadd"; - case ND_INS_CMPLEXADD: return "cmplexadd"; - case ND_INS_CMPLXADD: return "cmplxadd"; - case ND_INS_CMPNBEXADD: return "cmpnbexadd"; - case ND_INS_CMPNCXADD: return "cmpncxadd"; - case ND_INS_CMPNLEXADD: return "cmpnlexadd"; - case ND_INS_CMPNLXADD: return "cmpnlxadd"; - case ND_INS_CMPNOXADD: return "cmpnoxadd"; - case ND_INS_CMPNPXADD: return "cmpnpxadd"; - case ND_INS_CMPNSXADD: return "cmpnsxadd"; - case ND_INS_CMPNZXADD: return "cmpnzxadd"; - case ND_INS_CMPOXADD: return "cmpoxadd"; - case ND_INS_CMPPD: return "cmppd"; - case ND_INS_CMPPS: return "cmpps"; - case ND_INS_CMPPXADD: return "cmppxadd"; - case ND_INS_CMPS: return "cmps"; - case ND_INS_CMPSD: return "cmpsd"; - case ND_INS_CMPSS: return "cmpss"; - case ND_INS_CMPSXADD: return "cmpsxadd"; - case ND_INS_CMPXCHG: return "cmpxchg"; - case ND_INS_CMPXCHG16B: return "cmpxchg16b"; - case ND_INS_CMPXCHG8B: return "cmpxchg8b"; - case ND_INS_CMPZXADD: return "cmpzxadd"; - case ND_INS_COMISD: return "comisd"; - case ND_INS_COMISS: return "comiss"; - case ND_INS_CPUID: return "cpuid"; - case ND_INS_CPU_READ: return "cpuread"; - case ND_INS_CPU_WRITE: return "cpuwrite"; - case ND_INS_CQO: return "cqo"; - case ND_INS_CRC32: return "crc32"; - case ND_INS_CVTDQ2PD: return "cvtdq2pd"; - case ND_INS_CVTDQ2PS: return "cvtdq2ps"; - case ND_INS_CVTPD2DQ: return "cvtpd2dq"; - case ND_INS_CVTPD2PI: return "cvtpd2pi"; - case ND_INS_CVTPD2PS: return "cvtpd2ps"; - case ND_INS_CVTPI2PD: return "cvtpi2pd"; - case ND_INS_CVTPI2PS: return "cvtpi2ps"; - case ND_INS_CVTPS2DQ: return "cvtps2dq"; - case ND_INS_CVTPS2PD: return "cvtps2pd"; - case ND_INS_CVTPS2PI: return "cvtps2pi"; - case ND_INS_CVTSD2SI: return "cvtsd2si"; - case ND_INS_CVTSD2SS: return "cvtsd2ss"; - case ND_INS_CVTSI2SD: return "cvtsi2sd"; - case ND_INS_CVTSI2SS: return "cvtsi2ss"; - case ND_INS_CVTSS2SD: return "cvtss2sd"; - case ND_INS_CVTSS2SI: return "cvtss2si"; - case ND_INS_CVTTPD2DQ: return "cvttpd2dq"; - case ND_INS_CVTTPD2PI: return "cvttpd2pi"; - case ND_INS_CVTTPS2DQ: return "cvttps2dq"; - case ND_INS_CVTTPS2PI: return "cvttps2pi"; - case ND_INS_CVTTSD2SI: return "cvttsd2si"; - case ND_INS_CVTTSS2SI: return "cvttss2si"; - case ND_INS_CWD: return "cwd"; - case ND_INS_CWDE: return "cwde"; - case ND_INS_DAA: return "daa"; - case ND_INS_DAS: return "das"; - case ND_INS_DEC: return "dec"; - case ND_INS_DELAY: return "delay"; - case ND_INS_DIV: return "div"; - case ND_INS_DIVPD: return "divpd"; - case ND_INS_DIVPS: return "divps"; - case ND_INS_DIVSD: return "divsd"; - case ND_INS_DIVSS: return "divss"; - case ND_INS_DMINT: return "dmint"; - case ND_INS_DPPD: return "dppd"; - case ND_INS_DPPS: return "dpps"; - case ND_INS_EMMS: return "emms"; - case ND_INS_ENCLS: return "encls"; - case ND_INS_ENCLU: return "enclu"; - case ND_INS_ENCLV: return "enclv"; - case ND_INS_ENCODEKEY128: return "encodekey128"; - case ND_INS_ENCODEKEY256: return "encodekey256"; - case ND_INS_ENDBR: return "endbr"; - case ND_INS_ENQCMD: return "enqcmd"; - case ND_INS_ENQCMDS: return "enqcmds"; - case ND_INS_ENTER: return "enter"; - case ND_INS_ERETS: return "erets"; - case ND_INS_ERETU: return "eretu"; - case ND_INS_EXTRACTPS: return "extractps"; - case ND_INS_EXTRQ: return "extrq"; - case ND_INS_F2XM1: return "f2xm1"; - case ND_INS_FABS: return "fabs"; - case ND_INS_FADD: return "fadd"; - case ND_INS_FADDP: return "faddp"; - case ND_INS_FBLD: return "fbld"; - case ND_INS_FBSTP: return "fbstp"; - case ND_INS_FCHS: return "fchs"; - case ND_INS_FCMOVB: return "fcmovb"; - case ND_INS_FCMOVBE: return "fcmovbe"; - case ND_INS_FCMOVE: return "fcmove"; - case ND_INS_FCMOVNB: return "fcmovnb"; - case ND_INS_FCMOVNBE: return "fcmovnbe"; - case ND_INS_FCMOVNE: return "fcmovne"; - case ND_INS_FCMOVNU: return "fcmovnu"; - case ND_INS_FCMOVU: return "fcmovu"; - case ND_INS_FCOM: return "fcom"; - case ND_INS_FCOMI: return "fcomi"; - case ND_INS_FCOMIP: return "fcomip"; - case ND_INS_FCOMP: return "fcomp"; - case ND_INS_FCOMPP: return "fcompp"; - case ND_INS_FCOS: return "fcos"; - case ND_INS_FDECSTP: return "fdecstp"; - case ND_INS_FDIV: return "fdiv"; - case ND_INS_FDIVP: return "fdivp"; - case ND_INS_FDIVR: return "fdivr"; - case ND_INS_FDIVRP: return "fdivrp"; - case ND_INS_FEMMS: return "femms"; - case ND_INS_FFREE: return "ffree"; - case ND_INS_FFREEP: return "ffreep"; - case ND_INS_FIADD: return "fiadd"; - case ND_INS_FICOM: return "ficom"; - case ND_INS_FICOMP: return "ficomp"; - case ND_INS_FIDIV: return "fidiv"; - case ND_INS_FIDIVR: return "fidivr"; - case ND_INS_FILD: return "fild"; - case ND_INS_FIMUL: return "fimul"; - case ND_INS_FINCSTP: return "fincstp"; - case ND_INS_FIST: return "fist"; - case ND_INS_FISTP: return "fistp"; - case ND_INS_FISTTP: return "fisttp"; - case ND_INS_FISUB: return "fisub"; - case ND_INS_FISUBR: return "fisubr"; - case ND_INS_FLD: return "fld"; - case ND_INS_FLD1: return "fld1"; - case ND_INS_FLDCW: return "fldcw"; - case ND_INS_FLDENV: return "fldenv"; - case ND_INS_FLDL2E: return "fldl2e"; - case ND_INS_FLDL2T: return "fldl2t"; - case ND_INS_FLDLG2: return "fldlg2"; - case ND_INS_FLDLN2: return "fldln2"; - case ND_INS_FLDPI: return "fldpi"; - case ND_INS_FLDZ: return "fldz"; - case ND_INS_FMUL: return "fmul"; - case ND_INS_FMULP: return "fmulp"; - case ND_INS_FNCLEX: return "fnclex"; - case ND_INS_FNDISI: return "fndisi"; - case ND_INS_FNINIT: return "fninit"; - case ND_INS_FNOP: return "fnop"; - case ND_INS_FNSAVE: return "fnsave"; - case ND_INS_FNSTCW: return "fnstcw"; - case ND_INS_FNSTENV: return "fnstenv"; - case ND_INS_FNSTSW: return "fnstsw"; - case ND_INS_FPATAN: return "fpatan"; - case ND_INS_FPREM: return "fprem"; - case ND_INS_FPREM1: return "fprem1"; - case ND_INS_FPTAN: return "fptan"; - case ND_INS_FRINEAR: return "frinear"; - case ND_INS_FRNDINT: return "frndint"; - case ND_INS_FRSTOR: return "frstor"; - case ND_INS_FSCALE: return "fscale"; - case ND_INS_FSIN: return "fsin"; - case ND_INS_FSINCOS: return "fsincos"; - case ND_INS_FSQRT: return "fsqrt"; - case ND_INS_FST: return "fst"; - case ND_INS_FSTDW: return "fstdw"; - case ND_INS_FSTP: return "fstp"; - case ND_INS_FSTPNCE: return "fstpnce"; - case ND_INS_FSTSG: return "fstsg"; - case ND_INS_FSUB: return "fsub"; - case ND_INS_FSUBP: return "fsubp"; - case ND_INS_FSUBR: return "fsubr"; - case ND_INS_FSUBRP: return "fsubrp"; - case ND_INS_FTST: return "ftst"; - case ND_INS_FUCOM: return "fucom"; - case ND_INS_FUCOMI: return "fucomi"; - case ND_INS_FUCOMIP: return "fucomip"; - case ND_INS_FUCOMP: return "fucomp"; - case ND_INS_FUCOMPP: return "fucompp"; - case ND_INS_FXAM: return "fxam"; - case ND_INS_FXCH: return "fxch"; - case ND_INS_FXRSTOR: return "fxrstor"; - case ND_INS_FXRSTOR64: return "fxrstor64"; - case ND_INS_FXSAVE: return "fxsave"; - case ND_INS_FXSAVE64: return "fxsave64"; - case ND_INS_FXTRACT: return "fxtract"; - case ND_INS_FYL2X: return "fyl2x"; - case ND_INS_FYL2XP1: return "fyl2xp1"; - case ND_INS_GETSEC: return "getsec"; - case ND_INS_GF2P8AFFINEINVQB: return "gf2p8affineinvqb"; - case ND_INS_GF2P8AFFINEQB: return "gf2p8affineqb"; - case ND_INS_GF2P8MULB: return "gf2p8mulb"; - case ND_INS_HADDPD: return "haddpd"; - case ND_INS_HADDPS: return "haddps"; - case ND_INS_HLT: return "hlt"; - case ND_INS_HRESET: return "hreset"; - case ND_INS_HSUBPD: return "hsubpd"; - case ND_INS_HSUBPS: return "hsubps"; - case ND_INS_IDIV: return "idiv"; - case ND_INS_IMUL: return "imul"; - case ND_INS_IN: return "in"; - case ND_INS_INC: return "inc"; - case ND_INS_INCSSP: return "incssp"; - case ND_INS_INS: return "ins"; - case ND_INS_INSERTPS: return "insertps"; - case ND_INS_INSERTQ: return "insertq"; - case ND_INS_INT: return "int"; - case ND_INS_INT1: return "int1"; - case ND_INS_INT3: return "int3"; - case ND_INS_INTO: return "into"; - case ND_INS_INVD: return "invd"; - case ND_INS_INVEPT: return "invept"; - case ND_INS_INVLPG: return "invlpg"; - case ND_INS_INVLPGA: return "invlpga"; - case ND_INS_INVLPGB: return "invlpgb"; - case ND_INS_INVPCID: return "invpcid"; - case ND_INS_INVVPID: return "invvpid"; - case ND_INS_IRET: return "iret"; - case ND_INS_JMPE: return "jmpe"; - case ND_INS_JMPFD: return "jmpfd"; - case ND_INS_JMPFI: return "jmpfi"; - case ND_INS_JMPNI: return "jmpni"; - case ND_INS_JMPNR: return "jmpnr"; - case ND_INS_Jcc: return "jcc"; - case ND_INS_JrCXZ: return "jrcxz"; - case ND_INS_KADD: return "kadd"; - case ND_INS_KAND: return "kand"; - case ND_INS_KANDN: return "kandn"; - case ND_INS_KMERGE2L1H: return "kmerge2l1h"; - case ND_INS_KMERGE2L1L: return "kmerge2l1l"; - case ND_INS_KMOV: return "kmov"; - case ND_INS_KNOT: return "knot"; - case ND_INS_KOR: return "kor"; - case ND_INS_KORTEST: return "kortest"; - case ND_INS_KSHIFTL: return "kshiftl"; - case ND_INS_KSHIFTR: return "kshiftr"; - case ND_INS_KTEST: return "ktest"; - case ND_INS_KUNPCKBW: return "kunpckbw"; - case ND_INS_KUNPCKDQ: return "kunpckdq"; - case ND_INS_KUNPCKWD: return "kunpckwd"; - case ND_INS_KXNOR: return "kxnor"; - case ND_INS_KXOR: return "kxor"; - case ND_INS_LAHF: return "lahf"; - case ND_INS_LAR: return "lar"; - case ND_INS_LDDQU: return "lddqu"; - case ND_INS_LDMXCSR: return "ldmxcsr"; - case ND_INS_LDS: return "lds"; - case ND_INS_LDTILECFG: return "ldtilecfg"; - case ND_INS_LEA: return "lea"; - case ND_INS_LEAVE: return "leave"; - case ND_INS_LES: return "les"; - case ND_INS_LFENCE: return "lfence"; - case ND_INS_LFS: return "lfs"; - case ND_INS_LGDT: return "lgdt"; - case ND_INS_LGS: return "lgs"; - case ND_INS_LIDT: return "lidt"; - case ND_INS_LKGS: return "lkgs"; - case ND_INS_LLDT: return "lldt"; - case ND_INS_LLWPCB: return "llwpcb"; - case ND_INS_LMSW: return "lmsw"; - case ND_INS_LOADIWKEY: return "loadiwkey"; - case ND_INS_LODS: return "lods"; - case ND_INS_LOOP: return "loop"; - case ND_INS_LOOPNZ: return "loopnz"; - case ND_INS_LOOPZ: return "loopz"; - case ND_INS_LSL: return "lsl"; - case ND_INS_LSS: return "lss"; - case ND_INS_LTR: return "ltr"; - case ND_INS_LWPINS: return "lwpins"; - case ND_INS_LWPVAL: return "lwpval"; - case ND_INS_LZCNT: return "lzcnt"; - case ND_INS_MASKMOVDQU: return "maskmovdqu"; - case ND_INS_MASKMOVQ: return "maskmovq"; - case ND_INS_MAXPD: return "maxpd"; - case ND_INS_MAXPS: return "maxps"; - case ND_INS_MAXSD: return "maxsd"; - case ND_INS_MAXSS: return "maxss"; - case ND_INS_MCOMMIT: return "mcommit"; - case ND_INS_MFENCE: return "mfence"; - case ND_INS_MINPD: return "minpd"; - case ND_INS_MINPS: return "minps"; - case ND_INS_MINSD: return "minsd"; - case ND_INS_MINSS: return "minss"; - case ND_INS_MONITOR: return "monitor"; - case ND_INS_MONITORX: return "monitorx"; - case ND_INS_MONTMUL: return "montmul"; - case ND_INS_MOV: return "mov"; - case ND_INS_MOVAPD: return "movapd"; - case ND_INS_MOVAPS: return "movaps"; - case ND_INS_MOVBE: return "movbe"; - case ND_INS_MOVD: return "movd"; - case ND_INS_MOVDDUP: return "movddup"; - case ND_INS_MOVDIR64B: return "movdir64b"; - case ND_INS_MOVDIRI: return "movdiri"; - case ND_INS_MOVDQ2Q: return "movdq2q"; - case ND_INS_MOVDQA: return "movdqa"; - case ND_INS_MOVDQU: return "movdqu"; - case ND_INS_MOVHLPS: return "movhlps"; - case ND_INS_MOVHPD: return "movhpd"; - case ND_INS_MOVHPS: return "movhps"; - case ND_INS_MOVLHPS: return "movlhps"; - case ND_INS_MOVLPD: return "movlpd"; - case ND_INS_MOVLPS: return "movlps"; - case ND_INS_MOVMSKPD: return "movmskpd"; - case ND_INS_MOVMSKPS: return "movmskps"; - case ND_INS_MOVNTDQ: return "movntdq"; - case ND_INS_MOVNTDQA: return "movntdqa"; - case ND_INS_MOVNTI: return "movnti"; - case ND_INS_MOVNTPD: return "movntpd"; - case ND_INS_MOVNTPS: return "movntps"; - case ND_INS_MOVNTQ: return "movntq"; - case ND_INS_MOVNTSD: return "movntsd"; - case ND_INS_MOVNTSS: return "movntss"; - case ND_INS_MOVQ: return "movq"; - case ND_INS_MOVQ2DQ: return "movq2dq"; - case ND_INS_MOVS: return "movs"; - case ND_INS_MOVSD: return "movsd"; - case ND_INS_MOVSHDUP: return "movshdup"; - case ND_INS_MOVSLDUP: return "movsldup"; - case ND_INS_MOVSS: return "movss"; - case ND_INS_MOVSX: return "movsx"; - case ND_INS_MOVSXD: return "movsxd"; - case ND_INS_MOVUPD: return "movupd"; - case ND_INS_MOVUPS: return "movups"; - case ND_INS_MOVZX: return "movzx"; - case ND_INS_MOV_CR: return "movcr"; - case ND_INS_MOV_DR: return "movdr"; - case ND_INS_MOV_TR: return "movtr"; - case ND_INS_MPSADBW: return "mpsadbw"; - case ND_INS_MUL: return "mul"; - case ND_INS_MULPD: return "mulpd"; - case ND_INS_MULPS: return "mulps"; - case ND_INS_MULSD: return "mulsd"; - case ND_INS_MULSS: return "mulss"; - case ND_INS_MULX: return "mulx"; - case ND_INS_MWAIT: return "mwait"; - case ND_INS_MWAITX: return "mwaitx"; - case ND_INS_NEG: return "neg"; - case ND_INS_NOP: return "nop"; - case ND_INS_NOT: return "not"; - case ND_INS_OR: return "or"; - case ND_INS_ORPD: return "orpd"; - case ND_INS_ORPS: return "orps"; - case ND_INS_OUT: return "out"; - case ND_INS_OUTS: return "outs"; - case ND_INS_PABSB: return "pabsb"; - case ND_INS_PABSD: return "pabsd"; - case ND_INS_PABSW: return "pabsw"; - case ND_INS_PACKSSDW: return "packssdw"; - case ND_INS_PACKSSWB: return "packsswb"; - case ND_INS_PACKUSDW: return "packusdw"; - case ND_INS_PACKUSWB: return "packuswb"; - case ND_INS_PADDB: return "paddb"; - case ND_INS_PADDD: return "paddd"; - case ND_INS_PADDQ: return "paddq"; - case ND_INS_PADDSB: return "paddsb"; - case ND_INS_PADDSW: return "paddsw"; - case ND_INS_PADDUSB: return "paddusb"; - case ND_INS_PADDUSW: return "paddusw"; - case ND_INS_PADDW: return "paddw"; - case ND_INS_PALIGNR: return "palignr"; - case ND_INS_PAND: return "pand"; - case ND_INS_PANDN: return "pandn"; - case ND_INS_PAUSE: return "pause"; - case ND_INS_PAVGB: return "pavgb"; - case ND_INS_PAVGUSB: return "pavgusb"; - case ND_INS_PAVGW: return "pavgw"; - case ND_INS_PBLENDVB: return "pblendvb"; - case ND_INS_PBLENDW: return "pblendw"; - case ND_INS_PBNDKB: return "pbndkb"; - case ND_INS_PCLMULQDQ: return "pclmulqdq"; - case ND_INS_PCMPEQB: return "pcmpeqb"; - case ND_INS_PCMPEQD: return "pcmpeqd"; - case ND_INS_PCMPEQQ: return "pcmpeqq"; - case ND_INS_PCMPEQW: return "pcmpeqw"; - case ND_INS_PCMPESTRI: return "pcmpestri"; - case ND_INS_PCMPESTRM: return "pcmpestrm"; - case ND_INS_PCMPGTB: return "pcmpgtb"; - case ND_INS_PCMPGTD: return "pcmpgtd"; - case ND_INS_PCMPGTQ: return "pcmpgtq"; - case ND_INS_PCMPGTW: return "pcmpgtw"; - case ND_INS_PCMPISTRI: return "pcmpistri"; - case ND_INS_PCMPISTRM: return "pcmpistrm"; - case ND_INS_PCONFIG: return "pconfig"; - case ND_INS_PDEP: return "pdep"; - case ND_INS_PEXT: return "pext"; - case ND_INS_PEXTRB: return "pextrb"; - case ND_INS_PEXTRD: return "pextrd"; - case ND_INS_PEXTRQ: return "pextrq"; - case ND_INS_PEXTRW: return "pextrw"; - case ND_INS_PF2ID: return "pf2id"; - case ND_INS_PF2IW: return "pf2iw"; - case ND_INS_PFACC: return "pfacc"; - case ND_INS_PFADD: return "pfadd"; - case ND_INS_PFCMPEQ: return "pfcmpeq"; - case ND_INS_PFCMPGE: return "pfcmpge"; - case ND_INS_PFCMPGT: return "pfcmpgt"; - case ND_INS_PFMAX: return "pfmax"; - case ND_INS_PFMIN: return "pfmin"; - case ND_INS_PFMUL: return "pfmul"; - case ND_INS_PFNACC: return "pfnacc"; - case ND_INS_PFPNACC: return "pfpnacc"; - case ND_INS_PFRCP: return "pfrcp"; - case ND_INS_PFRCPIT1: return "pfrcpit1"; - case ND_INS_PFRCPIT2: return "pfrcpit2"; - case ND_INS_PFRCPV: return "pfrcpv"; - case ND_INS_PFRSQIT1: return "pfrsqit1"; - case ND_INS_PFRSQRT: return "pfrsqrt"; - case ND_INS_PFRSQRTV: return "pfrsqrtv"; - case ND_INS_PFSUB: return "pfsub"; - case ND_INS_PFSUBR: return "pfsubr"; - case ND_INS_PHADDD: return "phaddd"; - case ND_INS_PHADDSW: return "phaddsw"; - case ND_INS_PHADDW: return "phaddw"; - case ND_INS_PHMINPOSUW: return "phminposuw"; - case ND_INS_PHSUBD: return "phsubd"; - case ND_INS_PHSUBSW: return "phsubsw"; - case ND_INS_PHSUBW: return "phsubw"; - case ND_INS_PI2FD: return "pi2fd"; - case ND_INS_PI2FW: return "pi2fw"; - case ND_INS_PINSRB: return "pinsrb"; - case ND_INS_PINSRD: return "pinsrd"; - case ND_INS_PINSRQ: return "pinsrq"; - case ND_INS_PINSRW: return "pinsrw"; - case ND_INS_PMADDUBSW: return "pmaddubsw"; - case ND_INS_PMADDWD: return "pmaddwd"; - case ND_INS_PMAXSB: return "pmaxsb"; - case ND_INS_PMAXSD: return "pmaxsd"; - case ND_INS_PMAXSW: return "pmaxsw"; - case ND_INS_PMAXUB: return "pmaxub"; - case ND_INS_PMAXUD: return "pmaxud"; - case ND_INS_PMAXUW: return "pmaxuw"; - case ND_INS_PMINSB: return "pminsb"; - case ND_INS_PMINSD: return "pminsd"; - case ND_INS_PMINSW: return "pminsw"; - case ND_INS_PMINUB: return "pminub"; - case ND_INS_PMINUD: return "pminud"; - case ND_INS_PMINUW: return "pminuw"; - case ND_INS_PMOVMSKB: return "pmovmskb"; - case ND_INS_PMOVSXBD: return "pmovsxbd"; - case ND_INS_PMOVSXBQ: return "pmovsxbq"; - case ND_INS_PMOVSXBW: return "pmovsxbw"; - case ND_INS_PMOVSXDQ: return "pmovsxdq"; - case ND_INS_PMOVSXWD: return "pmovsxwd"; - case ND_INS_PMOVSXWQ: return "pmovsxwq"; - case ND_INS_PMOVZXBD: return "pmovzxbd"; - case ND_INS_PMOVZXBQ: return "pmovzxbq"; - case ND_INS_PMOVZXBW: return "pmovzxbw"; - case ND_INS_PMOVZXDQ: return "pmovzxdq"; - case ND_INS_PMOVZXWD: return "pmovzxwd"; - case ND_INS_PMOVZXWQ: return "pmovzxwq"; - case ND_INS_PMULDQ: return "pmuldq"; - case ND_INS_PMULHRSW: return "pmulhrsw"; - case ND_INS_PMULHRW: return "pmulhrw"; - case ND_INS_PMULHUW: return "pmulhuw"; - case ND_INS_PMULHW: return "pmulhw"; - case ND_INS_PMULLD: return "pmulld"; - case ND_INS_PMULLW: return "pmullw"; - case ND_INS_PMULUDQ: return "pmuludq"; - case ND_INS_POP: return "pop"; - case ND_INS_POPA: return "popa"; - case ND_INS_POPAD: return "popad"; - case ND_INS_POPCNT: return "popcnt"; - case ND_INS_POPF: return "popf"; - case ND_INS_POR: return "por"; - case ND_INS_PREFETCH: return "prefetch"; - case ND_INS_PREFETCHE: return "prefetche"; - case ND_INS_PREFETCHIT0: return "prefetchit0"; - case ND_INS_PREFETCHIT1: return "prefetchit1"; - case ND_INS_PREFETCHM: return "prefetchm"; - case ND_INS_PREFETCHNTA: return "prefetchnta"; - case ND_INS_PREFETCHT0: return "prefetcht0"; - case ND_INS_PREFETCHT1: return "prefetcht1"; - case ND_INS_PREFETCHT2: return "prefetcht2"; - case ND_INS_PREFETCHW: return "prefetchw"; - case ND_INS_PREFETCHWT1: return "prefetchwt1"; - case ND_INS_PSADBW: return "psadbw"; - case ND_INS_PSHUFB: return "pshufb"; - case ND_INS_PSHUFD: return "pshufd"; - case ND_INS_PSHUFHW: return "pshufhw"; - case ND_INS_PSHUFLW: return "pshuflw"; - case ND_INS_PSHUFW: return "pshufw"; - case ND_INS_PSIGNB: return "psignb"; - case ND_INS_PSIGND: return "psignd"; - case ND_INS_PSIGNW: return "psignw"; - case ND_INS_PSLLD: return "pslld"; - case ND_INS_PSLLDQ: return "pslldq"; - case ND_INS_PSLLQ: return "psllq"; - case ND_INS_PSLLW: return "psllw"; - case ND_INS_PSMASH: return "psmash"; - case ND_INS_PSRAD: return "psrad"; - case ND_INS_PSRAW: return "psraw"; - case ND_INS_PSRLD: return "psrld"; - case ND_INS_PSRLDQ: return "psrldq"; - case ND_INS_PSRLQ: return "psrlq"; - case ND_INS_PSRLW: return "psrlw"; - case ND_INS_PSUBB: return "psubb"; - case ND_INS_PSUBD: return "psubd"; - case ND_INS_PSUBQ: return "psubq"; - case ND_INS_PSUBSB: return "psubsb"; - case ND_INS_PSUBSW: return "psubsw"; - case ND_INS_PSUBUSB: return "psubusb"; - case ND_INS_PSUBUSW: return "psubusw"; - case ND_INS_PSUBW: return "psubw"; - case ND_INS_PSWAPD: return "pswapd"; - case ND_INS_PTEST: return "ptest"; - case ND_INS_PTWRITE: return "ptwrite"; - case ND_INS_PUNPCKHBW: return "punpckhbw"; - case ND_INS_PUNPCKHDQ: return "punpckhdq"; - case ND_INS_PUNPCKHQDQ: return "punpckhqdq"; - case ND_INS_PUNPCKHWD: return "punpckhwd"; - case ND_INS_PUNPCKLBW: return "punpcklbw"; - case ND_INS_PUNPCKLDQ: return "punpckldq"; - case ND_INS_PUNPCKLQDQ: return "punpcklqdq"; - case ND_INS_PUNPCKLWD: return "punpcklwd"; - case ND_INS_PUSH: return "push"; - case ND_INS_PUSHA: return "pusha"; - case ND_INS_PUSHAD: return "pushad"; - case ND_INS_PUSHF: return "pushf"; - case ND_INS_PVALIDATE: return "pvalidate"; - case ND_INS_PXOR: return "pxor"; - case ND_INS_RCL: return "rcl"; - case ND_INS_RCPPS: return "rcpps"; - case ND_INS_RCPSS: return "rcpss"; - case ND_INS_RCR: return "rcr"; - case ND_INS_RDFSBASE: return "rdfsbase"; - case ND_INS_RDGSBASE: return "rdgsbase"; - case ND_INS_RDMSR: return "rdmsr"; - case ND_INS_RDMSRLIST: return "rdmsrlist"; - case ND_INS_RDPID: return "rdpid"; - case ND_INS_RDPKRU: return "rdpkru"; - case ND_INS_RDPMC: return "rdpmc"; - case ND_INS_RDPRU: return "rdpru"; - case ND_INS_RDRAND: return "rdrand"; - case ND_INS_RDSEED: return "rdseed"; - case ND_INS_RDSHR: return "rdshr"; - case ND_INS_RDTSC: return "rdtsc"; - case ND_INS_RDTSCP: return "rdtscp"; - case ND_INS_RETF: return "retf"; - case ND_INS_RETN: return "retn"; - case ND_INS_RMPADJUST: return "rmpadjust"; - case ND_INS_RMPQUERY: return "rmpquery"; - case ND_INS_RMPUPDATE: return "rmpupdate"; - case ND_INS_ROL: return "rol"; - case ND_INS_ROR: return "ror"; - case ND_INS_RORX: return "rorx"; - case ND_INS_ROUNDPD: return "roundpd"; - case ND_INS_ROUNDPS: return "roundps"; - case ND_INS_ROUNDSD: return "roundsd"; - case ND_INS_ROUNDSS: return "roundss"; - case ND_INS_RSDC: return "rsdc"; - case ND_INS_RSLDT: return "rsldt"; - case ND_INS_RSM: return "rsm"; - case ND_INS_RSQRTPS: return "rsqrtps"; - case ND_INS_RSQRTSS: return "rsqrtss"; - case ND_INS_RSSSP: return "rsssp"; - case ND_INS_RSTORSSP: return "rstorssp"; - case ND_INS_RSTS: return "rsts"; - case ND_INS_SAHF: return "sahf"; - case ND_INS_SAL: return "sal"; - case ND_INS_SALC: return "salc"; - case ND_INS_SAR: return "sar"; - case ND_INS_SARX: return "sarx"; - case ND_INS_SAVEPREVSSP: return "saveprevssp"; - case ND_INS_SBB: return "sbb"; - case ND_INS_SCAS: return "scas"; - case ND_INS_SEAMOPS: return "seamops"; - case ND_INS_SEAMCALL: return "seamcall"; - case ND_INS_SEAMRET: return "seamret"; - case ND_INS_SENDUIPI: return "senduipi"; - case ND_INS_SERIALIZE: return "serialize"; - case ND_INS_SETSSBSY: return "setssbsy"; - case ND_INS_SETcc: return "setcc"; - case ND_INS_SFENCE: return "sfence"; - case ND_INS_SGDT: return "sgdt"; - case ND_INS_SHA1MSG1: return "sha1msg1"; - case ND_INS_SHA1MSG2: return "sha1msg2"; - case ND_INS_SHA1NEXTE: return "sha1nexte"; - case ND_INS_SHA1RNDS4: return "sha1rnds4"; - case ND_INS_SHA256MSG1: return "sha256msg1"; - case ND_INS_SHA256MSG2: return "sha256msg2"; - case ND_INS_SHA256RNDS2: return "sha256rnds2"; - case ND_INS_SHL: return "shl"; - case ND_INS_SHLD: return "shld"; - case ND_INS_SHLX: return "shlx"; - case ND_INS_SHR: return "shr"; - case ND_INS_SHRD: return "shrd"; - case ND_INS_SHRX: return "shrx"; - case ND_INS_SHUFPD: return "shufpd"; - case ND_INS_SHUFPS: return "shufps"; - case ND_INS_SIDT: return "sidt"; - case ND_INS_SKINIT: return "skinit"; - case ND_INS_SLDT: return "sldt"; - case ND_INS_SLWPCB: return "slwpcb"; - case ND_INS_SMINT: return "smint"; - case ND_INS_SMSW: return "smsw"; - case ND_INS_SPFLT: return "spflt"; - case ND_INS_SQRTPD: return "sqrtpd"; - case ND_INS_SQRTPS: return "sqrtps"; - case ND_INS_SQRTSD: return "sqrtsd"; - case ND_INS_SQRTSS: return "sqrtss"; - case ND_INS_STAC: return "stac"; - case ND_INS_STC: return "stc"; - case ND_INS_STD: return "std"; - case ND_INS_STGI: return "stgi"; - case ND_INS_STI: return "sti"; - case ND_INS_STMXCSR: return "stmxcsr"; - case ND_INS_STOS: return "stos"; - case ND_INS_STR: return "str"; - case ND_INS_STTILECFG: return "sttilecfg"; - case ND_INS_STUI: return "stui"; - case ND_INS_SUB: return "sub"; - case ND_INS_SUBPD: return "subpd"; - case ND_INS_SUBPS: return "subps"; - case ND_INS_SUBSD: return "subsd"; - case ND_INS_SUBSS: return "subss"; - case ND_INS_SVDC: return "svdc"; - case ND_INS_SVLDT: return "svldt"; - case ND_INS_SVTS: return "svts"; - case ND_INS_SWAPGS: return "swapgs"; - case ND_INS_SYSCALL: return "syscall"; - case ND_INS_SYSENTER: return "sysenter"; - case ND_INS_SYSEXIT: return "sysexit"; - case ND_INS_SYSRET: return "sysret"; - case ND_INS_T1MSKC: return "t1mskc"; - case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps"; - case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps"; - case ND_INS_TDCALL: return "tdcall"; - case ND_INS_TDPBF16PS: return "tdpbf16ps"; - case ND_INS_TDPBSSD: return "tdpbssd"; - case ND_INS_TDPBSUD: return "tdpbsud"; - case ND_INS_TDPBUSD: return "tdpbusd"; - case ND_INS_TDPBUUD: return "tdpbuud"; - case ND_INS_TDPFP16PS: return "tdpfp16ps"; - case ND_INS_TEST: return "test"; - case ND_INS_TESTUI: return "testui"; - case ND_INS_TILELOADD: return "tileloadd"; - case ND_INS_TILELOADDT1: return "tileloaddt1"; - case ND_INS_TILERELEASE: return "tilerelease"; - case ND_INS_TILESTORED: return "tilestored"; - case ND_INS_TILEZERO: return "tilezero"; - case ND_INS_TLBSYNC: return "tlbsync"; - case ND_INS_TPAUSE: return "tpause"; - case ND_INS_TZCNT: return "tzcnt"; - case ND_INS_TZMSK: return "tzmsk"; - case ND_INS_UCOMISD: return "ucomisd"; - case ND_INS_UCOMISS: return "ucomiss"; - case ND_INS_UD0: return "ud0"; - case ND_INS_UD1: return "ud1"; - case ND_INS_UD2: return "ud2"; - case ND_INS_UIRET: return "uiret"; - case ND_INS_UMONITOR: return "umonitor"; - case ND_INS_UMWAIT: return "umwait"; - case ND_INS_UNPCKHPD: return "unpckhpd"; - case ND_INS_UNPCKHPS: return "unpckhps"; - case ND_INS_UNPCKLPD: return "unpcklpd"; - case ND_INS_UNPCKLPS: return "unpcklps"; - case ND_INS_V4FMADDPS: return "v4fmaddps"; - case ND_INS_V4FMADDSS: return "v4fmaddss"; - case ND_INS_V4FNMADDPS: return "v4fnmaddps"; - case ND_INS_V4FNMADDSS: return "v4fnmaddss"; - case ND_INS_VADDPD: return "vaddpd"; - case ND_INS_VADDPH: return "vaddph"; - case ND_INS_VADDPS: return "vaddps"; - case ND_INS_VADDSD: return "vaddsd"; - case ND_INS_VADDSH: return "vaddsh"; - case ND_INS_VADDSS: return "vaddss"; - case ND_INS_VADDSUBPD: return "vaddsubpd"; - case ND_INS_VADDSUBPS: return "vaddsubps"; - case ND_INS_VAESDEC: return "vaesdec"; - case ND_INS_VAESDECLAST: return "vaesdeclast"; - case ND_INS_VAESENC: return "vaesenc"; - case ND_INS_VAESENCLAST: return "vaesenclast"; - case ND_INS_VAESIMC: return "vaesimc"; - case ND_INS_VAESKEYGENASSIST: return "vaeskeygenassist"; - case ND_INS_VALIGND: return "valignd"; - case ND_INS_VALIGNQ: return "valignq"; - case ND_INS_VANDNPD: return "vandnpd"; - case ND_INS_VANDNPS: return "vandnps"; - case ND_INS_VANDPD: return "vandpd"; - case ND_INS_VANDPS: return "vandps"; - case ND_INS_VBCSTNEBF162PS: return "vbcstnebf162ps"; - case ND_INS_VBCSTNESH2PS: return "vbcstnesh2ps"; - case ND_INS_VBLENDMPD: return "vblendmpd"; - case ND_INS_VBLENDMPS: return "vblendmps"; - case ND_INS_VBLENDPD: return "vblendpd"; - case ND_INS_VBLENDPS: return "vblendps"; - case ND_INS_VBLENDVPD: return "vblendvpd"; - case ND_INS_VBLENDVPS: return "vblendvps"; - case ND_INS_VBROADCASTF128: return "vbroadcastf128"; - case ND_INS_VBROADCASTF32X2: return "vbroadcastf32x2"; - case ND_INS_VBROADCASTF32X4: return "vbroadcastf32x4"; - case ND_INS_VBROADCASTF32X8: return "vbroadcastf32x8"; - case ND_INS_VBROADCASTF64X2: return "vbroadcastf64x2"; - case ND_INS_VBROADCASTF64X4: return "vbroadcastf64x4"; - case ND_INS_VBROADCASTI128: return "vbroadcasti128"; - case ND_INS_VBROADCASTI32X2: return "vbroadcasti32x2"; - case ND_INS_VBROADCASTI32X4: return "vbroadcasti32x4"; - case ND_INS_VBROADCASTI32X8: return "vbroadcasti32x8"; - case ND_INS_VBROADCASTI64X2: return "vbroadcasti64x2"; - case ND_INS_VBROADCASTI64X4: return "vbroadcasti64x4"; - case ND_INS_VBROADCASTSD: return "vbroadcastsd"; - case ND_INS_VBROADCASTSS: return "vbroadcastss"; - case ND_INS_VCMPPD: return "vcmppd"; - case ND_INS_VCMPPH: return "vcmpph"; - case ND_INS_VCMPPS: return "vcmpps"; - case ND_INS_VCMPSD: return "vcmpsd"; - case ND_INS_VCMPSH: return "vcmpsh"; - case ND_INS_VCMPSS: return "vcmpss"; - case ND_INS_VCOMISD: return "vcomisd"; - case ND_INS_VCOMISH: return "vcomish"; - case ND_INS_VCOMISS: return "vcomiss"; - case ND_INS_VCOMPRESSPD: return "vcompresspd"; - case ND_INS_VCOMPRESSPS: return "vcompressps"; - case ND_INS_VCVTDQ2PD: return "vcvtdq2pd"; - case ND_INS_VCVTDQ2PH: return "vcvtdq2ph"; - case ND_INS_VCVTDQ2PS: return "vcvtdq2ps"; - case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16"; - case ND_INS_VCVTNEEBF162PS: return "vcvtneebf162ps"; - case ND_INS_VCVTNEEPH2PS: return "vcvtneeph2ps"; - case ND_INS_VCVTNEOBF162PS: return "vcvtneobf162ps"; - case ND_INS_VCVTNEOPH2PS: return "vcvtneoph2ps"; - case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16"; - case ND_INS_VCVTPD2DQ: return "vcvtpd2dq"; - case ND_INS_VCVTPD2PH: return "vcvtpd2ph"; - case ND_INS_VCVTPD2PS: return "vcvtpd2ps"; - case ND_INS_VCVTPD2QQ: return "vcvtpd2qq"; - case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq"; - case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq"; - case ND_INS_VCVTPH2DQ: return "vcvtph2dq"; - case ND_INS_VCVTPH2PD: return "vcvtph2pd"; - case ND_INS_VCVTPH2PS: return "vcvtph2ps"; - case ND_INS_VCVTPH2PSX: return "vcvtph2psx"; - case ND_INS_VCVTPH2QQ: return "vcvtph2qq"; - case ND_INS_VCVTPH2UDQ: return "vcvtph2udq"; - case ND_INS_VCVTPH2UQQ: return "vcvtph2uqq"; - case ND_INS_VCVTPH2UW: return "vcvtph2uw"; - case ND_INS_VCVTPH2W: return "vcvtph2w"; - case ND_INS_VCVTPS2DQ: return "vcvtps2dq"; - case ND_INS_VCVTPS2PD: return "vcvtps2pd"; - case ND_INS_VCVTPS2PH: return "vcvtps2ph"; - case ND_INS_VCVTPS2PHX: return "vcvtps2phx"; - case ND_INS_VCVTPS2QQ: return "vcvtps2qq"; - case ND_INS_VCVTPS2UDQ: return "vcvtps2udq"; - case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq"; - case ND_INS_VCVTQQ2PD: return "vcvtqq2pd"; - case ND_INS_VCVTQQ2PH: return "vcvtqq2ph"; - case ND_INS_VCVTQQ2PS: return "vcvtqq2ps"; - case ND_INS_VCVTSD2SH: return "vcvtsd2sh"; - case ND_INS_VCVTSD2SI: return "vcvtsd2si"; - case ND_INS_VCVTSD2SS: return "vcvtsd2ss"; - case ND_INS_VCVTSD2USI: return "vcvtsd2usi"; - case ND_INS_VCVTSH2SD: return "vcvtsh2sd"; - case ND_INS_VCVTSH2SI: return "vcvtsh2si"; - case ND_INS_VCVTSH2SS: return "vcvtsh2ss"; - case ND_INS_VCVTSH2USI: return "vcvtsh2usi"; - case ND_INS_VCVTSI2SD: return "vcvtsi2sd"; - case ND_INS_VCVTSI2SH: return "vcvtsi2sh"; - case ND_INS_VCVTSI2SS: return "vcvtsi2ss"; - case ND_INS_VCVTSS2SD: return "vcvtss2sd"; - case ND_INS_VCVTSS2SH: return "vcvtss2sh"; - case ND_INS_VCVTSS2SI: return "vcvtss2si"; - case ND_INS_VCVTSS2USI: return "vcvtss2usi"; - case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq"; - case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq"; - case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq"; - case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq"; - case ND_INS_VCVTTPH2DQ: return "vcvttph2dq"; - case ND_INS_VCVTTPH2QQ: return "vcvttph2qq"; - case ND_INS_VCVTTPH2UDQ: return "vcvttph2udq"; - case ND_INS_VCVTTPH2UQQ: return "vcvttph2uqq"; - case ND_INS_VCVTTPH2UW: return "vcvttph2uw"; - case ND_INS_VCVTTPH2W: return "vcvttph2w"; - case ND_INS_VCVTTPS2DQ: return "vcvttps2dq"; - case ND_INS_VCVTTPS2QQ: return "vcvttps2qq"; - case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq"; - case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq"; - case ND_INS_VCVTTSD2SI: return "vcvttsd2si"; - case ND_INS_VCVTTSD2USI: return "vcvttsd2usi"; - case ND_INS_VCVTTSH2SI: return "vcvttsh2si"; - case ND_INS_VCVTTSH2USI: return "vcvttsh2usi"; - case ND_INS_VCVTTSS2SI: return "vcvttss2si"; - case ND_INS_VCVTTSS2USI: return "vcvttss2usi"; - case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd"; - case ND_INS_VCVTUDQ2PH: return "vcvtudq2ph"; - case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps"; - case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd"; - case ND_INS_VCVTUQQ2PH: return "vcvtuqq2ph"; - case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps"; - case ND_INS_VCVTUSI2SD: return "vcvtusi2sd"; - case ND_INS_VCVTUSI2SH: return "vcvtusi2sh"; - case ND_INS_VCVTUSI2SS: return "vcvtusi2ss"; - case ND_INS_VCVTUW2PH: return "vcvtuw2ph"; - case ND_INS_VCVTW2PH: return "vcvtw2ph"; - case ND_INS_VDBPSADBW: return "vdbpsadbw"; - case ND_INS_VDIVPD: return "vdivpd"; - case ND_INS_VDIVPH: return "vdivph"; - case ND_INS_VDIVPS: return "vdivps"; - case ND_INS_VDIVSD: return "vdivsd"; - case ND_INS_VDIVSH: return "vdivsh"; - case ND_INS_VDIVSS: return "vdivss"; - case ND_INS_VDPBF16PS: return "vdpbf16ps"; - case ND_INS_VDPPD: return "vdppd"; - case ND_INS_VDPPS: return "vdpps"; - case ND_INS_VERR: return "verr"; - case ND_INS_VERW: return "verw"; - case ND_INS_VEXP2PD: return "vexp2pd"; - case ND_INS_VEXP2PS: return "vexp2ps"; - case ND_INS_VEXPANDPD: return "vexpandpd"; - case ND_INS_VEXPANDPS: return "vexpandps"; - case ND_INS_VEXTRACTF128: return "vextractf128"; - case ND_INS_VEXTRACTF32X4: return "vextractf32x4"; - case ND_INS_VEXTRACTF32X8: return "vextractf32x8"; - case ND_INS_VEXTRACTF64X2: return "vextractf64x2"; - case ND_INS_VEXTRACTF64X4: return "vextractf64x4"; - case ND_INS_VEXTRACTI128: return "vextracti128"; - case ND_INS_VEXTRACTI32X4: return "vextracti32x4"; - case ND_INS_VEXTRACTI32X8: return "vextracti32x8"; - case ND_INS_VEXTRACTI64X2: return "vextracti64x2"; - case ND_INS_VEXTRACTI64X4: return "vextracti64x4"; - case ND_INS_VEXTRACTPS: return "vextractps"; - case ND_INS_VFCMADDCPH: return "vfcmaddcph"; - case ND_INS_VFCMADDCSH: return "vfcmaddcsh"; - case ND_INS_VFCMULCPH: return "vfcmulcph"; - case ND_INS_VFCMULCSH: return "vfcmulcsh"; - case ND_INS_VFIXUPIMMPD: return "vfixupimmpd"; - case ND_INS_VFIXUPIMMPS: return "vfixupimmps"; - case ND_INS_VFIXUPIMMSD: return "vfixupimmsd"; - case ND_INS_VFIXUPIMMSS: return "vfixupimmss"; - case ND_INS_VFMADD132PD: return "vfmadd132pd"; - case ND_INS_VFMADD132PH: return "vfmadd132ph"; - case ND_INS_VFMADD132PS: return "vfmadd132ps"; - case ND_INS_VFMADD132SD: return "vfmadd132sd"; - case ND_INS_VFMADD132SH: return "vfmadd132sh"; - case ND_INS_VFMADD132SS: return "vfmadd132ss"; - case ND_INS_VFMADD213PD: return "vfmadd213pd"; - case ND_INS_VFMADD213PH: return "vfmadd213ph"; - case ND_INS_VFMADD213PS: return "vfmadd213ps"; - case ND_INS_VFMADD213SD: return "vfmadd213sd"; - case ND_INS_VFMADD213SH: return "vfmadd213sh"; - case ND_INS_VFMADD213SS: return "vfmadd213ss"; - case ND_INS_VFMADD231PD: return "vfmadd231pd"; - case ND_INS_VFMADD231PH: return "vfmadd231ph"; - case ND_INS_VFMADD231PS: return "vfmadd231ps"; - case ND_INS_VFMADD231SD: return "vfmadd231sd"; - case ND_INS_VFMADD231SH: return "vfmadd231sh"; - case ND_INS_VFMADD231SS: return "vfmadd231ss"; - case ND_INS_VFMADDCPH: return "vfmaddcph"; - case ND_INS_VFMADDCSH: return "vfmaddcsh"; - case ND_INS_VFMADDPD: return "vfmaddpd"; - case ND_INS_VFMADDPS: return "vfmaddps"; - case ND_INS_VFMADDSD: return "vfmaddsd"; - case ND_INS_VFMADDSS: return "vfmaddss"; - case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd"; - case ND_INS_VFMADDSUB132PH: return "vfmaddsub132ph"; - case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps"; - case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd"; - case ND_INS_VFMADDSUB213PH: return "vfmaddsub213ph"; - case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps"; - case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd"; - case ND_INS_VFMADDSUB231PH: return "vfmaddsub231ph"; - case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps"; - case ND_INS_VFMADDSUBPD: return "vfmaddsubpd"; - case ND_INS_VFMADDSUBPS: return "vfmaddsubps"; - case ND_INS_VFMSUB132PD: return "vfmsub132pd"; - case ND_INS_VFMSUB132PH: return "vfmsub132ph"; - case ND_INS_VFMSUB132PS: return "vfmsub132ps"; - case ND_INS_VFMSUB132SD: return "vfmsub132sd"; - case ND_INS_VFMSUB132SH: return "vfmsub132sh"; - case ND_INS_VFMSUB132SS: return "vfmsub132ss"; - case ND_INS_VFMSUB213PD: return "vfmsub213pd"; - case ND_INS_VFMSUB213PH: return "vfmsub213ph"; - case ND_INS_VFMSUB213PS: return "vfmsub213ps"; - case ND_INS_VFMSUB213SD: return "vfmsub213sd"; - case ND_INS_VFMSUB213SH: return "vfmsub213sh"; - case ND_INS_VFMSUB213SS: return "vfmsub213ss"; - case ND_INS_VFMSUB231PD: return "vfmsub231pd"; - case ND_INS_VFMSUB231PH: return "vfmsub231ph"; - case ND_INS_VFMSUB231PS: return "vfmsub231ps"; - case ND_INS_VFMSUB231SD: return "vfmsub231sd"; - case ND_INS_VFMSUB231SH: return "vfmsub231sh"; - case ND_INS_VFMSUB231SS: return "vfmsub231ss"; - case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd"; - case ND_INS_VFMSUBADD132PH: return "vfmsubadd132ph"; - case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps"; - case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd"; - case ND_INS_VFMSUBADD213PH: return "vfmsubadd213ph"; - case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps"; - case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd"; - case ND_INS_VFMSUBADD231PH: return "vfmsubadd231ph"; - case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps"; - case ND_INS_VFMSUBADDPD: return "vfmsubaddpd"; - case ND_INS_VFMSUBADDPS: return "vfmsubaddps"; - case ND_INS_VFMSUBPD: return "vfmsubpd"; - case ND_INS_VFMSUBPS: return "vfmsubps"; - case ND_INS_VFMSUBSD: return "vfmsubsd"; - case ND_INS_VFMSUBSS: return "vfmsubss"; - case ND_INS_VFMULCPH: return "vfmulcph"; - case ND_INS_VFMULCSH: return "vfmulcsh"; - case ND_INS_VFNMADD132PD: return "vfnmadd132pd"; - case ND_INS_VFNMADD132PH: return "vfnmadd132ph"; - case ND_INS_VFNMADD132PS: return "vfnmadd132ps"; - case ND_INS_VFNMADD132SD: return "vfnmadd132sd"; - case ND_INS_VFNMADD132SH: return "vfnmadd132sh"; - case ND_INS_VFNMADD132SS: return "vfnmadd132ss"; - case ND_INS_VFNMADD213PD: return "vfnmadd213pd"; - case ND_INS_VFNMADD213PH: return "vfnmadd213ph"; - case ND_INS_VFNMADD213PS: return "vfnmadd213ps"; - case ND_INS_VFNMADD213SD: return "vfnmadd213sd"; - case ND_INS_VFNMADD213SH: return "vfnmadd213sh"; - case ND_INS_VFNMADD213SS: return "vfnmadd213ss"; - case ND_INS_VFNMADD231PD: return "vfnmadd231pd"; - case ND_INS_VFNMADD231PH: return "vfnmadd231ph"; - case ND_INS_VFNMADD231PS: return "vfnmadd231ps"; - case ND_INS_VFNMADD231SD: return "vfnmadd231sd"; - case ND_INS_VFNMADD231SH: return "vfnmadd231sh"; - case ND_INS_VFNMADD231SS: return "vfnmadd231ss"; - case ND_INS_VFNMADDPD: return "vfnmaddpd"; - case ND_INS_VFNMADDPS: return "vfnmaddps"; - case ND_INS_VFNMADDSD: return "vfnmaddsd"; - case ND_INS_VFNMADDSS: return "vfnmaddss"; - case ND_INS_VFNMSUB132PD: return "vfnmsub132pd"; - case ND_INS_VFNMSUB132PH: return "vfnmsub132ph"; - case ND_INS_VFNMSUB132PS: return "vfnmsub132ps"; - case ND_INS_VFNMSUB132SD: return "vfnmsub132sd"; - case ND_INS_VFNMSUB132SH: return "vfnmsub132sh"; - case ND_INS_VFNMSUB132SS: return "vfnmsub132ss"; - case ND_INS_VFNMSUB213PD: return "vfnmsub213pd"; - case ND_INS_VFNMSUB213PH: return "vfnmsub213ph"; - case ND_INS_VFNMSUB213PS: return "vfnmsub213ps"; - case ND_INS_VFNMSUB213SD: return "vfnmsub213sd"; - case ND_INS_VFNMSUB213SH: return "vfnmsub213sh"; - case ND_INS_VFNMSUB213SS: return "vfnmsub213ss"; - case ND_INS_VFNMSUB231PD: return "vfnmsub231pd"; - case ND_INS_VFNMSUB231PH: return "vfnmsub231ph"; - case ND_INS_VFNMSUB231PS: return "vfnmsub231ps"; - case ND_INS_VFNMSUB231SD: return "vfnmsub231sd"; - case ND_INS_VFNMSUB231SH: return "vfnmsub231sh"; - case ND_INS_VFNMSUB231SS: return "vfnmsub231ss"; - case ND_INS_VFNMSUBPD: return "vfnmsubpd"; - case ND_INS_VFNMSUBPS: return "vfnmsubps"; - case ND_INS_VFNMSUBSD: return "vfnmsubsd"; - case ND_INS_VFNMSUBSS: return "vfnmsubss"; - case ND_INS_VFPCLASSPD: return "vfpclasspd"; - case ND_INS_VFPCLASSPH: return "vfpclassph"; - case ND_INS_VFPCLASSPS: return "vfpclassps"; - case ND_INS_VFPCLASSSD: return "vfpclasssd"; - case ND_INS_VFPCLASSSH: return "vfpclasssh"; - case ND_INS_VFPCLASSSS: return "vfpclassss"; - case ND_INS_VFRCZPD: return "vfrczpd"; - case ND_INS_VFRCZPS: return "vfrczps"; - case ND_INS_VFRCZSD: return "vfrczsd"; - case ND_INS_VFRCZSS: return "vfrczss"; - case ND_INS_VGATHERDPD: return "vgatherdpd"; - case ND_INS_VGATHERDPS: return "vgatherdps"; - case ND_INS_VGATHERPF0DPD: return "vgatherpf0dpd"; - case ND_INS_VGATHERPF0DPS: return "vgatherpf0dps"; - case ND_INS_VGATHERPF0QPD: return "vgatherpf0qpd"; - case ND_INS_VGATHERPF0QPS: return "vgatherpf0qps"; - case ND_INS_VGATHERPF1DPD: return "vgatherpf1dpd"; - case ND_INS_VGATHERPF1DPS: return "vgatherpf1dps"; - case ND_INS_VGATHERPF1QPD: return "vgatherpf1qpd"; - case ND_INS_VGATHERPF1QPS: return "vgatherpf1qps"; - case ND_INS_VGATHERQPD: return "vgatherqpd"; - case ND_INS_VGATHERQPS: return "vgatherqps"; - case ND_INS_VGETEXPPD: return "vgetexppd"; - case ND_INS_VGETEXPPH: return "vgetexpph"; - case ND_INS_VGETEXPPS: return "vgetexpps"; - case ND_INS_VGETEXPSD: return "vgetexpsd"; - case ND_INS_VGETEXPSH: return "vgetexpsh"; - case ND_INS_VGETEXPSS: return "vgetexpss"; - case ND_INS_VGETMANTPD: return "vgetmantpd"; - case ND_INS_VGETMANTPH: return "vgetmantph"; - case ND_INS_VGETMANTPS: return "vgetmantps"; - case ND_INS_VGETMANTSD: return "vgetmantsd"; - case ND_INS_VGETMANTSH: return "vgetmantsh"; - case ND_INS_VGETMANTSS: return "vgetmantss"; - case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb"; - case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb"; - case ND_INS_VGF2P8MULB: return "vgf2p8mulb"; - case ND_INS_VHADDPD: return "vhaddpd"; - case ND_INS_VHADDPS: return "vhaddps"; - case ND_INS_VHSUBPD: return "vhsubpd"; - case ND_INS_VHSUBPS: return "vhsubps"; - case ND_INS_VINSERTF128: return "vinsertf128"; - case ND_INS_VINSERTF32X4: return "vinsertf32x4"; - case ND_INS_VINSERTF32X8: return "vinsertf32x8"; - case ND_INS_VINSERTF64X2: return "vinsertf64x2"; - case ND_INS_VINSERTF64X4: return "vinsertf64x4"; - case ND_INS_VINSERTI128: return "vinserti128"; - case ND_INS_VINSERTI32X4: return "vinserti32x4"; - case ND_INS_VINSERTI32X8: return "vinserti32x8"; - case ND_INS_VINSERTI64X2: return "vinserti64x2"; - case ND_INS_VINSERTI64X4: return "vinserti64x4"; - case ND_INS_VINSERTPS: return "vinsertps"; - case ND_INS_VLDDQU: return "vlddqu"; - case ND_INS_VLDMXCSR: return "vldmxcsr"; - case ND_INS_VMASKMOVDQU: return "vmaskmovdqu"; - case ND_INS_VMASKMOVPD: return "vmaskmovpd"; - case ND_INS_VMASKMOVPS: return "vmaskmovps"; - case ND_INS_VMAXPD: return "vmaxpd"; - case ND_INS_VMAXPH: return "vmaxph"; - case ND_INS_VMAXPS: return "vmaxps"; - case ND_INS_VMAXSD: return "vmaxsd"; - case ND_INS_VMAXSH: return "vmaxsh"; - case ND_INS_VMAXSS: return "vmaxss"; - case ND_INS_VMCALL: return "vmcall"; - case ND_INS_VMCLEAR: return "vmclear"; - case ND_INS_VMFUNC: return "vmfunc"; - case ND_INS_VMGEXIT: return "vmgexit"; - case ND_INS_VMINPD: return "vminpd"; - case ND_INS_VMINPH: return "vminph"; - case ND_INS_VMINPS: return "vminps"; - case ND_INS_VMINSD: return "vminsd"; - case ND_INS_VMINSH: return "vminsh"; - case ND_INS_VMINSS: return "vminss"; - case ND_INS_VMLAUNCH: return "vmlaunch"; - case ND_INS_VMLOAD: return "vmload"; - case ND_INS_VMMCALL: return "vmmcall"; - case ND_INS_VMOVAPD: return "vmovapd"; - case ND_INS_VMOVAPS: return "vmovaps"; - case ND_INS_VMOVD: return "vmovd"; - case ND_INS_VMOVDDUP: return "vmovddup"; - case ND_INS_VMOVDQA: return "vmovdqa"; - case ND_INS_VMOVDQA32: return "vmovdqa32"; - case ND_INS_VMOVDQA64: return "vmovdqa64"; - case ND_INS_VMOVDQU: return "vmovdqu"; - case ND_INS_VMOVDQU16: return "vmovdqu16"; - case ND_INS_VMOVDQU32: return "vmovdqu32"; - case ND_INS_VMOVDQU64: return "vmovdqu64"; - case ND_INS_VMOVDQU8: return "vmovdqu8"; - case ND_INS_VMOVHLPS: return "vmovhlps"; - case ND_INS_VMOVHPD: return "vmovhpd"; - case ND_INS_VMOVHPS: return "vmovhps"; - case ND_INS_VMOVLHPS: return "vmovlhps"; - case ND_INS_VMOVLPD: return "vmovlpd"; - case ND_INS_VMOVLPS: return "vmovlps"; - case ND_INS_VMOVMSKPD: return "vmovmskpd"; - case ND_INS_VMOVMSKPS: return "vmovmskps"; - case ND_INS_VMOVNTDQ: return "vmovntdq"; - case ND_INS_VMOVNTDQA: return "vmovntdqa"; - case ND_INS_VMOVNTPD: return "vmovntpd"; - case ND_INS_VMOVNTPS: return "vmovntps"; - case ND_INS_VMOVQ: return "vmovq"; - case ND_INS_VMOVSD: return "vmovsd"; - case ND_INS_VMOVSH: return "vmovsh"; - case ND_INS_VMOVSHDUP: return "vmovshdup"; - case ND_INS_VMOVSLDUP: return "vmovsldup"; - case ND_INS_VMOVSS: return "vmovss"; - case ND_INS_VMOVUPD: return "vmovupd"; - case ND_INS_VMOVUPS: return "vmovups"; - case ND_INS_VMOVW: return "vmovw"; - case ND_INS_VMPSADBW: return "vmpsadbw"; - case ND_INS_VMPTRLD: return "vmptrld"; - case ND_INS_VMPTRST: return "vmptrst"; - case ND_INS_VMREAD: return "vmread"; - case ND_INS_VMRESUME: return "vmresume"; - case ND_INS_VMRUN: return "vmrun"; - case ND_INS_VMSAVE: return "vmsave"; - case ND_INS_VMULPD: return "vmulpd"; - case ND_INS_VMULPH: return "vmulph"; - case ND_INS_VMULPS: return "vmulps"; - case ND_INS_VMULSD: return "vmulsd"; - case ND_INS_VMULSH: return "vmulsh"; - case ND_INS_VMULSS: return "vmulss"; - case ND_INS_VMWRITE: return "vmwrite"; - case ND_INS_VMXOFF: return "vmxoff"; - case ND_INS_VMXON: return "vmxon"; - case ND_INS_VORPD: return "vorpd"; - case ND_INS_VORPS: return "vorps"; - case ND_INS_VP2INTERSECTD: return "vp2intersectd"; - case ND_INS_VP2INTERSECTQ: return "vp2intersectq"; - case ND_INS_VP4DPWSSD: return "vp4dpwssd"; - case ND_INS_VP4DPWSSDS: return "vp4dpwssds"; - case ND_INS_VPABSB: return "vpabsb"; - case ND_INS_VPABSD: return "vpabsd"; - case ND_INS_VPABSQ: return "vpabsq"; - case ND_INS_VPABSW: return "vpabsw"; - case ND_INS_VPACKSSDW: return "vpackssdw"; - case ND_INS_VPACKSSWB: return "vpacksswb"; - case ND_INS_VPACKUSDW: return "vpackusdw"; - case ND_INS_VPACKUSWB: return "vpackuswb"; - case ND_INS_VPADDB: return "vpaddb"; - case ND_INS_VPADDD: return "vpaddd"; - case ND_INS_VPADDQ: return "vpaddq"; - case ND_INS_VPADDSB: return "vpaddsb"; - case ND_INS_VPADDSW: return "vpaddsw"; - case ND_INS_VPADDUSB: return "vpaddusb"; - case ND_INS_VPADDUSW: return "vpaddusw"; - case ND_INS_VPADDW: return "vpaddw"; - case ND_INS_VPALIGNR: return "vpalignr"; - case ND_INS_VPAND: return "vpand"; - case ND_INS_VPANDD: return "vpandd"; - case ND_INS_VPANDN: return "vpandn"; - case ND_INS_VPANDND: return "vpandnd"; - case ND_INS_VPANDNQ: return "vpandnq"; - case ND_INS_VPANDQ: return "vpandq"; - case ND_INS_VPAVGB: return "vpavgb"; - case ND_INS_VPAVGW: return "vpavgw"; - case ND_INS_VPBLENDD: return "vpblendd"; - case ND_INS_VPBLENDMB: return "vpblendmb"; - case ND_INS_VPBLENDMD: return "vpblendmd"; - case ND_INS_VPBLENDMQ: return "vpblendmq"; - case ND_INS_VPBLENDMW: return "vpblendmw"; - case ND_INS_VPBLENDVB: return "vpblendvb"; - case ND_INS_VPBLENDW: return "vpblendw"; - case ND_INS_VPBROADCASTB: return "vpbroadcastb"; - case ND_INS_VPBROADCASTD: return "vpbroadcastd"; - case ND_INS_VPBROADCASTMB2Q: return "vpbroadcastmb2q"; - case ND_INS_VPBROADCASTMW2D: return "vpbroadcastmw2d"; - case ND_INS_VPBROADCASTQ: return "vpbroadcastq"; - case ND_INS_VPBROADCASTW: return "vpbroadcastw"; - case ND_INS_VPCLMULQDQ: return "vpclmulqdq"; - case ND_INS_VPCMOV: return "vpcmov"; - case ND_INS_VPCMPB: return "vpcmpb"; - case ND_INS_VPCMPD: return "vpcmpd"; - case ND_INS_VPCMPEQB: return "vpcmpeqb"; - case ND_INS_VPCMPEQD: return "vpcmpeqd"; - case ND_INS_VPCMPEQQ: return "vpcmpeqq"; - case ND_INS_VPCMPEQW: return "vpcmpeqw"; - case ND_INS_VPCMPESTRI: return "vpcmpestri"; - case ND_INS_VPCMPESTRM: return "vpcmpestrm"; - case ND_INS_VPCMPGTB: return "vpcmpgtb"; - case ND_INS_VPCMPGTD: return "vpcmpgtd"; - case ND_INS_VPCMPGTQ: return "vpcmpgtq"; - case ND_INS_VPCMPGTW: return "vpcmpgtw"; - case ND_INS_VPCMPISTRI: return "vpcmpistri"; - case ND_INS_VPCMPISTRM: return "vpcmpistrm"; - case ND_INS_VPCMPQ: return "vpcmpq"; - case ND_INS_VPCMPUB: return "vpcmpub"; - case ND_INS_VPCMPUD: return "vpcmpud"; - case ND_INS_VPCMPUQ: return "vpcmpuq"; - case ND_INS_VPCMPUW: return "vpcmpuw"; - case ND_INS_VPCMPW: return "vpcmpw"; - case ND_INS_VPCOMB: return "vpcomb"; - case ND_INS_VPCOMD: return "vpcomd"; - case ND_INS_VPCOMPRESSB: return "vpcompressb"; - case ND_INS_VPCOMPRESSD: return "vpcompressd"; - case ND_INS_VPCOMPRESSQ: return "vpcompressq"; - case ND_INS_VPCOMPRESSW: return "vpcompressw"; - case ND_INS_VPCOMQ: return "vpcomq"; - case ND_INS_VPCOMUB: return "vpcomub"; - case ND_INS_VPCOMUD: return "vpcomud"; - case ND_INS_VPCOMUQ: return "vpcomuq"; - case ND_INS_VPCOMUW: return "vpcomuw"; - case ND_INS_VPCOMW: return "vpcomw"; - case ND_INS_VPCONFLICTD: return "vpconflictd"; - case ND_INS_VPCONFLICTQ: return "vpconflictq"; - case ND_INS_VPDPBSSD: return "vpdpbssd"; - case ND_INS_VPDPBSSDS: return "vpdpbssds"; - case ND_INS_VPDPBSUD: return "vpdpbsud"; - case ND_INS_VPDPBSUDS: return "vpdpbsuds"; - case ND_INS_VPDPBUSD: return "vpdpbusd"; - case ND_INS_VPDPBUSDS: return "vpdpbusds"; - case ND_INS_VPDPBUUD: return "vpdpbuud"; - case ND_INS_VPDPBUUDS: return "vpdpbuuds"; - case ND_INS_VPDPWSSD: return "vpdpwssd"; - case ND_INS_VPDPWSSDS: return "vpdpwssds"; - case ND_INS_VPDPWSUD: return "vpdpwsud"; - case ND_INS_VPDPWSUDS: return "vpdpwsuds"; - case ND_INS_VPDPWUSD: return "vpdpwusd"; - case ND_INS_VPDPWUSDS: return "vpdpwusds"; - case ND_INS_VPDPWUUD: return "vpdpwuud"; - case ND_INS_VPDPWUUDS: return "vpdpwuuds"; - case ND_INS_VPERM2F128: return "vperm2f128"; - case ND_INS_VPERM2I128: return "vperm2i128"; - case ND_INS_VPERMB: return "vpermb"; - case ND_INS_VPERMD: return "vpermd"; - case ND_INS_VPERMI2B: return "vpermi2b"; - case ND_INS_VPERMI2D: return "vpermi2d"; - case ND_INS_VPERMI2PD: return "vpermi2pd"; - case ND_INS_VPERMI2PS: return "vpermi2ps"; - case ND_INS_VPERMI2Q: return "vpermi2q"; - case ND_INS_VPERMI2W: return "vpermi2w"; - case ND_INS_VPERMIL2PD: return "vpermil2pd"; - case ND_INS_VPERMIL2PS: return "vpermil2ps"; - case ND_INS_VPERMILPD: return "vpermilpd"; - case ND_INS_VPERMILPS: return "vpermilps"; - case ND_INS_VPERMPD: return "vpermpd"; - case ND_INS_VPERMPS: return "vpermps"; - case ND_INS_VPERMQ: return "vpermq"; - case ND_INS_VPERMT2B: return "vpermt2b"; - case ND_INS_VPERMT2D: return "vpermt2d"; - case ND_INS_VPERMT2PD: return "vpermt2pd"; - case ND_INS_VPERMT2PS: return "vpermt2ps"; - case ND_INS_VPERMT2Q: return "vpermt2q"; - case ND_INS_VPERMT2W: return "vpermt2w"; - case ND_INS_VPERMW: return "vpermw"; - case ND_INS_VPEXPANDB: return "vpexpandb"; - case ND_INS_VPEXPANDD: return "vpexpandd"; - case ND_INS_VPEXPANDQ: return "vpexpandq"; - case ND_INS_VPEXPANDW: return "vpexpandw"; - case ND_INS_VPEXTRB: return "vpextrb"; - case ND_INS_VPEXTRD: return "vpextrd"; - case ND_INS_VPEXTRQ: return "vpextrq"; - case ND_INS_VPEXTRW: return "vpextrw"; - case ND_INS_VPGATHERDD: return "vpgatherdd"; - case ND_INS_VPGATHERDQ: return "vpgatherdq"; - case ND_INS_VPGATHERQD: return "vpgatherqd"; - case ND_INS_VPGATHERQQ: return "vpgatherqq"; - case ND_INS_VPHADDBD: return "vphaddbd"; - case ND_INS_VPHADDBQ: return "vphaddbq"; - case ND_INS_VPHADDBW: return "vphaddbw"; - case ND_INS_VPHADDD: return "vphaddd"; - case ND_INS_VPHADDDQ: return "vphadddq"; - case ND_INS_VPHADDSW: return "vphaddsw"; - case ND_INS_VPHADDUBD: return "vphaddubd"; - case ND_INS_VPHADDUBQ: return "vphaddubq"; - case ND_INS_VPHADDUBW: return "vphaddubw"; - case ND_INS_VPHADDUDQ: return "vphaddudq"; - case ND_INS_VPHADDUWD: return "vphadduwd"; - case ND_INS_VPHADDUWQ: return "vphadduwq"; - case ND_INS_VPHADDW: return "vphaddw"; - case ND_INS_VPHADDWD: return "vphaddwd"; - case ND_INS_VPHADDWQ: return "vphaddwq"; - case ND_INS_VPHMINPOSUW: return "vphminposuw"; - case ND_INS_VPHSUBBW: return "vphsubbw"; - case ND_INS_VPHSUBD: return "vphsubd"; - case ND_INS_VPHSUBDQ: return "vphsubdq"; - case ND_INS_VPHSUBSW: return "vphsubsw"; - case ND_INS_VPHSUBW: return "vphsubw"; - case ND_INS_VPHSUBWD: return "vphsubwd"; - case ND_INS_VPINSRB: return "vpinsrb"; - case ND_INS_VPINSRD: return "vpinsrd"; - case ND_INS_VPINSRQ: return "vpinsrq"; - case ND_INS_VPINSRW: return "vpinsrw"; - case ND_INS_VPLZCNTD: return "vplzcntd"; - case ND_INS_VPLZCNTQ: return "vplzcntq"; - case ND_INS_VPMACSDD: return "vpmacsdd"; - case ND_INS_VPMACSDQH: return "vpmacsdqh"; - case ND_INS_VPMACSDQL: return "vpmacsdql"; - case ND_INS_VPMACSSDD: return "vpmacssdd"; - case ND_INS_VPMACSSDQH: return "vpmacssdqh"; - case ND_INS_VPMACSSDQL: return "vpmacssdql"; - case ND_INS_VPMACSSWD: return "vpmacsswd"; - case ND_INS_VPMACSSWW: return "vpmacssww"; - case ND_INS_VPMACSWD: return "vpmacswd"; - case ND_INS_VPMACSWW: return "vpmacsww"; - case ND_INS_VPMADCSSWD: return "vpmadcsswd"; - case ND_INS_VPMADCSWD: return "vpmadcswd"; - case ND_INS_VPMADD52HUQ: return "vpmadd52huq"; - case ND_INS_VPMADD52LUQ: return "vpmadd52luq"; - case ND_INS_VPMADDUBSW: return "vpmaddubsw"; - case ND_INS_VPMADDWD: return "vpmaddwd"; - case ND_INS_VPMASKMOVD: return "vpmaskmovd"; - case ND_INS_VPMASKMOVQ: return "vpmaskmovq"; - case ND_INS_VPMAXSB: return "vpmaxsb"; - case ND_INS_VPMAXSD: return "vpmaxsd"; - case ND_INS_VPMAXSQ: return "vpmaxsq"; - case ND_INS_VPMAXSW: return "vpmaxsw"; - case ND_INS_VPMAXUB: return "vpmaxub"; - case ND_INS_VPMAXUD: return "vpmaxud"; - case ND_INS_VPMAXUQ: return "vpmaxuq"; - case ND_INS_VPMAXUW: return "vpmaxuw"; - case ND_INS_VPMINSB: return "vpminsb"; - case ND_INS_VPMINSD: return "vpminsd"; - case ND_INS_VPMINSQ: return "vpminsq"; - case ND_INS_VPMINSW: return "vpminsw"; - case ND_INS_VPMINUB: return "vpminub"; - case ND_INS_VPMINUD: return "vpminud"; - case ND_INS_VPMINUQ: return "vpminuq"; - case ND_INS_VPMINUW: return "vpminuw"; - case ND_INS_VPMOVB2M: return "vpmovb2m"; - case ND_INS_VPMOVD2M: return "vpmovd2m"; - case ND_INS_VPMOVDB: return "vpmovdb"; - case ND_INS_VPMOVDW: return "vpmovdw"; - case ND_INS_VPMOVM2B: return "vpmovm2b"; - case ND_INS_VPMOVM2D: return "vpmovm2d"; - case ND_INS_VPMOVM2Q: return "vpmovm2q"; - case ND_INS_VPMOVM2W: return "vpmovm2w"; - case ND_INS_VPMOVMSKB: return "vpmovmskb"; - case ND_INS_VPMOVQ2M: return "vpmovq2m"; - case ND_INS_VPMOVQB: return "vpmovqb"; - case ND_INS_VPMOVQD: return "vpmovqd"; - case ND_INS_VPMOVQW: return "vpmovqw"; - case ND_INS_VPMOVSDB: return "vpmovsdb"; - case ND_INS_VPMOVSDW: return "vpmovsdw"; - case ND_INS_VPMOVSQB: return "vpmovsqb"; - case ND_INS_VPMOVSQD: return "vpmovsqd"; - case ND_INS_VPMOVSQW: return "vpmovsqw"; - case ND_INS_VPMOVSWB: return "vpmovswb"; - case ND_INS_VPMOVSXBD: return "vpmovsxbd"; - case ND_INS_VPMOVSXBQ: return "vpmovsxbq"; - case ND_INS_VPMOVSXBW: return "vpmovsxbw"; - case ND_INS_VPMOVSXDQ: return "vpmovsxdq"; - case ND_INS_VPMOVSXWD: return "vpmovsxwd"; - case ND_INS_VPMOVSXWQ: return "vpmovsxwq"; - case ND_INS_VPMOVUSDB: return "vpmovusdb"; - case ND_INS_VPMOVUSDW: return "vpmovusdw"; - case ND_INS_VPMOVUSQB: return "vpmovusqb"; - case ND_INS_VPMOVUSQD: return "vpmovusqd"; - case ND_INS_VPMOVUSQW: return "vpmovusqw"; - case ND_INS_VPMOVUSWB: return "vpmovuswb"; - case ND_INS_VPMOVW2M: return "vpmovw2m"; - case ND_INS_VPMOVWB: return "vpmovwb"; - case ND_INS_VPMOVZXBD: return "vpmovzxbd"; - case ND_INS_VPMOVZXBQ: return "vpmovzxbq"; - case ND_INS_VPMOVZXBW: return "vpmovzxbw"; - case ND_INS_VPMOVZXDQ: return "vpmovzxdq"; - case ND_INS_VPMOVZXWD: return "vpmovzxwd"; - case ND_INS_VPMOVZXWQ: return "vpmovzxwq"; - case ND_INS_VPMULDQ: return "vpmuldq"; - case ND_INS_VPMULHRSW: return "vpmulhrsw"; - case ND_INS_VPMULHUW: return "vpmulhuw"; - case ND_INS_VPMULHW: return "vpmulhw"; - case ND_INS_VPMULLD: return "vpmulld"; - case ND_INS_VPMULLQ: return "vpmullq"; - case ND_INS_VPMULLW: return "vpmullw"; - case ND_INS_VPMULTISHIFTQB: return "vpmultishiftqb"; - case ND_INS_VPMULUDQ: return "vpmuludq"; - case ND_INS_VPOPCNTB: return "vpopcntb"; - case ND_INS_VPOPCNTD: return "vpopcntd"; - case ND_INS_VPOPCNTQ: return "vpopcntq"; - case ND_INS_VPOPCNTW: return "vpopcntw"; - case ND_INS_VPOR: return "vpor"; - case ND_INS_VPORD: return "vpord"; - case ND_INS_VPORQ: return "vporq"; - case ND_INS_VPPERM: return "vpperm"; - case ND_INS_VPROLD: return "vprold"; - case ND_INS_VPROLQ: return "vprolq"; - case ND_INS_VPROLVD: return "vprolvd"; - case ND_INS_VPROLVQ: return "vprolvq"; - case ND_INS_VPRORD: return "vprord"; - case ND_INS_VPRORQ: return "vprorq"; - case ND_INS_VPRORVD: return "vprorvd"; - case ND_INS_VPRORVQ: return "vprorvq"; - case ND_INS_VPROTB: return "vprotb"; - case ND_INS_VPROTD: return "vprotd"; - case ND_INS_VPROTQ: return "vprotq"; - case ND_INS_VPROTW: return "vprotw"; - case ND_INS_VPSADBW: return "vpsadbw"; - case ND_INS_VPSCATTERDD: return "vpscatterdd"; - case ND_INS_VPSCATTERDQ: return "vpscatterdq"; - case ND_INS_VPSCATTERQD: return "vpscatterqd"; - case ND_INS_VPSCATTERQQ: return "vpscatterqq"; - case ND_INS_VPSHAB: return "vpshab"; - case ND_INS_VPSHAD: return "vpshad"; - case ND_INS_VPSHAQ: return "vpshaq"; - case ND_INS_VPSHAW: return "vpshaw"; - case ND_INS_VPSHLB: return "vpshlb"; - case ND_INS_VPSHLD: return "vpshld"; - case ND_INS_VPSHLDD: return "vpshldd"; - case ND_INS_VPSHLDQ: return "vpshldq"; - case ND_INS_VPSHLDVD: return "vpshldvd"; - case ND_INS_VPSHLDVQ: return "vpshldvq"; - case ND_INS_VPSHLDVW: return "vpshldvw"; - case ND_INS_VPSHLDW: return "vpshldw"; - case ND_INS_VPSHLQ: return "vpshlq"; - case ND_INS_VPSHLW: return "vpshlw"; - case ND_INS_VPSHRDD: return "vpshrdd"; - case ND_INS_VPSHRDQ: return "vpshrdq"; - case ND_INS_VPSHRDVD: return "vpshrdvd"; - case ND_INS_VPSHRDVQ: return "vpshrdvq"; - case ND_INS_VPSHRDVW: return "vpshrdvw"; - case ND_INS_VPSHRDW: return "vpshrdw"; - case ND_INS_VPSHUFB: return "vpshufb"; - case ND_INS_VPSHUFBITQMB: return "vpshufbitqmb"; - case ND_INS_VPSHUFD: return "vpshufd"; - case ND_INS_VPSHUFHW: return "vpshufhw"; - case ND_INS_VPSHUFLW: return "vpshuflw"; - case ND_INS_VPSIGNB: return "vpsignb"; - case ND_INS_VPSIGND: return "vpsignd"; - case ND_INS_VPSIGNW: return "vpsignw"; - case ND_INS_VPSLLD: return "vpslld"; - case ND_INS_VPSLLDQ: return "vpslldq"; - case ND_INS_VPSLLQ: return "vpsllq"; - case ND_INS_VPSLLVD: return "vpsllvd"; - case ND_INS_VPSLLVQ: return "vpsllvq"; - case ND_INS_VPSLLVW: return "vpsllvw"; - case ND_INS_VPSLLW: return "vpsllw"; - case ND_INS_VPSRAD: return "vpsrad"; - case ND_INS_VPSRAQ: return "vpsraq"; - case ND_INS_VPSRAVD: return "vpsravd"; - case ND_INS_VPSRAVQ: return "vpsravq"; - case ND_INS_VPSRAVW: return "vpsravw"; - case ND_INS_VPSRAW: return "vpsraw"; - case ND_INS_VPSRLD: return "vpsrld"; - case ND_INS_VPSRLDQ: return "vpsrldq"; - case ND_INS_VPSRLQ: return "vpsrlq"; - case ND_INS_VPSRLVD: return "vpsrlvd"; - case ND_INS_VPSRLVQ: return "vpsrlvq"; - case ND_INS_VPSRLVW: return "vpsrlvw"; - case ND_INS_VPSRLW: return "vpsrlw"; - case ND_INS_VPSUBB: return "vpsubb"; - case ND_INS_VPSUBD: return "vpsubd"; - case ND_INS_VPSUBQ: return "vpsubq"; - case ND_INS_VPSUBSB: return "vpsubsb"; - case ND_INS_VPSUBSW: return "vpsubsw"; - case ND_INS_VPSUBUSB: return "vpsubusb"; - case ND_INS_VPSUBUSW: return "vpsubusw"; - case ND_INS_VPSUBW: return "vpsubw"; - case ND_INS_VPTERNLOGD: return "vpternlogd"; - case ND_INS_VPTERNLOGQ: return "vpternlogq"; - case ND_INS_VPTEST: return "vptest"; - case ND_INS_VPTESTMB: return "vptestmb"; - case ND_INS_VPTESTMD: return "vptestmd"; - case ND_INS_VPTESTMQ: return "vptestmq"; - case ND_INS_VPTESTMW: return "vptestmw"; - case ND_INS_VPTESTNMB: return "vptestnmb"; - case ND_INS_VPTESTNMD: return "vptestnmd"; - case ND_INS_VPTESTNMQ: return "vptestnmq"; - case ND_INS_VPTESTNMW: return "vptestnmw"; - case ND_INS_VPUNPCKHBW: return "vpunpckhbw"; - case ND_INS_VPUNPCKHDQ: return "vpunpckhdq"; - case ND_INS_VPUNPCKHQDQ: return "vpunpckhqdq"; - case ND_INS_VPUNPCKHWD: return "vpunpckhwd"; - case ND_INS_VPUNPCKLBW: return "vpunpcklbw"; - case ND_INS_VPUNPCKLDQ: return "vpunpckldq"; - case ND_INS_VPUNPCKLQDQ: return "vpunpcklqdq"; - case ND_INS_VPUNPCKLWD: return "vpunpcklwd"; - case ND_INS_VPXOR: return "vpxor"; - case ND_INS_VPXORD: return "vpxord"; - case ND_INS_VPXORQ: return "vpxorq"; - case ND_INS_VRANGEPD: return "vrangepd"; - case ND_INS_VRANGEPS: return "vrangeps"; - case ND_INS_VRANGESD: return "vrangesd"; - case ND_INS_VRANGESS: return "vrangess"; - case ND_INS_VRCP14PD: return "vrcp14pd"; - case ND_INS_VRCP14PS: return "vrcp14ps"; - case ND_INS_VRCP14SD: return "vrcp14sd"; - case ND_INS_VRCP14SS: return "vrcp14ss"; - case ND_INS_VRCP28PD: return "vrcp28pd"; - case ND_INS_VRCP28PS: return "vrcp28ps"; - case ND_INS_VRCP28SD: return "vrcp28sd"; - case ND_INS_VRCP28SS: return "vrcp28ss"; - case ND_INS_VRCPPH: return "vrcpph"; - case ND_INS_VRCPPS: return "vrcpps"; - case ND_INS_VRCPSH: return "vrcpsh"; - case ND_INS_VRCPSS: return "vrcpss"; - case ND_INS_VREDUCEPD: return "vreducepd"; - case ND_INS_VREDUCEPH: return "vreduceph"; - case ND_INS_VREDUCEPS: return "vreduceps"; - case ND_INS_VREDUCESD: return "vreducesd"; - case ND_INS_VREDUCESH: return "vreducesh"; - case ND_INS_VREDUCESS: return "vreducess"; - case ND_INS_VRNDSCALEPD: return "vrndscalepd"; - case ND_INS_VRNDSCALEPH: return "vrndscaleph"; - case ND_INS_VRNDSCALEPS: return "vrndscaleps"; - case ND_INS_VRNDSCALESD: return "vrndscalesd"; - case ND_INS_VRNDSCALESH: return "vrndscalesh"; - case ND_INS_VRNDSCALESS: return "vrndscaless"; - case ND_INS_VROUNDPD: return "vroundpd"; - case ND_INS_VROUNDPS: return "vroundps"; - case ND_INS_VROUNDSD: return "vroundsd"; - case ND_INS_VROUNDSS: return "vroundss"; - case ND_INS_VRSQRT14PD: return "vrsqrt14pd"; - case ND_INS_VRSQRT14PS: return "vrsqrt14ps"; - case ND_INS_VRSQRT14SD: return "vrsqrt14sd"; - case ND_INS_VRSQRT14SS: return "vrsqrt14ss"; - case ND_INS_VRSQRT28PD: return "vrsqrt28pd"; - case ND_INS_VRSQRT28PS: return "vrsqrt28ps"; - case ND_INS_VRSQRT28SD: return "vrsqrt28sd"; - case ND_INS_VRSQRT28SS: return "vrsqrt28ss"; - case ND_INS_VRSQRTPH: return "vrsqrtph"; - case ND_INS_VRSQRTPS: return "vrsqrtps"; - case ND_INS_VRSQRTSH: return "vrsqrtsh"; - case ND_INS_VRSQRTSS: return "vrsqrtss"; - case ND_INS_VSCALEFPD: return "vscalefpd"; - case ND_INS_VSCALEFPH: return "vscalefph"; - case ND_INS_VSCALEFPS: return "vscalefps"; - case ND_INS_VSCALEFSD: return "vscalefsd"; - case ND_INS_VSCALEFSH: return "vscalefsh"; - case ND_INS_VSCALEFSS: return "vscalefss"; - case ND_INS_VSCATTERDPD: return "vscatterdpd"; - case ND_INS_VSCATTERDPS: return "vscatterdps"; - case ND_INS_VSCATTERPF0DPD: return "vscatterpf0dpd"; - case ND_INS_VSCATTERPF0DPS: return "vscatterpf0dps"; - case ND_INS_VSCATTERPF0QPD: return "vscatterpf0qpd"; - case ND_INS_VSCATTERPF0QPS: return "vscatterpf0qps"; - case ND_INS_VSCATTERPF1DPD: return "vscatterpf1dpd"; - case ND_INS_VSCATTERPF1DPS: return "vscatterpf1dps"; - case ND_INS_VSCATTERPF1QPD: return "vscatterpf1qpd"; - case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps"; - case ND_INS_VSCATTERQPD: return "vscatterqpd"; - case ND_INS_VSCATTERQPS: return "vscatterqps"; - case ND_INS_VSHA512MSG1: return "vsha512msg1"; - case ND_INS_VSHA512MSG2: return "vsha512msg2"; - case ND_INS_VSHA512RNDS2: return "vsha512rnds2"; - case ND_INS_VSHUFF32X4: return "vshuff32x4"; - case ND_INS_VSHUFF64X2: return "vshuff64x2"; - case ND_INS_VSHUFI32X4: return "vshufi32x4"; - case ND_INS_VSHUFI64X2: return "vshufi64x2"; - case ND_INS_VSHUFPD: return "vshufpd"; - case ND_INS_VSHUFPS: return "vshufps"; - case ND_INS_VSM3MSG1: return "vsm3msg1"; - case ND_INS_VSM3MSG2: return "vsm3msg2"; - case ND_INS_VSM3RNDS2: return "vsm3rnds2"; - case ND_INS_VSM4KEY4: return "vsm4key4"; - case ND_INS_VSM4RNDS4: return "vsm4rnds4"; - case ND_INS_VSQRTPD: return "vsqrtpd"; - case ND_INS_VSQRTPH: return "vsqrtph"; - case ND_INS_VSQRTPS: return "vsqrtps"; - case ND_INS_VSQRTSD: return "vsqrtsd"; - case ND_INS_VSQRTSH: return "vsqrtsh"; - case ND_INS_VSQRTSS: return "vsqrtss"; - case ND_INS_VSTMXCSR: return "vstmxcsr"; - case ND_INS_VSUBPD: return "vsubpd"; - case ND_INS_VSUBPH: return "vsubph"; - case ND_INS_VSUBPS: return "vsubps"; - case ND_INS_VSUBSD: return "vsubsd"; - case ND_INS_VSUBSH: return "vsubsh"; - case ND_INS_VSUBSS: return "vsubss"; - case ND_INS_VTESTPD: return "vtestpd"; - case ND_INS_VTESTPS: return "vtestps"; - case ND_INS_VUCOMISD: return "vucomisd"; - case ND_INS_VUCOMISH: return "vucomish"; - case ND_INS_VUCOMISS: return "vucomiss"; - case ND_INS_VUNPCKHPD: return "vunpckhpd"; - case ND_INS_VUNPCKHPS: return "vunpckhps"; - case ND_INS_VUNPCKLPD: return "vunpcklpd"; - case ND_INS_VUNPCKLPS: return "vunpcklps"; - case ND_INS_VXORPD: return "vxorpd"; - case ND_INS_VXORPS: return "vxorps"; - case ND_INS_VZEROALL: return "vzeroall"; - case ND_INS_VZEROUPPER: return "vzeroupper"; - case ND_INS_WAIT: return "wait"; - case ND_INS_WBINVD: return "wbinvd"; - case ND_INS_WBNOINVD: return "wbnoinvd"; - case ND_INS_WRFSBASE: return "wrfsbase"; - case ND_INS_WRGSBASE: return "wrgsbase"; - case ND_INS_WRMSR: return "wrmsr"; - case ND_INS_WRMSRLIST: return "wrmsrlist"; - case ND_INS_WRMSRNS: return "wrmsrns"; - case ND_INS_WRPKRU: return "wrpkru"; - case ND_INS_WRSHR: return "wrshr"; - case ND_INS_WRSS: return "wrss"; - case ND_INS_WRUSS: return "wruss"; - case ND_INS_XABORT: return "xabort"; - case ND_INS_XADD: return "xadd"; - case ND_INS_XBEGIN: return "xbegin"; - case ND_INS_XCHG: return "xchg"; - case ND_INS_XCRYPTCBC: return "xcryptcbc"; - case ND_INS_XCRYPTCFB: return "xcryptcfb"; - case ND_INS_XCRYPTCTR: return "xcryptctr"; - case ND_INS_XCRYPTECB: return "xcryptecb"; - case ND_INS_XCRYPTOFB: return "xcryptofb"; - case ND_INS_XEND: return "xend"; - case ND_INS_XGETBV: return "xgetbv"; - case ND_INS_XLATB: return "xlatb"; - case ND_INS_XOR: return "xor"; - case ND_INS_XORPD: return "xorpd"; - case ND_INS_XORPS: return "xorps"; - case ND_INS_XRESLDTRK: return "xresldtrk"; - case ND_INS_XRSTOR: return "xrstor"; - case ND_INS_XRSTORS: return "xrstors"; - case ND_INS_XSAVE: return "xsave"; - case ND_INS_XSAVEC: return "xsavec"; - case ND_INS_XSAVEOPT: return "xsaveopt"; - case ND_INS_XSAVES: return "xsaves"; - case ND_INS_XSETBV: return "xsetbv"; - case ND_INS_XSHA1: return "xsha1"; - case ND_INS_XSHA256: return "xsha256"; - case ND_INS_XSTORE: return "xstore"; - case ND_INS_XSUSLDTRK: return "xsusldtrk"; - case ND_INS_XTEST: return "xtest"; - default: return "unhandled!"; - } - - return ""; -} - - -std::string ins_cat_to_str(ND_INS_CATEGORY category) -{ - switch (category) { - case ND_CAT_INVALID: return "invalid"; - case ND_CAT_3DNOW: return "3dnow"; - case ND_CAT_AES: return "aes"; - case ND_CAT_AESKL: return "aeskl"; - case ND_CAT_AMX: return "amx"; - case ND_CAT_ARITH: return "arith"; - case ND_CAT_AVX: return "avx"; - case ND_CAT_AVX2: return "avx2"; - case ND_CAT_AVX2GATHER: return "avx2gather"; - case ND_CAT_AVX512: return "avx512"; - case ND_CAT_AVX512BF16: return "avx512bf16"; - case ND_CAT_AVX512FP16: return "avx512fp16"; - case ND_CAT_AVX512VBMI: return "avx512vbmi"; - case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect"; - case ND_CAT_AVXIFMA: return "avxifma"; - case ND_CAT_AVXNECONVERT: return "avxneconvert"; - case ND_CAT_AVXVNNI: return "avxvnni"; - case ND_CAT_AVXVNNIINT16: return "avxvnniint16"; - case ND_CAT_AVXVNNIINT8: return "avxvnniint8"; - case ND_CAT_BITBYTE: return "bitbyte"; - case ND_CAT_BLEND: return "blend"; - case ND_CAT_BMI1: return "bmi1"; - case ND_CAT_BMI2: return "bmi2"; - case ND_CAT_BROADCAST: return "broadcast"; - case ND_CAT_CALL: return "call"; - case ND_CAT_CET: return "cet"; - case ND_CAT_CLDEMOTE: return "cldemote"; - case ND_CAT_CMOV: return "cmov"; - case ND_CAT_CMPCCXADD: return "cmpccxadd"; - case ND_CAT_COMPRESS: return "compress"; - case ND_CAT_COND_BR: return "cond_br"; - case ND_CAT_CONFLICT: return "conflict"; - case ND_CAT_CONVERT: return "convert"; - case ND_CAT_DATAXFER: return "dataxfer"; - case ND_CAT_DECIMAL: return "decimal"; - case ND_CAT_ENQCMD: return "enqcmd"; - case ND_CAT_EXPAND: return "expand"; - case ND_CAT_FLAGOP: return "flagop"; - case ND_CAT_FMA4: return "fma4"; - case ND_CAT_GATHER: return "gather"; - case ND_CAT_GFNI: return "gfni"; - case ND_CAT_HRESET: return "hreset"; - case ND_CAT_I386: return "i386"; - case ND_CAT_IFMA: return "ifma"; - case ND_CAT_INTERRUPT: return "interrupt"; - case ND_CAT_IO: return "io"; - case ND_CAT_IOSTRINGOP: return "iostringop"; - case ND_CAT_KL: return "kl"; - case ND_CAT_KMASK: return "kmask"; - case ND_CAT_KNL: return "knl"; - case ND_CAT_LKGS: return "lkgs"; - case ND_CAT_LOGIC: return "logic"; - case ND_CAT_LOGICAL: return "logical"; - case ND_CAT_LOGICAL_FP: return "logical_fp"; - case ND_CAT_LWP: return "lwp"; - case ND_CAT_LZCNT: return "lzcnt"; - case ND_CAT_MISC: return "misc"; - case ND_CAT_MMX: return "mmx"; - case ND_CAT_MOVDIR64B: return "movdir64b"; - case ND_CAT_MOVDIRI: return "movdiri"; - case ND_CAT_MPX: return "mpx"; - case ND_CAT_NOP: return "nop"; - case ND_CAT_PADLOCK: return "padlock"; - case ND_CAT_PCLMULQDQ: return "pclmulqdq"; - case ND_CAT_PCONFIG: return "pconfig"; - case ND_CAT_POP: return "pop"; - case ND_CAT_PREFETCH: return "prefetch"; - case ND_CAT_PTWRITE: return "ptwrite"; - case ND_CAT_PUSH: return "push"; - case ND_CAT_RAOINT: return "raoint"; - case ND_CAT_RDPID: return "rdpid"; - case ND_CAT_RDRAND: return "rdrand"; - case ND_CAT_RDSEED: return "rdseed"; - case ND_CAT_RDWRFSGS: return "rdwrfsgs"; - case ND_CAT_RET: return "ret"; - case ND_CAT_ROTATE: return "rotate"; - case ND_CAT_SCATTER: return "scatter"; - case ND_CAT_SEGOP: return "segop"; - case ND_CAT_SEMAPHORE: return "semaphore"; - case ND_CAT_SGX: return "sgx"; - case ND_CAT_SHA: return "sha"; - case ND_CAT_SHA512: return "sha512"; - case ND_CAT_SHIFT: return "shift"; - case ND_CAT_SM3: return "sm3"; - case ND_CAT_SM4: return "sm4"; - case ND_CAT_SMAP: return "smap"; - case ND_CAT_SSE: return "sse"; - case ND_CAT_SSE2: return "sse2"; - case ND_CAT_STRINGOP: return "stringop"; - case ND_CAT_STTNI: return "sttni"; - case ND_CAT_SYSCALL: return "syscall"; - case ND_CAT_SYSRET: return "sysret"; - case ND_CAT_SYSTEM: return "system"; - case ND_CAT_TDX: return "tdx"; - case ND_CAT_UD: return "ud"; - case ND_CAT_UINTR: return "uintr"; - case ND_CAT_UNCOND_BR: return "uncond_br"; - case ND_CAT_UNKNOWN: return "unknown"; - case ND_CAT_VAES: return "vaes"; - case ND_CAT_VFMA: return "vfma"; - case ND_CAT_VFMAPS: return "vfmaps"; - case ND_CAT_VNNI: return "vnni"; - case ND_CAT_VNNIW: return "vnniw"; - case ND_CAT_VPCLMULQDQ: return "vpclmulqdq"; - case ND_CAT_VPOPCNT: return "vpopcnt"; - case ND_CAT_VTX: return "vtx"; - case ND_CAT_WAITPKG: return "waitpkg"; - case ND_CAT_WBNOINVD: return "wbnoinvd"; - case ND_CAT_WIDE_KL: return "wide_kl"; - case ND_CAT_WIDENOP: return "widenop"; - case ND_CAT_X87_ALU: return "x87_alu"; - case ND_CAT_XOP: return "xop"; - case ND_CAT_XSAVE: return "xsave"; - } - - return ""; -} - - -std::string ins_set_to_str(ND_INS_SET ins_set) -{ - switch (ins_set) { - case ND_SET_INVALID: return "invalid"; - case ND_SET_3DNOW: return "3dnow"; - case ND_SET_ADX: return "adx"; - case ND_SET_AES: return "aes"; - case ND_SET_AMD: return "amd"; - case ND_SET_AMXBF16: return "amxbf16"; - case ND_SET_AMXCOMPLEX: return "amxcomplex"; - case ND_SET_AMXFP16: return "amxfp16"; - case ND_SET_AMXINT8: return "amxint8"; - case ND_SET_AMXTILE: return "amxtile"; - case ND_SET_AVX: return "avx"; - case ND_SET_AVX2: return "avx2"; - case ND_SET_AVX2GATHER: return "avx2gather"; - case ND_SET_AVX5124FMAPS: return "avx5124fmaps"; - case ND_SET_AVX5124VNNIW: return "avx5124vnniw"; - case ND_SET_AVX512BF16: return "avx512bf16"; - case ND_SET_AVX512BITALG: return "avx512bitalg"; - case ND_SET_AVX512BW: return "avx512bw"; - case ND_SET_AVX512CD: return "avx512cd"; - case ND_SET_AVX512DQ: return "avx512dq"; - case ND_SET_AVX512ER: return "avx512er"; - case ND_SET_AVX512F: return "avx512f"; - case ND_SET_AVX512FP16: return "avx512fp16"; - case ND_SET_AVX512IFMA: return "avx512ifma"; - case ND_SET_AVX512PF: return "avx512pf"; - case ND_SET_AVX512VBMI: return "avx512vbmi"; - case ND_SET_AVX512VBMI2: return "avx512vbmi2"; - case ND_SET_AVX512VNNI: return "avx512vnni"; - case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect"; - case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq"; - case ND_SET_AVXIFMA: return "avxifma"; - case ND_SET_AVXNECONVERT: return "avxneconvert"; - case ND_SET_AVXVNNI: return "avxvnni"; - case ND_SET_AVXVNNIINT16: return "avxvnniint16"; - case ND_SET_AVXVNNIINT8: return "avxvnniint8"; - case ND_SET_BMI1: return "bmi1"; - case ND_SET_BMI2: return "bmi2"; - case ND_SET_CET_SS: return "cet_ss"; - case ND_SET_CET_IBT: return "cet_ibt"; - case ND_SET_CLDEMOTE: return "cldemote"; - case ND_SET_CLFSH: return "clfsh"; - case ND_SET_CLFSHOPT: return "clfshopt"; - case ND_SET_CLWB: return "clwb"; - case ND_SET_CLZERO: return "clzero"; - case ND_SET_CMPCCXADD: return "cmpccxadd"; - case ND_SET_CMPXCHG16B: return "cmpxchg16b"; - case ND_SET_CYRIX: return "cyrix"; - case ND_SET_CYRIX_SMM: return "cyrix_smm"; - case ND_SET_ENQCMD: return "enqcmd"; - case ND_SET_F16C: return "f16c"; - case ND_SET_FMA: return "fma"; - case ND_SET_FMA4: return "fma4"; - case ND_SET_FRED: return "fred"; - case ND_SET_FXSAVE: return "fxsave"; - case ND_SET_GFNI: return "gfni"; - case ND_SET_HRESET: return "hreset"; - case ND_SET_I186: return "i186"; - case ND_SET_I286PROT: return "i286prot"; - case ND_SET_I286REAL: return "i286real"; - case ND_SET_I386: return "i386"; - case ND_SET_I486: return "i486"; - case ND_SET_I486REAL: return "i486real"; - case ND_SET_I64: return "i64"; - case ND_SET_I86: return "i86"; - case ND_SET_INVLPGB: return "invlpgb"; - case ND_SET_INVPCID: return "invpcid"; - case ND_SET_KL: return "kl"; - case ND_SET_LKGS: return "lkgs"; - case ND_SET_LONGMODE: return "longmode"; - case ND_SET_LWP: return "lwp"; - case ND_SET_LZCNT: return "lzcnt"; - case ND_SET_MCOMMIT: return "mcommit"; - case ND_SET_MMX: return "mmx"; - case ND_SET_MOVBE: return "movbe"; - case ND_SET_MOVDIR64B: return "movdir64b"; - case ND_SET_MOVDIRI: return "movdiri"; - case ND_SET_MPX: return "mpx"; - case ND_SET_MSRLIST: return "msrlist"; - case ND_SET_MWAITT: return "mwaitt"; - case ND_SET_PAUSE: return "pause"; - case ND_SET_PCLMULQDQ: return "pclmulqdq"; - case ND_SET_PCONFIG: return "pconfig"; - case ND_SET_PENTIUMREAL: return "pentiumreal"; - case ND_SET_PKU: return "pku"; - case ND_SET_POPCNT: return "popcnt"; - case ND_SET_PPRO: return "ppro"; - case ND_SET_PREFETCHITI: return "prefetchiti"; - case ND_SET_PREFETCH_NOP: return "prefetch_nop"; - case ND_SET_PTWRITE: return "ptwrite"; - case ND_SET_RAOINT: return "raoint"; - case ND_SET_RDPID: return "rdpid"; - case ND_SET_RDPMC: return "rdpmc"; - case ND_SET_RDPRU: return "rdpru"; - case ND_SET_RDRAND: return "rdrand"; - case ND_SET_RDSEED: return "rdseed"; - case ND_SET_RDTSCP: return "rdtscp"; - case ND_SET_RDWRFSGS: return "rdwrfsgs"; - case ND_SET_SERIALIZE: return "serialize"; - case ND_SET_SGX: return "sgx"; - case ND_SET_SHA: return "sha"; - case ND_SET_SHA512: return "sha512"; - case ND_SET_SM3: return "sm3"; - case ND_SET_SM4: return "sm4"; - case ND_SET_SMAP: return "smap"; - case ND_SET_SMX: return "smx"; - case ND_SET_SNP: return "snp"; - case ND_SET_SSE: return "sse"; - case ND_SET_SSE2: return "sse2"; - case ND_SET_SSE3: return "sse3"; - case ND_SET_SSE4: return "sse4"; - case ND_SET_SSE42: return "sse42"; - case ND_SET_SSE4A: return "sse4a"; - case ND_SET_SSSE3: return "ssse3"; - case ND_SET_SVM: return "svm"; - case ND_SET_TBM: return "tbm"; - case ND_SET_TDX: return "tdx"; - case ND_SET_TSE: return "tse"; - case ND_SET_TSX: return "tsx"; - case ND_SET_TSXLDTRK: return "tsxldtrk"; - case ND_SET_UD: return "ud"; - case ND_SET_UINTR: return "uintr"; - case ND_SET_UNKNOWN: return "unknown"; - case ND_SET_VAES: return "vaes"; - case ND_SET_VPCLMULQDQ: return "vpclmulqdq"; - case ND_SET_VTX: return "vtx"; - case ND_SET_WAITPKG: return "waitpkg"; - case ND_SET_WBNOINVD: return "wbnoinvd"; - case ND_SET_WRMSRNS: return "wrmsrns"; - case ND_SET_X87: return "x87"; - case ND_SET_XOP: return "xop"; - case ND_SET_XSAVE: return "xsave"; - case ND_SET_XSAVEC: return "xsavec"; - case ND_SET_XSAVES: return "xsaves"; - } - - return ""; -} - - -std::string reg_to_str(const int reg, const ND_REG_TYPE type) -{ - switch (type) { - case ND_REG_NOT_PRESENT: - return "not_preset"; - - case ND_REG_GPR: - switch (reg) { - case NDR_RAX: return "rax"; - case NDR_RCX: return "rcx"; - case NDR_RDX: return "rdx"; - case NDR_RBX: return "rbx"; - case NDR_RSP: return "rsp"; - case NDR_RBP: return "rbp"; - case NDR_RSI: return "rsi"; - case NDR_RDI: return "rdi"; - case NDR_R8: return "r8"; - case NDR_R9: return "r9"; - case NDR_R10: return "r10"; - case NDR_R11: return "r11"; - case NDR_R12: return "r12"; - case NDR_R13: return "r13"; - case NDR_R14: return "r14"; - case NDR_R15: return "r15"; - } - - return ""; - - case ND_REG_SEG: - switch (reg) { - case NDR_ES: return "es"; - case NDR_CS: return "cs"; - case NDR_SS: return "ss"; - case NDR_DS: return "ds"; - case NDR_FS: return "fs"; - case NDR_GS: return "gs"; - case NDR_INV6: return "inv6"; - case NDR_INV7: return "inv7"; - } - - return ""; - - case ND_REG_FPU: - return "fpu"; - case ND_REG_MMX: - return "mmx"; - case ND_REG_SSE: - return "sse"; - case ND_REG_CR: - return "cr"; - case ND_REG_DR: - return "dr"; - case ND_REG_TR: - return "tr"; - case ND_REG_BND: - return "bnd"; - case ND_REG_MSK: - return "msk"; - case ND_REG_TILE: - return "tile"; - case ND_REG_MSR: - return "msr"; - case ND_REG_XCR: - return "xcr"; - case ND_REG_SYS: - return "sys"; - case ND_REG_X87: - return "x87"; - case ND_REG_MXCSR: - return "mxcsr"; - case ND_REG_PKRU: - return "pkru"; - case ND_REG_SSP: - return "ssp"; - case ND_REG_FLG: - return "flg"; - case ND_REG_RIP: - return "rip"; - case ND_REG_UIF: - return "uif"; - } - - return ""; -} - - -std::string reg_type_to_str(const ND_REG_TYPE type) -{ - switch (type) { - case ND_REG_NOT_PRESENT: - return "present"; - case ND_REG_GPR: - return "gpr"; - case ND_REG_SEG: - return "seg"; - case ND_REG_FPU: - return "fpu"; - case ND_REG_MMX: - return "mmx"; - case ND_REG_SSE: - return "sse"; - case ND_REG_CR: - return "cr"; - case ND_REG_DR: - return "dr"; - case ND_REG_TR: - return "tr"; - case ND_REG_BND: - return "bnd"; - case ND_REG_MSK: - return "msk"; - case ND_REG_TILE: - return "tile"; - case ND_REG_MSR: - return "msr"; - case ND_REG_XCR: - return "xcr"; - case ND_REG_SYS: - return "sys"; - case ND_REG_X87: - return "x87"; - case ND_REG_MXCSR: - return "mxcsr"; - case ND_REG_PKRU: - return "pkru"; - case ND_REG_SSP: - return "ssp"; - case ND_REG_FLG: - return "flg"; - case ND_REG_RIP: - return "rip"; - case ND_REG_UIF: - return "uif"; - } - - return ""; -} diff --git a/disasmtool_lix/dumpers.cpp.bak b/disasmtool_lix/dumpers.cpp.bak deleted file mode 100644 index b74d9c2..0000000 --- a/disasmtool_lix/dumpers.cpp.bak +++ /dev/null @@ -1,1933 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#include "disasm.hpp" - - -std::string enc_mode_to_str(const uint8_t enc_mode) -{ - switch (enc_mode) { - case ND_ENCM_LEGACY: return "legacy"; - case ND_ENCM_XOP: return "xop"; - case ND_ENCM_VEX: return "vex"; - case ND_ENCM_EVEX: return "evex"; - } - - return ""; -} - - -std::string op_enc_to_str(const ND_OPERAND_ENCODING Encoding) -{ - switch (Encoding) { - case ND_OPE_NP: return "NP"; - case ND_OPE_R: return "R"; - case ND_OPE_M: return "M"; - case ND_OPE_V: return "V"; - case ND_OPE_O: return "O"; - case ND_OPE_I: return "I"; - case ND_OPE_D: return "D"; - case ND_OPE_C: return "C"; - case ND_OPE_1: return "1"; - case ND_OPE_A: return "A"; - case ND_OPE_L: return "L"; - case ND_OPE_E: return "E"; - case ND_OPE_S: return "S"; - default: return ""; - } -} - - -std::string op_type_to_str(const ND_OPERAND_TYPE type) -{ - switch(type) { - case ND_OP_NOT_PRESENT: - return "not_present"; - case ND_OP_REG: - return "register"; - case ND_OP_MEM: - return "memory"; - case ND_OP_IMM: - return "immediate"; - case ND_OP_OFFS: - return "offset"; - case ND_OP_ADDR: - return "address"; - case ND_OP_CONST: - return "const"; - case ND_OP_BANK: - return "bank"; - } - - return ""; -} - - -std::string ins_class_to_str(const ND_INS_CLASS cls) -{ - switch (cls) { - case ND_INS_INVALID: return "invalid"; - case ND_INS_AAA: return "aaa"; - case ND_INS_AAD: return "aad"; - case ND_INS_AAM: return "aam"; - case ND_INS_AAS: return "aas"; - case ND_INS_ADC: return "adc"; - case ND_INS_ADCX: return "adcx"; - case ND_INS_ADD: return "add"; - case ND_INS_ADDPD: return "addpd"; - case ND_INS_ADDPS: return "addps"; - case ND_INS_ADDSD: return "addsd"; - case ND_INS_ADDSS: return "addss"; - case ND_INS_ADDSUBPD: return "addsubpd"; - case ND_INS_ADDSUBPS: return "addsubps"; - case ND_INS_ADOX: return "adox"; - case ND_INS_AESDEC: return "aesdec"; - case ND_INS_AESDEC128KL: return "aesdec128kl"; - case ND_INS_AESDEC256KL: return "aesdec256kl"; - case ND_INS_AESDECWIDE128KL: return "aesdecwide128kl"; - case ND_INS_AESDECWIDE256KL: return "aesdecwide256kl"; - case ND_INS_AESDECLAST: return "aesdeclast"; - case ND_INS_AESENC: return "aesenc"; - case ND_INS_AESENC128KL: return "aesenc128kl"; - case ND_INS_AESENC256KL: return "aesenc256kl"; - case ND_INS_AESENCWIDE128KL: return "aesencwide128kl"; - case ND_INS_AESENCWIDE256KL: return "aesencwide256kl"; - case ND_INS_AESENCLAST: return "aesenclast"; - case ND_INS_AESIMC: return "aesimc"; - case ND_INS_AESKEYGENASSIST: return "aeskeygenassist"; - case ND_INS_ALTINST: return "altinst"; - case ND_INS_AND: return "and"; - case ND_INS_ANDN: return "andn"; - case ND_INS_ANDNPD: return "andnpd"; - case ND_INS_ANDNPS: return "andnps"; - case ND_INS_ANDPD: return "andpd"; - case ND_INS_ANDPS: return "andps"; - case ND_INS_ARPL: return "arpl"; - case ND_INS_BEXTR: return "bextr"; - case ND_INS_BLCFILL: return "blcfill"; - case ND_INS_BLCI: return "blci"; - case ND_INS_BLCIC: return "blcic"; - case ND_INS_BLCMSK: return "blcmsk"; - case ND_INS_BLCS: return "blcs"; - case ND_INS_BLENDPD: return "blendpd"; - case ND_INS_BLENDPS: return "blendps"; - case ND_INS_BLENDVPD: return "blendvpd"; - case ND_INS_BLENDVPS: return "blendvps"; - case ND_INS_BLSFILL: return "blsfill"; - case ND_INS_BLSI: return "blsi"; - case ND_INS_BLSIC: return "blsic"; - case ND_INS_BLSMSK: return "blsmsk"; - case ND_INS_BLSR: return "blsr"; - case ND_INS_BNDCL: return "bndcl"; - case ND_INS_BNDCN: return "bndcn"; - case ND_INS_BNDCU: return "bndcu"; - case ND_INS_BNDLDX: return "bndldx"; - case ND_INS_BNDMK: return "bndmk"; - case ND_INS_BNDMOV: return "bndmov"; - case ND_INS_BNDSTX: return "bndstx"; - case ND_INS_BOUND: return "bound"; - case ND_INS_BSF: return "bsf"; - case ND_INS_BSR: return "bsr"; - case ND_INS_BSWAP: return "bswap"; - case ND_INS_BT: return "bt"; - case ND_INS_BTC: return "btc"; - case ND_INS_BTR: return "btr"; - case ND_INS_BTS: return "bts"; - case ND_INS_BZHI: return "bzhi"; - case ND_INS_CALLFD: return "callfd"; - case ND_INS_CALLFI: return "callfi"; - case ND_INS_CALLNI: return "callni"; - case ND_INS_CALLNR: return "callnr"; - case ND_INS_CBW: return "cbw"; - case ND_INS_CDQ: return "cdq"; - case ND_INS_CDQE: return "cdqe"; - case ND_INS_CLAC: return "clac"; - case ND_INS_CLC: return "clc"; - case ND_INS_CLD: return "cld"; - case ND_INS_CLDEMOTE: return "cldemote"; - case ND_INS_CLEVICT0: return "clevict0"; - case ND_INS_CLEVICT1: return "clevict1"; - case ND_INS_CLFLUSH: return "clflush"; - case ND_INS_CLFLUSHOPT: return "clflushopt"; - case ND_INS_CLGI: return "clgi"; - case ND_INS_CLI: return "cli"; - case ND_INS_CLRSSBSY: return "clrssbsy"; - case ND_INS_CLTS: return "clts"; - case ND_INS_CLWB: return "clwb"; - case ND_INS_CLZERO: return "clzero"; - case ND_INS_CMC: return "cmc"; - case ND_INS_CMOVcc: return "cmovcc"; - case ND_INS_CMP: return "cmp"; - case ND_INS_CMPPD: return "cmppd"; - case ND_INS_CMPPS: return "cmpps"; - case ND_INS_CMPS: return "cmps"; - case ND_INS_CMPSD: return "cmpsd"; - case ND_INS_CMPSS: return "cmpss"; - case ND_INS_CMPXCHG: return "cmpxchg"; - case ND_INS_CMPXCHG16B: return "cmpxchg16b"; - case ND_INS_CMPXCHG8B: return "cmpxchg8b"; - case ND_INS_COMISD: return "comisd"; - case ND_INS_COMISS: return "comiss"; - case ND_INS_CPUID: return "cpuid"; - case ND_INS_CPU_READ: return "cpuread"; - case ND_INS_CPU_WRITE: return "cpuwrite"; - case ND_INS_CQO: return "cqo"; - case ND_INS_CRC32: return "crc32"; - case ND_INS_CVTDQ2PD: return "cvtdq2pd"; - case ND_INS_CVTDQ2PS: return "cvtdq2ps"; - case ND_INS_CVTPD2DQ: return "cvtpd2dq"; - case ND_INS_CVTPD2PI: return "cvtpd2pi"; - case ND_INS_CVTPD2PS: return "cvtpd2ps"; - case ND_INS_CVTPI2PD: return "cvtpi2pd"; - case ND_INS_CVTPI2PS: return "cvtpi2ps"; - case ND_INS_CVTPS2DQ: return "cvtps2dq"; - case ND_INS_CVTPS2PD: return "cvtps2pd"; - case ND_INS_CVTPS2PI: return "cvtps2pi"; - case ND_INS_CVTSD2SI: return "cvtsd2si"; - case ND_INS_CVTSD2SS: return "cvtsd2ss"; - case ND_INS_CVTSI2SD: return "cvtsi2sd"; - case ND_INS_CVTSI2SS: return "cvtsi2ss"; - case ND_INS_CVTSS2SD: return "cvtss2sd"; - case ND_INS_CVTSS2SI: return "cvtss2si"; - case ND_INS_CVTTPD2DQ: return "cvttpd2dq"; - case ND_INS_CVTTPD2PI: return "cvttpd2pi"; - case ND_INS_CVTTPS2DQ: return "cvttps2dq"; - case ND_INS_CVTTPS2PI: return "cvttps2pi"; - case ND_INS_CVTTSD2SI: return "cvttsd2si"; - case ND_INS_CVTTSS2SI: return "cvttss2si"; - case ND_INS_CWD: return "cwd"; - case ND_INS_CWDE: return "cwde"; - case ND_INS_DAA: return "daa"; - case ND_INS_DAS: return "das"; - case ND_INS_DEC: return "dec"; - case ND_INS_DELAY: return "delay"; - case ND_INS_DIV: return "div"; - case ND_INS_DIVPD: return "divpd"; - case ND_INS_DIVPS: return "divps"; - case ND_INS_DIVSD: return "divsd"; - case ND_INS_DIVSS: return "divss"; - case ND_INS_DMINT: return "dmint"; - case ND_INS_DPPD: return "dppd"; - case ND_INS_DPPS: return "dpps"; - case ND_INS_EMMS: return "emms"; - case ND_INS_ENCLS: return "encls"; - case ND_INS_ENCLU: return "enclu"; - case ND_INS_ENCLV: return "enclv"; - case ND_INS_ENCODEKEY128: return "encodekey128"; - case ND_INS_ENCODEKEY256: return "encodekey256"; - case ND_INS_ENDBR: return "endbr"; - case ND_INS_ENQCMD: return "enqcmd"; - case ND_INS_ENQCMDS: return "enqcmds"; - case ND_INS_ENTER: return "enter"; - case ND_INS_ERETS: return "erets"; - case ND_INS_ERETU: return "eretu"; - case ND_INS_EXTRACTPS: return "extractps"; - case ND_INS_EXTRQ: return "extrq"; - case ND_INS_F2XM1: return "f2xm1"; - case ND_INS_FABS: return "fabs"; - case ND_INS_FADD: return "fadd"; - case ND_INS_FADDP: return "faddp"; - case ND_INS_FBLD: return "fbld"; - case ND_INS_FBSTP: return "fbstp"; - case ND_INS_FCHS: return "fchs"; - case ND_INS_FCMOVB: return "fcmovb"; - case ND_INS_FCMOVBE: return "fcmovbe"; - case ND_INS_FCMOVE: return "fcmove"; - case ND_INS_FCMOVNB: return "fcmovnb"; - case ND_INS_FCMOVNBE: return "fcmovnbe"; - case ND_INS_FCMOVNE: return "fcmovne"; - case ND_INS_FCMOVNU: return "fcmovnu"; - case ND_INS_FCMOVU: return "fcmovu"; - case ND_INS_FCOM: return "fcom"; - case ND_INS_FCOMI: return "fcomi"; - case ND_INS_FCOMIP: return "fcomip"; - case ND_INS_FCOMP: return "fcomp"; - case ND_INS_FCOMPP: return "fcompp"; - case ND_INS_FCOS: return "fcos"; - case ND_INS_FDECSTP: return "fdecstp"; - case ND_INS_FDIV: return "fdiv"; - case ND_INS_FDIVP: return "fdivp"; - case ND_INS_FDIVR: return "fdivr"; - case ND_INS_FDIVRP: return "fdivrp"; - case ND_INS_FEMMS: return "femms"; - case ND_INS_FFREE: return "ffree"; - case ND_INS_FFREEP: return "ffreep"; - case ND_INS_FIADD: return "fiadd"; - case ND_INS_FICOM: return "ficom"; - case ND_INS_FICOMP: return "ficomp"; - case ND_INS_FIDIV: return "fidiv"; - case ND_INS_FIDIVR: return "fidivr"; - case ND_INS_FILD: return "fild"; - case ND_INS_FIMUL: return "fimul"; - case ND_INS_FINCSTP: return "fincstp"; - case ND_INS_FIST: return "fist"; - case ND_INS_FISTP: return "fistp"; - case ND_INS_FISTTP: return "fisttp"; - case ND_INS_FISUB: return "fisub"; - case ND_INS_FISUBR: return "fisubr"; - case ND_INS_FLD: return "fld"; - case ND_INS_FLD1: return "fld1"; - case ND_INS_FLDCW: return "fldcw"; - case ND_INS_FLDENV: return "fldenv"; - case ND_INS_FLDL2E: return "fldl2e"; - case ND_INS_FLDL2T: return "fldl2t"; - case ND_INS_FLDLG2: return "fldlg2"; - case ND_INS_FLDLN2: return "fldln2"; - case ND_INS_FLDPI: return "fldpi"; - case ND_INS_FLDZ: return "fldz"; - case ND_INS_FMUL: return "fmul"; - case ND_INS_FMULP: return "fmulp"; - case ND_INS_FNCLEX: return "fnclex"; - case ND_INS_FNDISI: return "fndisi"; - case ND_INS_FNINIT: return "fninit"; - case ND_INS_FNOP: return "fnop"; - case ND_INS_FNSAVE: return "fnsave"; - case ND_INS_FNSTCW: return "fnstcw"; - case ND_INS_FNSTENV: return "fnstenv"; - case ND_INS_FNSTSW: return "fnstsw"; - case ND_INS_FPATAN: return "fpatan"; - case ND_INS_FPREM: return "fprem"; - case ND_INS_FPREM1: return "fprem1"; - case ND_INS_FPTAN: return "fptan"; - case ND_INS_FRINEAR: return "frinear"; - case ND_INS_FRNDINT: return "frndint"; - case ND_INS_FRSTOR: return "frstor"; - case ND_INS_FSCALE: return "fscale"; - case ND_INS_FSIN: return "fsin"; - case ND_INS_FSINCOS: return "fsincos"; - case ND_INS_FSQRT: return "fsqrt"; - case ND_INS_FST: return "fst"; - case ND_INS_FSTDW: return "fstdw"; - case ND_INS_FSTP: return "fstp"; - case ND_INS_FSTPNCE: return "fstpnce"; - case ND_INS_FSTSG: return "fstsg"; - case ND_INS_FSUB: return "fsub"; - case ND_INS_FSUBP: return "fsubp"; - case ND_INS_FSUBR: return "fsubr"; - case ND_INS_FSUBRP: return "fsubrp"; - case ND_INS_FTST: return "ftst"; - case ND_INS_FUCOM: return "fucom"; - case ND_INS_FUCOMI: return "fucomi"; - case ND_INS_FUCOMIP: return "fucomip"; - case ND_INS_FUCOMP: return "fucomp"; - case ND_INS_FUCOMPP: return "fucompp"; - case ND_INS_FXAM: return "fxam"; - case ND_INS_FXCH: return "fxch"; - case ND_INS_FXRSTOR: return "fxrstor"; - case ND_INS_FXRSTOR64: return "fxrstor64"; - case ND_INS_FXSAVE: return "fxsave"; - case ND_INS_FXSAVE64: return "fxsave64"; - case ND_INS_FXTRACT: return "fxtract"; - case ND_INS_FYL2X: return "fyl2x"; - case ND_INS_FYL2XP1: return "fyl2xp1"; - case ND_INS_GETSEC: return "getsec"; - case ND_INS_GF2P8AFFINEINVQB: return "gf2p8affineinvqb"; - case ND_INS_GF2P8AFFINEQB: return "gf2p8affineqb"; - case ND_INS_GF2P8MULB: return "gf2p8mulb"; - case ND_INS_HADDPD: return "haddpd"; - case ND_INS_HADDPS: return "haddps"; - case ND_INS_HLT: return "hlt"; - case ND_INS_HSUBPD: return "hsubpd"; - case ND_INS_HSUBPS: return "hsubps"; - case ND_INS_IDIV: return "idiv"; - case ND_INS_IMUL: return "imul"; - case ND_INS_IN: return "in"; - case ND_INS_INC: return "inc"; - case ND_INS_INCSSP: return "incssp"; - case ND_INS_INS: return "ins"; - case ND_INS_INSERTPS: return "insertps"; - case ND_INS_INSERTQ: return "insertq"; - case ND_INS_INT: return "int"; - case ND_INS_INT1: return "int1"; - case ND_INS_INT3: return "int3"; - case ND_INS_INTO: return "into"; - case ND_INS_INVD: return "invd"; - case ND_INS_INVEPT: return "invept"; - case ND_INS_INVLPG: return "invlpg"; - case ND_INS_INVLPGA: return "invlpga"; - case ND_INS_INVLPGB: return "invlpgb"; - case ND_INS_INVPCID: return "invpcid"; - case ND_INS_INVVPID: return "invvpid"; - case ND_INS_IRET: return "iret"; - case ND_INS_JMPE: return "jmpe"; - case ND_INS_JMPFD: return "jmpfd"; - case ND_INS_JMPFI: return "jmpfi"; - case ND_INS_JMPNI: return "jmpni"; - case ND_INS_JMPNR: return "jmpnr"; - case ND_INS_Jcc: return "jcc"; - case ND_INS_JrCXZ: return "jrcxz"; - case ND_INS_KADD: return "kadd"; - case ND_INS_KAND: return "kand"; - case ND_INS_KANDN: return "kandn"; - case ND_INS_KMERGE2L1H: return "kmerge2l1h"; - case ND_INS_KMERGE2L1L: return "kmerge2l1l"; - case ND_INS_KMOV: return "kmov"; - case ND_INS_KNOT: return "knot"; - case ND_INS_KOR: return "kor"; - case ND_INS_KORTEST: return "kortest"; - case ND_INS_KSHIFTL: return "kshiftl"; - case ND_INS_KSHIFTR: return "kshiftr"; - case ND_INS_KTEST: return "ktest"; - case ND_INS_KUNPCKBW: return "kunpckbw"; - case ND_INS_KUNPCKDQ: return "kunpckdq"; - case ND_INS_KUNPCKWD: return "kunpckwd"; - case ND_INS_KXNOR: return "kxnor"; - case ND_INS_KXOR: return "kxor"; - case ND_INS_LAHF: return "lahf"; - case ND_INS_LAR: return "lar"; - case ND_INS_LDDQU: return "lddqu"; - case ND_INS_LDMXCSR: return "ldmxcsr"; - case ND_INS_LDS: return "lds"; - case ND_INS_LDTILECFG: return "ldtilecfg"; - case ND_INS_LEA: return "lea"; - case ND_INS_LEAVE: return "leave"; - case ND_INS_LES: return "les"; - case ND_INS_LFENCE: return "lfence"; - case ND_INS_LFS: return "lfs"; - case ND_INS_LGDT: return "lgdt"; - case ND_INS_LGS: return "lgs"; - case ND_INS_LIDT: return "lidt"; - case ND_INS_LKGS: return "lkgs"; - case ND_INS_LLDT: return "lldt"; - case ND_INS_LLWPCB: return "llwpcb"; - case ND_INS_LMSW: return "lmsw"; - case ND_INS_LOADIWKEY: return "loadiwkey"; - case ND_INS_LODS: return "lods"; - case ND_INS_LOOP: return "loop"; - case ND_INS_LOOPNZ: return "loopnz"; - case ND_INS_LOOPZ: return "loopz"; - case ND_INS_LSL: return "lsl"; - case ND_INS_LSS: return "lss"; - case ND_INS_LTR: return "ltr"; - case ND_INS_LWPINS: return "lwpins"; - case ND_INS_LWPVAL: return "lwpval"; - case ND_INS_LZCNT: return "lzcnt"; - case ND_INS_MASKMOVDQU: return "maskmovdqu"; - case ND_INS_MASKMOVQ: return "maskmovq"; - case ND_INS_MAXPD: return "maxpd"; - case ND_INS_MAXPS: return "maxps"; - case ND_INS_MAXSD: return "maxsd"; - case ND_INS_MAXSS: return "maxss"; - case ND_INS_MCOMMIT: return "mcommit"; - case ND_INS_MFENCE: return "mfence"; - case ND_INS_MINPD: return "minpd"; - case ND_INS_MINPS: return "minps"; - case ND_INS_MINSD: return "minsd"; - case ND_INS_MINSS: return "minss"; - case ND_INS_MONITOR: return "monitor"; - case ND_INS_MONITORX: return "monitorx"; - case ND_INS_MONTMUL: return "montmul"; - case ND_INS_MOV: return "mov"; - case ND_INS_MOVAPD: return "movapd"; - case ND_INS_MOVAPS: return "movaps"; - case ND_INS_MOVBE: return "movbe"; - case ND_INS_MOVD: return "movd"; - case ND_INS_MOVDDUP: return "movddup"; - case ND_INS_MOVDIR64B: return "movdir64b"; - case ND_INS_MOVDIRI: return "movdiri"; - case ND_INS_MOVDQ2Q: return "movdq2q"; - case ND_INS_MOVDQA: return "movdqa"; - case ND_INS_MOVDQU: return "movdqu"; - case ND_INS_MOVHLPS: return "movhlps"; - case ND_INS_MOVHPD: return "movhpd"; - case ND_INS_MOVHPS: return "movhps"; - case ND_INS_MOVLHPS: return "movlhps"; - case ND_INS_MOVLPD: return "movlpd"; - case ND_INS_MOVLPS: return "movlps"; - case ND_INS_MOVMSKPD: return "movmskpd"; - case ND_INS_MOVMSKPS: return "movmskps"; - case ND_INS_MOVNTDQ: return "movntdq"; - case ND_INS_MOVNTDQA: return "movntdqa"; - case ND_INS_MOVNTI: return "movnti"; - case ND_INS_MOVNTPD: return "movntpd"; - case ND_INS_MOVNTPS: return "movntps"; - case ND_INS_MOVNTQ: return "movntq"; - case ND_INS_MOVNTSD: return "movntsd"; - case ND_INS_MOVNTSS: return "movntss"; - case ND_INS_MOVQ: return "movq"; - case ND_INS_MOVQ2DQ: return "movq2dq"; - case ND_INS_MOVS: return "movs"; - case ND_INS_MOVSD: return "movsd"; - case ND_INS_MOVSHDUP: return "movshdup"; - case ND_INS_MOVSLDUP: return "movsldup"; - case ND_INS_MOVSS: return "movss"; - case ND_INS_MOVSX: return "movsx"; - case ND_INS_MOVSXD: return "movsxd"; - case ND_INS_MOVUPD: return "movupd"; - case ND_INS_MOVUPS: return "movups"; - case ND_INS_MOVZX: return "movzx"; - case ND_INS_MOV_CR: return "movcr"; - case ND_INS_MOV_DR: return "movdr"; - case ND_INS_MOV_TR: return "movtr"; - case ND_INS_MPSADBW: return "mpsadbw"; - case ND_INS_MUL: return "mul"; - case ND_INS_MULPD: return "mulpd"; - case ND_INS_MULPS: return "mulps"; - case ND_INS_MULSD: return "mulsd"; - case ND_INS_MULSS: return "mulss"; - case ND_INS_MULX: return "mulx"; - case ND_INS_MWAIT: return "mwait"; - case ND_INS_MWAITX: return "mwaitx"; - case ND_INS_NEG: return "neg"; - case ND_INS_NOP: return "nop"; - case ND_INS_NOT: return "not"; - case ND_INS_OR: return "or"; - case ND_INS_ORPD: return "orpd"; - case ND_INS_ORPS: return "orps"; - case ND_INS_OUT: return "out"; - case ND_INS_OUTS: return "outs"; - case ND_INS_PABSB: return "pabsb"; - case ND_INS_PABSD: return "pabsd"; - case ND_INS_PABSW: return "pabsw"; - case ND_INS_PACKSSDW: return "packssdw"; - case ND_INS_PACKSSWB: return "packsswb"; - case ND_INS_PACKUSDW: return "packusdw"; - case ND_INS_PACKUSWB: return "packuswb"; - case ND_INS_PADDB: return "paddb"; - case ND_INS_PADDD: return "paddd"; - case ND_INS_PADDQ: return "paddq"; - case ND_INS_PADDSB: return "paddsb"; - case ND_INS_PADDSW: return "paddsw"; - case ND_INS_PADDUSB: return "paddusb"; - case ND_INS_PADDUSW: return "paddusw"; - case ND_INS_PADDW: return "paddw"; - case ND_INS_PALIGNR: return "palignr"; - case ND_INS_PAND: return "pand"; - case ND_INS_PANDN: return "pandn"; - case ND_INS_PAUSE: return "pause"; - case ND_INS_PAVGB: return "pavgb"; - case ND_INS_PAVGUSB: return "pavgusb"; - case ND_INS_PAVGW: return "pavgw"; - case ND_INS_PBLENDVB: return "pblendvb"; - case ND_INS_PBLENDW: return "pblendw"; - case ND_INS_PCLMULQDQ: return "pclmulqdq"; - case ND_INS_PCMPEQB: return "pcmpeqb"; - case ND_INS_PCMPEQD: return "pcmpeqd"; - case ND_INS_PCMPEQQ: return "pcmpeqq"; - case ND_INS_PCMPEQW: return "pcmpeqw"; - case ND_INS_PCMPESTRI: return "pcmpestri"; - case ND_INS_PCMPESTRM: return "pcmpestrm"; - case ND_INS_PCMPGTB: return "pcmpgtb"; - case ND_INS_PCMPGTD: return "pcmpgtd"; - case ND_INS_PCMPGTQ: return "pcmpgtq"; - case ND_INS_PCMPGTW: return "pcmpgtw"; - case ND_INS_PCMPISTRI: return "pcmpistri"; - case ND_INS_PCMPISTRM: return "pcmpistrm"; - case ND_INS_PCONFIG: return "pconfig"; - case ND_INS_PDEP: return "pdep"; - case ND_INS_PEXT: return "pext"; - case ND_INS_PEXTRB: return "pextrb"; - case ND_INS_PEXTRD: return "pextrd"; - case ND_INS_PEXTRQ: return "pextrq"; - case ND_INS_PEXTRW: return "pextrw"; - case ND_INS_PF2ID: return "pf2id"; - case ND_INS_PF2IW: return "pf2iw"; - case ND_INS_PFACC: return "pfacc"; - case ND_INS_PFADD: return "pfadd"; - case ND_INS_PFCMPEQ: return "pfcmpeq"; - case ND_INS_PFCMPGE: return "pfcmpge"; - case ND_INS_PFCMPGT: return "pfcmpgt"; - case ND_INS_PFMAX: return "pfmax"; - case ND_INS_PFMIN: return "pfmin"; - case ND_INS_PFMUL: return "pfmul"; - case ND_INS_PFNACC: return "pfnacc"; - case ND_INS_PFPNACC: return "pfpnacc"; - case ND_INS_PFRCP: return "pfrcp"; - case ND_INS_PFRCPIT1: return "pfrcpit1"; - case ND_INS_PFRCPIT2: return "pfrcpit2"; - case ND_INS_PFRCPV: return "pfrcpv"; - case ND_INS_PFRSQIT1: return "pfrsqit1"; - case ND_INS_PFRSQRT: return "pfrsqrt"; - case ND_INS_PFRSQRTV: return "pfrsqrtv"; - case ND_INS_PFSUB: return "pfsub"; - case ND_INS_PFSUBR: return "pfsubr"; - case ND_INS_PHADDD: return "phaddd"; - case ND_INS_PHADDSW: return "phaddsw"; - case ND_INS_PHADDW: return "phaddw"; - case ND_INS_PHMINPOSUW: return "phminposuw"; - case ND_INS_PHSUBD: return "phsubd"; - case ND_INS_PHSUBSW: return "phsubsw"; - case ND_INS_PHSUBW: return "phsubw"; - case ND_INS_PI2FD: return "pi2fd"; - case ND_INS_PI2FW: return "pi2fw"; - case ND_INS_PINSRB: return "pinsrb"; - case ND_INS_PINSRD: return "pinsrd"; - case ND_INS_PINSRQ: return "pinsrq"; - case ND_INS_PINSRW: return "pinsrw"; - case ND_INS_PMADDUBSW: return "pmaddubsw"; - case ND_INS_PMADDWD: return "pmaddwd"; - case ND_INS_PMAXSB: return "pmaxsb"; - case ND_INS_PMAXSD: return "pmaxsd"; - case ND_INS_PMAXSW: return "pmaxsw"; - case ND_INS_PMAXUB: return "pmaxub"; - case ND_INS_PMAXUD: return "pmaxud"; - case ND_INS_PMAXUW: return "pmaxuw"; - case ND_INS_PMINSB: return "pminsb"; - case ND_INS_PMINSD: return "pminsd"; - case ND_INS_PMINSW: return "pminsw"; - case ND_INS_PMINUB: return "pminub"; - case ND_INS_PMINUD: return "pminud"; - case ND_INS_PMINUW: return "pminuw"; - case ND_INS_PMOVMSKB: return "pmovmskb"; - case ND_INS_PMOVSXBD: return "pmovsxbd"; - case ND_INS_PMOVSXBQ: return "pmovsxbq"; - case ND_INS_PMOVSXBW: return "pmovsxbw"; - case ND_INS_PMOVSXDQ: return "pmovsxdq"; - case ND_INS_PMOVSXWD: return "pmovsxwd"; - case ND_INS_PMOVSXWQ: return "pmovsxwq"; - case ND_INS_PMOVZXBD: return "pmovzxbd"; - case ND_INS_PMOVZXBQ: return "pmovzxbq"; - case ND_INS_PMOVZXBW: return "pmovzxbw"; - case ND_INS_PMOVZXDQ: return "pmovzxdq"; - case ND_INS_PMOVZXWD: return "pmovzxwd"; - case ND_INS_PMOVZXWQ: return "pmovzxwq"; - case ND_INS_PMULDQ: return "pmuldq"; - case ND_INS_PMULHRSW: return "pmulhrsw"; - case ND_INS_PMULHRW: return "pmulhrw"; - case ND_INS_PMULHUW: return "pmulhuw"; - case ND_INS_PMULHW: return "pmulhw"; - case ND_INS_PMULLD: return "pmulld"; - case ND_INS_PMULLW: return "pmullw"; - case ND_INS_PMULUDQ: return "pmuludq"; - case ND_INS_POP: return "pop"; - case ND_INS_POPA: return "popa"; - case ND_INS_POPAD: return "popad"; - case ND_INS_POPCNT: return "popcnt"; - case ND_INS_POPF: return "popf"; - case ND_INS_POR: return "por"; - case ND_INS_PREFETCH: return "prefetch"; - case ND_INS_PREFETCHE: return "prefetche"; - case ND_INS_PREFETCHM: return "prefetchm"; - case ND_INS_PREFETCHNTA: return "prefetchnta"; - case ND_INS_PREFETCHT0: return "prefetcht0"; - case ND_INS_PREFETCHT1: return "prefetcht1"; - case ND_INS_PREFETCHT2: return "prefetcht2"; - case ND_INS_PREFETCHW: return "prefetchw"; - case ND_INS_PREFETCHWT1: return "prefetchwt1"; - case ND_INS_PSADBW: return "psadbw"; - case ND_INS_PSHUFB: return "pshufb"; - case ND_INS_PSHUFD: return "pshufd"; - case ND_INS_PSHUFHW: return "pshufhw"; - case ND_INS_PSHUFLW: return "pshuflw"; - case ND_INS_PSHUFW: return "pshufw"; - case ND_INS_PSIGNB: return "psignb"; - case ND_INS_PSIGND: return "psignd"; - case ND_INS_PSIGNW: return "psignw"; - case ND_INS_PSLLD: return "pslld"; - case ND_INS_PSLLDQ: return "pslldq"; - case ND_INS_PSLLQ: return "psllq"; - case ND_INS_PSLLW: return "psllw"; - case ND_INS_PSMASH: return "psmash"; - case ND_INS_PSRAD: return "psrad"; - case ND_INS_PSRAW: return "psraw"; - case ND_INS_PSRLD: return "psrld"; - case ND_INS_PSRLDQ: return "psrldq"; - case ND_INS_PSRLQ: return "psrlq"; - case ND_INS_PSRLW: return "psrlw"; - case ND_INS_PSUBB: return "psubb"; - case ND_INS_PSUBD: return "psubd"; - case ND_INS_PSUBQ: return "psubq"; - case ND_INS_PSUBSB: return "psubsb"; - case ND_INS_PSUBSW: return "psubsw"; - case ND_INS_PSUBUSB: return "psubusb"; - case ND_INS_PSUBUSW: return "psubusw"; - case ND_INS_PSUBW: return "psubw"; - case ND_INS_PSWAPD: return "pswapd"; - case ND_INS_PTEST: return "ptest"; - case ND_INS_PTWRITE: return "ptwrite"; - case ND_INS_PUNPCKHBW: return "punpckhbw"; - case ND_INS_PUNPCKHDQ: return "punpckhdq"; - case ND_INS_PUNPCKHQDQ: return "punpckhqdq"; - case ND_INS_PUNPCKHWD: return "punpckhwd"; - case ND_INS_PUNPCKLBW: return "punpcklbw"; - case ND_INS_PUNPCKLDQ: return "punpckldq"; - case ND_INS_PUNPCKLQDQ: return "punpcklqdq"; - case ND_INS_PUNPCKLWD: return "punpcklwd"; - case ND_INS_PUSH: return "push"; - case ND_INS_PUSHA: return "pusha"; - case ND_INS_PUSHAD: return "pushad"; - case ND_INS_PUSHF: return "pushf"; - case ND_INS_PVALIDATE: return "pvalidate"; - case ND_INS_PXOR: return "pxor"; - case ND_INS_RCL: return "rcl"; - case ND_INS_RCPPS: return "rcpps"; - case ND_INS_RCPSS: return "rcpss"; - case ND_INS_RCR: return "rcr"; - case ND_INS_RDFSBASE: return "rdfsbase"; - case ND_INS_RDGSBASE: return "rdgsbase"; - case ND_INS_RDMSR: return "rdmsr"; - case ND_INS_RDPID: return "rdpid"; - case ND_INS_RDPKRU: return "rdpkru"; - case ND_INS_RDPMC: return "rdpmc"; - case ND_INS_RDPRU: return "rdpru"; - case ND_INS_RDRAND: return "rdrand"; - case ND_INS_RDSEED: return "rdseed"; - case ND_INS_RDSHR: return "rdshr"; - case ND_INS_RDTSC: return "rdtsc"; - case ND_INS_RDTSCP: return "rdtscp"; - case ND_INS_RETF: return "retf"; - case ND_INS_RETN: return "retn"; - case ND_INS_RMPADJUST: return "rmpadjust"; - case ND_INS_RMPUPDATE: return "rmpupdate"; - case ND_INS_ROL: return "rol"; - case ND_INS_ROR: return "ror"; - case ND_INS_RORX: return "rorx"; - case ND_INS_ROUNDPD: return "roundpd"; - case ND_INS_ROUNDPS: return "roundps"; - case ND_INS_ROUNDSD: return "roundsd"; - case ND_INS_ROUNDSS: return "roundss"; - case ND_INS_RSDC: return "rsdc"; - case ND_INS_RSLDT: return "rsldt"; - case ND_INS_RSM: return "rsm"; - case ND_INS_RSQRTPS: return "rsqrtps"; - case ND_INS_RSQRTSS: return "rsqrtss"; - case ND_INS_RSSSP: return "rsssp"; - case ND_INS_RSTORSSP: return "rstorssp"; - case ND_INS_RSTS: return "rsts"; - case ND_INS_SAHF: return "sahf"; - case ND_INS_SAL: return "sal"; - case ND_INS_SALC: return "salc"; - case ND_INS_SAR: return "sar"; - case ND_INS_SARX: return "sarx"; - case ND_INS_SAVEPREVSSP: return "saveprevssp"; - case ND_INS_SBB: return "sbb"; - case ND_INS_SCAS: return "scas"; - case ND_INS_SEAMOPS: return "seamops"; - case ND_INS_SEAMCALL: return "seamcall"; - case ND_INS_SEAMRET: return "seamret"; - case ND_INS_SERIALIZE: return "serialize"; - case ND_INS_SETSSBSY: return "setssbsy"; - case ND_INS_SETcc: return "setcc"; - case ND_INS_SFENCE: return "sfence"; - case ND_INS_SGDT: return "sgdt"; - case ND_INS_SHA1MSG1: return "sha1msg1"; - case ND_INS_SHA1MSG2: return "sha1msg2"; - case ND_INS_SHA1NEXTE: return "sha1nexte"; - case ND_INS_SHA1RNDS4: return "sha1rnds4"; - case ND_INS_SHA256MSG1: return "sha256msg1"; - case ND_INS_SHA256MSG2: return "sha256msg2"; - case ND_INS_SHA256RNDS2: return "sha256rnds2"; - case ND_INS_SHL: return "shl"; - case ND_INS_SHLD: return "shld"; - case ND_INS_SHLX: return "shlx"; - case ND_INS_SHR: return "shr"; - case ND_INS_SHRD: return "shrd"; - case ND_INS_SHRX: return "shrx"; - case ND_INS_SHUFPD: return "shufpd"; - case ND_INS_SHUFPS: return "shufps"; - case ND_INS_SIDT: return "sidt"; - case ND_INS_SKINIT: return "skinit"; - case ND_INS_SLDT: return "sldt"; - case ND_INS_SLWPCB: return "slwpcb"; - case ND_INS_SMINT: return "smint"; - case ND_INS_SMSW: return "smsw"; - case ND_INS_SPFLT: return "spflt"; - case ND_INS_SQRTPD: return "sqrtpd"; - case ND_INS_SQRTPS: return "sqrtps"; - case ND_INS_SQRTSD: return "sqrtsd"; - case ND_INS_SQRTSS: return "sqrtss"; - case ND_INS_STAC: return "stac"; - case ND_INS_STC: return "stc"; - case ND_INS_STD: return "std"; - case ND_INS_STGI: return "stgi"; - case ND_INS_STI: return "sti"; - case ND_INS_STMXCSR: return "stmxcsr"; - case ND_INS_STOS: return "stos"; - case ND_INS_STR: return "str"; - case ND_INS_STTILECFG: return "sttilecfg"; - case ND_INS_SUB: return "sub"; - case ND_INS_SUBPD: return "subpd"; - case ND_INS_SUBPS: return "subps"; - case ND_INS_SUBSD: return "subsd"; - case ND_INS_SUBSS: return "subss"; - case ND_INS_SVDC: return "svdc"; - case ND_INS_SVLDT: return "svldt"; - case ND_INS_SVTS: return "svts"; - case ND_INS_SWAPGS: return "swapgs"; - case ND_INS_SYSCALL: return "syscall"; - case ND_INS_SYSENTER: return "sysenter"; - case ND_INS_SYSEXIT: return "sysexit"; - case ND_INS_SYSRET: return "sysret"; - case ND_INS_T1MSKC: return "t1mskc"; - case ND_INS_TDCALL: return "tdcall"; - case ND_INS_TDPBF16PS: return "tdpbf16ps"; - case ND_INS_TDPBSSD: return "tdpbssd"; - case ND_INS_TDPBSUD: return "tdpbsud"; - case ND_INS_TDPBUSD: return "tdpbusd"; - case ND_INS_TDPBUUD: return "tdpbuud"; - case ND_INS_TEST: return "test"; - case ND_INS_TILELOADD: return "tileloadd"; - case ND_INS_TILELOADDT1: return "tileloaddt1"; - case ND_INS_TILERELEASE: return "tilerelease"; - case ND_INS_TILESTORED: return "tilestored"; - case ND_INS_TILEZERO: return "tilezero"; - case ND_INS_TLBSYNC: return "tlbsync"; - case ND_INS_TPAUSE: return "tpause"; - case ND_INS_TZCNT: return "tzcnt"; - case ND_INS_TZMSK: return "tzmsk"; - case ND_INS_UCOMISD: return "ucomisd"; - case ND_INS_UCOMISS: return "ucomiss"; - case ND_INS_UD0: return "ud0"; - case ND_INS_UD1: return "ud1"; - case ND_INS_UD2: return "ud2"; - case ND_INS_UMONITOR: return "umonitor"; - case ND_INS_UMWAIT: return "umwait"; - case ND_INS_UNPCKHPD: return "unpckhpd"; - case ND_INS_UNPCKHPS: return "unpckhps"; - case ND_INS_UNPCKLPD: return "unpcklpd"; - case ND_INS_UNPCKLPS: return "unpcklps"; - case ND_INS_V4FMADDPS: return "v4fmaddps"; - case ND_INS_V4FMADDSS: return "v4fmaddss"; - case ND_INS_V4FNMADDPS: return "v4fnmaddps"; - case ND_INS_V4FNMADDSS: return "v4fnmaddss"; - case ND_INS_VADDPD: return "vaddpd"; - case ND_INS_VADDPS: return "vaddps"; - case ND_INS_VADDSD: return "vaddsd"; - case ND_INS_VADDSS: return "vaddss"; - case ND_INS_VADDSUBPD: return "vaddsubpd"; - case ND_INS_VADDSUBPS: return "vaddsubps"; - case ND_INS_VAESDEC: return "vaesdec"; - case ND_INS_VAESDECLAST: return "vaesdeclast"; - case ND_INS_VAESENC: return "vaesenc"; - case ND_INS_VAESENCLAST: return "vaesenclast"; - case ND_INS_VAESIMC: return "vaesimc"; - case ND_INS_VAESKEYGENASSIST: return "vaeskeygenassist"; - case ND_INS_VALIGND: return "valignd"; - case ND_INS_VALIGNQ: return "valignq"; - case ND_INS_VANDNPD: return "vandnpd"; - case ND_INS_VANDNPS: return "vandnps"; - case ND_INS_VANDPD: return "vandpd"; - case ND_INS_VANDPS: return "vandps"; - case ND_INS_VBLENDMPD: return "vblendmpd"; - case ND_INS_VBLENDMPS: return "vblendmps"; - case ND_INS_VBLENDPD: return "vblendpd"; - case ND_INS_VBLENDPS: return "vblendps"; - case ND_INS_VBLENDVPD: return "vblendvpd"; - case ND_INS_VBLENDVPS: return "vblendvps"; - case ND_INS_VBROADCASTF128: return "vbroadcastf128"; - case ND_INS_VBROADCASTF32X2: return "vbroadcastf32x2"; - case ND_INS_VBROADCASTF32X4: return "vbroadcastf32x4"; - case ND_INS_VBROADCASTF32X8: return "vbroadcastf32x8"; - case ND_INS_VBROADCASTF64X2: return "vbroadcastf64x2"; - case ND_INS_VBROADCASTF64X4: return "vbroadcastf64x4"; - case ND_INS_VBROADCASTI128: return "vbroadcasti128"; - case ND_INS_VBROADCASTI32X2: return "vbroadcasti32x2"; - case ND_INS_VBROADCASTI32X4: return "vbroadcasti32x4"; - case ND_INS_VBROADCASTI32X8: return "vbroadcasti32x8"; - case ND_INS_VBROADCASTI64X2: return "vbroadcasti64x2"; - case ND_INS_VBROADCASTI64X4: return "vbroadcasti64x4"; - case ND_INS_VBROADCASTSD: return "vbroadcastsd"; - case ND_INS_VBROADCASTSS: return "vbroadcastss"; - case ND_INS_VCMPPD: return "vcmppd"; - case ND_INS_VCMPPS: return "vcmpps"; - case ND_INS_VCMPSD: return "vcmpsd"; - case ND_INS_VCMPSS: return "vcmpss"; - case ND_INS_VCOMISD: return "vcomisd"; - case ND_INS_VCOMISS: return "vcomiss"; - case ND_INS_VCOMPRESSPD: return "vcompresspd"; - case ND_INS_VCOMPRESSPS: return "vcompressps"; - case ND_INS_VCVTDQ2PD: return "vcvtdq2pd"; - case ND_INS_VCVTDQ2PS: return "vcvtdq2ps"; - case ND_INS_VCVTNE2PS2BF16: return "vcvtne2ps2bf16"; - case ND_INS_VCVTNEPS2BF16: return "vcvtneps2bf16"; - case ND_INS_VCVTPD2DQ: return "vcvtpd2dq"; - case ND_INS_VCVTPD2PS: return "vcvtpd2ps"; - case ND_INS_VCVTPD2QQ: return "vcvtpd2qq"; - case ND_INS_VCVTPD2UDQ: return "vcvtpd2udq"; - case ND_INS_VCVTPD2UQQ: return "vcvtpd2uqq"; - case ND_INS_VCVTPH2PS: return "vcvtph2ps"; - case ND_INS_VCVTPS2DQ: return "vcvtps2dq"; - case ND_INS_VCVTPS2PD: return "vcvtps2pd"; - case ND_INS_VCVTPS2PH: return "vcvtps2ph"; - case ND_INS_VCVTPS2QQ: return "vcvtps2qq"; - case ND_INS_VCVTPS2UDQ: return "vcvtps2udq"; - case ND_INS_VCVTPS2UQQ: return "vcvtps2uqq"; - case ND_INS_VCVTQQ2PD: return "vcvtqq2pd"; - case ND_INS_VCVTQQ2PS: return "vcvtqq2ps"; - case ND_INS_VCVTSD2SI: return "vcvtsd2si"; - case ND_INS_VCVTSD2SS: return "vcvtsd2ss"; - case ND_INS_VCVTSD2USI: return "vcvtsd2usi"; - case ND_INS_VCVTSI2SD: return "vcvtsi2sd"; - case ND_INS_VCVTSI2SS: return "vcvtsi2ss"; - case ND_INS_VCVTSS2SD: return "vcvtss2sd"; - case ND_INS_VCVTSS2SI: return "vcvtss2si"; - case ND_INS_VCVTSS2USI: return "vcvtss2usi"; - case ND_INS_VCVTTPD2DQ: return "vcvttpd2dq"; - case ND_INS_VCVTTPD2QQ: return "vcvttpd2qq"; - case ND_INS_VCVTTPD2UDQ: return "vcvttpd2udq"; - case ND_INS_VCVTTPD2UQQ: return "vcvttpd2uqq"; - case ND_INS_VCVTTPS2DQ: return "vcvttps2dq"; - case ND_INS_VCVTTPS2QQ: return "vcvttps2qq"; - case ND_INS_VCVTTPS2UDQ: return "vcvttps2udq"; - case ND_INS_VCVTTPS2UQQ: return "vcvttps2uqq"; - case ND_INS_VCVTTSD2SI: return "vcvttsd2si"; - case ND_INS_VCVTTSD2USI: return "vcvttsd2usi"; - case ND_INS_VCVTTSS2SI: return "vcvttss2si"; - case ND_INS_VCVTTSS2USI: return "vcvttss2usi"; - case ND_INS_VCVTUDQ2PD: return "vcvtudq2pd"; - case ND_INS_VCVTUDQ2PS: return "vcvtudq2ps"; - case ND_INS_VCVTUQQ2PD: return "vcvtuqq2pd"; - case ND_INS_VCVTUQQ2PS: return "vcvtuqq2ps"; - case ND_INS_VCVTUSI2SD: return "vcvtusi2sd"; - case ND_INS_VCVTUSI2SS: return "vcvtusi2ss"; - case ND_INS_VDBPSADBW: return "vdbpsadbw"; - case ND_INS_VDIVPD: return "vdivpd"; - case ND_INS_VDIVPS: return "vdivps"; - case ND_INS_VDIVSD: return "vdivsd"; - case ND_INS_VDIVSS: return "vdivss"; - case ND_INS_VDPBF16PS: return "vdpbf16ps"; - case ND_INS_VDPPD: return "vdppd"; - case ND_INS_VDPPS: return "vdpps"; - case ND_INS_VERR: return "verr"; - case ND_INS_VERW: return "verw"; - case ND_INS_VEXP2PD: return "vexp2pd"; - case ND_INS_VEXP2PS: return "vexp2ps"; - case ND_INS_VEXPANDPD: return "vexpandpd"; - case ND_INS_VEXPANDPS: return "vexpandps"; - case ND_INS_VEXTRACTF128: return "vextractf128"; - case ND_INS_VEXTRACTF32X4: return "vextractf32x4"; - case ND_INS_VEXTRACTF32X8: return "vextractf32x8"; - case ND_INS_VEXTRACTF64X2: return "vextractf64x2"; - case ND_INS_VEXTRACTF64X4: return "vextractf64x4"; - case ND_INS_VEXTRACTI128: return "vextracti128"; - case ND_INS_VEXTRACTI32X4: return "vextracti32x4"; - case ND_INS_VEXTRACTI32X8: return "vextracti32x8"; - case ND_INS_VEXTRACTI64X2: return "vextracti64x2"; - case ND_INS_VEXTRACTI64X4: return "vextracti64x4"; - case ND_INS_VEXTRACTPS: return "vextractps"; - case ND_INS_VFIXUPIMMPD: return "vfixupimmpd"; - case ND_INS_VFIXUPIMMPS: return "vfixupimmps"; - case ND_INS_VFIXUPIMMSD: return "vfixupimmsd"; - case ND_INS_VFIXUPIMMSS: return "vfixupimmss"; - case ND_INS_VFMADD132PD: return "vfmadd132pd"; - case ND_INS_VFMADD132PS: return "vfmadd132ps"; - case ND_INS_VFMADD132SD: return "vfmadd132sd"; - case ND_INS_VFMADD132SS: return "vfmadd132ss"; - case ND_INS_VFMADD213PD: return "vfmadd213pd"; - case ND_INS_VFMADD213PS: return "vfmadd213ps"; - case ND_INS_VFMADD213SD: return "vfmadd213sd"; - case ND_INS_VFMADD213SS: return "vfmadd213ss"; - case ND_INS_VFMADD231PD: return "vfmadd231pd"; - case ND_INS_VFMADD231PS: return "vfmadd231ps"; - case ND_INS_VFMADD231SD: return "vfmadd231sd"; - case ND_INS_VFMADD231SS: return "vfmadd231ss"; - case ND_INS_VFMADDPD: return "vfmaddpd"; - case ND_INS_VFMADDPS: return "vfmaddps"; - case ND_INS_VFMADDSD: return "vfmaddsd"; - case ND_INS_VFMADDSS: return "vfmaddss"; - case ND_INS_VFMADDSUB132PD: return "vfmaddsub132pd"; - case ND_INS_VFMADDSUB132PS: return "vfmaddsub132ps"; - case ND_INS_VFMADDSUB213PD: return "vfmaddsub213pd"; - case ND_INS_VFMADDSUB213PS: return "vfmaddsub213ps"; - case ND_INS_VFMADDSUB231PD: return "vfmaddsub231pd"; - case ND_INS_VFMADDSUB231PS: return "vfmaddsub231ps"; - case ND_INS_VFMADDSUBPD: return "vfmaddsubpd"; - case ND_INS_VFMADDSUBPS: return "vfmaddsubps"; - case ND_INS_VFMSUB132PD: return "vfmsub132pd"; - case ND_INS_VFMSUB132PS: return "vfmsub132ps"; - case ND_INS_VFMSUB132SD: return "vfmsub132sd"; - case ND_INS_VFMSUB132SS: return "vfmsub132ss"; - case ND_INS_VFMSUB213PD: return "vfmsub213pd"; - case ND_INS_VFMSUB213PS: return "vfmsub213ps"; - case ND_INS_VFMSUB213SD: return "vfmsub213sd"; - case ND_INS_VFMSUB213SS: return "vfmsub213ss"; - case ND_INS_VFMSUB231PD: return "vfmsub231pd"; - case ND_INS_VFMSUB231PS: return "vfmsub231ps"; - case ND_INS_VFMSUB231SD: return "vfmsub231sd"; - case ND_INS_VFMSUB231SS: return "vfmsub231ss"; - case ND_INS_VFMSUBADD132PD: return "vfmsubadd132pd"; - case ND_INS_VFMSUBADD132PS: return "vfmsubadd132ps"; - case ND_INS_VFMSUBADD213PD: return "vfmsubadd213pd"; - case ND_INS_VFMSUBADD213PS: return "vfmsubadd213ps"; - case ND_INS_VFMSUBADD231PD: return "vfmsubadd231pd"; - case ND_INS_VFMSUBADD231PS: return "vfmsubadd231ps"; - case ND_INS_VFMSUBADDPD: return "vfmsubaddpd"; - case ND_INS_VFMSUBADDPS: return "vfmsubaddps"; - case ND_INS_VFMSUBPD: return "vfmsubpd"; - case ND_INS_VFMSUBPS: return "vfmsubps"; - case ND_INS_VFMSUBSD: return "vfmsubsd"; - case ND_INS_VFMSUBSS: return "vfmsubss"; - case ND_INS_VFNMADD132PD: return "vfnmadd132pd"; - case ND_INS_VFNMADD132PS: return "vfnmadd132ps"; - case ND_INS_VFNMADD132SD: return "vfnmadd132sd"; - case ND_INS_VFNMADD132SS: return "vfnmadd132ss"; - case ND_INS_VFNMADD213PD: return "vfnmadd213pd"; - case ND_INS_VFNMADD213PS: return "vfnmadd213ps"; - case ND_INS_VFNMADD213SD: return "vfnmadd213sd"; - case ND_INS_VFNMADD213SS: return "vfnmadd213ss"; - case ND_INS_VFNMADD231PD: return "vfnmadd231pd"; - case ND_INS_VFNMADD231PS: return "vfnmadd231ps"; - case ND_INS_VFNMADD231SD: return "vfnmadd231sd"; - case ND_INS_VFNMADD231SS: return "vfnmadd231ss"; - case ND_INS_VFNMADDPD: return "vfnmaddpd"; - case ND_INS_VFNMADDPS: return "vfnmaddps"; - case ND_INS_VFNMADDSD: return "vfnmaddsd"; - case ND_INS_VFNMADDSS: return "vfnmaddss"; - case ND_INS_VFNMSUB132PD: return "vfnmsub132pd"; - case ND_INS_VFNMSUB132PS: return "vfnmsub132ps"; - case ND_INS_VFNMSUB132SD: return "vfnmsub132sd"; - case ND_INS_VFNMSUB132SS: return "vfnmsub132ss"; - case ND_INS_VFNMSUB213PD: return "vfnmsub213pd"; - case ND_INS_VFNMSUB213PS: return "vfnmsub213ps"; - case ND_INS_VFNMSUB213SD: return "vfnmsub213sd"; - case ND_INS_VFNMSUB213SS: return "vfnmsub213ss"; - case ND_INS_VFNMSUB231PD: return "vfnmsub231pd"; - case ND_INS_VFNMSUB231PS: return "vfnmsub231ps"; - case ND_INS_VFNMSUB231SD: return "vfnmsub231sd"; - case ND_INS_VFNMSUB231SS: return "vfnmsub231ss"; - case ND_INS_VFNMSUBPD: return "vfnmsubpd"; - case ND_INS_VFNMSUBPS: return "vfnmsubps"; - case ND_INS_VFNMSUBSD: return "vfnmsubsd"; - case ND_INS_VFNMSUBSS: return "vfnmsubss"; - case ND_INS_VFPCLASSPD: return "vfpclasspd"; - case ND_INS_VFPCLASSPS: return "vfpclassps"; - case ND_INS_VFPCLASSSD: return "vfpclasssd"; - case ND_INS_VFPCLASSSS: return "vfpclassss"; - case ND_INS_VFRCZPD: return "vfrczpd"; - case ND_INS_VFRCZPS: return "vfrczps"; - case ND_INS_VFRCZSD: return "vfrczsd"; - case ND_INS_VFRCZSS: return "vfrczss"; - case ND_INS_VGATHERDPD: return "vgatherdpd"; - case ND_INS_VGATHERDPS: return "vgatherdps"; - case ND_INS_VGATHERPF0DPD: return "vgatherpf0dpd"; - case ND_INS_VGATHERPF0DPS: return "vgatherpf0dps"; - case ND_INS_VGATHERPF0QPD: return "vgatherpf0qpd"; - case ND_INS_VGATHERPF0QPS: return "vgatherpf0qps"; - case ND_INS_VGATHERPF1DPD: return "vgatherpf1dpd"; - case ND_INS_VGATHERPF1DPS: return "vgatherpf1dps"; - case ND_INS_VGATHERPF1QPD: return "vgatherpf1qpd"; - case ND_INS_VGATHERPF1QPS: return "vgatherpf1qps"; - case ND_INS_VGATHERQPD: return "vgatherqpd"; - case ND_INS_VGATHERQPS: return "vgatherqps"; - case ND_INS_VGETEXPPD: return "vgetexppd"; - case ND_INS_VGETEXPPS: return "vgetexpps"; - case ND_INS_VGETEXPSD: return "vgetexpsd"; - case ND_INS_VGETEXPSS: return "vgetexpss"; - case ND_INS_VGETMANTPD: return "vgetmantpd"; - case ND_INS_VGETMANTPS: return "vgetmantps"; - case ND_INS_VGETMANTSD: return "vgetmantsd"; - case ND_INS_VGETMANTSS: return "vgetmantss"; - case ND_INS_VGF2P8AFFINEINVQB: return "vgf2p8affineinvqb"; - case ND_INS_VGF2P8AFFINEQB: return "vgf2p8affineqb"; - case ND_INS_VGF2P8MULB: return "vgf2p8mulb"; - case ND_INS_VHADDPD: return "vhaddpd"; - case ND_INS_VHADDPS: return "vhaddps"; - case ND_INS_VHSUBPD: return "vhsubpd"; - case ND_INS_VHSUBPS: return "vhsubps"; - case ND_INS_VINSERTF128: return "vinsertf128"; - case ND_INS_VINSERTF32X4: return "vinsertf32x4"; - case ND_INS_VINSERTF32X8: return "vinsertf32x8"; - case ND_INS_VINSERTF64X2: return "vinsertf64x2"; - case ND_INS_VINSERTF64X4: return "vinsertf64x4"; - case ND_INS_VINSERTI128: return "vinserti128"; - case ND_INS_VINSERTI32X4: return "vinserti32x4"; - case ND_INS_VINSERTI32X8: return "vinserti32x8"; - case ND_INS_VINSERTI64X2: return "vinserti64x2"; - case ND_INS_VINSERTI64X4: return "vinserti64x4"; - case ND_INS_VINSERTPS: return "vinsertps"; - case ND_INS_VLDDQU: return "vlddqu"; - case ND_INS_VLDMXCSR: return "vldmxcsr"; - case ND_INS_VMASKMOVDQU: return "vmaskmovdqu"; - case ND_INS_VMASKMOVPD: return "vmaskmovpd"; - case ND_INS_VMASKMOVPS: return "vmaskmovps"; - case ND_INS_VMAXPD: return "vmaxpd"; - case ND_INS_VMAXPS: return "vmaxps"; - case ND_INS_VMAXSD: return "vmaxsd"; - case ND_INS_VMAXSS: return "vmaxss"; - case ND_INS_VMCALL: return "vmcall"; - case ND_INS_VMCLEAR: return "vmclear"; - case ND_INS_VMFUNC: return "vmfunc"; - case ND_INS_VMGEXIT: return "vmgexit"; - case ND_INS_VMINPD: return "vminpd"; - case ND_INS_VMINPS: return "vminps"; - case ND_INS_VMINSD: return "vminsd"; - case ND_INS_VMINSS: return "vminss"; - case ND_INS_VMLAUNCH: return "vmlaunch"; - case ND_INS_VMLOAD: return "vmload"; - case ND_INS_VMMCALL: return "vmmcall"; - case ND_INS_VMOVAPD: return "vmovapd"; - case ND_INS_VMOVAPS: return "vmovaps"; - case ND_INS_VMOVD: return "vmovd"; - case ND_INS_VMOVDDUP: return "vmovddup"; - case ND_INS_VMOVDQA: return "vmovdqa"; - case ND_INS_VMOVDQA32: return "vmovdqa32"; - case ND_INS_VMOVDQA64: return "vmovdqa64"; - case ND_INS_VMOVDQU: return "vmovdqu"; - case ND_INS_VMOVDQU16: return "vmovdqu16"; - case ND_INS_VMOVDQU32: return "vmovdqu32"; - case ND_INS_VMOVDQU64: return "vmovdqu64"; - case ND_INS_VMOVDQU8: return "vmovdqu8"; - case ND_INS_VMOVHLPS: return "vmovhlps"; - case ND_INS_VMOVHPD: return "vmovhpd"; - case ND_INS_VMOVHPS: return "vmovhps"; - case ND_INS_VMOVLHPS: return "vmovlhps"; - case ND_INS_VMOVLPD: return "vmovlpd"; - case ND_INS_VMOVLPS: return "vmovlps"; - case ND_INS_VMOVMSKPD: return "vmovmskpd"; - case ND_INS_VMOVMSKPS: return "vmovmskps"; - case ND_INS_VMOVNTDQ: return "vmovntdq"; - case ND_INS_VMOVNTDQA: return "vmovntdqa"; - case ND_INS_VMOVNTPD: return "vmovntpd"; - case ND_INS_VMOVNTPS: return "vmovntps"; - case ND_INS_VMOVQ: return "vmovq"; - case ND_INS_VMOVSD: return "vmovsd"; - case ND_INS_VMOVSHDUP: return "vmovshdup"; - case ND_INS_VMOVSLDUP: return "vmovsldup"; - case ND_INS_VMOVSS: return "vmovss"; - case ND_INS_VMOVUPD: return "vmovupd"; - case ND_INS_VMOVUPS: return "vmovups"; - case ND_INS_VMPSADBW: return "vmpsadbw"; - case ND_INS_VMPTRLD: return "vmptrld"; - case ND_INS_VMPTRST: return "vmptrst"; - case ND_INS_VMREAD: return "vmread"; - case ND_INS_VMRESUME: return "vmresume"; - case ND_INS_VMRUN: return "vmrun"; - case ND_INS_VMSAVE: return "vmsave"; - case ND_INS_VMULPD: return "vmulpd"; - case ND_INS_VMULPS: return "vmulps"; - case ND_INS_VMULSD: return "vmulsd"; - case ND_INS_VMULSS: return "vmulss"; - case ND_INS_VMWRITE: return "vmwrite"; - case ND_INS_VMXOFF: return "vmxoff"; - case ND_INS_VMXON: return "vmxon"; - case ND_INS_VORPD: return "vorpd"; - case ND_INS_VORPS: return "vorps"; - case ND_INS_VP2INTERSECTD: return "vp2intersectd"; - case ND_INS_VP2INTERSECTQ: return "vp2intersectq"; - case ND_INS_VP4DPWSSD: return "vp4dpwssd"; - case ND_INS_VP4DPWSSDS: return "vp4dpwssds"; - case ND_INS_VPABSB: return "vpabsb"; - case ND_INS_VPABSD: return "vpabsd"; - case ND_INS_VPABSQ: return "vpabsq"; - case ND_INS_VPABSW: return "vpabsw"; - case ND_INS_VPACKSSDW: return "vpackssdw"; - case ND_INS_VPACKSSWB: return "vpacksswb"; - case ND_INS_VPACKUSDW: return "vpackusdw"; - case ND_INS_VPACKUSWB: return "vpackuswb"; - case ND_INS_VPADDB: return "vpaddb"; - case ND_INS_VPADDD: return "vpaddd"; - case ND_INS_VPADDQ: return "vpaddq"; - case ND_INS_VPADDSB: return "vpaddsb"; - case ND_INS_VPADDSW: return "vpaddsw"; - case ND_INS_VPADDUSB: return "vpaddusb"; - case ND_INS_VPADDUSW: return "vpaddusw"; - case ND_INS_VPADDW: return "vpaddw"; - case ND_INS_VPALIGNR: return "vpalignr"; - case ND_INS_VPAND: return "vpand"; - case ND_INS_VPANDD: return "vpandd"; - case ND_INS_VPANDN: return "vpandn"; - case ND_INS_VPANDND: return "vpandnd"; - case ND_INS_VPANDNQ: return "vpandnq"; - case ND_INS_VPANDQ: return "vpandq"; - case ND_INS_VPAVGB: return "vpavgb"; - case ND_INS_VPAVGW: return "vpavgw"; - case ND_INS_VPBLENDD: return "vpblendd"; - case ND_INS_VPBLENDMB: return "vpblendmb"; - case ND_INS_VPBLENDMD: return "vpblendmd"; - case ND_INS_VPBLENDMQ: return "vpblendmq"; - case ND_INS_VPBLENDMW: return "vpblendmw"; - case ND_INS_VPBLENDVB: return "vpblendvb"; - case ND_INS_VPBLENDW: return "vpblendw"; - case ND_INS_VPBROADCASTB: return "vpbroadcastb"; - case ND_INS_VPBROADCASTD: return "vpbroadcastd"; - case ND_INS_VPBROADCASTMB2Q: return "vpbroadcastmb2q"; - case ND_INS_VPBROADCASTMW2D: return "vpbroadcastmw2d"; - case ND_INS_VPBROADCASTQ: return "vpbroadcastq"; - case ND_INS_VPBROADCASTW: return "vpbroadcastw"; - case ND_INS_VPCLMULQDQ: return "vpclmulqdq"; - case ND_INS_VPCMOV: return "vpcmov"; - case ND_INS_VPCMPB: return "vpcmpb"; - case ND_INS_VPCMPD: return "vpcmpd"; - case ND_INS_VPCMPEQB: return "vpcmpeqb"; - case ND_INS_VPCMPEQD: return "vpcmpeqd"; - case ND_INS_VPCMPEQQ: return "vpcmpeqq"; - case ND_INS_VPCMPEQW: return "vpcmpeqw"; - case ND_INS_VPCMPESTRI: return "vpcmpestri"; - case ND_INS_VPCMPESTRM: return "vpcmpestrm"; - case ND_INS_VPCMPGTB: return "vpcmpgtb"; - case ND_INS_VPCMPGTD: return "vpcmpgtd"; - case ND_INS_VPCMPGTQ: return "vpcmpgtq"; - case ND_INS_VPCMPGTW: return "vpcmpgtw"; - case ND_INS_VPCMPISTRI: return "vpcmpistri"; - case ND_INS_VPCMPISTRM: return "vpcmpistrm"; - case ND_INS_VPCMPQ: return "vpcmpq"; - case ND_INS_VPCMPUB: return "vpcmpub"; - case ND_INS_VPCMPUD: return "vpcmpud"; - case ND_INS_VPCMPUQ: return "vpcmpuq"; - case ND_INS_VPCMPUW: return "vpcmpuw"; - case ND_INS_VPCMPW: return "vpcmpw"; - case ND_INS_VPCOMB: return "vpcomb"; - case ND_INS_VPCOMD: return "vpcomd"; - case ND_INS_VPCOMPRESSB: return "vpcompressb"; - case ND_INS_VPCOMPRESSD: return "vpcompressd"; - case ND_INS_VPCOMPRESSQ: return "vpcompressq"; - case ND_INS_VPCOMPRESSW: return "vpcompressw"; - case ND_INS_VPCOMQ: return "vpcomq"; - case ND_INS_VPCOMUB: return "vpcomub"; - case ND_INS_VPCOMUD: return "vpcomud"; - case ND_INS_VPCOMUQ: return "vpcomuq"; - case ND_INS_VPCOMUW: return "vpcomuw"; - case ND_INS_VPCOMW: return "vpcomw"; - case ND_INS_VPCONFLICTD: return "vpconflictd"; - case ND_INS_VPCONFLICTQ: return "vpconflictq"; - case ND_INS_VPDPBUSD: return "vpdpbusd"; - case ND_INS_VPDPBUSDS: return "vpdpbusds"; - case ND_INS_VPDPWSSD: return "vpdpwssd"; - case ND_INS_VPDPWSSDS: return "vpdpwssds"; - case ND_INS_VPERM2F128: return "vperm2f128"; - case ND_INS_VPERM2I128: return "vperm2i128"; - case ND_INS_VPERMB: return "vpermb"; - case ND_INS_VPERMD: return "vpermd"; - case ND_INS_VPERMI2B: return "vpermi2b"; - case ND_INS_VPERMI2D: return "vpermi2d"; - case ND_INS_VPERMI2PD: return "vpermi2pd"; - case ND_INS_VPERMI2PS: return "vpermi2ps"; - case ND_INS_VPERMI2Q: return "vpermi2q"; - case ND_INS_VPERMI2W: return "vpermi2w"; - case ND_INS_VPERMIL2PD: return "vpermil2pd"; - case ND_INS_VPERMIL2PS: return "vpermil2ps"; - case ND_INS_VPERMILPD: return "vpermilpd"; - case ND_INS_VPERMILPS: return "vpermilps"; - case ND_INS_VPERMPD: return "vpermpd"; - case ND_INS_VPERMPS: return "vpermps"; - case ND_INS_VPERMQ: return "vpermq"; - case ND_INS_VPERMT2B: return "vpermt2b"; - case ND_INS_VPERMT2D: return "vpermt2d"; - case ND_INS_VPERMT2PD: return "vpermt2pd"; - case ND_INS_VPERMT2PS: return "vpermt2ps"; - case ND_INS_VPERMT2Q: return "vpermt2q"; - case ND_INS_VPERMT2W: return "vpermt2w"; - case ND_INS_VPERMW: return "vpermw"; - case ND_INS_VPEXPANDB: return "vpexpandb"; - case ND_INS_VPEXPANDD: return "vpexpandd"; - case ND_INS_VPEXPANDQ: return "vpexpandq"; - case ND_INS_VPEXPANDW: return "vpexpandw"; - case ND_INS_VPEXTRB: return "vpextrb"; - case ND_INS_VPEXTRD: return "vpextrd"; - case ND_INS_VPEXTRQ: return "vpextrq"; - case ND_INS_VPEXTRW: return "vpextrw"; - case ND_INS_VPGATHERDD: return "vpgatherdd"; - case ND_INS_VPGATHERDQ: return "vpgatherdq"; - case ND_INS_VPGATHERQD: return "vpgatherqd"; - case ND_INS_VPGATHERQQ: return "vpgatherqq"; - case ND_INS_VPHADDBD: return "vphaddbd"; - case ND_INS_VPHADDBQ: return "vphaddbq"; - case ND_INS_VPHADDBW: return "vphaddbw"; - case ND_INS_VPHADDD: return "vphaddd"; - case ND_INS_VPHADDDQ: return "vphadddq"; - case ND_INS_VPHADDSW: return "vphaddsw"; - case ND_INS_VPHADDUBD: return "vphaddubd"; - case ND_INS_VPHADDUBQ: return "vphaddubq"; - case ND_INS_VPHADDUBW: return "vphaddubw"; - case ND_INS_VPHADDUDQ: return "vphaddudq"; - case ND_INS_VPHADDUWD: return "vphadduwd"; - case ND_INS_VPHADDUWQ: return "vphadduwq"; - case ND_INS_VPHADDW: return "vphaddw"; - case ND_INS_VPHADDWD: return "vphaddwd"; - case ND_INS_VPHADDWQ: return "vphaddwq"; - case ND_INS_VPHMINPOSUW: return "vphminposuw"; - case ND_INS_VPHSUBBW: return "vphsubbw"; - case ND_INS_VPHSUBD: return "vphsubd"; - case ND_INS_VPHSUBDQ: return "vphsubdq"; - case ND_INS_VPHSUBSW: return "vphsubsw"; - case ND_INS_VPHSUBW: return "vphsubw"; - case ND_INS_VPHSUBWD: return "vphsubwd"; - case ND_INS_VPINSRB: return "vpinsrb"; - case ND_INS_VPINSRD: return "vpinsrd"; - case ND_INS_VPINSRQ: return "vpinsrq"; - case ND_INS_VPINSRW: return "vpinsrw"; - case ND_INS_VPLZCNTD: return "vplzcntd"; - case ND_INS_VPLZCNTQ: return "vplzcntq"; - case ND_INS_VPMACSDD: return "vpmacsdd"; - case ND_INS_VPMACSDQH: return "vpmacsdqh"; - case ND_INS_VPMACSDQL: return "vpmacsdql"; - case ND_INS_VPMACSSDD: return "vpmacssdd"; - case ND_INS_VPMACSSDQH: return "vpmacssdqh"; - case ND_INS_VPMACSSDQL: return "vpmacssdql"; - case ND_INS_VPMACSSWD: return "vpmacsswd"; - case ND_INS_VPMACSSWW: return "vpmacssww"; - case ND_INS_VPMACSWD: return "vpmacswd"; - case ND_INS_VPMACSWW: return "vpmacsww"; - case ND_INS_VPMADCSSWD: return "vpmadcsswd"; - case ND_INS_VPMADCSWD: return "vpmadcswd"; - case ND_INS_VPMADD52HUQ: return "vpmadd52huq"; - case ND_INS_VPMADD52LUQ: return "vpmadd52luq"; - case ND_INS_VPMADDUBSW: return "vpmaddubsw"; - case ND_INS_VPMADDWD: return "vpmaddwd"; - case ND_INS_VPMASKMOVD: return "vpmaskmovd"; - case ND_INS_VPMASKMOVQ: return "vpmaskmovq"; - case ND_INS_VPMAXSB: return "vpmaxsb"; - case ND_INS_VPMAXSD: return "vpmaxsd"; - case ND_INS_VPMAXSQ: return "vpmaxsq"; - case ND_INS_VPMAXSW: return "vpmaxsw"; - case ND_INS_VPMAXUB: return "vpmaxub"; - case ND_INS_VPMAXUD: return "vpmaxud"; - case ND_INS_VPMAXUQ: return "vpmaxuq"; - case ND_INS_VPMAXUW: return "vpmaxuw"; - case ND_INS_VPMINSB: return "vpminsb"; - case ND_INS_VPMINSD: return "vpminsd"; - case ND_INS_VPMINSQ: return "vpminsq"; - case ND_INS_VPMINSW: return "vpminsw"; - case ND_INS_VPMINUB: return "vpminub"; - case ND_INS_VPMINUD: return "vpminud"; - case ND_INS_VPMINUQ: return "vpminuq"; - case ND_INS_VPMINUW: return "vpminuw"; - case ND_INS_VPMOVB2M: return "vpmovb2m"; - case ND_INS_VPMOVD2M: return "vpmovd2m"; - case ND_INS_VPMOVDB: return "vpmovdb"; - case ND_INS_VPMOVDW: return "vpmovdw"; - case ND_INS_VPMOVM2B: return "vpmovm2b"; - case ND_INS_VPMOVM2D: return "vpmovm2d"; - case ND_INS_VPMOVM2Q: return "vpmovm2q"; - case ND_INS_VPMOVM2W: return "vpmovm2w"; - case ND_INS_VPMOVMSKB: return "vpmovmskb"; - case ND_INS_VPMOVQ2M: return "vpmovq2m"; - case ND_INS_VPMOVQB: return "vpmovqb"; - case ND_INS_VPMOVQD: return "vpmovqd"; - case ND_INS_VPMOVQW: return "vpmovqw"; - case ND_INS_VPMOVSDB: return "vpmovsdb"; - case ND_INS_VPMOVSDW: return "vpmovsdw"; - case ND_INS_VPMOVSQB: return "vpmovsqb"; - case ND_INS_VPMOVSQD: return "vpmovsqd"; - case ND_INS_VPMOVSQW: return "vpmovsqw"; - case ND_INS_VPMOVSWB: return "vpmovswb"; - case ND_INS_VPMOVSXBD: return "vpmovsxbd"; - case ND_INS_VPMOVSXBQ: return "vpmovsxbq"; - case ND_INS_VPMOVSXBW: return "vpmovsxbw"; - case ND_INS_VPMOVSXDQ: return "vpmovsxdq"; - case ND_INS_VPMOVSXWD: return "vpmovsxwd"; - case ND_INS_VPMOVSXWQ: return "vpmovsxwq"; - case ND_INS_VPMOVUSDB: return "vpmovusdb"; - case ND_INS_VPMOVUSDW: return "vpmovusdw"; - case ND_INS_VPMOVUSQB: return "vpmovusqb"; - case ND_INS_VPMOVUSQD: return "vpmovusqd"; - case ND_INS_VPMOVUSQW: return "vpmovusqw"; - case ND_INS_VPMOVUSWB: return "vpmovuswb"; - case ND_INS_VPMOVW2M: return "vpmovw2m"; - case ND_INS_VPMOVWB: return "vpmovwb"; - case ND_INS_VPMOVZXBD: return "vpmovzxbd"; - case ND_INS_VPMOVZXBQ: return "vpmovzxbq"; - case ND_INS_VPMOVZXBW: return "vpmovzxbw"; - case ND_INS_VPMOVZXDQ: return "vpmovzxdq"; - case ND_INS_VPMOVZXWD: return "vpmovzxwd"; - case ND_INS_VPMOVZXWQ: return "vpmovzxwq"; - case ND_INS_VPMULDQ: return "vpmuldq"; - case ND_INS_VPMULHRSW: return "vpmulhrsw"; - case ND_INS_VPMULHUW: return "vpmulhuw"; - case ND_INS_VPMULHW: return "vpmulhw"; - case ND_INS_VPMULLD: return "vpmulld"; - case ND_INS_VPMULLQ: return "vpmullq"; - case ND_INS_VPMULLW: return "vpmullw"; - case ND_INS_VPMULTISHIFTQB: return "vpmultishiftqb"; - case ND_INS_VPMULUDQ: return "vpmuludq"; - case ND_INS_VPOPCNTB: return "vpopcntb"; - case ND_INS_VPOPCNTD: return "vpopcntd"; - case ND_INS_VPOPCNTQ: return "vpopcntq"; - case ND_INS_VPOPCNTW: return "vpopcntw"; - case ND_INS_VPOR: return "vpor"; - case ND_INS_VPORD: return "vpord"; - case ND_INS_VPORQ: return "vporq"; - case ND_INS_VPPERM: return "vpperm"; - case ND_INS_VPROLD: return "vprold"; - case ND_INS_VPROLQ: return "vprolq"; - case ND_INS_VPROLVD: return "vprolvd"; - case ND_INS_VPROLVQ: return "vprolvq"; - case ND_INS_VPRORD: return "vprord"; - case ND_INS_VPRORQ: return "vprorq"; - case ND_INS_VPRORVD: return "vprorvd"; - case ND_INS_VPRORVQ: return "vprorvq"; - case ND_INS_VPROTB: return "vprotb"; - case ND_INS_VPROTD: return "vprotd"; - case ND_INS_VPROTQ: return "vprotq"; - case ND_INS_VPROTW: return "vprotw"; - case ND_INS_VPSADBW: return "vpsadbw"; - case ND_INS_VPSCATTERDD: return "vpscatterdd"; - case ND_INS_VPSCATTERDQ: return "vpscatterdq"; - case ND_INS_VPSCATTERQD: return "vpscatterqd"; - case ND_INS_VPSCATTERQQ: return "vpscatterqq"; - case ND_INS_VPSHAB: return "vpshab"; - case ND_INS_VPSHAD: return "vpshad"; - case ND_INS_VPSHAQ: return "vpshaq"; - case ND_INS_VPSHAW: return "vpshaw"; - case ND_INS_VPSHLB: return "vpshlb"; - case ND_INS_VPSHLD: return "vpshld"; - case ND_INS_VPSHLDD: return "vpshldd"; - case ND_INS_VPSHLDQ: return "vpshldq"; - case ND_INS_VPSHLDVD: return "vpshldvd"; - case ND_INS_VPSHLDVQ: return "vpshldvq"; - case ND_INS_VPSHLDVW: return "vpshldvw"; - case ND_INS_VPSHLDW: return "vpshldw"; - case ND_INS_VPSHLQ: return "vpshlq"; - case ND_INS_VPSHLW: return "vpshlw"; - case ND_INS_VPSHRDD: return "vpshrdd"; - case ND_INS_VPSHRDQ: return "vpshrdq"; - case ND_INS_VPSHRDVD: return "vpshrdvd"; - case ND_INS_VPSHRDVQ: return "vpshrdvq"; - case ND_INS_VPSHRDVW: return "vpshrdvw"; - case ND_INS_VPSHRDW: return "vpshrdw"; - case ND_INS_VPSHUFB: return "vpshufb"; - case ND_INS_VPSHUFBITQMB: return "vpshufbitqmb"; - case ND_INS_VPSHUFD: return "vpshufd"; - case ND_INS_VPSHUFHW: return "vpshufhw"; - case ND_INS_VPSHUFLW: return "vpshuflw"; - case ND_INS_VPSIGNB: return "vpsignb"; - case ND_INS_VPSIGND: return "vpsignd"; - case ND_INS_VPSIGNW: return "vpsignw"; - case ND_INS_VPSLLD: return "vpslld"; - case ND_INS_VPSLLDQ: return "vpslldq"; - case ND_INS_VPSLLQ: return "vpsllq"; - case ND_INS_VPSLLVD: return "vpsllvd"; - case ND_INS_VPSLLVQ: return "vpsllvq"; - case ND_INS_VPSLLVW: return "vpsllvw"; - case ND_INS_VPSLLW: return "vpsllw"; - case ND_INS_VPSRAD: return "vpsrad"; - case ND_INS_VPSRAQ: return "vpsraq"; - case ND_INS_VPSRAVD: return "vpsravd"; - case ND_INS_VPSRAVQ: return "vpsravq"; - case ND_INS_VPSRAVW: return "vpsravw"; - case ND_INS_VPSRAW: return "vpsraw"; - case ND_INS_VPSRLD: return "vpsrld"; - case ND_INS_VPSRLDQ: return "vpsrldq"; - case ND_INS_VPSRLQ: return "vpsrlq"; - case ND_INS_VPSRLVD: return "vpsrlvd"; - case ND_INS_VPSRLVQ: return "vpsrlvq"; - case ND_INS_VPSRLVW: return "vpsrlvw"; - case ND_INS_VPSRLW: return "vpsrlw"; - case ND_INS_VPSUBB: return "vpsubb"; - case ND_INS_VPSUBD: return "vpsubd"; - case ND_INS_VPSUBQ: return "vpsubq"; - case ND_INS_VPSUBSB: return "vpsubsb"; - case ND_INS_VPSUBSW: return "vpsubsw"; - case ND_INS_VPSUBUSB: return "vpsubusb"; - case ND_INS_VPSUBUSW: return "vpsubusw"; - case ND_INS_VPSUBW: return "vpsubw"; - case ND_INS_VPTERNLOGD: return "vpternlogd"; - case ND_INS_VPTERNLOGQ: return "vpternlogq"; - case ND_INS_VPTEST: return "vptest"; - case ND_INS_VPTESTMB: return "vptestmb"; - case ND_INS_VPTESTMD: return "vptestmd"; - case ND_INS_VPTESTMQ: return "vptestmq"; - case ND_INS_VPTESTMW: return "vptestmw"; - case ND_INS_VPTESTNMB: return "vptestnmb"; - case ND_INS_VPTESTNMD: return "vptestnmd"; - case ND_INS_VPTESTNMQ: return "vptestnmq"; - case ND_INS_VPTESTNMW: return "vptestnmw"; - case ND_INS_VPUNPCKHBW: return "vpunpckhbw"; - case ND_INS_VPUNPCKHDQ: return "vpunpckhdq"; - case ND_INS_VPUNPCKHQDQ: return "vpunpckhqdq"; - case ND_INS_VPUNPCKHWD: return "vpunpckhwd"; - case ND_INS_VPUNPCKLBW: return "vpunpcklbw"; - case ND_INS_VPUNPCKLDQ: return "vpunpckldq"; - case ND_INS_VPUNPCKLQDQ: return "vpunpcklqdq"; - case ND_INS_VPUNPCKLWD: return "vpunpcklwd"; - case ND_INS_VPXOR: return "vpxor"; - case ND_INS_VPXORD: return "vpxord"; - case ND_INS_VPXORQ: return "vpxorq"; - case ND_INS_VRANGEPD: return "vrangepd"; - case ND_INS_VRANGEPS: return "vrangeps"; - case ND_INS_VRANGESD: return "vrangesd"; - case ND_INS_VRANGESS: return "vrangess"; - case ND_INS_VRCP14PD: return "vrcp14pd"; - case ND_INS_VRCP14PS: return "vrcp14ps"; - case ND_INS_VRCP14SD: return "vrcp14sd"; - case ND_INS_VRCP14SS: return "vrcp14ss"; - case ND_INS_VRCP28PD: return "vrcp28pd"; - case ND_INS_VRCP28PS: return "vrcp28ps"; - case ND_INS_VRCP28SD: return "vrcp28sd"; - case ND_INS_VRCP28SS: return "vrcp28ss"; - case ND_INS_VRCPPS: return "vrcpps"; - case ND_INS_VRCPSS: return "vrcpss"; - case ND_INS_VREDUCEPD: return "vreducepd"; - case ND_INS_VREDUCEPS: return "vreduceps"; - case ND_INS_VREDUCESD: return "vreducesd"; - case ND_INS_VREDUCESS: return "vreducess"; - case ND_INS_VRNDSCALEPD: return "vrndscalepd"; - case ND_INS_VRNDSCALEPS: return "vrndscaleps"; - case ND_INS_VRNDSCALESD: return "vrndscalesd"; - case ND_INS_VRNDSCALESS: return "vrndscaless"; - case ND_INS_VROUNDPD: return "vroundpd"; - case ND_INS_VROUNDPS: return "vroundps"; - case ND_INS_VROUNDSD: return "vroundsd"; - case ND_INS_VROUNDSS: return "vroundss"; - case ND_INS_VRSQRT14PD: return "vrsqrt14pd"; - case ND_INS_VRSQRT14PS: return "vrsqrt14ps"; - case ND_INS_VRSQRT14SD: return "vrsqrt14sd"; - case ND_INS_VRSQRT14SS: return "vrsqrt14ss"; - case ND_INS_VRSQRT28PD: return "vrsqrt28pd"; - case ND_INS_VRSQRT28PS: return "vrsqrt28ps"; - case ND_INS_VRSQRT28SD: return "vrsqrt28sd"; - case ND_INS_VRSQRT28SS: return "vrsqrt28ss"; - case ND_INS_VRSQRTPS: return "vrsqrtps"; - case ND_INS_VRSQRTSS: return "vrsqrtss"; - case ND_INS_VSCALEFPD: return "vscalefpd"; - case ND_INS_VSCALEFPS: return "vscalefps"; - case ND_INS_VSCALEFSD: return "vscalefsd"; - case ND_INS_VSCALEFSS: return "vscalefss"; - case ND_INS_VSCATTERDPD: return "vscatterdpd"; - case ND_INS_VSCATTERDPS: return "vscatterdps"; - case ND_INS_VSCATTERPF0DPD: return "vscatterpf0dpd"; - case ND_INS_VSCATTERPF0DPS: return "vscatterpf0dps"; - case ND_INS_VSCATTERPF0QPD: return "vscatterpf0qpd"; - case ND_INS_VSCATTERPF0QPS: return "vscatterpf0qps"; - case ND_INS_VSCATTERPF1DPD: return "vscatterpf1dpd"; - case ND_INS_VSCATTERPF1DPS: return "vscatterpf1dps"; - case ND_INS_VSCATTERPF1QPD: return "vscatterpf1qpd"; - case ND_INS_VSCATTERPF1QPS: return "vscatterpf1qps"; - case ND_INS_VSCATTERQPD: return "vscatterqpd"; - case ND_INS_VSCATTERQPS: return "vscatterqps"; - case ND_INS_VSHUFF32X4: return "vshuff32x4"; - case ND_INS_VSHUFF64X2: return "vshuff64x2"; - case ND_INS_VSHUFI32X4: return "vshufi32x4"; - case ND_INS_VSHUFI64X2: return "vshufi64x2"; - case ND_INS_VSHUFPD: return "vshufpd"; - case ND_INS_VSHUFPS: return "vshufps"; - case ND_INS_VSQRTPD: return "vsqrtpd"; - case ND_INS_VSQRTPS: return "vsqrtps"; - case ND_INS_VSQRTSD: return "vsqrtsd"; - case ND_INS_VSQRTSS: return "vsqrtss"; - case ND_INS_VSTMXCSR: return "vstmxcsr"; - case ND_INS_VSUBPD: return "vsubpd"; - case ND_INS_VSUBPS: return "vsubps"; - case ND_INS_VSUBSD: return "vsubsd"; - case ND_INS_VSUBSS: return "vsubss"; - case ND_INS_VTESTPD: return "vtestpd"; - case ND_INS_VTESTPS: return "vtestps"; - case ND_INS_VUCOMISD: return "vucomisd"; - case ND_INS_VUCOMISS: return "vucomiss"; - case ND_INS_VUNPCKHPD: return "vunpckhpd"; - case ND_INS_VUNPCKHPS: return "vunpckhps"; - case ND_INS_VUNPCKLPD: return "vunpcklpd"; - case ND_INS_VUNPCKLPS: return "vunpcklps"; - case ND_INS_VXORPD: return "vxorpd"; - case ND_INS_VXORPS: return "vxorps"; - case ND_INS_VZEROALL: return "vzeroall"; - case ND_INS_VZEROUPPER: return "vzeroupper"; - case ND_INS_WAIT: return "wait"; - case ND_INS_WBINVD: return "wbinvd"; - case ND_INS_WBNOINVD: return "wbnoinvd"; - case ND_INS_WRFSBASE: return "wrfsbase"; - case ND_INS_WRGSBASE: return "wrgsbase"; - case ND_INS_WRMSR: return "wrmsr"; - case ND_INS_WRPKRU: return "wrpkru"; - case ND_INS_WRSHR: return "wrshr"; - case ND_INS_WRSS: return "wrss"; - case ND_INS_WRUSS: return "wruss"; - case ND_INS_XABORT: return "xabort"; - case ND_INS_XADD: return "xadd"; - case ND_INS_XBEGIN: return "xbegin"; - case ND_INS_XCHG: return "xchg"; - case ND_INS_XCRYPTCBC: return "xcryptcbc"; - case ND_INS_XCRYPTCFB: return "xcryptcfb"; - case ND_INS_XCRYPTCTR: return "xcryptctr"; - case ND_INS_XCRYPTECB: return "xcryptecb"; - case ND_INS_XCRYPTOFB: return "xcryptofb"; - case ND_INS_XEND: return "xend"; - case ND_INS_XGETBV: return "xgetbv"; - case ND_INS_XLATB: return "xlatb"; - case ND_INS_XOR: return "xor"; - case ND_INS_XORPD: return "xorpd"; - case ND_INS_XORPS: return "xorps"; - case ND_INS_XRESLDTRK: return "xresldtrik"; - case ND_INS_XRSTOR: return "xrstor"; - case ND_INS_XRSTORS: return "xrstors"; - case ND_INS_XSAVE: return "xsave"; - case ND_INS_XSAVEC: return "xsavec"; - case ND_INS_XSAVEOPT: return "xsaveopt"; - case ND_INS_XSAVES: return "xsaves"; - case ND_INS_XSETBV: return "xsetbv"; - case ND_INS_XSHA1: return "xsha1"; - case ND_INS_XSHA256: return "xsha256"; - case ND_INS_XSUSLDTRK: return "xsusldtrk"; - case ND_INS_XSTORE: return "xstore"; - case ND_INS_XTEST: return "xtest"; - case ND_INS_HRESET: return "hreset"; - case ND_INS_CLUI: return "clui"; - case ND_INS_STUI: return "stui"; - case ND_INS_TESTUI: return "testui"; - case ND_INS_UIRET: return "uiret"; - case ND_INS_SENDUIPI: return "senduipi"; - default: return "unhandled!"; - } - - return ""; -} - - -std::string ins_cat_to_str(ND_INS_CATEGORY category) -{ - switch (category) { - case ND_CAT_INVALID: return "invalid"; - case ND_CAT_3DNOW: return "3dnow"; - case ND_CAT_AES: return "aes"; - case ND_CAT_AESKL: return "aeskl"; - case ND_CAT_AMX: return "amx"; - case ND_CAT_ARITH: return "arith"; - case ND_CAT_AVX: return "avx"; - case ND_CAT_AVX2: return "avx2"; - case ND_CAT_AVX2GATHER: return "avx2gather"; - case ND_CAT_AVX512: return "avx512"; - case ND_CAT_AVX512BF16: return "avx512bf16"; - case ND_CAT_AVX512VBMI: return "avx512vbmi"; - case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect"; - case ND_CAT_AVX512FP16: return "avx512fp16"; - case ND_CAT_AVXVNNI: return "avxvnni"; - case ND_CAT_BITBYTE: return "bitbyte"; - case ND_CAT_BLEND: return "blend"; - case ND_CAT_BMI1: return "bmi1"; - case ND_CAT_BMI2: return "bmi2"; - case ND_CAT_BROADCAST: return "broadcast"; - case ND_CAT_CALL: return "call"; - case ND_CAT_CET: return "cet"; - case ND_CAT_CLDEMOTE: return "cldemote"; - case ND_CAT_CMOV: return "cmov"; - case ND_CAT_COMPRESS: return "compress"; - case ND_CAT_COND_BR: return "cond_br"; - case ND_CAT_CONFLICT: return "conflict"; - case ND_CAT_CONVERT: return "convert"; - case ND_CAT_DATAXFER: return "dataxfer"; - case ND_CAT_DECIMAL: return "decimal"; - case ND_CAT_ENQCMD: return "enqcmd"; - case ND_CAT_EXPAND: return "expand"; - case ND_CAT_FLAGOP: return "flagop"; - case ND_CAT_FMA4: return "fma4"; - case ND_CAT_GATHER: return "gather"; - case ND_CAT_GFNI: return "gfni"; - case ND_CAT_HRESET: return "hreset"; - case ND_CAT_I386: return "i386"; - case ND_CAT_IFMA: return "ifma"; - case ND_CAT_INTERRUPT: return "interrupt"; - case ND_CAT_IO: return "io"; - case ND_CAT_IOSTRINGOP: return "iostringop"; - case ND_CAT_KL: return "kl"; - case ND_CAT_KMASK: return "kmask"; - case ND_CAT_KNL: return "knl"; - case ND_CAT_LKGS: return "lkgs"; - case ND_CAT_LOGIC: return "logic"; - case ND_CAT_LOGICAL: return "logical"; - case ND_CAT_LOGICAL_FP: return "logical_fp"; - case ND_CAT_LWP: return "lwp"; - case ND_CAT_LZCNT: return "lzcnt"; - case ND_CAT_MISC: return "misc"; - case ND_CAT_MMX: return "mmx"; - case ND_CAT_MOVDIR64B: return "movdir64b"; - case ND_CAT_MOVDIRI: return "movdiri"; - case ND_CAT_MPX: return "mpx"; - case ND_CAT_NOP: return "nop"; - case ND_CAT_PADLOCK: return "padlock"; - case ND_CAT_PCLMULQDQ: return "pclmulqdq"; - case ND_CAT_PCONFIG: return "pconfig"; - case ND_CAT_POP: return "pop"; - case ND_CAT_PREFETCH: return "prefetch"; - case ND_CAT_PTWRITE: return "ptwrite"; - case ND_CAT_PUSH: return "push"; - case ND_CAT_RDPID: return "rdpid"; - case ND_CAT_RDRAND: return "rdrand"; - case ND_CAT_RDSEED: return "rdseed"; - case ND_CAT_RDWRFSGS: return "rdwrfsgs"; - case ND_CAT_RET: return "ret"; - case ND_CAT_ROTATE: return "rotate"; - case ND_CAT_SCATTER: return "scatter"; - case ND_CAT_SEGOP: return "segop"; - case ND_CAT_SEMAPHORE: return "semaphore"; - case ND_CAT_SGX: return "sgx"; - case ND_CAT_SHA: return "sha"; - case ND_CAT_SHIFT: return "shift"; - case ND_CAT_SMAP: return "smap"; - case ND_CAT_SSE: return "sse"; - case ND_CAT_SSE2: return "sse2"; - case ND_CAT_STRINGOP: return "stringop"; - case ND_CAT_STTNI: return "sttni"; - case ND_CAT_SYSCALL: return "syscall"; - case ND_CAT_SYSRET: return "sysret"; - case ND_CAT_SYSTEM: return "system"; - case ND_CAT_TDX: return "tdx"; - case ND_CAT_UD: return "ud"; - case ND_CAT_UINTR: return "uintr"; - case ND_CAT_UNCOND_BR: return "uncond_br"; - case ND_CAT_UNKNOWN: return "unknown"; - case ND_CAT_VAES: return "vaes"; - case ND_CAT_VFMA: return "vfma"; - case ND_CAT_VFMAPS: return "vfmaps"; - case ND_CAT_VNNI: return "vnni"; - case ND_CAT_VNNIW: return "vnniw"; - case ND_CAT_VPCLMULQDQ: return "vpclmulqdq"; - case ND_CAT_VPOPCNT: return "vpopcnt"; - case ND_CAT_VTX: return "vtx"; - case ND_CAT_WAITPKG: return "waitpkg"; - case ND_CAT_WBNOINVD: return "wbnoinvd"; - case ND_CAT_WIDE_KL: return "wide_kl"; - case ND_CAT_WIDENOP: return "widenop"; - case ND_CAT_X87_ALU: return "x87_alu"; - case ND_CAT_XOP: return "xop"; - case ND_CAT_XSAVE: return "xsave"; - } - - return ""; -} - - -std::string ins_set_to_str(ND_INS_SET ins_set) -{ - switch (ins_set) { - case ND_SET_INVALID: return "invalid"; - case ND_SET_3DNOW: return "3dnow"; - case ND_SET_ADX: return "adx"; - case ND_SET_AES: return "aes"; - case ND_SET_AMD: return "amd"; - case ND_SET_AMXBF16: return "amxbf16"; - case ND_SET_AMXINT8: return "amxint8"; - case ND_SET_AMXTILE: return "amxtile"; - case ND_SET_AVX: return "avx"; - case ND_SET_AVX2: return "avx2"; - case ND_SET_AVX2GATHER: return "avx2gather"; - case ND_SET_AVX5124FMAPS: return "avx5124fmaps"; - case ND_SET_AVX5124VNNIW: return "avx5124vnniw"; - case ND_SET_AVX512BF16: return "avx512bf16"; - case ND_SET_AVX512BITALG: return "avx512bitalg"; - case ND_SET_AVX512BW: return "avx512bw"; - case ND_SET_AVX512CD: return "avx512cd"; - case ND_SET_AVX512DQ: return "avx512dq"; - case ND_SET_AVX512ER: return "avx512er"; - case ND_SET_AVX512F: return "avx512f"; - case ND_SET_AVX512IFMA: return "avx512ifma"; - case ND_SET_AVX512PF: return "avx512pf"; - case ND_SET_AVX512VBMI: return "avx512vbmi"; - case ND_SET_AVX512VBMI2: return "avx512vbmi2"; - case ND_SET_AVX512VNNI: return "avx512vnni"; - case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect"; - case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq"; - case ND_SET_AVX512FP16: return "avx512fp16"; - case ND_SET_AVXVNNI: return "avxvnni"; - case ND_SET_BMI1: return "bmi1"; - case ND_SET_BMI2: return "bmi2"; - case ND_SET_CET_SS: return "cet_ss"; - case ND_SET_CET_IBT: return "cet_ibt"; - case ND_SET_CLDEMOTE: return "cldemote"; - case ND_SET_CLFSH: return "clfsh"; - case ND_SET_CLFSHOPT: return "clfshopt"; - case ND_SET_CLWB: return "clwb"; - case ND_SET_CLZERO: return "clzero"; - case ND_SET_CMPXCHG16B: return "cmpxchg16b"; - case ND_SET_CYRIX: return "cyrix"; - case ND_SET_CYRIX_SMM: return "cyrix_smm"; - case ND_SET_ENQCMD: return "enqcmd"; - case ND_SET_F16C: return "f16c"; - case ND_SET_FMA: return "fma"; - case ND_SET_FMA4: return "fma4"; - case ND_SET_FRED: return "fred"; - case ND_SET_FXSAVE: return "fxsave"; - case ND_SET_GFNI: return "gfni"; - case ND_SET_HRESET: return "hreset"; - case ND_SET_I186: return "i186"; - case ND_SET_INVLPGB: return "invlpgb"; - case ND_SET_I286PROT: return "i286prot"; - case ND_SET_I286REAL: return "i286real"; - case ND_SET_I386: return "i386"; - case ND_SET_I486: return "i486"; - case ND_SET_I486REAL: return "i486real"; - case ND_SET_I64: return "i64"; - case ND_SET_I86: return "i86"; - case ND_SET_INVPCID: return "invpcid"; - case ND_SET_KL: return "kl"; - case ND_SET_LKGS: return "lkgs"; - case ND_SET_LONGMODE: return "longmode"; - case ND_SET_LWP: return "lwp"; - case ND_SET_LZCNT: return "lzcnt"; - case ND_SET_MCOMMIT: return "mcommit"; - case ND_SET_MMX: return "mmx"; - case ND_SET_MOVBE: return "movbe"; - case ND_SET_MOVDIR64B: return "movdir64b"; - case ND_SET_MOVDIRI: return "movdiri"; - case ND_SET_MPX: return "mpx"; - case ND_SET_MWAITT: return "mwaitt"; - case ND_SET_PAUSE: return "pause"; - case ND_SET_PCLMULQDQ: return "pclmulqdq"; - case ND_SET_PCONFIG: return "pconfig"; - case ND_SET_PENTIUMREAL: return "pentiumreal"; - case ND_SET_PKU: return "pku"; - case ND_SET_POPCNT: return "popcnt"; - case ND_SET_PPRO: return "ppro"; - case ND_SET_PREFETCH_NOP: return "prefetch_nop"; - case ND_SET_PTWRITE: return "ptwrite"; - case ND_SET_RDPID: return "rdpid"; - case ND_SET_RDPMC: return "rdpmc"; - case ND_SET_RDPRU: return "rdpru"; - case ND_SET_RDRAND: return "rdrand"; - case ND_SET_RDSEED: return "rdseed"; - case ND_SET_RDTSCP: return "rdtscp"; - case ND_SET_RDWRFSGS: return "rdwrfsgs"; - case ND_SET_SERIALIZE: return "serialize"; - case ND_SET_SGX: return "sgx"; - case ND_SET_SHA: return "sha"; - case ND_SET_SMAP: return "smap"; - case ND_SET_SMX: return "smx"; - case ND_SET_SNP: return "snp"; - case ND_SET_SSE: return "sse"; - case ND_SET_SSE2: return "sse2"; - case ND_SET_SSE3: return "sse3"; - case ND_SET_SSE4: return "sse4"; - case ND_SET_SSE42: return "sse42"; - case ND_SET_SSE4A: return "sse4a"; - case ND_SET_SSSE3: return "ssse3"; - case ND_SET_SVM: return "svm"; - case ND_SET_TBM: return "tbm"; - case ND_SET_TDX: return "tdx"; - case ND_SET_TSX: return "tsx"; - case ND_SET_TSXLDTRK: return "tsxldtrk"; - case ND_SET_UD: return "ud"; - case ND_SET_UINTR: return "uintr"; - case ND_SET_UNKNOWN: return "unknown"; - case ND_SET_VAES: return "vaes"; - case ND_SET_VPCLMULQDQ: return "vpclmulqdq"; - case ND_SET_VTX: return "vtx"; - case ND_SET_WAITPKG: return "waitpkg"; - case ND_SET_WBNOINVD: return "wbnoinvd"; - case ND_SET_X87: return "x87"; - case ND_SET_XOP: return "xop"; - case ND_SET_XSAVE: return "xsave"; - case ND_SET_XSAVEC: return "xsavec"; - case ND_SET_XSAVES: return "xsaves"; - } - - return ""; -} - - -std::string reg_to_str(const int reg, const ND_REG_TYPE type) -{ - switch (type) { - case ND_REG_NOT_PRESENT: - return "not_preset"; - - case ND_REG_GPR: - switch (reg) { - case NDR_RAX: return "rax"; - case NDR_RCX: return "rcx"; - case NDR_RDX: return "rdx"; - case NDR_RBX: return "rbx"; - case NDR_RSP: return "rsp"; - case NDR_RBP: return "rbp"; - case NDR_RSI: return "rsi"; - case NDR_RDI: return "rdi"; - case NDR_R8: return "r8"; - case NDR_R9: return "r9"; - case NDR_R10: return "r10"; - case NDR_R11: return "r11"; - case NDR_R12: return "r12"; - case NDR_R13: return "r13"; - case NDR_R14: return "r14"; - case NDR_R15: return "r15"; - } - - return ""; - - case ND_REG_SEG: - switch (reg) { - case NDR_ES: return "es"; - case NDR_CS: return "cs"; - case NDR_SS: return "ss"; - case NDR_DS: return "ds"; - case NDR_FS: return "fs"; - case NDR_GS: return "gs"; - case NDR_INV6: return "inv6"; - case NDR_INV7: return "inv7"; - } - - return ""; - - case ND_REG_FPU: - return "fpu"; - case ND_REG_MMX: - return "mmx"; - case ND_REG_SSE: - return "sse"; - case ND_REG_CR: - return "cr"; - case ND_REG_DR: - return "dr"; - case ND_REG_TR: - return "tr"; - case ND_REG_BND: - return "bnd"; - case ND_REG_MSK: - return "msk"; - case ND_REG_TILE: - return "tile"; - case ND_REG_MSR: - return "msr"; - case ND_REG_XCR: - return "xcr"; - case ND_REG_SYS: - return "sys"; - case ND_REG_X87: - return "x87"; - case ND_REG_MXCSR: - return "mxcsr"; - case ND_REG_PKRU: - return "pkru"; - case ND_REG_SSP: - return "ssp"; - case ND_REG_FLG: - return "flg"; - case ND_REG_RIP: - return "rip"; - case ND_REG_UIF: - return "uif"; - } - - return ""; -} - - -std::string reg_type_to_str(const ND_REG_TYPE type) -{ - switch (type) { - case ND_REG_NOT_PRESENT: - return "present"; - case ND_REG_GPR: - return "gpr"; - case ND_REG_SEG: - return "seg"; - case ND_REG_FPU: - return "fpu"; - case ND_REG_MMX: - return "mmx"; - case ND_REG_SSE: - return "sse"; - case ND_REG_CR: - return "cr"; - case ND_REG_DR: - return "dr"; - case ND_REG_TR: - return "tr"; - case ND_REG_BND: - return "bnd"; - case ND_REG_MSK: - return "msk"; - case ND_REG_TILE: - return "tile"; - case ND_REG_MSR: - return "msr"; - case ND_REG_XCR: - return "xcr"; - case ND_REG_SYS: - return "sys"; - case ND_REG_X87: - return "x87"; - case ND_REG_MXCSR: - return "mxcsr"; - case ND_REG_PKRU: - return "pkru"; - case ND_REG_SSP: - return "ssp"; - case ND_REG_FLG: - return "flg"; - case ND_REG_RIP: - return "rip"; - case ND_REG_UIF: - return "uif"; - } - - return ""; -} diff --git a/disasmtool_lix/external/argparse.h b/disasmtool_lix/external/argparse.h deleted file mode 100644 index 478079b..0000000 --- a/disasmtool_lix/external/argparse.h +++ /dev/null @@ -1,566 +0,0 @@ -/** - * License: Apache 2.0 with LLVM Exception or GPL v3 - * - * Author: Jesse Laning - */ - -#ifndef ARGPARSE_H -#define ARGPARSE_H - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -namespace argparse { -namespace detail { -static inline bool _not_space(int ch) { return !std::isspace(ch); } -static inline void _ltrim(std::string &s, bool (*f)(int) = _not_space) { - s.erase(s.begin(), std::find_if(s.begin(), s.end(), f)); -} -static inline void _rtrim(std::string &s, bool (*f)(int) = _not_space) { - s.erase(std::find_if(s.rbegin(), s.rend(), f).base(), s.end()); -} -static inline void _trim(std::string &s, bool (*f)(int) = _not_space) { - _ltrim(s, f); - _rtrim(s, f); -} -static inline std::string _ltrim_copy(std::string s, - bool (*f)(int) = _not_space) { - _ltrim(s, f); - return s; -} -static inline std::string _rtrim_copy(std::string s, - bool (*f)(int) = _not_space) { - _rtrim(s, f); - return s; -} -static inline std::string _trim_copy(std::string s, - bool (*f)(int) = _not_space) { - _trim(s, f); - return s; -} -template -static inline std::string _join(InputIt begin, InputIt end, - const std::string &separator = " ") { - std::ostringstream ss; - if (begin != end) { - ss << *begin++; - } - while (begin != end) { - ss << separator; - ss << *begin++; - } - return ss.str(); -} -static inline bool _is_number(const std::string &arg) { - std::istringstream iss(arg); - float f; - iss >> std::noskipws >> f; - return iss.eof() && !iss.fail(); -} - -static inline int _find_equal(const std::string &s) { - for (size_t i = 0; i < s.length(); ++i) { - // if find graph symbol before equal, end search - // i.e. don't accept --asd)f=0 arguments - // but allow --asd_f and --asd-f arguments - if (std::ispunct(static_cast(s[i]))) { - if (s[i] == '=') { - return static_cast(i); - } else if (s[i] == '_' || s[i] == '-') { - continue; - } - return -1; - } - } - return -1; -} - -static inline size_t _find_name_end(const std::string &s) { - size_t i; - for (i = 0; i < s.length(); ++i) { - if (std::ispunct(static_cast(s[i]))) { - break; - } - } - return i; -} - -namespace is_vector_impl { -template -struct is_vector : std::false_type {}; -template -struct is_vector> : std::true_type {}; -} // namespace is_vector_impl - -// type trait to utilize the implementation type traits as well as decay the -// type -template -struct is_vector { - static constexpr bool const value = - is_vector_impl::is_vector::type>::value; -}; -} // namespace detail - -class ArgumentParser { - private: - public: - class Argument; - - class Result { - public: - Result() {} - Result(std::string err) noexcept : _error(true), _what(err) {} - - operator bool() const { return _error; } - - friend std::ostream &operator<<(std::ostream &os, const Result &dt); - - const std::string &what() const { return _what; } - - private: - bool _error{false}; - std::string _what{}; - }; - - class Argument { - public: - enum Position : int { LAST = -1, DONT_CARE = -2 }; - enum Count : int { ANY = -1 }; - - Argument &name(const std::string &name) { - _names.push_back(name); - return *this; - } - - Argument &names(std::vector names) { - _names.insert(_names.end(), names.begin(), names.end()); - return *this; - } - - Argument &description(const std::string &description) { - _desc = description; - return *this; - } - - Argument &required(bool req) { - _required = req; - return *this; - } - - Argument &position(int position) { - if (position != Position::LAST) { - // position + 1 because technically argument zero is the name of the - // executable - _position = position + 1; - } else { - _position = position; - } - return *this; - } - - Argument &count(int count) { - _count = count; - return *this; - } - - bool found() const { return _found; } - - template - typename std::enable_if::value, T>::type get() { - T t = T(); - typename T::value_type vt; - for (auto &s : _values) { - std::istringstream in(s); - in >> vt; - t.push_back(vt); - } - return t; - } - - template - typename std::enable_if::value, T>::type get() { - std::istringstream in(get()); - T t = T(); - in >> t >> std::ws; - return t; - } - - private: - Argument(const std::string &name, const std::string &desc, - bool required = false) - : _desc(desc), _required(required) { - _names.push_back(name); - } - - Argument() {} - - friend class ArgumentParser; - int _position{Position::DONT_CARE}; - int _count{Count::ANY}; - std::vector _names{}; - std::string _desc{}; - bool _found{false}; - bool _required{false}; - int _index{-1}; - - std::vector _values{}; - }; - - ArgumentParser(const std::string &bin, const std::string &desc) - : _bin(bin), _desc(desc) {} - - Argument &add_argument() { - _arguments.push_back({}); - _arguments.back()._index = static_cast(_arguments.size()) - 1; - return _arguments.back(); - } - - Argument &add_argument(const std::string &name, const std::string &long_name, - const std::string &desc, const bool required = false) { - _arguments.push_back(Argument(name, desc, required)); - _arguments.back()._names.push_back(long_name); - _arguments.back()._index = static_cast(_arguments.size()) - 1; - return _arguments.back(); - } - - Argument &add_argument(const std::string &name, const std::string &desc, - const bool required = false) { - _arguments.push_back(Argument(name, desc, required)); - _arguments.back()._index = static_cast(_arguments.size()) - 1; - return _arguments.back(); - } - - void print_help(size_t count = 0, size_t page = 0) { - if (page * count > _arguments.size()) { - return; - } - if (page == 0) { - std::cout << "Usage: " << _bin; - if (_positional_arguments.empty()) { - std::cout << " [options...]" << std::endl; - } else { - int current = 1; - for (auto &v : _positional_arguments) { - if (v.first != Argument::Position::LAST) { - for (; current < v.first; current++) { - std::cout << " [" << current << "]"; - } - std::cout - << " [" - << detail::_ltrim_copy( - _arguments[static_cast(v.second)]._names[0], - [](int c) -> bool { return c != static_cast('-'); }) - << "]"; - } - } - auto it = _positional_arguments.find(Argument::Position::LAST); - if (it == _positional_arguments.end()) { - std::cout << " [options...]"; - } else { - std::cout - << " [options...] [" - << detail::_ltrim_copy( - _arguments[static_cast(it->second)]._names[0], - [](int c) -> bool { return c != static_cast('-'); }) - << "]"; - } - std::cout << std::endl; - } - std::cout << "Options:" << std::endl; - } - if (count == 0) { - page = 0; - count = _arguments.size(); - } - for (size_t i = page * count; - i < std::min(page * count + count, _arguments.size()); i++) { - Argument &a = _arguments[i]; - std::string name = a._names[0]; - for (size_t n = 1; n < a._names.size(); ++n) { - name.append(", " + a._names[n]); - } - std::cout << " " << std::setw(23) << std::left << name << std::setw(23) - << a._desc; - if (a._required) { - std::cout << " (Required)"; - } - std::cout << std::endl; - } - } - - Result parse(int argc, const char *argv[]) { - Result err; - if (argc > 1) { - // build name map - for (auto &a : _arguments) { - for (auto &n : a._names) { - std::string name = detail::_ltrim_copy( - n, [](int c) -> bool { return c != static_cast('-'); }); - if (_name_map.find(name) != _name_map.end()) { - return Result("Duplicate of argument name: " + n); - } - _name_map[name] = a._index; - } - if (a._position >= 0 || a._position == Argument::Position::LAST) { - _positional_arguments[a._position] = a._index; - } - } - if (err) { - return err; - } - - // parse - std::string current_arg; - size_t arg_len; - for (int argv_index = 1; argv_index < argc; ++argv_index) { - current_arg = std::string(argv[argv_index]); - arg_len = current_arg.length(); - if (arg_len == 0) { - continue; - } - if (_help_enabled && (current_arg == "-h" || current_arg == "--help")) { - _arguments[static_cast(_name_map["help"])]._found = true; - } else if (argv_index == argc - 1 && - _positional_arguments.find(Argument::Position::LAST) != - _positional_arguments.end()) { - err = _end_argument(); - Result b = err; - err = _add_value(current_arg, Argument::Position::LAST); - if (b) { - return b; - } - if (err) { - return err; - } - } else if (arg_len >= 2 && - !detail::_is_number(current_arg)) { // ignores the case if - // the arg is just a - - // look for -a (short) or --arg (long) args - if (current_arg[0] == '-') { - err = _end_argument(); - if (err) { - return err; - } - // look for --arg (long) args - if (current_arg[1] == '-') { - err = _begin_argument(current_arg.substr(2), true, argv_index); - if (err) { - return err; - } - } else { // short args - err = _begin_argument(current_arg.substr(1), false, argv_index); - if (err) { - return err; - } - } - } else { // argument value - err = _add_value(current_arg, argv_index); - if (err) { - return err; - } - } - } else { // argument value - err = _add_value(current_arg, argv_index); - if (err) { - return err; - } - } - } - } - if (_help_enabled && exists("help")) { - return Result(); - } - err = _end_argument(); - if (err) { - return err; - } - for (auto &p : _positional_arguments) { - Argument &a = _arguments[static_cast(p.second)]; - if (a._values.size() > 0 && a._values[0][0] == '-') { - std::string name = detail::_ltrim_copy(a._values[0], [](int c) -> bool { - return c != static_cast('-'); - }); - if (_name_map.find(name) != _name_map.end()) { - if (a._position == Argument::Position::LAST) { - return Result( - "Poisitional argument expected at the end, but argument " + - a._values[0] + " found instead"); - } else { - return Result("Poisitional argument expected in position " + - std::to_string(a._position) + ", but argument " + - a._values[0] + " found instead"); - } - } - } - } - for (auto &a : _arguments) { - if (a._required && !a._found) { - return Result("Required argument not found: " + a._names[0]); - } - if (a._position >= 0 && argc >= a._position && !a._found) { - return Result("Argument " + a._names[0] + " expected in position " + - std::to_string(a._position)); - } - } - return Result(); - } - - void enable_help() { - add_argument("-h", "--help", "Shows this page", false); - _help_enabled = true; - } - - bool exists(const std::string &name) const { - std::string n = detail::_ltrim_copy( - name, [](int c) -> bool { return c != static_cast('-'); }); - auto it = _name_map.find(n); - if (it != _name_map.end()) { - return _arguments[static_cast(it->second)]._found; - } - return false; - } - - template - T get(const std::string &name) { - auto t = _name_map.find(name); - if (t != _name_map.end()) { - return _arguments[static_cast(t->second)].get(); - } - return T(); - } - - private: - Result _begin_argument(const std::string &arg, bool longarg, int position) { - auto it = _positional_arguments.find(position); - if (it != _positional_arguments.end()) { - Result err = _end_argument(); - Argument &a = _arguments[static_cast(it->second)]; - a._values.push_back((longarg ? "--" : "-") + arg); - a._found = true; - return err; - } - if (_current != -1) { - return Result("Current argument left open"); - } - size_t name_end = detail::_find_name_end(arg); - std::string arg_name = arg.substr(0, name_end); - if (longarg) { - int equal_pos = detail::_find_equal(arg); - auto nmf = _name_map.find(arg_name); - if (nmf == _name_map.end()) { - return Result("Unrecognized command line option '" + arg_name + "'"); - } - _current = nmf->second; - _arguments[static_cast(nmf->second)]._found = true; - if (equal_pos == 0 || - (equal_pos < 0 && - arg_name.length() < arg.length())) { // malformed argument - return Result("Malformed argument: " + arg); - } else if (equal_pos > 0) { - std::string arg_value = arg.substr(name_end + 1); - _add_value(arg_value, position); - } - } else { - Result r; - if (arg_name.length() == 1) { - return _begin_argument(arg, true, position); - } else { - for (char &c : arg_name) { - r = _begin_argument(std::string(1, c), true, position); - if (r) { - return r; - } - r = _end_argument(); - if (r) { - return r; - } - } - } - } - return Result(); - } - - Result _add_value(const std::string &value, int location) { - if (_current >= 0) { - Result err; - Argument &a = _arguments[static_cast(_current)]; - if (a._count >= 0 && static_cast(a._values.size()) >= a._count) { - err = _end_argument(); - if (err) { - return err; - } - goto unnamed; - } - a._values.push_back(value); - if (a._count >= 0 && static_cast(a._values.size()) >= a._count) { - err = _end_argument(); - if (err) { - return err; - } - } - return Result(); - } else { - unnamed: - auto it = _positional_arguments.find(location); - if (it != _positional_arguments.end()) { - Argument &a = _arguments[static_cast(it->second)]; - a._values.push_back(value); - a._found = true; - } - // TODO - return Result(); - } - } - - Result _end_argument() { - if (_current >= 0) { - Argument &a = _arguments[static_cast(_current)]; - _current = -1; - if (static_cast(a._values.size()) < a._count) { - return Result("Too few arguments given for " + a._names[0]); - } - if (a._count >= 0) { - if (static_cast(a._values.size()) > a._count) { - return Result("Too many arguments given for " + a._names[0]); - } - } - } - return Result(); - } - - bool _help_enabled{false}; - int _current{-1}; - std::string _bin{}; - std::string _desc{}; - std::vector _arguments{}; - std::map _positional_arguments{}; - std::map _name_map{}; -}; - -std::ostream &operator<<(std::ostream &os, const ArgumentParser::Result &r) { - os << r.what(); - return os; -} -template <> -inline std::string ArgumentParser::Argument::get() { - return detail::_join(_values.begin(), _values.end()); -} -template <> -inline std::vector -ArgumentParser::Argument::get>() { - return _values; -} - -} // namespace argparse -#endif diff --git a/disasmtool_lix/rapidjson.cpp b/disasmtool_lix/rapidjson.cpp deleted file mode 100644 index 99975bc..0000000 --- a/disasmtool_lix/rapidjson.cpp +++ /dev/null @@ -1,1209 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#include "disasm.hpp" - -#include - -#include -#include -#include - - -using namespace rapidjson; - - -static void _start_object(Writer &writer) -{ - writer.StartObject(); -} - - -static void _start_object(Writer &writer, const char *key) -{ - writer.Key(key); - writer.StartObject(); -} - -static void _end_object(Writer &writer) -{ - writer.EndObject(); -} - - -static void _start_array(Writer &writer) -{ - writer.StartArray(); -} - - -static void _start_array(Writer &writer, const char *key) -{ - writer.Key(key); - writer.StartArray(); -} - -static void _end_array(Writer &writer) -{ - writer.EndArray(); -} - - -static void _write_uint(Writer &writer, unsigned int value) -{ - writer.Uint(value); -} - - -static void _write_uint(Writer &writer, const char *key, unsigned int value) -{ - writer.Key(key); - writer.Uint(value); -} - - -static void _write_int(Writer &writer, int value) -{ - writer.Int(value); -} - - -static void _write_int(Writer &writer, const char *key, int value) -{ - writer.Key(key); - writer.Int(value); -} - - -static void _write_uint64(Writer &writer, uint64_t value) -{ - writer.Int(value); -} - - -static void _write_uint64(Writer &writer, const char *key, uint64_t value) -{ - writer.Key(key); - writer.Int(value); -} - - -static void _write_int64(Writer &writer, int64_t value) -{ - writer.Int(value); -} - - -static void _write_int64(Writer &writer, const char *key, int64_t value) -{ - writer.Key(key); - writer.Int(value); -} - - -static void _write_string(Writer &writer, const std::string& value) -{ - writer.String(value.c_str()); -} - - -static void _write_string(Writer &writer, const char *key, const std::string& value) -{ - writer.Key(key); - writer.String(value.c_str()); -} - - -static void _write_string(Writer &writer, const char *value) -{ - writer.String(value); -} - - -static void _write_string(Writer &writer, const char *key, const char *value) -{ - writer.Key(key); - writer.String(value); -} - - -static void _write_bool(Writer &writer, bool value) -{ - writer.Bool(value); -} - - -static void _write_bool(Writer &writer, const char *key, bool value) -{ - writer.Key(key); - writer.Bool(value); -} - - -static int _disasm_size_to_int(const uint8_t mode) -{ - switch (mode) { - case 0: return 16; - case 1: return 32; - case 2: return 64; - } - - return mode; -} - - -static void _write_rex(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasRex) - return; - - _start_object(writer, "rex"); - - _write_uint(writer, "value", instrux->Rex.Rex); - - _write_uint(writer, "b", static_cast(instrux->Rex.b)); - _write_uint(writer, "x", static_cast(instrux->Rex.x)); - _write_uint(writer, "r", static_cast(instrux->Rex.r)); - _write_uint(writer, "w", static_cast(instrux->Rex.w)); - - _end_object(writer); -} - - -static void _write_modrm(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasModRm) - return; - - _start_object(writer, "modrm"); - - _write_uint(writer, "value", instrux->ModRm.ModRm); - _write_uint(writer, "rm", static_cast(instrux->ModRm.rm)); - _write_uint(writer, "reg", static_cast(instrux->ModRm.reg)); - _write_uint(writer, "mod", static_cast(instrux->ModRm.mod)); - - _end_object(writer); -} - - -static void _write_sib(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasSib) - return; - - _start_object(writer, "sib"); - - _write_uint(writer, "value", instrux->Sib.Sib); - _write_uint(writer, "base", static_cast(instrux->Sib.base)); - _write_uint(writer, "index", static_cast(instrux->Sib.index)); - _write_uint(writer, "scale", static_cast(instrux->Sib.scale)); - - _end_object(writer); -} - - -static void _write_drex(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasDrex) - return; - - _start_object(writer, "drex"); - - _write_uint(writer, "value", instrux->Drex.Drex); - _write_uint(writer, "b", static_cast(instrux->Drex.b)); - _write_uint(writer, "x", static_cast(instrux->Drex.x)); - _write_uint(writer, "r", static_cast(instrux->Drex.r)); - _write_uint(writer, "oc", static_cast(instrux->Drex.oc0)); - _write_uint(writer, "vd", static_cast(instrux->Drex.vd)); - _write_uint(writer, "d", static_cast(instrux->Drex.d)); - - _end_object(writer); -} - - -static void _write_vex2(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasVex || ND_VEXM_2B != instrux->VexMode) - return; - - _start_object(writer, "vex2"); - - _start_array(writer, "value"); - _write_uint(writer, instrux->Vex2.Vex[0]); - _write_uint(writer, instrux->Vex2.Vex[1]); - _end_array(writer); - - _write_uint(writer, "op", instrux->Vex2.op); - _write_uint(writer, "p", static_cast(instrux->Vex2.p)); - _write_uint(writer, "l", static_cast(instrux->Vex2.l)); - _write_uint(writer, "v", static_cast(instrux->Vex2.v)); - _write_uint(writer, "r", static_cast(instrux->Vex2.r)); - - _end_object(writer); -} - - -static void _write_vex3(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasVex || ND_VEXM_3B != instrux->VexMode) - return; - - _start_object(writer, "vex3"); - - _start_array(writer, "value"); - _write_uint(writer, instrux->Vex3.Vex[0]); - _write_uint(writer, instrux->Vex3.Vex[1]); - _write_uint(writer, instrux->Vex3.Vex[2]); - _end_array(writer); - - _write_uint(writer, "op", instrux->Vex3.op); - _write_uint(writer, "m", static_cast(instrux->Vex3.m)); - _write_uint(writer, "b", static_cast(instrux->Vex3.b)); - _write_uint(writer, "x", static_cast(instrux->Vex3.x)); - _write_uint(writer, "r", static_cast(instrux->Vex3.r)); - _write_uint(writer, "p", static_cast(instrux->Vex3.p)); - _write_uint(writer, "l", static_cast(instrux->Vex3.l)); - _write_uint(writer, "v", static_cast(instrux->Vex3.v)); - _write_uint(writer, "w", static_cast(instrux->Vex3.w)); - - _end_object(writer); -} - - -static void _write_xop(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasXop) - return; - - _start_object(writer, "xop"); - - _start_array(writer, "value"); - _write_uint(writer, instrux->Xop.Xop[0]); - _write_uint(writer, instrux->Xop.Xop[1]); - _write_uint(writer, instrux->Xop.Xop[2]); - _end_array(writer); - - _write_uint(writer, "op", instrux->Xop.op); - _write_uint(writer, "m", static_cast(instrux->Xop.m)); - _write_uint(writer, "b", static_cast(instrux->Xop.b)); - _write_uint(writer, "x", static_cast(instrux->Xop.x)); - _write_uint(writer, "r", static_cast(instrux->Xop.r)); - _write_uint(writer, "p", static_cast(instrux->Xop.p)); - _write_uint(writer, "l", static_cast(instrux->Xop.l)); - _write_uint(writer, "v", static_cast(instrux->Xop.v)); - _write_uint(writer, "w", static_cast(instrux->Xop.w)); - - _end_object(writer); -} - - -static void _write_evex(Writer &writer, const INSTRUX *instrux) -{ - if (!instrux->HasEvex) - return; - - _start_object(writer, "evex"); - - _start_array(writer, "value"); - _write_uint(writer, instrux->Evex.Evex[0]); - _write_uint(writer, instrux->Evex.Evex[1]); - _write_uint(writer, instrux->Evex.Evex[2]); - _write_uint(writer, instrux->Evex.Evex[3]); - _end_array(writer); - - _write_uint(writer, "op", instrux->Evex.op); - _write_uint(writer, "m", static_cast(instrux->Evex.m)); - _write_uint(writer, "zero", static_cast(instrux->Evex.zero)); - _write_uint(writer, "rp", static_cast(instrux->Evex.rp)); - _write_uint(writer, "b", static_cast(instrux->Evex.b)); - _write_uint(writer, "x", static_cast(instrux->Evex.x)); - _write_uint(writer, "r", static_cast(instrux->Evex.r)); - _write_uint(writer, "p", static_cast(instrux->Evex.p)); - _write_uint(writer, "one", static_cast(instrux->Evex.one)); - _write_uint(writer, "v", static_cast(instrux->Evex.v)); - _write_uint(writer, "w", static_cast(instrux->Evex.w)); - _write_uint(writer, "a", static_cast(instrux->Evex.a)); - _write_uint(writer, "vp", static_cast(instrux->Evex.vp)); - _write_uint(writer, "bm", static_cast(instrux->Evex.bm)); - _write_uint(writer, "l", static_cast(instrux->Evex.l)); - _write_uint(writer, "z", static_cast(instrux->Evex.z)); - - _end_object(writer); -} - - -static void _write_exs(Writer &writer, const INSTRUX *instrux) -{ - _start_object(writer, "exs"); - - _write_uint(writer, "w", static_cast(instrux->Exs.w)); - _write_uint(writer, "r", static_cast(instrux->Exs.r)); - _write_uint(writer, "x", static_cast(instrux->Exs.x)); - _write_uint(writer, "b", static_cast(instrux->Exs.b)); - _write_uint(writer, "rp", static_cast(instrux->Exs.rp)); - _write_uint(writer, "p", static_cast(instrux->Exs.p)); - _write_uint(writer, "m", static_cast(instrux->Exs.m)); - _write_uint(writer, "l", static_cast(instrux->Exs.l)); - _write_uint(writer, "v", static_cast(instrux->Exs.v)); - _write_uint(writer, "vp", static_cast(instrux->Exs.vp)); - _write_uint(writer, "bm", static_cast(instrux->Exs.bm)); - _write_uint(writer, "e", static_cast(instrux->Exs.e)); - _write_uint(writer, "z", static_cast(instrux->Exs.z)); - _write_uint(writer, "k", static_cast(instrux->Exs.k)); - _write_uint(writer, "s", static_cast(instrux->Exs.s)); - - _end_object(writer); -} - - -static void _write_prefixes(Writer &writer, const INSTRUX *instrux) -{ - _start_array(writer, "prefixes"); - - if (instrux->HasRex) - _write_string(writer, "rex"); - - if (instrux->HasVex) - _write_string(writer, "vex"); - - if (instrux->HasXop) - _write_string(writer, "xop"); - - if (instrux->HasEvex) - _write_string(writer, "evex"); - - if (instrux->HasMvex) - _write_string(writer, "mvex"); - - if (instrux->HasOpSize) - _write_string(writer, "op_size"); - - if (instrux->HasAddrSize) - _write_string(writer, "addr_size"); - - if (instrux->HasLock) - _write_string(writer, "lock"); - - if (instrux->HasRepnzXacquireBnd) - _write_string(writer, "repnz_xacquire_bnd"); - - if (instrux->HasRepRepzXrelease) - _write_string(writer, "rep_repz_xrelease"); - - if (instrux->HasSeg) - _write_string(writer, "seg"); - - _end_array(writer); -} - - -static void _write_chunks(Writer &writer, const INSTRUX *instrux) -{ - _start_array(writer, "chunks"); - - if (instrux->HasModRm) - _write_string(writer, "mod_rm"); - - if (instrux->HasSib) - _write_string(writer, "sib"); - - if (instrux->HasDrex) - _write_string(writer, "drex"); - - if (instrux->HasDisp) - _write_string(writer, "disp"); - - if (instrux->HasAddr) - _write_string(writer, "addr"); - - if (instrux->HasMoffset) - _write_string(writer, "moffset"); - - if (instrux->HasImm1) - _write_string(writer, "imm1"); - - if (instrux->HasImm2) - _write_string(writer, "imm2"); - - if (instrux->HasImm3) - _write_string(writer, "imm3"); - - if (instrux->HasRelOffs) - _write_string(writer, "rel_offs"); - - if (instrux->HasSseImm) - _write_string(writer, "sse_imm"); - - if (instrux->HasCompDisp) - _write_string(writer, "comp_disp"); - - if (instrux->HasBroadcast) - _write_string(writer, "broadcast"); - - if (instrux->HasMask) - _write_string(writer, "mask"); - - if (instrux->HasZero) - _write_string(writer, "zero"); - - if (instrux->HasEr) - _write_string(writer, "er"); - - if (instrux->HasSae) - _write_string(writer, "sae"); - - if (instrux->SignDisp) - _write_string(writer, "sign_disp"); - - _end_array(writer); -} - - -static void _write_access(Writer &writer, const char *key, const uint8_t access) -{ - _start_array(writer, key); - - if (access & ND_ACCESS_READ) - _write_string(writer, "read"); - - if (access & ND_ACCESS_WRITE) - _write_string(writer, "write"); - - if (access & ND_ACCESS_COND_READ) - _write_string(writer, "cond_read"); - - if (access & ND_ACCESS_COND_WRITE) - _write_string(writer, "cond_write"); - - if (access == ND_ACCESS_NONE) - _write_string(writer, "none"); - - _end_array(writer); -} - - -static void _start_write_default_op(Writer &writer, const ND_OPERAND &op) -{ - _start_object(writer); - - _start_array(writer, "flags"); - - if (op.Flags.IsDefault) - _write_string(writer, "default"); - - if (op.Flags.SignExtendedOp1) - _write_string(writer, "sign_extended_op1"); - - if (op.Flags.SignExtendedDws) - _write_string(writer, "sign_extended_dws"); - - _end_array(writer); - - _write_uint(writer, "size", op.Size); - _write_uint(writer, "raw_size", op.RawSize); - - _write_access(writer, "access", op.Access.Access); - - _start_object(writer, "decorator"); - - if (op.Decorator.HasMask) - _write_uint(writer, "mask", op.Decorator.Mask.Msk); // TODO: k0-k7 - - if (op.Decorator.HasZero) - _write_bool(writer, "zeroing", true); - - if (op.Decorator.HasBroadcast) { - _start_object(writer, "broadcast"); - - _write_uint(writer, "count", op.Decorator.Broadcast.Count); - _write_uint(writer, "size", op.Decorator.Broadcast.Size); - - _end_object(writer); - } - - if (op.Decorator.HasEr) - _write_bool(writer, "er", true); - - if (op.Decorator.HasSae) - _write_bool(writer, "sae", true); - - _end_object(writer); // "decorator" - - switch (op.Type) { - case ND_OP_NOT_PRESENT: - _write_string(writer, "type", "not_preset"); - break; - - case ND_OP_REG: - _write_string(writer, "type", "register"); - break; - - case ND_OP_MEM: - _write_string(writer, "type", "memory"); - break; - - case ND_OP_IMM: - _write_string(writer, "type", "immediate"); - break; - - case ND_OP_OFFS: - _write_string(writer, "type", "offset"); - break; - - case ND_OP_ADDR: - _write_string(writer, "type", "address"); - break; - - case ND_OP_CONST: - _write_string(writer, "type", "constant"); - break; - - case ND_OP_BANK: - _write_string(writer, "type", "bank"); - break; - - default: - _write_string(writer, "type", ""); - break; - } - - // returns without closing the object -} - - -static void _write_op_reg(Writer &writer, const ND_OPERAND &op) -{ - const auto& reg = op.Info.Register; - - _write_uint(writer, "size", reg.Size); - - _write_string(writer, "reg_type", reg_type_to_str(reg.Type)); - _write_string(writer, "reg", reg_to_str(reg.Reg, reg.Type)); - - _write_uint(writer, "reg_id", reg.Reg); - _write_uint(writer, "count", reg.Count); - - if (reg.IsHigh8) - _write_bool(writer, "is_high8", true); - - if (reg.IsBlock) - _write_bool(writer, "is_block", true); -} - - -static void _write_op_mem(Writer &writer, const ND_OPERAND &op) -{ - const auto& mem = op.Info.Memory; - - _start_array(writer, "flags"); - - if (mem.IsRipRel) - _write_string(writer, "rip_rel"); - - if (mem.IsStack) - _write_string(writer, "stack"); - - if (mem.IsString) - _write_string(writer, "string"); - - if (mem.IsShadowStack) - _write_string(writer, "shadow_stack"); - - if (mem.IsDirect) - _write_string(writer, "direct"); - - if (mem.IsBitbase) - _write_string(writer, "bitbase"); - - if (mem.IsAG) - _write_string(writer, "ag"); - - if (mem.IsMib) - _write_string(writer, "mib"); - - if (mem.HasBroadcast) - _write_string(writer, "broadcast"); - - _end_array(writer); - - if (mem.IsVsib) { - _start_object(writer, "vsib"); - - _write_uint(writer, "index_size", mem.Vsib.IndexSize); - _write_uint(writer, "elem_size", mem.Vsib.ElemSize); - _write_uint(writer, "elem_count", mem.Vsib.ElemCount); - - _end_object(writer); - } - - if (mem.HasSeg) - _write_uint(writer, "seg", mem.Seg); - - if (mem.HasBase) { - _write_uint(writer, "base_size", mem.BaseSize); - _write_uint(writer, "base", mem.Base); - } - - if (mem.HasIndex) { - _write_uint(writer, "index_size", mem.IndexSize); - _write_uint(writer, "index", mem.Index); - _write_uint(writer, "scale", mem.Scale); - } - - if (mem.HasDisp || mem.HasCompDisp) { - if (mem.HasDisp) - _write_uint(writer, "disp_size", mem.DispSize); - - if (mem.HasCompDisp) - _write_uint(writer, "comp_disp_size", mem.CompDispSize); - - _write_uint(writer, "disp", mem.Disp); - } -} - - -static void _write_operands(Writer &writer, const INSTRUX *instrux) -{ - _start_array(writer, "operands"); - - for (auto i = 0; i < instrux->OperandsCount; i++) { - const auto& op = instrux->Operands[i]; - - _start_write_default_op(writer, op); - - _start_object(writer, "info"); - - switch (op.Type) { - case ND_OP_REG: - _write_op_reg(writer, op); - break; - - case ND_OP_MEM: - _write_op_mem(writer, op); - break; - - case ND_OP_IMM: - _write_uint64(writer, "imm", op.Info.Immediate.Imm); - break; - - case ND_OP_OFFS: - _write_uint64(writer, "rel", op.Info.RelativeOffset.Rel); - break; - - case ND_OP_ADDR: - _write_uint(writer, "base_seg", op.Info.Address.BaseSeg); - _write_uint64(writer, "offset", op.Info.Address.Offset); - - break; - - case ND_OP_CONST: - _write_uint64(writer, "const", op.Info.Constant.Const); - break; - - case ND_OP_NOT_PRESENT: - case ND_OP_BANK: - break; - } - - _end_object(writer); // "info" - _end_object(writer); // the one from _start_write_default_op - } - - _end_array(writer); -} - - -static void _write_valid_modes(Writer &writer, const ND_VALID_MODES &modes) -{ - _start_array(writer, "valid_modes"); - - if (modes.Ring0) - _write_string(writer, "ring0"); - - if (modes.Ring1) - _write_string(writer, "ring1"); - - if (modes.Ring2) - _write_string(writer, "ring2"); - - if (modes.Ring3) - _write_string(writer, "ring3"); - - if (modes.Real) - _write_string(writer, "real"); - - if (modes.V8086) - _write_string(writer, "v8086"); - - if (modes.Protected) - _write_string(writer, "protected"); - - if (modes.Compat) - _write_string(writer, "compatibility"); - - if (modes.Long) - _write_string(writer, "long"); - - if (modes.Smm) - _write_string(writer, "smm"); - - if (modes.Sgx) - _write_string(writer, "sgx"); - - if (modes.Tsx) - _write_string(writer, "tsx"); - - if (modes.VmxRoot) - _write_string(writer, "vmx_root"); - - if (modes.VmxNonRoot) - _write_string(writer, "vmx_non_root"); - - if (modes.VmxOff) - _write_string(writer, "vmx_off"); - - _end_array(writer); -} - - -static void _write_valid_prefixes(Writer &writer, const ND_VALID_PREFIXES &prefixes) -{ - _start_array(writer, "valid_prefixes"); - - if (prefixes.Rep) - _write_string(writer, "rep"); - - if (prefixes.RepCond) - _write_string(writer, "rep_cond"); - - if (prefixes.Lock) - _write_string(writer, "lock"); - - if (prefixes.Hle) - _write_string(writer, "hle"); - - if (prefixes.Xacquire) - _write_string(writer, "xacquire"); - - if (prefixes.Xrelease) - _write_string(writer, "xrelease"); - - if (prefixes.Bnd) - _write_string(writer, "bnd"); - - if (prefixes.Bhint) - _write_string(writer, "bhint"); - - if (prefixes.HleNoLock) - _write_string(writer, "hle_no_lock"); - - if (prefixes.Dnt) - _write_string(writer, "dnt"); - - _end_array(writer); -} - - -static void _write_valid_decorators(Writer &writer, const ND_VALID_DECORATORS &decorators) -{ - _start_array(writer, "valid_decorators"); - - if (decorators.Er) - _write_string(writer, "er"); - - if (decorators.Sae) - _write_string(writer, "Sae"); - - if (decorators.Zero) - _write_string(writer, "Zero"); - - if (decorators.Mask) - _write_string(writer, "mask"); - - if (decorators.Broadcast) - _write_string(writer, "broadcast"); - - _end_array(writer); -} - - -static void _write_cpuid_flag(Writer &writer, const ND_CPUID_FLAG &cpuid_flag) -{ - if (0 == cpuid_flag.Flag) - return; - - _start_object(writer, "cpuid_flag"); - - _write_uint64(writer, "flag", cpuid_flag.Flag); - _write_uint(writer, "leaf", cpuid_flag.Leaf); - _write_uint(writer, "sub_leaf", static_cast(cpuid_flag.SubLeaf)); - _write_uint(writer, "reg", static_cast(cpuid_flag.Reg)); - _write_uint(writer, "bit", static_cast(cpuid_flag.Bit)); - - _end_object(writer); -} - - -static void _write_rflags(Writer &writer, const ND_RFLAGS &rflags, const char *key) -{ - _start_array(writer, key); - - if (rflags.CF) - _write_string(writer, "cf"); - - if (rflags.PF) - _write_string(writer, "pf"); - - if (rflags.AF) - _write_string(writer, "af"); - - if (rflags.ZF) - _write_string(writer, "zf"); - - if (rflags.SF) - _write_string(writer, "sf"); - - if (rflags.TF) - _write_string(writer, "tf"); - - if (rflags.IF) - _write_string(writer, "if"); - - if (rflags.DF) - _write_string(writer, "df"); - - if (rflags.OF) - _write_string(writer, "of"); - - if (rflags.IOPL) - _write_string(writer, "iopl"); - - if (rflags.NT) - _write_string(writer, "nt"); - - if (rflags.RF) - _write_string(writer, "rf"); - - if (rflags.VM) - _write_string(writer, "vm"); - - if (rflags.AC) - _write_string(writer, "ac"); - - if (rflags.VIF) - _write_string(writer, "vif"); - - if (rflags.VIP) - _write_string(writer, "vip"); - - if (rflags.ID) - _write_string(writer, "id"); - - _end_array(writer); -} - - -static void _write_flags_access(Writer &writer, INSTRUX *instrux) -{ - if (ND_ACCESS_NONE == instrux->FlagsAccess.RegAccess) - return; - - _start_object(writer, "flags_access"); - - _write_access(writer, "access", instrux->FlagsAccess.RegAccess); - - if ((instrux->FlagsAccess.RegAccess & ND_ACCESS_ANY_READ) && instrux->FlagsAccess.Tested.Raw) - _write_rflags(writer, instrux->FlagsAccess.Tested, "tested"); - - if ((instrux->FlagsAccess.RegAccess & ND_ACCESS_ANY_WRITE) && instrux->FlagsAccess.Modified.Raw) - _write_rflags(writer, instrux->FlagsAccess.Modified, "modified"); - - if (instrux->FlagsAccess.Set.Raw) - _write_rflags(writer, instrux->FlagsAccess.Set, "set"); - - if (instrux->FlagsAccess.Cleared.Raw) - _write_rflags(writer, instrux->FlagsAccess.Cleared, "cleared"); - - if (instrux->FlagsAccess.Undefined.Raw) - _write_rflags(writer, instrux->FlagsAccess.Undefined, "undefined"); - - _end_object(writer); -} - - -StringBuffer instrux_to_json(INSTRUX *instrux, size_t rip, bool text_only /* = false */) -{ - char text[ND_MIN_BUF_SIZE]; - - auto status = NdToText(instrux, rip, sizeof(text), text); - if (!ND_SUCCESS(status)) - text[0] = 0; - - auto s = StringBuffer {nullptr, 4096}; - auto writer = Writer {s, nullptr}; - - _start_object(writer); - - _write_string(writer, "text", text); - - if (text_only) { - _end_object(writer); - return s; - } - - _write_uint(writer, "def_code", _disasm_size_to_int(instrux->DefCode)); - _write_uint(writer, "def_data", _disasm_size_to_int(instrux->DefData)); - _write_uint(writer, "def_stack", _disasm_size_to_int(instrux->DefStack)); - - _write_string(writer, "enc_mode", enc_mode_to_str(instrux->EncMode)); - - _write_uint(writer, "addr_mode", _disasm_size_to_int(instrux->AddrMode)); - _write_uint(writer, "op_mode", _disasm_size_to_int(instrux->OpMode)); - _write_uint(writer, "ef_op_mode", _disasm_size_to_int(instrux->EfOpMode)); - _write_uint(writer, "vec_mode", _disasm_size_to_int(instrux->VecMode) * 8); - _write_uint(writer, "ef_vec_mnode", _disasm_size_to_int(instrux->EfVecMode) * 8); - - _write_rex(writer, instrux); - _write_modrm(writer, instrux); - _write_sib(writer, instrux); - _write_drex(writer, instrux); - _write_vex2(writer, instrux); - _write_vex3(writer, instrux); - _write_xop(writer, instrux); - _write_evex(writer, instrux); - - if (instrux->Rep) - _write_uint(writer, "rep", instrux->Rep); - - if (instrux->Seg) - _write_uint(writer, "seg", instrux->Seg); - - _write_uint(writer, "stack_words", instrux->StackWords); - - _write_exs(writer, instrux); - _write_prefixes(writer, instrux); - _write_chunks(writer, instrux); - - if (instrux->IsRepeated) - _write_bool(writer, "is_repeated", true); - - if (instrux->IsXacquireEnabled) - _write_bool(writer, "is_xacquire_enabled", true); - - if (instrux->IsXreleaseEnabled) - _write_bool(writer, "is_xrelease_enabled", true); - - if (instrux->IsRipRelative) - _write_bool(writer, "is_rip_relative", true); - - if (instrux->IsCetTracked) - _write_bool(writer, "is_cet_tracked", true); - - if (instrux->HasMandatory66) - _write_bool(writer, "mandatory_66", true); - - if (instrux->HasMandatoryF2) - _write_bool(writer, "mandatory_f2", true); - - if (instrux->HasMandatoryF3) - _write_bool(writer, "mandatory_f3", true); - - _write_uint(writer, "length", instrux->Length); - _write_uint(writer, "word_length", static_cast(instrux->WordLength)); - _write_uint(writer, "pref_length", static_cast(instrux->PrefLength)); - - _start_object(writer, "address"); - - _write_uint(writer, "ip", instrux->Address.Ip); - _write_uint(writer, "cs", instrux->Address.Cs); - - _end_object(writer); - - _write_uint(writer, "op_offset", static_cast(instrux->OpOffset)); - _write_uint(writer, "main_op_offset", static_cast(instrux->MainOpOffset)); - - if (instrux->HasAddr) { - _start_object(writer, "addr"); - - _write_uint(writer, "len", static_cast(instrux->AddrLength)); - _write_uint(writer, "offset", static_cast(instrux->AddrOffset)); - - _end_object(writer); - } - - if (instrux->HasMoffset) { - _start_object(writer, "moffset"); - - _write_uint64(writer, "value", instrux->Moffset); - _write_uint(writer, "len", static_cast(instrux->MoffsetLength)); - _write_uint(writer, "offset", static_cast(instrux->MoffsetOffset)); - - _end_object(writer); - }; - - if (instrux->HasDisp) { - _start_object(writer, "displacement"); - - _write_uint(writer, "value", instrux->Displacement); - _write_uint(writer, "len", static_cast(instrux->DispLength)); - _write_uint(writer, "offset", static_cast(instrux->DispOffset)); - - _end_object(writer); - } - - if (instrux->HasRelOffs) { - _start_object(writer, "relative_offset"); - - _write_uint(writer, "value", instrux->RelativeOffset); - _write_uint(writer, "len", static_cast(instrux->RelOffsLength)); - _write_uint(writer, "offset", static_cast(instrux->RelOffsOffset)); - - _end_object(writer); - } - - if (instrux->HasImm1) { - _start_object(writer, "immediate1"); - - _write_uint64(writer, "value", instrux->Immediate1); - _write_uint(writer, "len", static_cast(instrux->Imm1Length)); - _write_uint(writer, "offset", static_cast(instrux->Imm1Offset)); - - _end_object(writer); - } - - if (instrux->HasImm2) { - _start_object(writer, "immediate2"); - - _write_uint(writer, "value", instrux->Immediate2); - _write_uint(writer, "len", static_cast(instrux->Imm2Length)); - _write_uint(writer, "offset", static_cast(instrux->Imm2Offset)); - - _end_object(writer); - } - - if (instrux->HasImm3) { - _start_object(writer, "immediate3"); - - _write_uint(writer, "value", instrux->Immediate3); - _write_uint(writer, "len", static_cast(instrux->Imm3Length)); - _write_uint(writer, "offset", static_cast(instrux->Imm3Offset)); - - _end_object(writer); - } - - if (instrux->HasSseImm) { - _start_object(writer, "sse_immediate"); - - _write_uint(writer, "value", instrux->SseImmediate); - _write_uint(writer, "offset", static_cast(instrux->SseImmOffset)); - - _end_object(writer); - } - - _write_uint(writer, "sse_condition", instrux->SseCondition); - _write_uint(writer, "condition", instrux->Condition); - - _write_uint(writer, "operands_count", instrux->OperandsCount); - _write_uint(writer, "exp_operands_count", instrux->ExpOperandsCount); - _write_uint(writer, "operands_encoding_map", instrux->OperandsEncodingMap); - - _write_operands(writer, instrux); - - _write_access(writer, "rip_access", instrux->RipAccess); - _write_access(writer, "memory_access", instrux->MemoryAccess); - _write_access(writer, "stack_access", instrux->StackAccess); - - _write_flags_access(writer, instrux); - - _write_uint(writer, "attributes", instrux->Attributes); - - _write_string(writer, "class", ins_class_to_str(instrux->Iclass)); - _write_string(writer, "category", ins_cat_to_str(instrux->Category)); - _write_string(writer, "set", ins_set_to_str(instrux->IsaSet)); - - _write_cpuid_flag(writer, instrux->CpuidFlag); - - _write_valid_modes(writer, instrux->ValidModes); - _write_valid_prefixes(writer, instrux->ValidPrefixes); - _write_valid_decorators(writer, instrux->ValidDecorators); - - _write_string(writer, "mnemonic", instrux->Mnemonic); - - _start_array(writer, "opcode_bytes"); - - for (int i = 0; i < instrux->OpLength; i++) - _write_uint(writer, instrux->OpCodeBytes[i]); - - _end_array(writer); - - _write_uint(writer, "primary_opcode", instrux->PrimaryOpCode); - - _start_array(writer, "bytes"); - - for (int i = 0; i < instrux->Length; i++) - _write_uint(writer, instrux->InstructionBytes[i]); - - _end_array(writer); - - _end_object(writer); - - return s; -} - - -StringBuffer byte_to_json(uint8_t byte, size_t rip) -{ - auto s = StringBuffer {nullptr, 64}; - auto writer = Writer {s, nullptr}; - - _start_object(writer); - - _write_uint(writer, "byte", byte); - _write_uint(writer, "length", 1); - _write_uint64(writer, "rip", rip); - - _end_object(writer); - - return s; -} - - -const char *json_to_string(StringBuffer &j) -{ - return j.GetString(); -} - -bool regs_from_json(const std::string &str, SHEMU_GPR_REGS ®s, bool &update_rsp) -{ - Document d; - if (d.Parse(str.c_str()).IsNull()) { - return false; - } - - regs.RegRax = d["rax"].GetUint64(); - regs.RegRcx = d["rcx"].GetUint64(); - regs.RegRdx = d["rdx"].GetUint64(); - regs.RegRbx = d["rbx"].GetUint64(); - regs.RegRsp = d["rsp"].GetUint64(); - regs.RegRbp = d["rbp"].GetUint64(); - regs.RegRsi = d["rsi"].GetUint64(); - regs.RegRdi = d["rdi"].GetUint64(); - regs.RegR8 = d["r8"].GetUint64(); - regs.RegR9 = d["r9"].GetUint64(); - regs.RegR10 = d["r10"].GetUint64(); - regs.RegR11 = d["r11"].GetUint64(); - regs.RegR12 = d["r12"].GetUint64(); - regs.RegR13 = d["r13"].GetUint64(); - regs.RegR14 = d["r14"].GetUint64(); - regs.RegR15 = d["r15"].GetUint64(); - - if ((update_rsp = !d["rsp"].IsNull())) { - regs.RegRsp = d["rsp"].GetUint64(); - } - - if (!d["rip"].IsNull()) - regs.RegRip = d["rip"].GetUint64(); - - return true; -} diff --git a/inc/bddisasm.h b/inc/bddisasm.h index 492c975..e71970b 100644 --- a/inc/bddisasm.h +++ b/inc/bddisasm.h @@ -5,1666 +5,6 @@ #ifndef BDDISASM_H #define BDDISASM_H -#include "disasmtypes.h" -#include "disasmstatus.h" -#include "registers.h" -#include "constants.h" -#include "cpuidflags.h" -#include "version.h" - -#ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable: 4214) // Bitfield in type other than int. -#pragma warning(disable: 4201) // Nonstandard extension used: nameless struct/union. -#endif - -// -// Preferred vendor; the disassembler will try to be smart and disassemble as much as it can, but if there are -// encoding conflicts, than an alternate vendor can be selected. Note that this has effect only on conflicting -// encodings. -// -#define ND_VEND_ANY 0 // Generic decode, include any vendor. -#define ND_VEND_INTEL 1 // Prefer Intel. -#define ND_VEND_AMD 2 // Prefer AMD. -#define ND_VEND_GEODE 3 // Prefer Geode. -#define ND_VEND_CYRIX 4 // Prefer Cyrix. - -// -// These control what instructions should be decoded if they map onto the wide NOP space (0F 1A and 0F 1B). Those are -// tricky, because they might be NOP if the feature is disabled, but might be something else (even #UD) if the feature -// is enabled. Ergo, we allow the user to select whether said feature is on or off, so that he controls whether he -// sees the NOPs or the MPX/CET/CLDEMOTE/etc. instructions instead. -// -#define ND_FEAT_NONE 0x00 // No feature/mode enabled. -#define ND_FEAT_MPX 0x01 // MPX support enabled. -#define ND_FEAT_CET 0x02 // CET support enabled. -#define ND_FEAT_CLDEMOTE 0x04 // CLDEMOTE support enabled. -#define ND_FEAT_PITI 0x08 // PREFETCHITI support enabled. -#define ND_FEAT_ALL 0xFF // Decode as if all features are enabled. This is default. - -// -// Code type -// -#define ND_CODE_16 0 // 16 bit decode mode. -#define ND_CODE_32 1 // 32 bit decode mode. -#define ND_CODE_64 2 // 64 bit decode mode. - -// -// Data type -// -#define ND_DATA_16 0 // 16 bit data size. -#define ND_DATA_32 1 // 32 bit data size. -#define ND_DATA_64 2 // 64 bit data size. - -// -// Stack type -// -#define ND_STACK_16 0 // 16 bit stack size. -#define ND_STACK_32 1 // 32 bit stack size. -#define ND_STACK_64 2 // 64 bit stack size. - -// -// Addressing mode -// -#define ND_ADDR_16 0 // 16 bit addressing. -#define ND_ADDR_32 1 // 32 bit addressing. -#define ND_ADDR_64 2 // 64 bit addressing. - -// -// Operand mode/size -// -#define ND_OPSZ_16 0 // 16 bit operand size. -#define ND_OPSZ_32 1 // 32 bit operand size. -#define ND_OPSZ_64 2 // 64 bit operand size. - -// -// Vector mode/size -// -#define ND_VECM_128 0 // 128 bit vector size. -#define ND_VECM_256 1 // 256 bit vector size. -#define ND_VECM_512 2 // 512 bit vector size. - -// -// Encoding mode -// -#define ND_ENCM_LEGACY 0 // Legacy encoded instruction. -#define ND_ENCM_XOP 1 // XOP encoded instruction. -#define ND_ENCM_VEX 2 // VEX (bot 2B or 3B) encoded instruction. -#define ND_ENCM_EVEX 3 // EVEX encoded instruction. - -// -// VEX prefixes -// -#define ND_VEXM_2B 0 // 2B VEX prefix (0xC5). -#define ND_VEXM_3B 1 // 3B VEX prefix (0xC4). - - -// -// Size definitions -// -#define ND_SIZE_8BIT 1 // 1 byte. -#define ND_SIZE_16BIT 2 // 1 word or 2 bytes. -#define ND_SIZE_32BIT 4 // 1 double word or 4 bytes. -#define ND_SIZE_48BIT 6 // 1 fword or 6 bytes. -#define ND_SIZE_64BIT 8 // 1 qword or 8 bytes. -#define ND_SIZE_80BIT 10 // 1 fpu word or 10 bytes. -#define ND_SIZE_112BIT 14 // FPU environment, 14 bytes. -#define ND_SIZE_128BIT 16 // 1 xmm word or 16 bytes. -#define ND_SIZE_224BIT 28 // FPU environment, 28 bytes. -#define ND_SIZE_256BIT 32 // 1 ymm word or 32 bytes. -#define ND_SIZE_384BIT 48 // 48 bytes, used for Key Locker handles. -#define ND_SIZE_512BIT 64 // 1 zmm word or 64 bytes. Used also for Key Locker handles. -#define ND_SIZE_752BIT 94 // FPU state, 94 bytes. -#define ND_SIZE_864BIT 108 // FPU state, 108 bytes. -#define ND_SIZE_4096BIT 512 // Extended state, 512 bytes. -#define ND_SIZE_1KB 1024 // Tile register, 1KB. -#define ND_SIZE_CACHE_LINE 0xFFFFFFFE // The size of a cache line. -#define ND_SIZE_UNKNOWN 0xFFFFFFFF // Unknown/invalid size. - - -typedef ND_UINT32 ND_OPERAND_SIZE; - -typedef ND_UINT32 ND_REG_SIZE; - - -// -// Prefix definitions -// -#define ND_PREFIX_G0_LOCK 0xF0 // LOCK prefix. -#define ND_PREFIX_G1_REPNE_REPNZ 0xF2 // REPNE/REPNZ prefix. -#define ND_PREFIX_G1_XACQUIRE 0xF2 // XACQUIRE prefix. -#define ND_PREFIX_G1_REPE_REPZ 0xF3 // REPE/REPZ prefix. -#define ND_PREFIX_G1_XRELEASE 0xF3 // XRELEASE prefix. -#define ND_PREFIX_G1_BND 0xF2 // BND prefix. -#define ND_PREFIX_G2_SEG_CS 0x2E // CS segment override. -#define ND_PREFIX_G2_SEG_SS 0x36 // SS segment override. -#define ND_PREFIX_G2_SEG_DS 0x3E // DS segment override. -#define ND_PREFIX_G2_SEG_ES 0x26 // ES segment override. -#define ND_PREFIX_G2_SEG_FS 0x64 // FS segment override. -#define ND_PREFIX_G2_SEG_GS 0x65 // GS segment override. -#define ND_PREFIX_G2_BR_NOT_TAKEN 0x2E // Branch not taken hint. -#define ND_PREFIX_G2_BR_TAKEN 0x3E // Branch taken hint. -#define ND_PREFIX_G2_BR_ALT 0x64 // Alternating branch hint. -#define ND_PREFIX_G2_NO_TRACK 0x3E // Do not track prefix. -#define ND_PREFIX_G3_OPERAND_SIZE 0x66 // Operand size override. -#define ND_PREFIX_G4_ADDR_SIZE 0x67 // Address size override. - -#define ND_PREFIX_REX_MIN 0x40 // First REX prefix. -#define ND_PREFIX_REX_MAX 0x4F // Last REX prefix. -#define ND_PREFIX_VEX_2B 0xC5 // 2B VEX prefix. -#define ND_PREFIX_VEX_3B 0xC4 // 3B VEX prefix. -#define ND_PREFIX_XOP 0x8F // XOP prefix. -#define ND_PREFIX_EVEX 0x62 // EVEX prefix. - - -// -// Instruction flags -// -#define ND_FLAG_MODRM 0x00000001 // The instruction has modrm. -#define ND_FLAG_F64 0x00000002 // The operand is forced to 64 bit. Size changing prefix 0x66 is ignored. -#define ND_FLAG_D64 0x00000004 // The default operand size is 64 bit. Size changing prefix 0x66 - // changes the size to 16 bit. No 32 bit version can be encoded. -#define ND_FLAG_O64 0x00000008 // The instruction is available only in 64 bit mode. -#define ND_FLAG_I64 0x00000010 // The instruction is invalid in 64 bit mode. -#define ND_FLAG_COND 0x00000020 // The instruction has a condition code encoded in low 4 bits of the opcode. -#define ND_FLAG_SSE_CONDB 0x00000040 // The instruction has a SSE condition byte. -#define ND_FLAG_VSIB 0x00000080 // The instruction uses VSIB addressing mode. -#define ND_FLAG_MIB 0x00000100 // The instruction used MIB addressing mode. -#define ND_FLAG_LIG 0x00000200 // L flag inside XOP/VEX/EVEX is ignored. -#define ND_FLAG_WIG 0x00000400 // W flag inside XOP/VEX/EVEX is ignored. -#define ND_FLAG_3DNOW 0x00000800 // The instruction is 3DNow!. The opcode is the last byte. -#define ND_FLAG_LOCK_SPECIAL 0x00001000 // MOV to/from CR in 16/32 bit, on AMD, extend the access to - // high 8 CRs via the LOCK prefix. -#define ND_FLAG_MMASK 0x00002000 // Mandatory mask. The instruction does not accept k0 as mask. -#define ND_FLAG_NOMZ 0x00004000 // Zeroing is not permitted when accessing memory. -#define ND_FLAG_NOL0 0x00008000 // SSE 128 encoding is not permitted for the instruction. -#define ND_FLAG_NOA16 0x00010000 // The instruction does not support 16 bit addressing. -#define ND_FLAG_MFR 0x00020000 // The Mod inside Mod R/M is forced to reg. No SIB/disp present. -#define ND_FLAG_VECTOR 0x00040000 // The instruction is a SIMD instruction that operates on vector regs. -#define ND_FLAG_S66 0x00080000 // Special flag for mandatory 0x66 prefix that actually changes - // the default op length. -#define ND_FLAG_BITBASE 0x00100000 // The instruction uses bitbase addressing mode. -#define ND_FLAG_AG 0x00200000 // The instruction is an address generator; no actual memory access. -#define ND_FLAG_SHS 0x00400000 // The instruction does a shadow stack access. -#define ND_FLAG_CETT 0x00800000 // The instruction is CET tracked. -#define ND_FLAG_SERIAL 0x01000000 // The instruction is serializing. -#define ND_FLAG_NO_RIP_REL 0x02000000 // The instruction doesn't work with RIP relative addressing. -#define ND_FLAG_NO66 0x04000000 // The 0x66 prefix is not accepted by the instruction. -#define ND_FLAG_SIBMEM 0x08000000 // sibmem addressing is used (Intel AMX instructions). -#define ND_FLAG_I67 0x10000000 // Ignore the 0x67 prefix in 64 bit mode (Intel MPX instructions). -#define ND_FLAG_IER 0x20000000 // Ignore EVEX embedded rounding. -#define ND_FLAG_IWO64 0x40000000 // Ignore VEX/EVEX.W outside 64 bit mode. It behaves as if it's 0. - - -// -// Accepted prefixes map -// -#define ND_PREF_REP 0x0001 // The instruction supports REP prefix. -#define ND_PREF_REPC 0x0002 // The instruction supports REPZ/REPNZ prefixes. -#define ND_PREF_LOCK 0x0004 // The instruction supports LOCK prefix. -#define ND_PREF_HLE 0x0008 // The instruction supports XACQUIRE/XRELEASE prefixes. -#define ND_PREF_XACQUIRE 0x0010 // The instruction supports only XACQUIRE. -#define ND_PREF_XRELEASE 0x0020 // The instruction supports only XRELEASE. -#define ND_PREF_BND 0x0040 // The instruction supports BND prefix. -#define ND_PREF_BHINT 0x0080 // The instruction supports branch hints. -#define ND_PREF_HLE_WO_LOCK 0x0100 // HLE prefix is accepted without LOCK. -#define ND_PREF_DNT 0x0200 // The instruction supports the DNT (Do Not Track) CET prefix. - - -// -// Accepted decorators map. These are stored per-instruction. There are also per-operand indicators for -// each decorator. -// -#define ND_DECO_ER 0x01 // Embedded rounding is accepted. -#define ND_DECO_SAE 0x02 // Suppress all Exceptions is accepted. -#define ND_DECO_ZERO 0x04 // Zeroing is accepted. -#define ND_DECO_MASK 0x08 // Masking is accepted. -#define ND_DECO_BROADCAST 0x10 // Memory broadcast is accepted. - - -// -// Operand access flags. -// -#define ND_ACCESS_NONE 0x00 // The operand is not accessed. -#define ND_ACCESS_READ 0x01 // The operand is read. -#define ND_ACCESS_WRITE 0x02 // The operand is written. -#define ND_ACCESS_COND_READ 0x04 // The operand is read only if some conditions are met. -#define ND_ACCESS_COND_WRITE 0x08 // The operand is written only if some conditions are met (ie: CMOVcc). -#define ND_ACCESS_ANY_READ (ND_ACCESS_READ | ND_ACCESS_COND_READ) // Any read mask. -#define ND_ACCESS_ANY_WRITE (ND_ACCESS_WRITE | ND_ACCESS_COND_WRITE) // Any write mask. -#define ND_ACCESS_PREFETCH 0x10 // The operand is prefetched. - - -// -// Predicate/condition definitions. -// -#define ND_COND_OVERFLOW 0x0 // OF -#define ND_COND_CARRY 0x2 // CF -#define ND_COND_BELOW 0x2 // CF -#define ND_COND_NOT_ABOVE_OR_EQUAL 0x2 // CF -#define ND_COND_ZERO 0x4 // ZF -#define ND_COND_EQUAL 0x4 // ZF -#define ND_COND_BELOW_OR_EQUAL 0x6 // CF | ZF -#define ND_COND_NOT_ABOVE 0x6 // CF | ZF -#define ND_COND_SIGN 0x8 // SF -#define ND_COND_PARITY 0xA // PF -#define ND_COND_LESS 0xC // SF ^ OF -#define ND_COND_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF -#define ND_COND_NOT(p) ((p) | 0x1) // Negates the predicate. - -// Kept for backwards compatibility - renamed to ND_COND*. -#define ND_PRED_OVERFLOW 0x0 // OF -#define ND_PRED_CARRY 0x2 // CF -#define ND_PRED_BELOW 0x2 // CF -#define ND_PRED_NOT_ABOVE_OR_EQUAL 0x2 // CF -#define ND_PRED_ZERO 0x4 // ZF -#define ND_PRED_EQUAL 0x4 // ZF -#define ND_PRED_BELOW_OR_EQUAL 0x6 // CF | ZF -#define ND_PRED_NOT_ABOVE 0x6 // CF | ZF -#define ND_PRED_SIGN 0x8 // SF -#define ND_PRED_PARITY 0xA // PF -#define ND_PRED_LESS 0xC // SF ^ OF -#define ND_PRED_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF -#define ND_PRED_NOT(p) ((p) | 0x1) // Negates the predicate. - - -// -// Condition code definitions. These apply to condition codes encoded in instruction bytes as used by some SSE/AVX -// instructions. -// -#define ND_SSE_COND_EQ 0x00 // Equal. -#define ND_SSE_COND_LT 0x01 // Less-than. -#define ND_SSE_COND_LE 0x02 // Less-than or equal. -#define ND_SSE_COND_UNORD 0x03 // Unordered. -#define ND_SSE_COND_FALSE1 0x03 // False. -#define ND_SSE_COND_NEQ 0x04 // Not equal. -#define ND_SSE_COND_NLT 0x05 // Not less-than. -#define ND_SSE_COND_NLE 0x06 // Not less-than or equal. -#define ND_SSE_COND_ORD 0x07 // Ordered. -#define ND_SSE_COND_TRUE1 0x07 // True. -#define ND_SSE_COND_EQ_UQ 0x08 // Equal. -#define ND_SSE_COND_NGE 0x09 // Not greater-than or equal. -#define ND_SSE_COND_NGT 0x0A // Not greater-than. -#define ND_SSE_COND_FALSE 0x0B // False. -#define ND_SSE_COND_NEQ_OQ 0x0C // Not equal. -#define ND_SSE_COND_GE 0x0D // Greater-than or equal. -#define ND_SSE_COND_GT 0x0E // Greater-than. -#define ND_SSE_COND_TRUE 0x0F // True. -#define ND_SSE_COND_EQ_OS 0x10 // Equal. -#define ND_SSE_COND_LT_OQ 0x11 // Less-than. -#define ND_SSE_COND_LE_OQ 0x12 // Less-than or equal. -#define ND_SSE_COND_UNORD_S 0x13 // Unordered. -#define ND_SSE_COND_NEQ_US 0x14 // Not equal. -#define ND_SSE_COND_NLT_UQ 0x15 // Not less-than. -#define ND_SSE_COND_NLE_UQ 0x16 // Not less-than or equal. -#define ND_SSE_COND_ORD_S 0x17 // Ordered. -#define ND_SSE_COND_EQ_US 0x18 // Equal. -#define ND_SSE_COND_NGE_UQ 0x19 // Not greater-than or equal. -#define ND_SSE_COND_NGT_UQ 0x1A // Not greater-than. -#define ND_SSE_COND_FALSE_OS 0x1B // False. -#define ND_SSE_COND_NEQ_OS 0x1C // Not equal. -#define ND_SSE_COND_GE_OQ 0x1D // Greater-than or equal. -#define ND_SSE_COND_GT_OQ 0x1E // Greater-than. -#define ND_SSE_COND_TRUE_US 0x1F // True. - - -// -// Valid CPU modes. -// -// Group 1: ring -#define ND_MOD_R0 0x00000001 // Instruction valid in ring 0. -#define ND_MOD_R1 0x00000002 // Instruction valid in ring 1. -#define ND_MOD_R2 0x00000004 // Instruction valid in ring 2. -#define ND_MOD_R3 0x00000008 // Instruction valid in ring 3. - -// Group 2: operating mode. -#define ND_MOD_REAL 0x00000010 // Instruction valid in real mode. -#define ND_MOD_V8086 0x00000020 // Instruction valid in virtual 8086 mode. -#define ND_MOD_PROT 0x00000040 // Instruction valid in protected mode. -#define ND_MOD_COMPAT 0x00000080 // Instruction valid in compatibility mode. -#define ND_MOD_LONG 0x00000100 // Instruction valid in long mode. - -// Group 3: misc modes. -#define ND_MOD_SMM 0x00001000 // Instruction valid in System-Management Mode. -#define ND_MOD_SMM_OFF 0x00002000 // Instruction valid outside SMM. -#define ND_MOD_SGX 0x00004000 // Instruction valid in SGX enclaves. -#define ND_MOD_SGX_OFF 0x00008000 // Instruction valid outside SGX enclaves. -#define ND_MOD_TSX 0x00010000 // Instruction valid in TSX transactional regions. -#define ND_MOD_TSX_OFF 0x00020000 // Instruction valid outside TSX. - - -// Group 4: VMX -#define ND_MOD_VMXR 0x00040000 // Instruction valid in VMX Root mode. -#define ND_MOD_VMXN 0x00080000 // Instruction valid in VMX non-root mode. -#define ND_MOD_VMXR_SEAM 0x00100000 // Instruction valid in VMX root Secure Arbitration Mode. -#define ND_MOD_VMXN_SEAM 0x00200000 // Instruction valid in VMX non-root Secure Arbitration Mode. -#define ND_MOD_VMX_OFF 0x00400000 // Instruction valid outside VMX operation. - -#define ND_MOD_RING_MASK 0x0000000F // Valid ring mask. -#define ND_MOD_MODE_MASK 0x000001F0 // Valid mode mask. -#define ND_MOD_OTHER_MASK 0x0003F000 // Misc mask. -#define ND_MOD_VMX_MASK 0x007C0000 // VMX mask. - -// For instructions valid in any operating mode. -#define ND_MOD_ANY 0xFFFFFFFF // Instruction valid in any mode. - - -// -// Misc constants -// -#define ND_MAX_INSTRUCTION_LENGTH 15 // 15 bytes is the maximum instruction length supported by the x86 arch. -#define ND_MAX_MNEMONIC_LENGTH 32 // Should do for now. -#define ND_MIN_BUF_SIZE 128 // Textual disassembly minimal buffer size. -#define ND_MAX_OPERAND 10 // No more than 10 operands/instruction, but I'm generous. -#define ND_MAX_REGISTER_SIZE 64 // Maximum register size - 64 bytes. - -#define ND_MAX_GPR_REGS 16 // Max number of GPRs. -#define ND_MAX_SEG_REGS 8 // Max number of segment registers. -#define ND_MAX_FPU_REGS 8 // Max number of FPU registers. -#define ND_MAX_MMX_REGS 8 // Max number of MMX registers. -#define ND_MAX_SSE_REGS 32 // Max number of SSE registers. -#define ND_MAX_CR_REGS 16 // Max number of control registers. -#define ND_MAX_DR_REGS 16 // Max number of debug registers. -#define ND_MAX_TR_REGS 16 // Max number of test registers. -#define ND_MAX_MSK_REGS 8 // Max number of mask registers. -#define ND_MAX_BND_REGS 4 // Max number of bound registers. -#define ND_MAX_SYS_REGS 8 // Max number of system registers. -#define ND_MAX_X87_REGS 8 // Max number of x87 state/control registers registers. -#define ND_MAX_TILE_REGS 8 // Max number of tile registers. - - - -// -// Misc macros. -// - -// Sign extend 8 bit to 64 bit. -#define ND_SIGN_EX_8(x) (((x) & 0x00000080) ? (0xFFFFFFFFFFFFFF00 | (x)) : ((x) & 0xFF)) -// Sign extend 16 bit to 64 bit. -#define ND_SIGN_EX_16(x) (((x) & 0x00008000) ? (0xFFFFFFFFFFFF0000 | (x)) : ((x) & 0xFFFF)) -// Sign extend 32 bit to 64 bit. -#define ND_SIGN_EX_32(x) (((x) & 0x80000000) ? (0xFFFFFFFF00000000 | (x)) : ((x) & 0xFFFFFFFF)) -// Wrapper for for ND_SIGN_EX_8/ND_SIGN_EX_16/ND_SIGN_EX_32. Sign extend sz bytes to 64 bits. -#define ND_SIGN_EX(sz, x) ((sz) == 1 ? ND_SIGN_EX_8(x) : (sz) == 2 ? ND_SIGN_EX_16(x) : \ - (sz) == 4 ? ND_SIGN_EX_32(x) : (x)) -// Trim 64 bits to sz bytes. -#define ND_TRIM(sz, x) ((sz) == 1 ? (x) & 0xFF : (sz) == 2 ? (x) & 0xFFFF : \ - (sz) == 4 ? (x) & 0xFFFFFFFF : (x)) -// Returns most significant bit, given size in bytes sz. -#define ND_MSB(sz, x) ((sz) == 1 ? ((x) >> 7) & 1 : (sz) == 2 ? ((x) >> 15) & 1 : \ - (sz) == 4 ? ((x) >> 31) & 1 : ((x) >> 63) & 1) -// Returns least significant bit. -#define ND_LSB(sz, x) ((x) & 1) -// Convert a size in bytes to a bitmask. -#define ND_SIZE_TO_MASK(sz) (((sz) < 8) ? ((1ULL << ((sz) * 8)) - 1) : (0xFFFFFFFFFFFFFFFF)) -// Get bit at position bit from x. -#define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1) -// Return the sign of sz bytes long value x. -#define ND_GET_SIGN(sz, x) ND_MSB(sz, x) -// Sets the sign of the sz bytes long value x. -#define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x) - -#ifdef BIG_ENDIAN -#define ND_FETCH_64(b) ((ND_UINT64)ND_FETCH_32((char *)b) | ((ND_UINT64)ND_FETCH_32((char *)b + 4) << 32)) -#define ND_FETCH_32(b) ((ND_UINT32)ND_FETCH_16((char *)b) | ((ND_UINT32)ND_FETCH_16((char *)b + 2) << 16)) -#define ND_FETCH_16(b) ((((char *)b)[0]) | (((char *)b)[1] << 8)) -#define ND_FETCH_8(b) (*((char *)b)) -#else -#define ND_FETCH_64(b) (*((ND_UINT64 *)(b))) -#define ND_FETCH_32(b) (*((ND_UINT32 *)(b))) -#define ND_FETCH_16(b) (*((ND_UINT16 *)(b))) -#define ND_FETCH_8(b) (*((ND_UINT8 *)(b))) -#endif - - -// -// Helper macros which simply test the presence of various ND_FLAG_* in the instruction attributes. -// -#define ND_IS_3DNOW(ix) (!!((ix)->Attributes & ND_FLAG_3DNOW)) -#define ND_HAS_PREDICATE(ix) (!!((ix)->Attributes & ND_FLAG_COND)) -#define ND_HAS_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_COND)) -#define ND_HAS_SSE_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_SSE_CONDB)) -#define ND_HAS_MODRM(ix) (!!((ix)->Attributes & ND_FLAG_MODRM)) -#define ND_HAS_VSIB(ix) (!!((ix)->Attributes & ND_FLAG_VSIB)) -#define ND_HAS_MIB(ix) (!!((ix)->Attributes & ND_FLAG_MIB)) -#define ND_HAS_VECTOR(ix) (!!((ix)->Attributes & ND_FLAG_VECTOR)) -#define ND_HAS_BITBASE(ix) (!!((ix)->Attributes & ND_FLAG_BITBASE)) -#define ND_HAS_AG(ix) (!!((ix)->Attributes & ND_FLAG_AG)) -#define ND_HAS_SIBMEM(ix) (!!((ix)->Attributes & ND_FLAG_SIBMEM)) -#define ND_HAS_SHS(ix) (!!((ix)->Attributes & ND_FLAG_SHS)) -#define ND_HAS_CETT(ix) (!!((ix)->Attributes & ND_FLAG_CETT)) - -// -// Supported prefixes macros. -// -#define ND_REP_SUPPORT(ix) (!!((ix)->ValidPrefixes.Rep)) -#define ND_REPC_SUPPORT(ix) (!!((ix)->ValidPrefixes.RepCond)) -#define ND_LOCK_SUPPORT(ix) (!!((ix)->ValidPrefixes.Lock)) -#define ND_HLE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Hle)) -#define ND_XACQUIRE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xacquire)) -#define ND_XRELEASE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xrelease)) -#define ND_BND_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bnd)) -#define ND_BHINT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bhint)) -#define ND_DNT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Dnt)) - -// -// Decorators map macros. -// -#define ND_DECORATOR_SUPPORT(ix) ((ix)->ValidDecorators.Raw != 0) -#define ND_MASK_SUPPORT(ix) (!!((ix)->ValidDecorators.Mask)) -#define ND_ZERO_SUPPORT(ix) (!!((ix)->ValidDecorators.Zero)) -#define ND_ER_SUPPORT(ix) (!!((ix)->ValidDecorators.Er)) -#define ND_SAE_SUPPORT(ix) (!!((ix)->ValidDecorators.Sae)) -#define ND_BROADCAST_SUPPORT(ix) (!!((ix)->ValidDecorators.Broadcast)) - -// Generates a unique ID per register type, size and reg. The layout is the following: -// - bits [63, 60] (4 bits) - the operand type (ND_OP_REG) -// - bits [59, 52] (8 bits) - the register type -// - bits [51, 36] (16 bits) - the register size, in bytes -// - bits [35, 30] (6 bits) - the number of registers accessed starting with this reg (for block addressing) -// - bits [29, 9] (21 bits) - reserved -// - bit 8 - High8 indicator: indicates whether the reg is AH/CH/DH/BH -// - bits [7, 0] (8 bits) - the register ID -#define ND_OP_REG_ID(op) (((ND_UINT64)((op)->Type & 0xF) << 60) | \ - ((ND_UINT64)((op)->Info.Register.Type & 0xFF) << 52) | \ - ((ND_UINT64)((op)->Info.Register.Size & 0xFFFF) << 36) | \ - ((ND_UINT64)((op)->Info.Register.Count & 0x3F) << 30) | \ - ((ND_UINT64)((op)->Info.Register.IsHigh8 & 0x1) << 8) | \ - ((ND_UINT64)((op)->Info.Register.Reg))) - -// Example: ND_IS_OP_REG(op, ND_REG_GPR, 4, REG_ESP) -// Example: ND_IS_OP_REG(op, ND_REG_CR, 8, REG_CR3) -// Example: ND_IS_OP_REG(op, ND_REG_RIP, 8, 0) - -// Checks if the indicated operand op is a register of type t, with size s and index r. -#define ND_IS_OP_REG(op, t, s, r) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \ - ((ND_UINT64)((t) & 0xFF) << 52) | \ - ((ND_UINT64)((s) & 0xFFFF) << 36) | \ - ((ND_UINT64)(1) << 30) | \ - ((ND_UINT64)(r)))) - -// Checks if the indicated operand op is a register of type t, with size s and index r. -#define ND_IS_OP_REG_EX(op, t, s, r, b, h) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \ - ((ND_UINT64)((t) & 0xFF) << 52) | \ - ((ND_UINT64)((s) & 0xFFFF) << 36) | \ - ((ND_UINT64)((b) & 0x3F) << 30) | \ - ((ND_UINT64)((h) & 0x1) << 8) | \ - ((ND_UINT64)(r)))) - -// Checjs if the indicated operand is the stack. -#define ND_IS_OP_STACK(op) ((op)->Type == ND_OP_MEM && (op)->Info.Memory.IsStack) - - -// -// Operand types. -// -typedef enum _ND_OPERAND_TYPE -{ - ND_OP_NOT_PRESENT, // Indicates the absence of any operand. - ND_OP_REG, // The operand is a register. - ND_OP_MEM, // The operand is located in memory. - ND_OP_IMM, // The operand is an immediate. - ND_OP_OFFS, // The operand is a relative offset. - ND_OP_ADDR, // The operand is an absolute address, in the form seg:offset. - ND_OP_CONST, // The operand is an implicit constant. - ND_OP_BANK, // An entire bank/set of registers are being accessed. Used in PUSHA/POPA/XSAVE/LOADALL. -} ND_OPERAND_TYPE; - - -// -// Register types. -// -typedef enum _ND_REG_TYPE -{ - ND_REG_NOT_PRESENT, - ND_REG_GPR, // The register is a 8/16/32/64 bit general purpose register. - ND_REG_SEG, // The register is a segment register. - ND_REG_FPU, // The register is a 80-bit FPU register. - ND_REG_MMX, // The register is a 64-bit MMX register. - ND_REG_SSE, // The register is a 128/256/512 bit SSE vector register. - ND_REG_CR, // The register is a control register. - ND_REG_DR, // The register is a debug register. - ND_REG_TR, // The register is a test register. - ND_REG_BND, // The register is a bound register. - ND_REG_MSK, // The register is a mask register. - ND_REG_TILE, // The register is a tile register. - ND_REG_MSR, // The register is a model specific register. - ND_REG_XCR, // The register is a extended control register. - ND_REG_SYS, // The register is a system register. - ND_REG_X87, // The register is a x87 status/control register. - ND_REG_MXCSR, // The register is the MXCSR register. - ND_REG_PKRU, // The register is the PKRU register. - ND_REG_SSP, // The register is the SSP (Shadow Stack Pointer) register. - ND_REG_FLG, // The register is the FLAGS register. - ND_REG_RIP, // The register is the instruction pointer register. - ND_REG_UIF, // The register is the User Interrupt Flag. -} ND_REG_TYPE; - - -// -// Operand encoding types. -// -typedef enum _ND_OPERAND_ENCODING -{ - ND_OPE_NP, // No encoding present. - ND_OPE_R, // Operand encoded in modrm.reg. - ND_OPE_M, // Operand encoded in modrm.rm. - ND_OPE_V, // Operand encoded in Xop/Vex/Evex/Mvex.(v')vvvv - ND_OPE_D, // Operand is encoded inside subsequent instruction bytes. - ND_OPE_O, // Operand is encoded in low 3 bit of the opcode. - ND_OPE_I, // Operand is an immediate. - ND_OPE_C, // Operand is CL. - ND_OPE_1, // Operand is 1. - ND_OPE_L, // Operand is reg encoded in immediate. - ND_OPE_A, // Operand is encoded in Evex.aaa. - ND_OPE_E, // Operand is a MSR or XCR encoded in ECX register. - ND_OPE_S, // Operand is implicit/suppressed. Not encoded anywhere. -} ND_OPERAND_ENCODING; - - -// -// Instruction tuple type; used to determine compressed displacement size for disp8 EVEX instructions. Note that -// most of the EVEX encoded instructions use the compressed displacement addressing scheme. -// -typedef enum _ND_TUPLE -{ - ND_TUPLE_None, - ND_TUPLE_FV, // Full Vector - ND_TUPLE_HV, // Half Vector - ND_TUPLE_QV, // Quarter Vector - ND_TUPLE_T1S8, // Tuple1 scalar, size 8 bit - ND_TUPLE_T1S16, // Tuple1 scalar, size 16 bit - ND_TUPLE_T1S, // Tuple1 scalar, size 32/64 bit - ND_TUPLE_T1F, // Tuple1 float, size 32/64 bit - ND_TUPLE_T2, // Tuple2, 64/128 bit - ND_TUPLE_T4, // Tuple4, 128/256 bit - ND_TUPLE_T8, // Tuple8, 256 bit - ND_TUPLE_FVM, // Full Vector Memory - ND_TUPLE_HVM, // Half Vector Memory - ND_TUPLE_QVM, // Quarter Vector Memory - ND_TUPLE_OVM, // Oct Vector Memory - ND_TUPLE_M128, // M128, 128 bit - ND_TUPLE_DUP, // DUP (VMOVDDUP) - ND_TUPLE_T1_4X, // 4 x 32 bit Memory Elements are referenced -} ND_TUPLE; - - -// -// EVEX rounding control. -// -typedef enum _ND_ROUNDING -{ - ND_RND_RNE, // Round to nearest equal. - ND_RND_RD, // Round down. - ND_RND_RU, // Round up. - ND_RND_RZ, // round to zero. -} ND_ROUNDING; - - -// -// Exception classes. Different instruction sets or encodings are covered by different exception classes. -// -typedef enum _ND_EX_CLASS -{ - ND_EXC_None, - ND_EXC_SSE_AVX, // SSE/AVX exception class (for legacy encoded SSE instructions and VEX instructions). - ND_EXC_EVEX, // EVEX exception class (for EVEX encoded AVX* instructions). - ND_EXC_OPMASK, // Opmask instructions exception class. - ND_EXC_AMX, // AMX exception class type (for VEX encoded AMX instructions). -} ND_EX_CLASS; - - -// -// SSE/AVX exception types. Covers VEX instructions as well, except for AMX instructions. -// -typedef enum _ND_EX_TYPE_SSE_AVX -{ - ND_EXT_SSE_AVX_None, - ND_EXT_1, - ND_EXT_2, - ND_EXT_3, - ND_EXT_4, - ND_EXT_5, - ND_EXT_6, - ND_EXT_7, - ND_EXT_8, - ND_EXT_9, - ND_EXT_10, - ND_EXT_11, - ND_EXT_12, - ND_EXT_13, - ND_EXT_14, -} ND_EX_TYPE_SSE_AVX; - - -// -// EVEX exception types. -// -typedef enum _ND_EX_TYPE_EVEX -{ - ND_EXT_EVEX_None, - ND_EXT_E1, - ND_EXT_E1NF, - ND_EXT_E2, - ND_EXT_E3, - ND_EXT_E3NF, - ND_EXT_E4, - ND_EXT_E4S, // E4, with an additional case: if (dst == src1) or (dst == src2) - ND_EXT_E4nb, - ND_EXT_E4NF, - ND_EXT_E4NFnb, - ND_EXT_E5, - ND_EXT_E5NF, - ND_EXT_E6, - ND_EXT_E6NF, - ND_EXT_E7NM, - ND_EXT_E9, - ND_EXT_E9NF, - ND_EXT_E10, - ND_EXT_E10S, // E10, with an additional case: if (dst == src1) or (dst == src2) - ND_EXT_E10NF, - ND_EXT_E11, - ND_EXT_E12, - ND_EXT_E12NP, -} ND_EX_TYPE_EVEX; - - -// -// Opmask exception types. -// -typedef enum _ND_EX_TYPE_OPMASK -{ - ND_EXT_OPMASK_None, - ND_EXT_K20, - ND_EXT_K21, -} ND_EX_TYPE_OPMASK; - - -// -// AMX exception types. -// -typedef enum _ND_EX_TYPE_AMX -{ - ND_EXT_AMX_None, - ND_EXT_AMX_E1, - ND_EXT_AMX_E2, - ND_EXT_AMX_E3, - ND_EXT_AMX_E4, - ND_EXT_AMX_E5, - ND_EXT_AMX_E6, -} ND_EX_TYPE_AMX; - - -// -// Operand access mode. -// -typedef union _ND_OPERAND_ACCESS -{ - ND_UINT8 Access; - struct - { - ND_UINT8 Read : 1; // The operand is read. - ND_UINT8 Write : 1; // The operand is written. - ND_UINT8 CondRead : 1; // The operand is read only under some conditions. - ND_UINT8 CondWrite : 1; // The operand is written only under some conditions. - ND_UINT8 Prefetch : 1; // The operand is prefetched. - }; -} ND_OPERAND_ACCESS; - - -// -// Operand flags. -// -typedef union _ND_OPERAND_FLAGS -{ - ND_UINT8 Flags; - struct - { - ND_UINT8 IsDefault : 1; // 1 if the operand is default. This also applies to implicit ops. - ND_UINT8 SignExtendedOp1 : 1; // 1 if the operand is sign extended to the first operands' size. - ND_UINT8 SignExtendedDws : 1; // 1 if the operand is sign extended to the default word size. - }; -} ND_OPERAND_FLAGS; - - -// -// Constant operand. -// -typedef struct _ND_OPDESC_CONSTANT -{ - ND_UINT64 Const; // Instruction constant, ie ROL reg, 1. -} ND_OPDESC_CONSTANT; - - -// -// Immediate operand. -// -typedef struct _ND_OPDESC_IMMEDIATE -{ - ND_UINT64 Imm; // Immediate. Only Size bytes are valid. The rest are undefined. -} ND_OPDESC_IMMEDIATE; - - -// -// Relative offset operand. -// -typedef struct _ND_OPDESC_REL_OFFSET -{ - ND_UINT64 Rel; // Relative offset (relative to the current RIP). Sign extended. -} ND_OPDESC_RELOFFSET; - - -// -// Describes a register operand. Count registers are used starting with Reg. -// -typedef struct _ND_OPDESC_REGISTER -{ - ND_REG_TYPE Type; // The register type. See enum ND_REG_TYPE. - ND_REG_SIZE Size; // Indicates the register size. This may not be equal to the Size - // field, as a smaller amount of data may be processed from a - // register (especially if we have a SSE register or a mask register). - // Also note that as of now, 64 bytes is the maximum register size. - ND_UINT32 Reg; // The register number/ID. - ND_UINT32 Count; // The number of registers accessed, starting with Reg. - - ND_BOOL IsHigh8:1; // TRUE if this is AH, CH, DH or BH register. - ND_BOOL IsBlock:1; // TRUE if this is a block register addressing. -} ND_OPDESC_REGISTER; - - -// -// Describes an address operand. -// -typedef struct _ND_OPDESC_ADDRESS -{ - // Size is the size of the address. Usually 4 (16 bit mode) or 6 (32 bit mode) or 10 (64 bit). - ND_UINT16 BaseSeg; // Base segment selector of the address. - ND_UINT64 Offset; // Offset inside the segment. -} ND_OPDESC_ADDRESS; - - -// -// Shadow stack access types. -// -typedef enum _ND_SHSTK_ACCESS -{ - ND_SHSTK_NONE = 0, - ND_SHSTK_EXPLICIT, // Explicit memory operand accessed as shadow stack. - ND_SHSTK_SSP_LD_ST, // Shadow Stack Pointer (SSP) used as base for addressing using conventional load/store. - ND_SHSTK_SSP_PUSH_POP, // Shadow Stack Pointer (SSP) used as base for addressing using push/pop. - ND_SHSTK_PL0_SSP, // Privilege 0 SSP (IA32_PL0_SSP) used (SETSSBSY). -} ND_SHSTK_ACCESS; - - -// -// Describes a memory operand. -// -typedef struct _ND_OPDESC_MEMORY -{ - ND_BOOL HasSeg:1; // TRUE if segment is present & used. - ND_BOOL HasBase:1; // TRUE if base register is present. - ND_BOOL HasIndex:1; // TRUE if index & scale are present. - ND_BOOL HasDisp:1; // TRUE if displacement is present. - ND_BOOL HasCompDisp:1; // TRUE if compressed disp8 is used (EVEX instructions). - ND_BOOL HasBroadcast:1; // TRUE if the memory operand is a broadcast operand. - - ND_BOOL IsRipRel:1; // TRUE if this is a rip-relative addressing. Base, Index, Scale are - // all ignored. - ND_BOOL IsStack:1; // TRUE if this is a stack op. Note that explicit stack accesses are not - // included (eg: mov eax, [rsp] will NOT set IsStack). - ND_BOOL IsString:1; // TRUE for [RSI] and [RDI] operands inside string operations. - ND_BOOL IsShadowStack:1; // TRUE if this is a shadow stack access. Check out ShStkType for more info. - ND_BOOL IsDirect:1; // TRUE if direct addressing (MOV [...], EAX, 0xA3). - ND_BOOL IsBitbase:1; // TRUE if this is a bit base. Used for BT* instructions. The bitbase - // stored in the second operand must be added to the linear address. - ND_BOOL IsAG:1; // TRUE if the memory operand is address generation and no mem access is - // made. - ND_BOOL IsMib:1; // TRUE if MIB addressing is used (MPX instructions). - ND_BOOL IsVsib:1; // TRUE if the index register selects a vector register. - ND_BOOL IsSibMem:1; // TRUE if the addressing uses sibmem (AMX instructions). - - - ND_REG_SIZE BaseSize; // Base size, in bytes. Max 8 bytes. - ND_REG_SIZE IndexSize; // Ditto for index size. Max 8 bytes. - ND_UINT8 DispSize; // Displacement size. Max 4 bytes. - ND_UINT8 CompDispSize; // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64. - - ND_UINT8 ShStkType; // Shadow stack access type. Check out ND_SHSTK_ACCESS. - - struct - { - ND_UINT8 IndexSize; // VSIB index size. - ND_UINT8 ElemSize; // VSIB element size. - ND_UINT8 ElemCount; // Number of elements scattered/gathered/prefetched. - } Vsib; - - ND_UINT8 Seg; // Base segment used to address the memory. 0 = es, 1 = cs, etc. - ND_UINT8 Base; // Base register. Can only be a GPR. - ND_UINT8 Index; // Index register. Can be a vector reg (ZMM0-ZMM31). - ND_UINT8 Scale; // Scale: 1, 2, 4 or 8. Always present if Index is present. - - ND_UINT64 Disp; // Sign extended displacement. - -} ND_OPDESC_MEMORY; - - -// -// Describes a decorator. -// -typedef struct _ND_OPERAND_DECORATOR -{ - ND_BOOL HasMask:1; // TRUE if mask is present, 0 otherwise. - ND_BOOL HasZero:1; // TRUE if zeroing will be made, 0 if merging will be made. - ND_BOOL HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands. - - // These are used only to indicate where the SAE and ER decorators should be placed in the disassembly. - // Otherwise, SAE and ER are global, per instruction, and don't apply to a single operand. - ND_BOOL HasSae:1; // TRUE if SAE is present. - ND_BOOL HasEr:1; // TRUE if ER is present. - - // Mask register specifier. - struct - { - ND_UINT8 Msk; // Mask register used. Only k0-k7 can be encoded. - } Mask; - - // Broadcast specifier - struct - { - ND_UINT8 Count; // Number of times to broadcast the element. - ND_UINT8 Size; // Size of one element. - } Broadcast; - -} ND_OPERAND_DECORATOR; - - -// -// Extended operand information. -// -typedef struct _ND_OPERAND -{ - ND_OPERAND_TYPE Type; // Operand type. One of ND_OPERAND_TYPE enumerations. - ND_OPERAND_ENCODING Encoding; // Where is the operand encoded - modrm.reg, modrm.rm, etc. - ND_OPERAND_SIZE Size; // Operand size in bytes. This should be used when operating with - // the operand. It includes sign-extension or zero-extensions. - // Note that the Size field indicates the actual amount of data - // used for processing. If the operand type is a register, it MAY NOT - // indicate the register size. Use the Info.Register.Size - // field to get the actual register size. - ND_OPERAND_SIZE RawSize; // Raw size inside the instruction. This will usually be identical - // to Size; however, some instructions force the actual size of their - // operands to 64 bit; PUSH/POP or branches are good examples; although - // the raw size of the relative offset or the immediate will be RawSize, - // internally, the CPU will use Size (usually sign-extended). - ND_OPERAND_ACCESS Access; // Access mode (read, write, read-write, etc.) - ND_OPERAND_FLAGS Flags; // Misc operand flags. - - // Depending in the Type field, one of these subfields contains information about the operand. - union - { - ND_OPDESC_CONSTANT Constant; // Constant, if operand type is ND_OP_CONST. - ND_OPDESC_IMMEDIATE Immediate; // Immediate, if operand type is ND_OP_IMM. - ND_OPDESC_REGISTER Register; // Register, if operand type if ND_OP_REG. - ND_OPDESC_RELOFFSET RelativeOffset; // Relative offset, if operand type is ND_OP_REL_OFFS. - ND_OPDESC_ADDRESS Address; // Address, if operand type is ND_OP_ADDR. - ND_OPDESC_MEMORY Memory; // Memory, if operand type is ND_OP_MEM. - } Info; - - ND_OPERAND_DECORATOR Decorator; // Decorator information. - -} ND_OPERAND, *PND_OPERAND; - - - -// -// REX prefix. -// -typedef union _ND_REX -{ - ND_UINT8 Rex; - struct - { - ND_UINT8 b : 1; // b (rm or low opcode) extension field. - ND_UINT8 x : 1; // x (index) extension field. - ND_UINT8 r : 1; // r (reg) extension field. - ND_UINT8 w : 1; // w (size) extension field. Promotes to 64 bit. - }; -} ND_REX; - - -// -// Mod R/M byte. -// -typedef union _ND_MODRM -{ - ND_UINT8 ModRm; - struct - { - ND_UINT8 rm : 3; // rm field. - ND_UINT8 reg : 3; // reg field. - ND_UINT8 mod : 2; // mod field. Indicates memory access (0, 1 or 2), or register access (3). - }; -} ND_MODRM; - - -// -// SIB byte. -// -typedef union _ND_SIB -{ - ND_UINT8 Sib; - struct - { - ND_UINT8 base : 3; // Base register. - ND_UINT8 index : 3; // Index register. - ND_UINT8 scale : 2; // Scale. - }; -} ND_SIB; - - -// -// DREX byte. Exactly as AMD defined it. No actual instructions exist that use DREX encoding. -// -typedef union _ND_DREX -{ - ND_UINT8 Drex; - struct - { - ND_UINT8 b : 1; - ND_UINT8 x : 1; - ND_UINT8 r : 1; - ND_UINT8 oc0 : 1; - ND_UINT8 vd : 3; - ND_UINT8 d : 1; - }; -} ND_DREX; - - -// -// 2-bytes VEX. Exactly as Intel defined it. -// -typedef union _ND_VEX2 -{ - ND_UINT8 Vex[2]; - struct - { - ND_UINT8 op; // 0xC5 - - ND_UINT8 p : 2; // p0, p1 - ND_UINT8 l : 1; // L - ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 - ND_UINT8 r : 1; // ~R - }; -} ND_VEX2; - - -// -// 3-bytes VEX. Exactly as Intel defined it. -// -typedef union _ND_VEX3 -{ - ND_UINT8 Vex[3]; - struct - { - ND_UINT8 op; // 0xC4 - - ND_UINT8 m : 5; // m0, m1, m2, m3, m4 - ND_UINT8 b : 1; // ~B - ND_UINT8 x : 1; // ~X - ND_UINT8 r : 1; // ~R - - ND_UINT8 p : 2; // p0, p1 - ND_UINT8 l : 1; // L - ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 - ND_UINT8 w : 1; // W - }; -} ND_VEX3; - - -// -// XOP. Exactly as AMD defined it. -// -typedef union _ND_XOP -{ - ND_UINT8 Xop[3]; - struct - { - ND_UINT8 op; // 0x8F - - ND_UINT8 m : 5; // m0, m1, m2, m3, m4 - ND_UINT8 b : 1; // ~B - ND_UINT8 x : 1; // ~X - ND_UINT8 r : 1; // ~R - - ND_UINT8 p : 2; // p0, p1 - ND_UINT8 l : 1; // L - ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 - ND_UINT8 w : 1; // W - }; -} ND_XOP; - - -// -// EVEX prefix. Exactly as Intel defined it. -// -typedef union _ND_EVEX -{ - ND_UINT8 Evex[4]; - struct - { - ND_UINT8 op; // 0x62 - - ND_UINT8 m : 3; // m0, m1, m2. Indicates opcode map. - ND_UINT8 zero : 1; // 0, must be 0. - ND_UINT8 rp : 1; // ~R' - ND_UINT8 b : 1; // ~B - ND_UINT8 x : 1; // ~X - ND_UINT8 r : 1; // ~R - - ND_UINT8 p : 2; // p0, p1 - ND_UINT8 one : 1; // 1 - ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 - ND_UINT8 w : 1; // W - - ND_UINT8 a : 3; // a0, a1, a2 - ND_UINT8 vp : 1; // ~V' - ND_UINT8 bm : 1; // b - ND_UINT8 l : 2; // L'L - ND_UINT8 z : 1; // z - }; -} ND_EVEX; - - -// -// Describes the CPUID leaf, sub-leaf, register & bit that indicate whether an instruction is supported or not. -// If Leaf == ND_CFF_NO_LEAF, the instruction is supported on any CPU, and no CPUID flag exists. -// If SubLeaf == ND_CFF_NO_SUBLEAF, there is no subleaf to check. -// -typedef union _ND_CPUID_FLAG -{ - ND_UINT64 Flag; - struct - { - ND_UINT32 Leaf; // CPUID leaf. ND_CFF_NO_LEAF if not applicable. - ND_UINT32 SubLeaf : 24; // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable. - ND_UINT32 Reg : 3; // The register that contains info regarding the instruction. - ND_UINT32 Bit : 5; // Bit inside the register that indicates whether the instruction is present. - }; -} ND_CPUID_FLAG; - - -// -// Each instruction may accept one or more prefixes. This structure indicates which prefixes are valid for the -// given instruction. -// -typedef union _ND_VALID_PREFIXES -{ - ND_UINT16 Raw; - struct - { - ND_UINT16 Rep : 1; // The instruction supports REP prefix. - ND_UINT16 RepCond : 1; // The instruction supports REPZ/REPNZ prefixes. - ND_UINT16 Lock : 1; // The instruction supports LOCK prefix. - ND_UINT16 Hle : 1; // The instruction supports XACQUIRE/XRELEASE prefixes. - ND_UINT16 Xacquire : 1; // The instruction supports only XACQUIRE. - ND_UINT16 Xrelease : 1; // The instruction supports only XRELEASE. - ND_UINT16 Bnd : 1; // The instruction supports BND prefix. - ND_UINT16 Bhint : 1; // The instruction supports branch hints. - ND_UINT16 HleNoLock : 1; // HLE prefix is accepted without LOCK. - ND_UINT16 Dnt : 1; // The instruction supports the DNT (Do Not Track) CET prefix. - }; -} ND_VALID_PREFIXES, *PND_VALID_PREFIXES; - - -// -// Each instruction may accept several decorators. This instruction indicates which decorators are valid for the -// given instruction. -// -typedef union _ND_VALID_DECORATORS -{ - ND_UINT8 Raw; - struct - { - ND_UINT8 Er : 1; // The instruction supports embedded rounding mode. - ND_UINT8 Sae : 1; // The instruction supports suppress all exceptions mode. - ND_UINT8 Zero : 1; // The instruction supports zeroing. - ND_UINT8 Mask : 1; // The instruction supports mask registers. - ND_UINT8 Broadcast : 1; // The instruction supports broadcast. - }; -} ND_VALID_DECORATORS, *PND_VALID_DECORATORS; - - -// -// Each instruction is valid or invalid in any certain mode. This indicates which modes the instruction is valid in. -// If the bit is set, the isntruction is valid in that given mode. -// -typedef union _ND_VALID_MODES -{ - ND_UINT32 Raw; - struct - { - // Group 1: privilege level. - ND_UINT32 Ring0 : 1; // The instruction is valid in ring 0. - ND_UINT32 Ring1 : 1; // The instruction is valid in ring 1. - ND_UINT32 Ring2 : 1; // The instruction is valid in ring 2. - ND_UINT32 Ring3 : 1; // The instruction is valid in ring 3. - - // Group 2: operating mode - the CPU can be on only one of these modes at any moment. - ND_UINT32 Real : 1; // The instruction is valid in real mode. - ND_UINT32 V8086 : 1; // The instruction is valid in Virtual 8086 mode. - ND_UINT32 Protected : 1; // The instruction is valid in protected mode (32 bit). - ND_UINT32 Compat : 1; // The instruction is valid in compatibility mode (32 bit in 64 bit). - ND_UINT32 Long : 1; // The instruction is valid in long mode. - - ND_UINT32 Reserved : 3; // Reserved for padding/future use. - - // Group 3: special modes - these may be active inside other modes (example: TSX in Long mode). - ND_UINT32 Smm : 1; // The instruction is valid in System Management Mode. - ND_UINT32 SmmOff : 1; // The instruction is valid outside SMM. - ND_UINT32 Sgx : 1; // The instruction is valid in SGX mode. - ND_UINT32 SgxOff : 1; // The instruction is valid outside SGX. - ND_UINT32 Tsx : 1; // The instruction is valid in transactional regions. - ND_UINT32 TsxOff : 1; // The instruction is valid outside TSX. - - // Group 4: VMX mode - they engulf all the other modes. - ND_UINT32 VmxRoot : 1; // The instruction is valid in VMX root mode. - ND_UINT32 VmxNonRoot : 1;// The instruction is valid in VMX non root mode. - ND_UINT32 VmxRootSeam : 1; // The instruction is valid in VMX root SEAM. - ND_UINT32 VmxNonRootSeam : 1;// The instruction is valid in VMX non-root SEAM. - ND_UINT32 VmxOff : 1; // The instruction is valid outside VMX operation. - - }; -} ND_VALID_MODES, *PND_VALID_MODES; - - -// -// RFLAGS register. This structure reflects the actual position of each flag insdide the RFLAGS register, so it can -// be used for direct processing. -// -typedef union _ND_RFLAGS -{ - ND_UINT32 Raw; - struct - { - ND_UINT32 CF : 1; // Carry flag. - ND_UINT32 Reserved1 : 1; // Reserved, must be 1. - ND_UINT32 PF : 1; // Parity flag. - ND_UINT32 Reserved2 : 1; // Reserved. - ND_UINT32 AF : 1; // Auxiliary flag. - ND_UINT32 Reserved3 : 1; // Reserved. - ND_UINT32 ZF : 1; // Zero flag. - ND_UINT32 SF : 1; // Sign flag. - ND_UINT32 TF : 1; // Trap flag. - ND_UINT32 IF : 1; // Interrupt flag. - ND_UINT32 DF : 1; // Direction flag. - ND_UINT32 OF : 1; // Overflow flag. - ND_UINT32 IOPL : 2; // I/O privilege level flag. - ND_UINT32 NT : 1; // Nested task flag. - ND_UINT32 Reserved4 : 1; // Reserved. - ND_UINT32 RF : 1; // Resume flag. - ND_UINT32 VM : 1; // Virtual mode flag. - ND_UINT32 AC : 1; // Alignment check flag. - ND_UINT32 VIF : 1; // Virtual interrupts flag. - ND_UINT32 VIP : 1; // Virtual interrupt pending flag. - ND_UINT32 ID : 1; // CPUID identification flag. - }; -} ND_RFLAGS, *PND_RFLAGS; - - -#define ND_FPU_FLAG_SET_0 0 // The FPU status flag is cleared to 0. -#define ND_FPU_FLAG_SET_1 1 // The FPU status flag is set to 1. -#define ND_FPU_FLAG_MODIFIED 2 // The FPU status flag is modified according to a result. -#define ND_FPU_FLAG_UNDEFINED 3 // The FPU status flag is undefined or unaffected. - -// -// FPU status flags. Each status flag can be one of ND_FPU_FLAG*. -// -typedef struct _ND_FPU_FLAGS -{ - ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*. - ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*. -} ND_FPU_FLAGS, *PND_FPU_FLAGS; - - -// -// Branch information. -// -typedef struct _ND_BRANCH_INFO -{ - ND_UINT8 IsBranch : 1; - ND_UINT8 IsConditional : 1; - ND_UINT8 IsIndirect : 1; - ND_UINT8 IsFar : 1; -} ND_BRANCH_INFO; - - -// -// Describes a decoded instruction. All the possible information about the instruction is contained in this structure. -// You don't have to call any other APIs to gather any more info about it. -// -typedef struct _INSTRUX -{ - ND_UINT8 DefCode:4; // ND_CODE_*. Indicates disassembly mode. - ND_UINT8 DefData:4; // ND_DATA_*. Indicates default data size. - ND_UINT8 DefStack:4; // ND_STACK_*. Indicates default stack pointer width. - ND_UINT8 VendMode:4; // ND_VEND_*. Indicates vendor mode. - ND_UINT8 FeatMode; // ND_FEAT_*. Indicates which features are enabled. - ND_UINT8 EncMode:4; // ND_ENCM_*. Indicates encoding mode. - ND_UINT8 VexMode:4; // ND_VEX_*. Indicates the VEX mode, if any. - ND_UINT8 AddrMode:4; // ND_ADDR_*. Indicates addressing mode. - ND_UINT8 OpMode:4; // ND_OPSZ_*. Indicates operand mode/size. - ND_UINT8 EfOpMode:4; // ND_OPSZ_*. Indicates effective operand mode/size. - ND_UINT8 VecMode:4; // ND_VECM_*. Indicates vector length. - ND_UINT8 EfVecMode:4; // ND_VECM_*. Indicates effective vector length. - - // Prefixes. - ND_BOOL HasRex:1; // TRUE - REX is present. - ND_BOOL HasVex:1; // TRUE - VEX is present. - ND_BOOL HasXop:1; // TRUE - XOP is present. - ND_BOOL HasEvex:1; // TRUE - EVEX is present. - ND_BOOL HasMvex:1; // TRUE - MVEX is present. - ND_BOOL HasOpSize:1; // TRUE - 0x66 present. - ND_BOOL HasAddrSize:1; // TRUE - 0x67 present. - ND_BOOL HasLock:1; // TRUE - 0xF0 present. - ND_BOOL HasRepnzXacquireBnd:1; // TRUE - 0xF2 present. - ND_BOOL HasRepRepzXrelease:1; // TRUE - 0xF3 present. - ND_BOOL HasSeg:1; // TRUE - segment override present. - - // Indicators for prefix activation. - ND_BOOL IsRepeated:1; // TRUE - the instruction is REPed up to RCX times. - ND_BOOL IsXacquireEnabled:1; // TRUE - the instruction is XACQUIRE enabled. - ND_BOOL IsXreleaseEnabled:1; // TRUE - the instruction is XRELEASE enabled. - ND_BOOL IsRipRelative:1; // TRUE - the instruction uses RIP relative addressing. - ND_BOOL IsCetTracked:1; // TRUE - this is an indirect CALL/JMP that is CET tracked. - - // Instruction chunks. - ND_BOOL HasModRm:1; // TRUE - we have valid MODRM. - ND_BOOL HasSib:1; // TRUE - we have valid SIB. - ND_BOOL HasDrex:1; // TRUE - we have valid DREX. - ND_BOOL HasDisp:1; // TRUE - the instruction has displacement. - ND_BOOL HasAddr:1; // TRUE - the instruction contains a direct address (ie, CALL far 0x9A) - ND_BOOL HasMoffset:1; // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0) - ND_BOOL HasImm1:1; // TRUE - immediate present. - ND_BOOL HasImm2:1; // TRUE - second immediate present. - ND_BOOL HasImm3:1; // TRUE - third immediate present. - ND_BOOL HasRelOffs:1; // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x). - ND_BOOL HasSseImm:1; // TRUE - SSE immediate that encodes additional registers is present. - ND_BOOL HasCompDisp:1; // TRUE - the instruction uses compressed displacement - ND_BOOL HasBroadcast:1; // TRUE - the instruction uses broadcast addressing - ND_BOOL HasMask:1; // TRUE - the instruction has mask. - ND_BOOL HasZero:1; // TRUE - the instruction uses zeroing. - ND_BOOL HasEr:1; // TRUE - the instruction has embedded rounding. - ND_BOOL HasSae:1; // TRUE - the instruction has SAE. - ND_BOOL HasIgnEr:1; // TRUE - the instruction ignores embedded rounding. - - ND_BOOL SignDisp:1; // Displacement sign. 0 is positive, 1 is negative. - - // Encoding specifics. - ND_BOOL HasMandatory66:1; // 0x66 is mandatory prefix. Does not behave as size-changing prefix. - ND_BOOL HasMandatoryF2:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. - ND_BOOL HasMandatoryF3:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. - - // Instruction components lengths. Will be 0 if the given field is not present. - ND_UINT8 Length; // 1-15 valid. Instructions longer than 15 bytes will cause #GP. - - ND_UINT8 WordLength:4; // The length of the instruction word. 2, 4 or 8. - ND_UINT8 PrefLength:4; // The total number of bytes consumed by prefixes. This will also be - // the offset to the first opcode. The primary opcode will always be - // the last one, so at offset PrefixesLength + OpcodeLength - 1 - ND_UINT8 OpLength:4; // Number of opcode bytes. Max 3. - ND_UINT8 DispLength:4; // Displacement length, in bytes. Maximum 4. - ND_UINT8 AddrLength:4; // Absolute address length, in bytes. Maximum 8 bytes. - ND_UINT8 MoffsetLength:4; // Memory offset length, in bytes. Maximum 8 bytes. - ND_UINT8 Imm1Length:4; // First immediate length, in bytes. Maximum 8 bytes. - ND_UINT8 Imm2Length:4; // Second immediate length, in bytes. Maximum 8 bytes. - ND_UINT8 Imm3Length:4; // Third immediate length, in bytes. Maximum 8 bytes. - ND_UINT8 RelOffsLength:4; // Relative offset length, in bytes. Maximum 4 bytes. - - // Instruction components offsets. Will be 0 if the given field is not present. Prefixes ALWAYS start at offset 0. - ND_UINT8 OpOffset:4; // The offset of the first opcode, inside the instruction. - ND_UINT8 MainOpOffset:4; // The offset of the nominal opcode, inside the instruction. - ND_UINT8 DispOffset:4; // The offset of the displacement, inside the instruction - ND_UINT8 AddrOffset:4; // The offset of the hard-coded address. - ND_UINT8 MoffsetOffset:4; // The offset of the absolute address, inside the instruction - ND_UINT8 Imm1Offset:4; // The offset of the immediate, inside the instruction - ND_UINT8 Imm2Offset:4; // The offset of the second immediate, if any, inside the instruction - ND_UINT8 Imm3Offset:4; // The offset of the third immediate, if any, inside the instruction - ND_UINT8 RelOffsOffset:4; // The offset of the relative offset used in instruction. - ND_UINT8 SseImmOffset:4; // The offset of the SSE immediate, if any, inside the instruction. - ND_UINT8 ModRmOffset:4; // The offset of the mod rm byte inside the instruction, if any. - // If SIB is also present, it will always be at ModRmOffset + 1. - - ND_UINT8 StackWords; // Number of words accessed on/from the stack. - - ND_UINT8 Rep; // The last rep/repz/repnz prefix. 0 if none. - ND_UINT8 Seg; // The last segment override prefix. 0 if none. FS/GS if 64 bit. - ND_UINT8 Bhint; // The last segment override indicating a branch hint. - ND_REX Rex; // REX prefix. - ND_MODRM ModRm; // ModRM byte. - ND_SIB Sib; // SIB byte. - ND_DREX Drex; // DREX byte. Part of AMD SSE 5. Never shipped. - - union - { - ND_VEX2 Vex2; // VEX 2 prefix. - ND_VEX3 Vex3; // VEX 3 prefix. - ND_XOP Xop; // XOP prefix. - ND_EVEX Evex; // EVEX prefix. - }; - - // This structures contains the fields extracted from either REX, XOP, VEX, EVEX or MVEX fields. They're globally - // placed here, in order to avoid testing for each kind of prefix each time. Instead, one can use the different - // fields directly from here, regardless the actual encoding mode. - struct - { - ND_UINT32 w:1; // REX/XOP/VEX/EVEX/MVEX.W field - ND_UINT32 r:1; // REX/XOP/VEX/EVEX/MVEX.R field (reg extension) - ND_UINT32 x:1; // REX/XOP/VEX/EVEX/MVEX.X field (index extension) - ND_UINT32 b:1; // REX/XOP/VEX/EVEX/MVEX.B field (base extension) - ND_UINT32 rp:1; // EVEX/MVEX.R' (reg extension) - ND_UINT32 p:2; // XOP/VEX/EVEX/MVEX.pp (embedded prefix) - ND_UINT32 m:5; // XOP/VEX/EVEX/MVEX.mmmmm (decoding table) - ND_UINT32 l:2; // XOP/VEX.L or EVEX.L'L (vector length) - ND_UINT32 v:4; // XOP/VEX.VVVV or EVEX/MVEX.VVVV (additional operand) - ND_UINT32 vp:1; // EVEX/MVEX.V' (vvvv extension) - ND_UINT32 bm:1; // EVEX.b (broadcast) - ND_UINT32 e:1; // MVEX.e (eviction hint) - ND_UINT32 z:1; // EVEX.z (zero) - ND_UINT32 k:3; // EVEX.aaa/MVEX.kkk (mask registers) - ND_UINT32 s:3; // MVEX.sss (swizzle) - } Exs; - - union - { - struct - { - ND_UINT32 Ip; - ND_UINT16 Cs; - }; - } Address; // seg:offset address. - - ND_UINT64 Moffset; // Offset. Used by 'O' operands. It's an absolute address. - ND_UINT32 Displacement; // Displacement. Max 4 bytes. Used in ModRM instructions. - ND_UINT32 RelativeOffset; // Relative offset, used for branches. Max 4 bytes. - ND_UINT64 Immediate1; // Can be 8 bytes on x64 - ND_UINT8 Immediate2; // For enter, mainly. Can only be 1 byte. - ND_UINT8 Immediate3; // Third additional immediate. Limited to 1 byte for now. - ND_UINT8 SseImmediate; // This immediate actually selects a register. - ND_UINT8 SseCondition; // Condition code encoded in additional byte. - ND_UINT8 Condition; // Condition code encoded in low 4 bit of the opcode. - ND_UINT8 Predicate; // Same as Condition, kept for backwards compatibility. - - ND_UINT8 OperandsCount; // Number of operands. - ND_UINT8 ExpOperandsCount; // Number of explicit operands. Use this if you want to ignore - // implicit operands such as stack, flags, etc. - ND_UINT16 OperandsEncodingMap; // What parts of the instruction encode operands. - ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands. - - // As extracted from the operands themselves. - ND_UINT8 CsAccess; // CS access mode (read/write). Includes only implicit CS accesses. - ND_UINT8 RipAccess; // RIP access mode (read/write). - ND_UINT8 StackAccess; // Stack access mode (push/pop). - ND_UINT8 MemoryAccess; // Memory access mode (read/write, including stack or shadow stack). - - ND_BRANCH_INFO BranchInfo; // Branch information. - - struct - { - ND_UINT8 RegAccess; // RFLAGS access mode (read/write), as per the entire register. - ND_RFLAGS Tested; // Tested flags. - ND_RFLAGS Modified; // Modified (according to the result) flags. - ND_RFLAGS Set; // Flags that are always set to 1. - ND_RFLAGS Cleared; // Flags that are always cleared to 0. - ND_RFLAGS Undefined; // Undefined flags. - } FlagsAccess; - - ND_FPU_FLAGS FpuFlagsAccess; // FPU status word C0-C3 bits access. Valid only for FPU instructions! - - ND_UINT8 ExceptionClass; // ND_EX_CLASS_TYPE, indicates the exception class type. - ND_UINT8 ExceptionType; // Exception type. Depends on ExceptionClass. - ND_UINT8 TupleType; // EVEX tuple type, if EVEX. Check out ND_TUPLE. - ND_UINT8 RoundingMode; // EVEX rounding mode, if present. Check out ND_ROUNDING. - - // Stored inside the instruction entry as well. These are specific for an instruction and do not depend on - // encoding. Use the flags definitions (ND_FLAG_*, ND_PREF_*, ND_DECO_*, ND_EXOP_*) to access specific bits. - ND_UINT32 Attributes; // Instruction attributes/flags. A collection of ND_FLAG_*. - union - { - ND_INS_CLASS Instruction; // One of the ND_INS_* - ND_INS_CLASS Iclass; // Same as Instruction. - }; - ND_INS_CATEGORY Category; // One of the ND_CAT_* - ND_INS_SET IsaSet; // One of the ND_SET_* - ND_CPUID_FLAG CpuidFlag; // CPUID support flag. - ND_VALID_MODES ValidModes; // Valid CPU modes for the instruction. - ND_VALID_PREFIXES ValidPrefixes; // Indicates which prefixes are valid for this instruction. - ND_VALID_DECORATORS ValidDecorators; // What decorators are accepted by the instruction. - char Mnemonic[ND_MAX_MNEMONIC_LENGTH]; // Instruction mnemonic. - ND_UINT8 OpCodeBytes[3]; // Opcode bytes - escape codes and main op code - ND_UINT8 PrimaryOpCode; // Main/nominal opcode - ND_UINT8 InstructionBytes[16]; // The entire instruction. - -} INSTRUX, *PINSTRUX; - - -// -// Decoder context. Such a structure must be passed to the NdDecodeWithContext API. This structure must be initialized -// only once, and then it can be re-used across NdDecodeWithContext calls. -// -typedef struct _ND_CONTEXT -{ - ND_UINT64 DefCode : 4; // Decode mode - one of the ND_CODE_* values. - ND_UINT64 DefData : 4; // Data mode - one of the ND_DATA_* values. - ND_UINT64 DefStack : 4; // Stack mode - one of the ND_STACK_* values. - ND_UINT64 VendMode : 4; // Prefered vendor - one of the ND_VEND_* values. - ND_UINT64 FeatMode : 8; // Supported features mask. A combination of ND_FEAT_* values. - ND_UINT64 Reserved : 40; // Reserved for future use. -} ND_CONTEXT; - - -// -// Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack. -// Use NdGetFullAccessMap to populate this structure. -// -typedef struct _ND_ACCESS_MAP -{ - ND_UINT8 RipAccess; - ND_UINT8 FlagsAccess; - ND_UINT8 StackAccess; - ND_UINT8 MemAccess; - ND_UINT8 MxcsrAccess; - ND_UINT8 PkruAccess; - ND_UINT8 SspAccess; - ND_UINT8 GprAccess[ND_MAX_GPR_REGS]; - ND_UINT8 SegAccess[ND_MAX_SEG_REGS]; - ND_UINT8 FpuAccess[ND_MAX_FPU_REGS]; - ND_UINT8 MmxAccess[ND_MAX_MMX_REGS]; - ND_UINT8 SseAccess[ND_MAX_SSE_REGS]; - ND_UINT8 CrAccess [ND_MAX_CR_REGS ]; - ND_UINT8 DrAccess [ND_MAX_DR_REGS ]; - ND_UINT8 TrAccess [ND_MAX_TR_REGS ]; - ND_UINT8 BndAccess[ND_MAX_BND_REGS]; - ND_UINT8 MskAccess[ND_MAX_MSK_REGS]; - ND_UINT8 TmmAccess[ND_MAX_TILE_REGS]; - ND_UINT8 SysAccess[ND_MAX_SYS_REGS]; - ND_UINT8 X87Access[ND_MAX_X87_REGS]; -} ND_ACCESS_MAP, *PND_ACCESS_MAP; - - -// -// Operand reverse-lookup table. Each entry inside this structure contains the pointer to the relevant operand. -// Some rules govern this special structure: -// - It is not generated by default. The user must call NdGetOperandRlut manually to fill in this structure. -// - This structure holds pointers inside the INSTRUX provided to the NdGetOperandRlut function; please make sure -// you call NdGetOperandRlut again if the INSTRUX is relocated, as all the pointers will dangle. -// - Not all the operand types have a corresponding entry in ND_OPERAND_RLUT, only the usual ones. -// - Some operands may have multiple entries in ND_OPERAND_RLUT - for example, RMW (read-modify-write) instructions -// will have Dst1 and Src1 pointing to the same operand. -// - The implicit registers entries in ND_OPERAND_RLUT will point to the operand which is of that type, and implicit; -// for example, ND_OPERAND_RLUT.Rax will be NULL for `add rax, rcx`, since in this case, `rax` is not an implicit -// operand. For `cpuid`, however, ND_OPERAND_RLUT.Rax will point to the implicit `eax` register. -// Use NdGetOperandRlut to populate this structure. -// -typedef struct _ND_OPERAND_RLUT -{ - PND_OPERAND Dst1; // First destination operand. - PND_OPERAND Dst2; // Second destination operand. - PND_OPERAND Src1; // First source operand. - PND_OPERAND Src2; // Second source operand. - PND_OPERAND Src3; // Third source operand. - PND_OPERAND Src4; // Fourth source operand. - PND_OPERAND Mem1; // First memory operand. - PND_OPERAND Mem2; // Second memory operand. - PND_OPERAND Stack; // Stack operand. - PND_OPERAND Flags; // Flags register operand. - PND_OPERAND Rip; // Instruction Pointer register operand. - PND_OPERAND Cs; // Implicit CS operand. - PND_OPERAND Ss; // Implicit SS operand. - PND_OPERAND Rax; // Implicit accumulator register operand. - PND_OPERAND Rcx; // Implicit counter register operand. - PND_OPERAND Rdx; // Implicit data register operand - PND_OPERAND Rbx; // Implicit base address register operand. - PND_OPERAND Rsp; // Implicit stack pointer operand. - PND_OPERAND Rbp; // Implicit base pointer operand. - PND_OPERAND Rsi; // Implicit source index operand. - PND_OPERAND Rdi; // Implicit destination index operand. -} ND_OPERAND_RLUT; - - - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Returns the bddisasm version. -// -void -NdGetVersion( - ND_UINT32 *Major, - ND_UINT32 *Minor, - ND_UINT32 *Revision, - char **BuildDate, - char **BuildTime - ); - -// -// Decode one instruction. Note that this is equivalent to: -// NdDecodeEx(Instrux, Code, ND_MAX_INSTRUCTION_LEN, DefCode, DefData). -// This version should be used if the caller doesn't care about the length of the buffer. Otherwise, use the other -// decode API. -// -NDSTATUS -NdDecode( - INSTRUX *Instrux, // Output decoded instruction. - const ND_UINT8 *Code, // Buffer containing the instruction bytes. - ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. - ND_UINT8 DefData // Data mode - one of the ND_DATA_* value. - ); - -// -// Decode one instruction. Note that this is equivalent to: -// NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY). -// By default, the used vendor will be ND_VEND_ANY, so all instructions will be decoded. -// By default, the feature mode will be ND_FEAT_ALL, so all instructions will be decoded (but may yield error where -// otherwise a NOP would be encoded - use ND_FEAT_NONE in that case). -// -NDSTATUS -NdDecodeEx( - INSTRUX *Instrux, // Output decoded instruction. - const ND_UINT8 *Code, // Buffer containing the instruction bytes. - ND_SIZET Size, // Maximum size of the Code buffer. - ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. - ND_UINT8 DefData // Data mode - one of the ND_DATA_* value. - ); - -// -// Fills a ND_CONTEXT structure, and calls NdDecodeWithContext. The feature mode will be ND_FEAT_ALL by default. -// -NDSTATUS -NdDecodeEx2( - INSTRUX *Instrux, // Output decoded instruction. - const ND_UINT8 *Code, // Buffer containing the instruction bytes. - ND_SIZET Size, // Maximum size of the Code buffer. - ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. - ND_UINT8 DefData, // Data mode - one of the ND_DATA_* value. - ND_UINT8 DefStack, // Stack mode - one of the ND_STACK_* values. - ND_UINT8 PreferedVendor // Preferred vendor - one of the ND_VEND_* values. - ); - -// -// This API received a decode context, where it expects DefCode, DefData, DefStack, VendMode and FeatMode to be -// already initialized. The Context will not be modified by the decoder, so it can be reused across decode calls. -// The Context should initially be initialized using NdInitContext. This will ensure backwards compatibility -// by setting new fields to default values. -// Note that this is the base decoding API, and this ends up being called by all the other decoding APIs, after -// providing default arguments and filling them in the Context structure. For maximum speed, use this instead of -// the others. -// -NDSTATUS -NdDecodeWithContext( - INSTRUX *Instrux, // Output decoded instruction. - const ND_UINT8 *Code, // Buffer containing the instruction bytes. - ND_SIZET Size, // Maximum size of the Code buffer. - ND_CONTEXT *Context // Context describing decode mode, vendor mode and supported features. - ); - -// -// Convert the given instruction into textual representation (Intel syntax). -// -NDSTATUS -NdToText( - const INSTRUX *Instrux, - ND_UINT64 Rip, - ND_UINT32 BufferSize, - char *Buffer - ); - -// -// Returns true if the instruction is RIP relative. Note that this function is kept for backwards compatibility, since -// there already is a IsRipRelative field inside INSTRUX. -// -ND_BOOL -NdIsInstruxRipRelative( - const INSTRUX *Instrux - ); - -// -// Returns an access map that contains the access for each register. -// -NDSTATUS -NdGetFullAccessMap( - const INSTRUX *Instrux, - ND_ACCESS_MAP *AccessMap - ); - -// -// Returns an operand reverse-lookup. One can use the Rlut to quickly reference different kinds of operands in INSTRUX. -// -NDSTATUS -NdGetOperandRlut( - const INSTRUX *Instrux, - ND_OPERAND_RLUT *Rlut - ); - -// -// Initialize the decoder context. -// -void -NdInitContext( - ND_CONTEXT *Context - ); - -#ifdef __cplusplus -} -#endif - -// #pragma warning(default: 4214) // Bitfield in type other than int. -// #pragma warning(default: 4201) // Nonstandard extension used: nameless struct/union. -#ifdef _MSC_VER -#pragma warning(pop) -#endif +#include "bdx86_core.h" #endif // BDDISASM_H diff --git a/inc/disasmstatus.h b/inc/bddisasm_status.h similarity index 95% rename from inc/disasmstatus.h rename to inc/bddisasm_status.h index 050a632..d8e8a64 100644 --- a/inc/disasmstatus.h +++ b/inc/bddisasm_status.h @@ -2,8 +2,8 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#ifndef DISASMSTATUS_H -#define DISASMSTATUS_H +#ifndef BDDISASM_STATUS_H +#define BDDISASM_STATUS_H // // Return statuses. @@ -48,6 +48,7 @@ typedef ND_UINT32 NDSTATUS; #define ND_STATUS_SIBMEM_WITHOUT_SIB 0x80000042 // Instruction uses SIBMEM, but SIB is not present. #define ND_STATUS_INVALID_TILE_REGS 0x80000043 // Tile registers are not unique. #define ND_STATUS_INVALID_DEST_REGS 0x80000044 // Destination register is not unique (used as src). +#define ND_STATUS_INVALID_EVEX_BYTE3 0x80000045 // EVEX payload byte 3 is invalid. // Not encoding specific. @@ -60,4 +61,4 @@ typedef ND_UINT32 NDSTATUS; #define ND_SUCCESS(status) (status < 0x80000000) -#endif +#endif // BDDISASM_STATUS_H diff --git a/inc/disasmtypes.h b/inc/bddisasm_types.h similarity index 69% rename from inc/disasmtypes.h rename to inc/bddisasm_types.h index 2e51c0c..c1f5fc8 100644 --- a/inc/disasmtypes.h +++ b/inc/bddisasm_types.h @@ -2,8 +2,8 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#ifndef DISASM_TYPES_H -#define DISASM_TYPES_H +#ifndef BDDISASM_TYPES_H +#define BDDISASM_TYPES_H #if defined(_MSC_VER) || defined(__ICC) || defined(__INTEL_COMPILER) @@ -58,14 +58,17 @@ typedef int64_t ND_SINT64; #elif defined(_M_IX86) || defined(__i386__) #define ND_ARCH_X86 +#define ND_ARCH_IA32 #elif defined(_M_ARM64) || defined(__aarch64__) #define ND_ARCH_AARCH64 +#define ND_ARCH_A64 #elif defined(_M_ARM) || defined(__arm__) #define ND_ARCH_ARM +#define ND_ARCH_A32 #else @@ -75,11 +78,11 @@ typedef int64_t ND_SINT64; // Handle architecture definitions. -#if defined(ND_ARCH_X64) || defined(ND_ARCH_AARCH64) +#if defined(ND_ARCH_X64) || defined(ND_ARCH_A64) typedef ND_UINT64 ND_SIZET; -#elif defined(ND_ARCH_X86) || defined(ND_ARCH_ARM) +#elif defined(ND_ARCH_X86) || defined(ND_ARCH_A32) typedef ND_UINT32 ND_SIZET; @@ -93,8 +96,23 @@ typedef ND_UINT32 ND_SIZET; // Common definitions. typedef ND_UINT8 ND_BOOL; -#define ND_NULL ((void *)(0)) -#define ND_TRUE (1) -#define ND_FALSE (0) - +#if defined(__cplusplus) +#define ND_NULL nullptr +#else +#define ND_NULL ((void *)(0)) #endif +#define ND_TRUE (1) +#define ND_FALSE (0) + + +// Static assertion. +#ifdef _MSC_VER +// When used without include , automatically maps to _Static_assert. Using static_assert is prefered, as +// it works on both C and C++. +#define ND_STATIC_ASSERT static_assert +#else +// Reserved keyword. MSVC only recognizes this if you include . +#define ND_STATIC_ASSERT _Static_assert +#endif + +#endif // BDDISASM_TYPES_H diff --git a/inc/bddisasm_version.h b/inc/bddisasm_version.h new file mode 100644 index 0000000..9f586a1 --- /dev/null +++ b/inc/bddisasm_version.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BDDISASM_VERSION_H +#define BDDISASM_VERSION_H + +#define DISASM_VERSION_MAJOR 2 +#define DISASM_VERSION_MINOR 1 +#define DISASM_VERSION_REVISION 0 + +#define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR +#define SHEMU_VERSION_MINOR DISASM_VERSION_MINOR +#define SHEMU_VERSION_REVISION DISASM_VERSION_REVISION + +#endif // BDDISASM_VERSION_H diff --git a/inc/bdshemu.h b/inc/bdshemu.h index 4c25c84..c78f850 100644 --- a/inc/bdshemu.h +++ b/inc/bdshemu.h @@ -7,6 +7,7 @@ #include "bddisasm.h" +#include "bdshemu_x86.h" // @@ -14,7 +15,8 @@ // typedef void (*ShemuPrint)( - char *Data // Data to be printed. + char *Data, // Data to be printed. + void *Context // Optional, caller-defined, context. ); @@ -37,185 +39,207 @@ typedef ND_BOOL ); -// Percent of emulated instructions that must be NOP to consider a NOP sled is present. -#define SHEMU_DEFAULT_NOP_THRESHOLD 75 -// Consecutive printable characters on stack to consider a stack string access. -#define SHEMU_DEFAULT_STR_THRESHOLD 8 -// Will not emulate more than this number of external memory accesses. Once this threshold is exceeded, any external -// access will abort the emulation. -#define SHEMU_DEFAULT_MEM_THRESHOLD 0 - - -// -// General purpose registers. -// -typedef struct _SHEMU_GPR_REGS +typedef enum _SHEMU_ARCH_TYPE { - ND_UINT64 RegRax; - ND_UINT64 RegRcx; - ND_UINT64 RegRdx; - ND_UINT64 RegRbx; - ND_UINT64 RegRsp; - ND_UINT64 RegRbp; - ND_UINT64 RegRsi; - ND_UINT64 RegRdi; - ND_UINT64 RegR8; - ND_UINT64 RegR9; - ND_UINT64 RegR10; - ND_UINT64 RegR11; - ND_UINT64 RegR12; - ND_UINT64 RegR13; - ND_UINT64 RegR14; - ND_UINT64 RegR15; - ND_UINT64 RegCr2; - ND_UINT64 RegFlags; - ND_UINT64 RegDr7; - ND_UINT64 RegRip; - ND_UINT64 RegCr0; - ND_UINT64 RegCr4; - ND_UINT64 RegCr3; - ND_UINT64 RegCr8; - ND_UINT64 RegIdtBase; - ND_UINT64 RegIdtLimit; - ND_UINT64 RegGdtBase; - ND_UINT64 RegGdtLimit; - ND_UINT64 FpuRip; -} SHEMU_GPR_REGS, *PSHEMU_GPR_REGS; + SHEMU_ARCH_TYPE_NONE = 0, + + // X86 includes both IA-32 and x86-64. + // All SHEMU flags are supported. + SHEMU_ARCH_TYPE_X86, + +} SHEMU_ARCH_TYPE; -// -// Segment register (with its hidden part). -// -typedef struct _SHEMU_SEG -{ - ND_UINT64 Base; - ND_UINT64 Limit; - ND_UINT64 Selector; - ND_UINT64 AccessRights; -} SHEMU_SEG, *PSHEMU_SEG; - - -// -// The segment registers. -// -typedef struct _SHEMU_SEG_REGS -{ - SHEMU_SEG Es; - SHEMU_SEG Cs; - SHEMU_SEG Ss; - SHEMU_SEG Ds; - SHEMU_SEG Fs; - SHEMU_SEG Gs; -} SHEMU_SEG_REGS, *PSHEMU_SEG_REGS; - - -// -// Emulation context. All of these fields must be provided as input, although most of them can be 0. -// -typedef struct _SHEMU_CONTEXT +typedef struct _SHEMU_X86_CTX { // Current instruction. Doesn't have to be provided; it always contains the currently emulated instruction. // When #ShemuEmulate returns, this will contain the last emulated instruction. In case of an emulation failure, // it can be inspected, to gather more info about what went wrong. - INSTRUX Instruction; + INSTRUX Instruction; // General purpose registers state. On input, the initial state. Will be updated after each emulated instruction. - SHEMU_GPR_REGS Registers; + SHEMU_X86_GPR_REGS Registers; // Segment registers state. On input, the initial state. May be updated after some instructions. - SHEMU_SEG_REGS Segments; + SHEMU_X86_SEG_REGS Segments; // MMX register state. 8 x 8 bytes = 64 bytes for the MMX registers. Can be provided on input, if needed. - ND_UINT64 MmxRegisters[ND_MAX_MMX_REGS]; + ND_UINT64 MmxRegisters[ND_MAX_MMX_REGS]; // SSE registers state. 32 x 64 bytes = 2048 bytes for the SSE registers. Can be provided on input, if needed. - ND_UINT8 SseRegisters[ND_MAX_SSE_REGS][ND_MAX_REGISTER_SIZE]; + ND_UINT8 SseRegisters[ND_MAX_SSE_REGS][ND_MAX_REGISTER_SIZE]; // General purpose registers write bitmap. After the first write, a register will be marked dirty in here. // Should be 0 on input. - ND_UINT16 DirtyGprBitmap; + ND_UINT8 GprTracker[ND_MAX_GPR_REGS]; // Operating mode (ND_CODE_16, ND_CODE_32 or ND_CODE_64). Must be provided as input. - ND_UINT8 Mode; + ND_UINT8 Mode; // Operating ring (0, 1, 2, 3). Must be provided as input. - ND_UINT8 Ring; + ND_UINT8 Ring; - // The suspicious code to be emulated. Must be provided as input. - ND_UINT8 *Shellcode; +} SHEMU_X86_CTX; + + +#define SHEMU_ICACHE_SIZE 0x100 + +typedef struct SHEMU_ICACHE +{ + // Instruction cache. + ND_UINT8 Icache[SHEMU_ICACHE_SIZE]; + + // The first address that is cached. + ND_UINT64 Address; + + // Number of valid bytes inside the cache. Maximum SHEMU_ICACHE_SIZE. + ND_UINT64 Size; +} SHEMU_ICACHE; + + +typedef struct SHEMU_LOOP_TRACK +{ + // The address of the loop instruction. The loop instruction can be any taken conditional or unconditional + // branch that goes backwards. + ND_UINT64 Address; + + // The target of the loop instructions (the first instruction of the loop). + ND_UINT64 Target; + + // The current iteration number. + ND_UINT64 Iteration; + + // ND_TRUE whether tracking is active, and we are inside a loop. + ND_BOOL Active; + +} SHEMU_LOOP_TRACK; + + +// +// Emulation context. All of these fields must be provided as input, although most of them can be 0. +// +typedef struct _SHEMU_CONTEXT +{ + union + { + // Used when ArchType is SHEMU_ARCH_TYPE_X86. + SHEMU_X86_CTX X86; + + } Arch; + + // Indicates architecture mode. Must be provided as input. + SHEMU_ARCH_TYPE ArchType; + + // Instruction cache. Note that this caches instruction bytes, not decoded instructions. + SHEMU_ICACHE Icache; + + // Tracks emulated loops. + SHEMU_LOOP_TRACK LoopTrack; + + // The suspicious code to be emulated. Must be provided as input, as follows: + // - This buffer must be allocated by the caller, and it must be writeable. It should NOT point to process memory, + // as it will be modified by shemu in case of self-modifying code. + // - However, if the SHEMU_OPT_DIRECT_MAPPED_SHELL option is used, this field can point directly to process memory, + // but the AccessShellcode callback must also be provided. In this case, the buffer will NOT be modified by + // shemu. + ND_UINT8 *Shellcode; // Virtual stack. RSP will point somewhere inside. Must be allocated as input, and it can be initialized with // actual stack contents. Can also be 0-filled. - ND_UINT8 *Stack; + // This buffer must be allocated by the caller, and it must be writeable. It should not point to process memory, + // as it will be modified by shemu. + ND_UINT8 *Stack; // Internal use. Must be at least the size of the shell + stack. Needs not be initialized, but must be allocated // and accessible on input. - ND_UINT8 *Intbuf; + ND_UINT8 *Intbuf; // Shellcode base address (the address the shellcode would see). Must be provided as input. - ND_UINT64 ShellcodeBase; + ND_UINT64 ShellcodeBase; - // Stack base address (the RSP the shellcode would see). Must be provided as input. - ND_UINT64 StackBase; + // Stack base address (the stack the shellcode would see). Must be provided as input. + ND_UINT64 StackBase; // Shellcode size. Must be provided as input. Usually just a page in size, but can be larger. - ND_UINT32 ShellcodeSize; + ND_UINT64 ShellcodeSize; // Stack size. Must be provided as input. Minimum two pages. - ND_UINT32 StackSize; + ND_UINT64 StackSize; // Internal buffer size. Must be provided as input. Must be at least the size of the shell + stack. - ND_UINT32 IntbufSize; + ND_UINT64 IntbufSize; + + // Number of consecutive NOPs encountered at the beginning of the code. Should be 0 on input. + ND_UINT64 NopCount; - // Number of NOPs encountered. Should be 0 on input. - ND_UINT32 NopCount; + // Number of '00 00' (ADD [rax], al) instructions encountered. Should be 0 on input. + ND_UINT64 NullCount; // The length of the string constructed on the stack, if any. Should be 0 on input. - ND_UINT32 StrLength; + ND_UINT64 StrLength; // Number of external memory access (outside stack/shellcode). Should be 0 on input. - ND_UINT32 ExtMemAccess; + ND_UINT64 ExtMemAccess; // Number of emulated instructions. Should be 0 on input. Once InstructionsCount reaches MaxInstructionsCount, // emulation will stop. - ND_UINT32 InstructionsCount; + ND_UINT64 InstructionsCount; + + // Number of distinct addresses executed. Will be less than or equal to InstructionsCount. In case of an infinite + // loop (JMP $), this field will be 1, but the InstructionsCount will be infinite. In case of two overlapping + // instructions, this field will be incremented twice (for example, JMP $+1). + ND_UINT64 UniqueCount; // Max number of instructions that should be emulated. Once this limit has been reached, emulation will stop. // Lower values will mean faster processing, but less chances of detection. Higher values mean low performance, // but very high chances of yielding useful results. Must be provided as input. - ND_UINT32 MaxInstructionsCount; + ND_UINT64 MaxInstructionsCount; // Base address of the Thread Information Block (the TIB the shellcode would normally see). Must be provided as // input. - ND_UINT64 TibBase; + ND_UINT64 TibBase; - // Shellcode Flags (see SHEMU_FLAG_*). Must be provided as input. - ND_UINT64 Flags; + // Shellcode Flags (see SHEMU_FLAG_*). Should be 0 on input. Will be non-zero on output if a shellcode indicator + // has been met (check SHEMU_FLAG_* values for shellcode indicators). + // Note that this field should always be checked for detection. No matter the return value of the emulator, + // if this field is non-zero, a potential shellcode has been detected. This is valid even if + // SHEMU_OPT_STOP_ON_EXPLOIT is set: this option only guarantees that emulation will not continue once a shellcode + // has been encountered, but it does not guarantee that SHEMU_ABORT_SHELLCODE_DETECTED will be returned. + ND_UINT64 Flags; // Emulation options. See SHEMU_OPT_* for possible options. Must be provided as input. - ND_UINT32 Options; + ND_UINT64 Options; // Percent of NOPs (out of total instructions emulated) that trigger NOP sled detection. Must be provided as input. - ND_UINT32 NopThreshold; + // Defaults to SHEMU_DEFAULT_NOP_THRESHOLD. + ND_UINT32 NopThreshold; // Stack string length threshold. Stack-constructed strings must be at least this long to trigger stack string - // detection. Must be provided as input. - ND_UINT32 StrThreshold; + // detection. Must be provided as input. Defaults to SHEMU_DEFAULT_STR_THRESHOLD. + ND_UINT32 StrThreshold; // Number of external mem accesses threshold. No more than this number of external accesses will be issued. Must - // be provided as input. - ND_UINT32 MemThreshold; + // be provided as input. Defaults to SHEMU_DEFAULT_MEM_THRESHOLD. + ND_UINT32 MemThreshold; // Optional auxiliary data, provided by the integrator. Can be NULL, or can point to integrator specific data. // Shemu will not use this data in any way, but callbacks that receive a SHEMU_CONTEXT pointer (such as // #AccessMemory) can use it to reference integrator private information. - void *AuxData; + void *AuxData; // If provided, will be used for tracing. Can be NULL. - ShemuPrint Log; + ShemuPrint Log; // If provided, will try to access additional memory. Can be NULL. - ShemuMemAccess AccessMemory; + ShemuMemAccess AccessMemory; + + // Must be provided if the the SHEMU_OPT_DIRECT_MAPPED_SHELL option is used. This callback will be used to proxy + // all accesses made to the shellcode memory, including fetches, loads & stores. The AccessMemory callback is + // used only for accesses to memory that are not part of the Shellcode or the Stack. + ShemuMemAccess AccessShellcode; + + // Optional context to be passed to Log. Can be NULL. + void *LogContext; } SHEMU_CONTEXT, *PSHEMU_CONTEXT; @@ -223,57 +247,209 @@ typedef struct _SHEMU_CONTEXT typedef unsigned int SHEMU_STATUS; + // // Emulation abort reasons. // #define SHEMU_SUCCESS 0 // Successfully emulated up to MaxInstructions. -#define SHEMU_ABORT_GLA_OUTSIDE 1 // Address accessed outside the shellcode or stack page. -#define SHEMU_ABORT_BRANCH_OUTSIDE 2 // A branch outside the shellcode page. -#define SHEMU_ABORT_UNSUPPORTED_INSTRUX 3 // A valid but unsupported instruction was encountered. -#define SHEMU_ABORT_INVALID_INSTRUX 4 // An invalid instruction was encountered. -#define SHEMU_ABORT_ADDRESSING_UNSUPPORTED 5 // An unsupported addressing scheme used (ie, VSIB). +#define SHEMU_ABORT_GLA_OUTSIDE 1 // A load or store outside the shellcode or the stack. +#define SHEMU_ABORT_RIP_OUTSIDE 2 // A part of the instruction lies outside the shellcode. +#define SHEMU_ABORT_INSTRUX_NOT_SUPPORTED 3 // An unsupported instruction was encountered. +#define SHEMU_ABORT_OPERAND_NOT_SUPPORTED 4 // An unsupported operand was encountered. +#define SHEMU_ABORT_ADDRESSING_NOT_SUPPORTED 5 // An unsupported addressing scheme used (ie, VSIB). #define SHEMU_ABORT_REGISTER_NOT_SUPPORTED 6 // An unsupported register was used (ie, DR). #define SHEMU_ABORT_INVALID_PARAMETER 7 // An invalid parameter was supplied. -#define SHEMU_ABORT_OP_TOO_LARGE 8 // An operand that is too large was encountered. #define SHEMU_ABORT_NO_PRIVILEGE 9 // A privileged instruction outside kernel mode. #define SHEMU_ABORT_CANT_EMULATE 10 // A valid, but only partially handled instruction. -#define SHEMU_ABORT_SHELLCODE_DETECTED 0xFFFFFFFF // Shellcode criteria met (see the shellcode flags). +#define SHEMU_ABORT_INVALID_SELECTOR 11 // An invalid selector is loaded. +#define SHEMU_ABORT_UNDEFINED 12 // Valid encoding, but undefined cominbation of bits. +#define SHEMU_ABORT_UNPREDICTABLE 13 // Instruction behavior is unpredictable. +#define SHEMU_ABORT_MISALIGNED_PC 14 // PC is not aligned to a word. +#define SHEMU_ABORT_FETCH_ERROR 15 // Could not fetch instruction bytes. +#define SHEMU_ABORT_DECODE_ERROR 16 // Could not decode the instruction. + +#define SHEMU_ABORT_SHELLCODE_DETECTED 0xFFFFFFFF // Shellcode criteria met (see the shellcode flags). + // Note that this status may be returned if and only if + // the SHEMU_OPT_STOP_ON_EXPLOIT is used. + + +typedef enum SHEMU_FLAG_ID +{ + shemuFlagIdNopSled, + shemuFlagIdLoadRip, + shemuFlagIdWriteSelf, + shemuFlagIdTebAccessPeb, + shemuFlagIdSyscall, + shemuFlagIdStackStr, + shemuFlagIdTebAccessWow32, + shemuFlagIdHeavensGate, + shemuFlagIdStackPivot, + shemuFlagIdSudAccess, + + // Kernel specific flags. + shemuFlagIdKpcrAccess = 32, + shemuFlagIdSwapgs, + shemuFlagIdSyscallMsrRead, + shemuFlagIdSyscallMsrWrite, + shemuFlagIdSidt, +} SHEMU_FLAG_ID; + +#define SHEMU_FLAG(id) (1ull << (id)) // // Shellcode flags. // + // General and user-mode flags. -#define SHEMU_FLAG_NOP_SLED 0x00000001 // Long sequence of NOP instructions. -#define SHEMU_FLAG_LOAD_RIP 0x00000002 // The code loads RIP (CALL/POP, FNSTENV/POP, etc.) -#define SHEMU_FLAG_WRITE_SELF 0x00000004 // The code writes itself (decryption, unpacking, etc.) -#define SHEMU_FLAG_TIB_ACCESS 0x00000008 // The code accesses the PEB field inside TIB. -#define SHEMU_FLAG_SYSCALL 0x00000010 // The code does a direct syscall/sysenter/int 0x2e|0x80. -#define SHEMU_FLAG_STACK_STR 0x00000020 // The code constructs & uses strings on the stack. -#define SHEMU_FLAG_TIB_ACCESS_WOW32 0x00000040 // The code accesses the Wow32Reserved field inside TIB. -#define SHEMU_FLAG_HEAVENS_GATE 0x00000080 // The code uses Heaven's gate to switch into 64 bit mode. -#define SHEMU_FLAG_STACK_PIVOT 0x00000100 // The code switched the stack using XCHG esp, *. -#define SHEMU_FLAG_SUD_ACCESS 0x00000200 // The code accesses the KUSER_SHARED_DATA page. + +// Long sequence of NOP instructions. Generally present before the actual shellcode. This flag will only be set if: +// 1. Minimum MaxInstructions / 2 instructions have been emulated; +// 2. Minimum NopThreshold fraction (percent) of the emulated instructions are NOPs; +// 3. No other abort condition is met during emulation. +#define SHEMU_FLAG_NOP_SLED SHEMU_FLAG(shemuFlagIdNopSled) + +// The code loads RIP (CALL/POP, FNSTENV/POP, etc.). Almost always used by shellcodes in order to determine their +// position in memory. This flag will be set when the value of the instruction pointer is loaded into a general +// purpose register by any means. Techniques covered include, but are not limited to: +// 1. CALL + POP reg; +// 2. FP instruction + FNSTENV + loading the saved RIP from the saved FPU state. +// Loading the RIP via RIP relative addressing on x64 does not set this flag. +#define SHEMU_FLAG_LOAD_RIP SHEMU_FLAG(shemuFlagIdLoadRip) + +// The code writes itself (decryption, unpacking, etc.). Commonly seen if the shellcode decrypts itself in memory. +// This flag will only be set if previously written data is executed. This flag will not be set if, for example, +// chunks of data are written within the shellcode but never executed. +#define SHEMU_FLAG_WRITE_SELF SHEMU_FLAG(shemuFlagIdWriteSelf) + +// The code accesses the PEB field inside TEB. This is achieved via "FS:[0x30]" or "GS:[0x60]" accesses. Inside +// bdshemu, accesses to the linear address inside TEB is detected no mater how obfuscated - for example, the +// following instructions will all set this flag: +// 1. MOV eax, gs:[0x30] +// 2. MOV eax, 0x30; MOV eax, fs:[eax] +// 3. MOV eax, 0; MOV eax, fs:[eax+0x30] +#define SHEMU_FLAG_TIB_ACCESS SHEMU_FLAG(shemuFlagIdTebAccessPeb) +#define SHEMU_FLAG_TIB_ACCESS_PEB SHEMU_FLAG_TIB_ACCESS + +// The code does a direct syscall/sysenter/int 0x2e|0x80. This should never happen outside the legitimate ntdll +// module. However, payloads may issue direct system calls in order to avoid detection, or to simply avoid fixing +// imports manually. +// Note that this flag will be set when the SYSCALL, SYSENTER, INT 0x2E or INT 0x80 is executed, but only if +// the EAX register contains a value that resembles a valid system call (< 0x1000). +#define SHEMU_FLAG_SYSCALL SHEMU_FLAG(shemuFlagIdSyscall) + +// The code constructs & uses strings on the stack. The flag will be set only if: +// 1. The length of the string constructed on the stack is at least StrThreshold bytes long (default 8); +// 2. The constructed string is referenced by loading its address anywhere (including a register or memory). +#define SHEMU_FLAG_STACK_STR SHEMU_FLAG(shemuFlagIdStackStr) + +// The code accesses the Wow32Reserved field inside TIB. This is generally used to issue system calls from Wow64. +#define SHEMU_FLAG_TIB_ACCESS_WOW32 SHEMU_FLAG(shemuFlagIdTebAccessWow32) + +// The code uses Heaven's gate to switch into 64 bit mode. This can be abused by shellcodes in order to avoid +// detection by switching from legacy 32 bit mode to 64 bit mode. +#define SHEMU_FLAG_HEAVENS_GATE SHEMU_FLAG(shemuFlagIdHeavensGate) + +// The code switches the stack using XCHG esp, *. This is commonly executed by a shellcode once it receives +// control after a stack pivot. By itself, this flag is FP prone, and should generally not be used alone. +// This flag will only be set if several conditions are met: +// 1. The XCHG instruction is used to load a new value in the RSP register +// 2. The new value is naturally aligned (8 bytes in 64-bit mode, 4 bytes in 32-bit mode) +// 3. The new value points either inside the shellcode or the stack area, and at least 64 bytes are valid +#define SHEMU_FLAG_STACK_PIVOT SHEMU_FLAG(shemuFlagIdStackPivot) + +// The code accesses the KUSER_SHARED_DATA page. Commonly used by shellcodes which wish to issue direct system +// cals or to access various data located inside the SharedUserData page. Only accesses to the following fields +// will set this flag: +// 1. KdDebuggerEnabled (offset 0x2D4) +// 2. SystemCall (offset 0x308) +// 3. Cookie (offset 0x300) +#define SHEMU_FLAG_SUD_ACCESS SHEMU_FLAG(shemuFlagIdSudAccess) + + // Kernel specific flags. -#define SHEMU_FLAG_KPCR_ACCESS 0x00010000 // KPCR current thread access via gs:[0x188]/fs:[0x124]. -#define SHEMU_FLAG_SWAPGS 0x00020000 // SWAPGS was executed. -#define SHEMU_FLAG_SYSCALL_MSR_READ 0x00040000 // A SYSCALL/SYSENTER MSR read. -#define SHEMU_FLAG_SYSCALL_MSR_WRITE 0x00080000 // A SYSCALL/SYSENTER MSR write. -#define SHEMU_FLAG_SIDT 0x00100000 // SIDT was executed. + +// KPCR current thread access via gs:[0x188]/fs:[0x124]. Commonly used by kernel shellcodes in order to get the +// currently exeucting thread. +#define SHEMU_FLAG_KPCR_ACCESS SHEMU_FLAG(shemuFlagIdKpcrAccess) + +// SWAPGS was executed. Shellcodes may use this if they intercept a low-level event such as the SYSCALL. +#define SHEMU_FLAG_SWAPGS SHEMU_FLAG(shemuFlagIdSwapgs) + +// A SYSCALL/SYSENTER MSR was read. Commonly used to locate the nt image in order to manually fix imports. +#define SHEMU_FLAG_SYSCALL_MSR_READ SHEMU_FLAG(shemuFlagIdSyscallMsrRead) + +// A SYSCALL/SYSENTER MSR was written. Commonly used to intercept events such as SYSCALLs. +#define SHEMU_FLAG_SYSCALL_MSR_WRITE SHEMU_FLAG(shemuFlagIdSyscallMsrWrite) + +// SIDT was executed. Commonly used to locate the nt image in order to manually fix imports. +#define SHEMU_FLAG_SIDT SHEMU_FLAG(shemuFlagIdSidt) + + + +// +// Emulation thresholds. +// + +// Percent of emulated instructions that must be NOP to consider a NOP sled is present. +#define SHEMU_DEFAULT_NOP_THRESHOLD 75 + +// Consecutive printable characters on stack to consider a stack string access. +#define SHEMU_DEFAULT_STR_THRESHOLD 8 + +// Will not emulate more than this number of external memory accesses. Once this threshold is exceeded, any external +// access will abort the emulation. +#define SHEMU_DEFAULT_MEM_THRESHOLD 0 + + // // Emulation options. // -#define SHEMU_OPT_TRACE_EMULATION 0x00000001 // Trace each emulated instruction. -#define SHEMU_OPT_STOP_ON_EXPLOIT 0x00000002 // When shellcode indications are confirmed, stop emulation. -#define SHEMU_OPT_BYPASS_SELF_WRITES 0x00000004 // When a shellcode self-modifies, the modification will - // not be committed. Use this when emulating an already - // decoded shellcode, where emulating the decryption again - // will in fact scramble the shellcode and make it useless. -#define SHEMU_OPT_SUPPORT_AES 0x00010000 // Indicates that AES instructions are supported, and - // therefore, the AES intrinsics can be used to emulate - // AES decryption. + +// Trace each emulated instruction. +#define SHEMU_OPT_TRACE_EMULATION 0x0000000000000001 + +// When shellcode indications are confirmed, stop emulation. Note that this flag only guarantees that emulation +// will stop once we set any flag, but it does not guarantee that SHEMU_ABORT_SHELLCODE_DETECTED will be returned, +// as an emulation error may take place at any moment. Always check the Flags field of the SHEMU_CONTEXT structure +// to determine whether a detection took place or not. +#define SHEMU_OPT_STOP_ON_EXPLOIT 0x0000000000000002 + +// When a shellcode self-modifies, the modification will not be committed. Use this when emulating an already +// decoded shellcode, where emulating the decryption again will in fact scramble the shellcode and make it useless. +#define SHEMU_OPT_BYPASS_SELF_WRITES 0x0000000000000004 + +// Trace each memory access. +#define SHEMU_OPT_TRACE_MEMORY 0x0000000000000008 + +// Trace each identified dynamically constructed string. +#define SHEMU_OPT_TRACE_STRINGS 0x0000000000000010 + +// Shellcode is directly mapped, and it is not read in a dedicated buffer. No stores can be done to it. This +// allows for arbitrarly sized shellcodes to be emulated without the need to allocate separate memory & do +// copied of the target shellcode. Internally, pieces of the shellcode may still be cached. +// The size of IntBuf must be equal only to the size of the stack plus one page, and no extra memory +// needs to be allocated for the shellcode. When using this flag, the following features will not be available: +// 1. UniqueCount - it will simply indicate the total number of instructions emulated, NOT the number of unique +// instructions emulated +// 2. WRITE_SELF - self-write detection will be disabled +// Other features will work normally, as they don't require state tracking inside the IntBuf. +// When using this option, the SHEMU_OPT_BYPASS_SELF_WRITES is forced as well. +#define SHEMU_OPT_DIRECT_MAPPED_SHELL 0x0000000000000020 + +// Trace each identified loop. +#define SHEMU_OPT_TRACE_LOOPS 0x0000000000000080 + +// Indicates that AES instructions are supported, and therefore, the AES intrinsics can be used to emulate +// AES decryption. +#define SHEMU_OPT_SUPPORT_AES 0x0000000100000000 +// Emulate with APX support enabled. If not provided, APX and REX2 prefixed instructions will cause emulation to +// stop. +#define SHEMU_OPT_SUPPORT_APX 0x0000000200000000 + + // @@ -282,6 +458,8 @@ typedef unsigned int SHEMU_STATUS; #define SHEMU_INTERNAL_BUFFER_SIZE(ctx) ((ctx)->ShellcodeSize + (ctx)->StackSize) + + #ifdef __cplusplus extern "C" { #endif @@ -289,6 +467,11 @@ extern "C" { // // API // +SHEMU_STATUS +ShemuX86Emulate( + SHEMU_CONTEXT *Context + ); + SHEMU_STATUS ShemuEmulate( SHEMU_CONTEXT *Context diff --git a/inc/bdshemu_x86.h b/inc/bdshemu_x86.h new file mode 100644 index 0000000..1c22252 --- /dev/null +++ b/inc/bdshemu_x86.h @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BDSHEMU_X86_ +#define BDSHEMU_X86_ + +#include "bddisasm_types.h" + + +// +// General purpose registers. +// +typedef struct _SHEMU_X86_GPR_REGS +{ + ND_UINT64 RegRax; + ND_UINT64 RegRcx; + ND_UINT64 RegRdx; + ND_UINT64 RegRbx; + ND_UINT64 RegRsp; + ND_UINT64 RegRbp; + ND_UINT64 RegRsi; + ND_UINT64 RegRdi; + ND_UINT64 RegR8; + ND_UINT64 RegR9; + ND_UINT64 RegR10; + ND_UINT64 RegR11; + ND_UINT64 RegR12; + ND_UINT64 RegR13; + ND_UINT64 RegR14; + ND_UINT64 RegR15; + ND_UINT64 RegR16; + ND_UINT64 RegR17; + ND_UINT64 RegR18; + ND_UINT64 RegR19; + ND_UINT64 RegR20; + ND_UINT64 RegR21; + ND_UINT64 RegR22; + ND_UINT64 RegR23; + ND_UINT64 RegR24; + ND_UINT64 RegR25; + ND_UINT64 RegR26; + ND_UINT64 RegR27; + ND_UINT64 RegR28; + ND_UINT64 RegR29; + ND_UINT64 RegR30; + ND_UINT64 RegR31; + ND_UINT64 RegCr2; + ND_UINT64 RegFlags; + ND_UINT64 RegDr7; + ND_UINT64 RegRip; + ND_UINT64 RegCr0; + ND_UINT64 RegCr4; + ND_UINT64 RegCr3; + ND_UINT64 RegCr8; + ND_UINT64 RegIdtBase; + ND_UINT64 RegIdtLimit; + ND_UINT64 RegGdtBase; + ND_UINT64 RegGdtLimit; + ND_UINT64 FpuRip; +} SHEMU_X86_GPR_REGS, *PSHEMU_X86_GPR_REGS; + + +ND_STATIC_ASSERT(ND_MAX_GPR_REGS <= 32, "Too many General Purpose Registers defined in bddisasm! Make sure to update SHEMU_X86_GPR_REGS!"); + + +// +// Segment register (with its hidden part). +// +typedef struct _SHEMU_X86_SEG +{ + ND_UINT64 Base; + ND_UINT64 Limit; + ND_UINT64 Selector; + ND_UINT64 AccessRights; +} SHEMU_X86_SEG, *PSHEMU_X86_SEG; + + +// +// The segment registers. +// +typedef struct _SHEMU_X86_SEG_REGS +{ + SHEMU_X86_SEG Es; + SHEMU_X86_SEG Cs; + SHEMU_X86_SEG Ss; + SHEMU_X86_SEG Ds; + SHEMU_X86_SEG Fs; + SHEMU_X86_SEG Gs; +} SHEMU_X86_SEG_REGS, *PSHEMU_X86_SEG_REGS; + +#endif diff --git a/inc/constants.h b/inc/bdx86_constants.h similarity index 98% rename from inc/constants.h rename to inc/bdx86_constants.h index 9bf6400..87424a4 100644 --- a/inc/constants.h +++ b/inc/bdx86_constants.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Bitdefender + * Copyright (c) 2024 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ @@ -7,8 +7,8 @@ // This file was auto-generated by generate_tables.py. DO NOT MODIFY! // -#ifndef CONSTANTS_H -#define CONSTANTS_H +#ifndef BDX86_CONSTANTS_H +#define BDX86_CONSTANTS_H typedef enum _ND_INS_CLASS @@ -44,7 +44,6 @@ typedef enum _ND_INS_CLASS ND_INS_AESENCWIDE256KL, ND_INS_AESIMC, ND_INS_AESKEYGENASSIST, - ND_INS_ALTINST, ND_INS_AND, ND_INS_ANDN, ND_INS_ANDNPD, @@ -90,8 +89,10 @@ typedef enum _ND_INS_CLASS ND_INS_CALLNI, ND_INS_CALLNR, ND_INS_CBW, + ND_INS_CCMP, ND_INS_CDQ, ND_INS_CDQE, + ND_INS_CFCMOV, ND_INS_CLAC, ND_INS_CLC, ND_INS_CLD, @@ -137,10 +138,9 @@ typedef enum _ND_INS_CLASS ND_INS_COMISD, ND_INS_COMISS, ND_INS_CPUID, - ND_INS_CPU_READ, - ND_INS_CPU_WRITE, ND_INS_CQO, ND_INS_CRC32, + ND_INS_CTEST, ND_INS_CVTDQ2PD, ND_INS_CVTDQ2PS, ND_INS_CVTPD2DQ, @@ -174,7 +174,6 @@ typedef enum _ND_INS_CLASS ND_INS_DIVPS, ND_INS_DIVSD, ND_INS_DIVSS, - ND_INS_DMINT, ND_INS_DPPD, ND_INS_DPPS, ND_INS_EMMS, @@ -318,6 +317,7 @@ typedef enum _ND_INS_CLASS ND_INS_INVPCID, ND_INS_INVVPID, ND_INS_IRET, + ND_INS_JMPABS, ND_INS_JMPE, ND_INS_JMPFD, ND_INS_JMPFI, @@ -385,7 +385,6 @@ typedef enum _ND_INS_CLASS ND_INS_MINSS, ND_INS_MONITOR, ND_INS_MONITORX, - ND_INS_MONTMUL, ND_INS_MOV, ND_INS_MOVAPD, ND_INS_MOVAPS, @@ -560,10 +559,13 @@ typedef enum _ND_INS_CLASS ND_INS_PMULLW, ND_INS_PMULUDQ, ND_INS_POP, + ND_INS_POP2, + ND_INS_POP2P, ND_INS_POPA, ND_INS_POPAD, ND_INS_POPCNT, ND_INS_POPF, + ND_INS_POPP, ND_INS_POR, ND_INS_PREFETCH, ND_INS_PREFETCHE, @@ -616,9 +618,12 @@ typedef enum _ND_INS_CLASS ND_INS_PUNPCKLQDQ, ND_INS_PUNPCKLWD, ND_INS_PUSH, + ND_INS_PUSH2, + ND_INS_PUSH2P, ND_INS_PUSHA, ND_INS_PUSHAD, ND_INS_PUSHF, + ND_INS_PUSHP, ND_INS_PVALIDATE, ND_INS_PXOR, ND_INS_RCL, @@ -635,7 +640,6 @@ typedef enum _ND_INS_CLASS ND_INS_RDPRU, ND_INS_RDRAND, ND_INS_RDSEED, - ND_INS_RDSHR, ND_INS_RDTSC, ND_INS_RDTSCP, ND_INS_RETF, @@ -650,14 +654,11 @@ typedef enum _ND_INS_CLASS ND_INS_ROUNDPS, ND_INS_ROUNDSD, ND_INS_ROUNDSS, - ND_INS_RSDC, - ND_INS_RSLDT, ND_INS_RSM, ND_INS_RSQRTPS, ND_INS_RSQRTSS, ND_INS_RSSSP, ND_INS_RSTORSSP, - ND_INS_RSTS, ND_INS_SAHF, ND_INS_SAL, ND_INS_SALC, @@ -694,7 +695,6 @@ typedef enum _ND_INS_CLASS ND_INS_SKINIT, ND_INS_SLDT, ND_INS_SLWPCB, - ND_INS_SMINT, ND_INS_SMSW, ND_INS_SPFLT, ND_INS_SQRTPD, @@ -716,9 +716,6 @@ typedef enum _ND_INS_CLASS ND_INS_SUBPS, ND_INS_SUBSD, ND_INS_SUBSS, - ND_INS_SVDC, - ND_INS_SVLDT, - ND_INS_SVTS, ND_INS_SWAPGS, ND_INS_SYSCALL, ND_INS_SYSENTER, @@ -757,6 +754,8 @@ typedef enum _ND_INS_CLASS ND_INS_UNPCKHPS, ND_INS_UNPCKLPD, ND_INS_UNPCKLPS, + ND_INS_URDMSR, + ND_INS_UWRMSR, ND_INS_V4FMADDPS, ND_INS_V4FMADDSS, ND_INS_V4FNMADDPS, @@ -1624,18 +1623,12 @@ typedef enum _ND_INS_CLASS ND_INS_WRMSRLIST, ND_INS_WRMSRNS, ND_INS_WRPKRU, - ND_INS_WRSHR, ND_INS_WRSS, ND_INS_WRUSS, ND_INS_XABORT, ND_INS_XADD, ND_INS_XBEGIN, ND_INS_XCHG, - ND_INS_XCRYPTCBC, - ND_INS_XCRYPTCFB, - ND_INS_XCRYPTCTR, - ND_INS_XCRYPTECB, - ND_INS_XCRYPTOFB, ND_INS_XEND, ND_INS_XGETBV, ND_INS_XLATB, @@ -1650,9 +1643,6 @@ typedef enum _ND_INS_CLASS ND_INS_XSAVEOPT, ND_INS_XSAVES, ND_INS_XSETBV, - ND_INS_XSHA1, - ND_INS_XSHA256, - ND_INS_XSTORE, ND_INS_XSUSLDTRK, ND_INS_XTEST, @@ -1671,6 +1661,7 @@ typedef enum _ND_INS_SET ND_SET_AMXFP16, ND_SET_AMXINT8, ND_SET_AMXTILE, + ND_SET_APX_F, ND_SET_AVX, ND_SET_AVX2, ND_SET_AVX2GATHER, @@ -1707,8 +1698,6 @@ typedef enum _ND_INS_SET ND_SET_CLZERO, ND_SET_CMPCCXADD, ND_SET_CMPXCHG16B, - ND_SET_CYRIX, - ND_SET_CYRIX_SMM, ND_SET_ENQCMD, ND_SET_F16C, ND_SET_FMA, @@ -1783,6 +1772,7 @@ typedef enum _ND_INS_SET ND_SET_UD, ND_SET_UINTR, ND_SET_UNKNOWN, + ND_SET_USER_MSR, ND_SET_VAES, ND_SET_VPCLMULQDQ, ND_SET_VTX, @@ -1805,6 +1795,7 @@ typedef enum _ND_INS_TYPE ND_CAT_AES, ND_CAT_AESKL, ND_CAT_AMX, + ND_CAT_APX, ND_CAT_ARITH, ND_CAT_AVX, ND_CAT_AVX2, @@ -1862,7 +1853,6 @@ typedef enum _ND_INS_TYPE ND_CAT_MOVDIRI, ND_CAT_MPX, ND_CAT_NOP, - ND_CAT_PADLOCK, ND_CAT_PCLMULQDQ, ND_CAT_PCONFIG, ND_CAT_POP, @@ -1898,6 +1888,7 @@ typedef enum _ND_INS_TYPE ND_CAT_UINTR, ND_CAT_UNCOND_BR, ND_CAT_UNKNOWN, + ND_CAT_USER_MSR, ND_CAT_VAES, ND_CAT_VFMA, ND_CAT_VFMAPS, diff --git a/inc/bdx86_core.h b/inc/bdx86_core.h new file mode 100644 index 0000000..0f6958d --- /dev/null +++ b/inc/bdx86_core.h @@ -0,0 +1,1675 @@ +/* + * Copyright (c) 2020 Bitdefender + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef BDX86_CORE_H +#define BDX86_CORE_H + +#include "bddisasm_types.h" +#include "bddisasm_status.h" +#include "bddisasm_version.h" + +#include "bdx86_registers.h" +#include "bdx86_constants.h" +#include "bdx86_cpuidflags.h" + + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable: 4214) // Bitfield in type other than int. +#pragma warning(disable: 4201) // Nonstandard extension used: nameless struct/union. +#endif + +// +// Preferred vendor; the disassembler will try to be smart and disassemble as much as it can, but if there are +// encoding conflicts, than an alternate vendor can be selected. Note that this has effect only on conflicting +// encodings. +// +#define ND_VEND_ANY 0 // Generic decode, include any vendor. +#define ND_VEND_INTEL 1 // Prefer Intel. +#define ND_VEND_AMD 2 // Prefer AMD. +#define ND_VEND_MAX 2 + +// +// These control what instructions should be decoded if they map onto the wide NOP space (0F 1A and 0F 1B). Those are +// tricky, because they might be NOP if the feature is disabled, but might be something else (even #UD) if the feature +// is enabled. Ergo, we allow the user to select whether said feature is on or off, so that he controls whether he +// sees the NOPs or the MPX/CET/CLDEMOTE/etc. instructions instead. +// +#define ND_FEAT_NONE 0x00 // No feature/mode enabled. +#define ND_FEAT_MPX 0x01 // MPX support enabled. +#define ND_FEAT_CET 0x02 // CET support enabled. +#define ND_FEAT_CLDEMOTE 0x04 // CLDEMOTE support enabled. +#define ND_FEAT_PITI 0x08 // PREFETCHITI support enabled. +#define ND_FEAT_APX 0x10 // APX support enabled. +#define ND_FEAT_ALL 0xFF // Decode as if all features are enabled. This is default. + +// +// Code type +// +#define ND_CODE_16 0 // 16 bit decode mode. +#define ND_CODE_32 1 // 32 bit decode mode. +#define ND_CODE_64 2 // 64 bit decode mode. + +// +// Data type +// +#define ND_DATA_16 0 // 16 bit data size. +#define ND_DATA_32 1 // 32 bit data size. +#define ND_DATA_64 2 // 64 bit data size. + +// +// Stack type +// +#define ND_STACK_16 0 // 16 bit stack size. +#define ND_STACK_32 1 // 32 bit stack size. +#define ND_STACK_64 2 // 64 bit stack size. + +// +// Addressing mode +// +#define ND_ADDR_16 0 // 16 bit addressing. +#define ND_ADDR_32 1 // 32 bit addressing. +#define ND_ADDR_64 2 // 64 bit addressing. + +// +// Operand mode/size +// +#define ND_OPSZ_16 0 // 16 bit operand size. +#define ND_OPSZ_32 1 // 32 bit operand size. +#define ND_OPSZ_64 2 // 64 bit operand size. + +// +// Vector mode/size +// +#define ND_VECM_128 0 // 128 bit vector size. +#define ND_VECM_256 1 // 256 bit vector size. +#define ND_VECM_512 2 // 512 bit vector size. + +// +// Encoding mode +// +#define ND_ENCM_LEGACY 0 // Legacy encoded instruction. +#define ND_ENCM_XOP 1 // XOP encoded instruction. +#define ND_ENCM_VEX 2 // VEX (bot 2B or 3B) encoded instruction. +#define ND_ENCM_EVEX 3 // EVEX encoded instruction. + +// +// VEX mode +// +#define ND_VEXM_2B 0 // 2B VEX prefix (0xC5). +#define ND_VEXM_3B 1 // 3B VEX prefix (0xC4). + +// +// EVEX mode +// +#define ND_EVEXM_EVEX 0 // Regular EVEX. +#define ND_EVEXM_VEX 1 // EVEX extension for VEX instructions. +#define ND_EVEXM_LEGACY 2 // EVEX extension for legacy instructions. +#define ND_EVEXM_COND 3 // EVEX extension for conditional instructions. + + +// +// Size definitions +// +#define ND_SIZE_8BIT 1 // 1 byte. +#define ND_SIZE_16BIT 2 // 1 word or 2 bytes. +#define ND_SIZE_32BIT 4 // 1 double word or 4 bytes. +#define ND_SIZE_48BIT 6 // 1 fword or 6 bytes. +#define ND_SIZE_64BIT 8 // 1 qword or 8 bytes. +#define ND_SIZE_80BIT 10 // 1 fpu word or 10 bytes. +#define ND_SIZE_112BIT 14 // FPU environment, 14 bytes. +#define ND_SIZE_128BIT 16 // 1 xmm word or 16 bytes. +#define ND_SIZE_224BIT 28 // FPU environment, 28 bytes. +#define ND_SIZE_256BIT 32 // 1 ymm word or 32 bytes. +#define ND_SIZE_384BIT 48 // 48 bytes, used for Key Locker handles. +#define ND_SIZE_512BIT 64 // 1 zmm word or 64 bytes. Used also for Key Locker handles. +#define ND_SIZE_752BIT 94 // FPU state, 94 bytes. +#define ND_SIZE_864BIT 108 // FPU state, 108 bytes. +#define ND_SIZE_4096BIT 512 // Extended state, 512 bytes. +#define ND_SIZE_1KB 1024 // Tile register, 1KB. +#define ND_SIZE_CACHE_LINE 0xFFFFFFFE // The size of a cache line. +#define ND_SIZE_UNKNOWN 0xFFFFFFFF // Unknown/invalid size. + + +typedef ND_UINT32 ND_OPERAND_SIZE; + +typedef ND_UINT32 ND_REG_SIZE; + + +// +// Prefix definitions +// +#define ND_PREFIX_G0_LOCK 0xF0 // LOCK prefix. +#define ND_PREFIX_G1_REPNE_REPNZ 0xF2 // REPNE/REPNZ prefix. +#define ND_PREFIX_G1_XACQUIRE 0xF2 // XACQUIRE prefix. +#define ND_PREFIX_G1_REPE_REPZ 0xF3 // REPE/REPZ prefix. +#define ND_PREFIX_G1_XRELEASE 0xF3 // XRELEASE prefix. +#define ND_PREFIX_G1_BND 0xF2 // BND prefix. +#define ND_PREFIX_G2_SEG_CS 0x2E // CS segment override. +#define ND_PREFIX_G2_SEG_SS 0x36 // SS segment override. +#define ND_PREFIX_G2_SEG_DS 0x3E // DS segment override. +#define ND_PREFIX_G2_SEG_ES 0x26 // ES segment override. +#define ND_PREFIX_G2_SEG_FS 0x64 // FS segment override. +#define ND_PREFIX_G2_SEG_GS 0x65 // GS segment override. +#define ND_PREFIX_G2_BR_NOT_TAKEN 0x2E // Branch not taken hint. +#define ND_PREFIX_G2_BR_TAKEN 0x3E // Branch taken hint. +#define ND_PREFIX_G2_BR_ALT 0x64 // Alternating branch hint. +#define ND_PREFIX_G2_NO_TRACK 0x3E // Do not track prefix. +#define ND_PREFIX_G3_OPERAND_SIZE 0x66 // Operand size override. +#define ND_PREFIX_G4_ADDR_SIZE 0x67 // Address size override. + +#define ND_PREFIX_REX_MIN 0x40 // First REX prefix. +#define ND_PREFIX_REX_MAX 0x4F // Last REX prefix. +#define ND_PREFIX_VEX_2B 0xC5 // 2B VEX prefix. +#define ND_PREFIX_VEX_3B 0xC4 // 3B VEX prefix. +#define ND_PREFIX_XOP 0x8F // XOP prefix. +#define ND_PREFIX_EVEX 0x62 // EVEX prefix. +#define ND_PREFIX_REX2 0xD5 // REX2 prefix. + + +// +// Instruction attributes +// +#define ND_FLAG_MODRM 0x0000000000000001 // The instruction has modrm. +#define ND_FLAG_F64 0x0000000000000002 // The operand is forced to 64 bit. Size changing prefix 0x66 is ignored. +#define ND_FLAG_D64 0x0000000000000004 // The default operand size is 64 bit. Size changing prefix 0x66 + // changes the size to 16 bit. No 32 bit version can be encoded. +#define ND_FLAG_O64 0x0000000000000008 // The instruction is available only in 64 bit mode. +#define ND_FLAG_I64 0x0000000000000010 // The instruction is invalid in 64 bit mode. +#define ND_FLAG_COND 0x0000000000000020 // The instruction has a condition code encoded in low 4 bits of the opcode. +#define ND_FLAG_RESERVED0 0x0000000000000040 // Reserved. +#define ND_FLAG_VSIB 0x0000000000000080 // The instruction uses VSIB addressing mode. +#define ND_FLAG_MIB 0x0000000000000100 // The instruction used MIB addressing mode. +#define ND_FLAG_LIG 0x0000000000000200 // L flag inside XOP/VEX/EVEX is ignored. +#define ND_FLAG_WIG 0x0000000000000400 // W flag inside XOP/VEX/EVEX is ignored. +#define ND_FLAG_3DNOW 0x0000000000000800 // The instruction is 3DNow!. The opcode is the last byte. +#define ND_FLAG_LOCKSP 0x0000000000001000 // MOV to/from CR in 16/32 bit, on AMD, extend the access to + // high 8 CRs via the LOCK prefix. +#define ND_FLAG_LOCK_SPECIAL ND_FLAG_LOCKSP +#define ND_FLAG_MMASK 0x0000000000002000 // The instruction #UDs if K0 (no mask) is used. +#define ND_FLAG_NOMZ 0x0000000000004000 // The instruction #UDs if zeroing is used on memory. +#define ND_FLAG_NOL0 0x0000000000008000 // The instruction #UDs if vector length 128 is used. +#define ND_FLAG_NOA16 0x0000000000010000 // The instruction #UDs if 16-bit addressing is used. +#define ND_FLAG_MFR 0x0000000000020000 // The Mod inside Mod R/M is forced to reg. No SIB/disp present. +#define ND_FLAG_VECTOR 0x0000000000040000 // The instruction is a SIMD instruction that operates on vector regs. +#define ND_FLAG_S66 0x0000000000080000 // Special flag for mandatory 0x66 prefix that actually changes + // the default op length. +#define ND_FLAG_BITBASE 0x0000000000100000 // The instruction uses bitbase addressing mode. +#define ND_FLAG_AG 0x0000000000200000 // The instruction is an address generator; no actual memory access. +#define ND_FLAG_SHS 0x0000000000400000 // The instruction does a shadow stack access. +#define ND_FLAG_CETT 0x0000000000800000 // The instruction is CET tracked. +#define ND_FLAG_SERIAL 0x0000000001000000 // The instruction is serializing. +#define ND_FLAG_NORIPREL 0x0000000002000000 // The instruction #UDs if RIP-relative addressing is used. +#define ND_FLAG_NO_RIP_REL ND_FLAG_NORIPREL +#define ND_FLAG_NO66 0x0000000004000000 // The instruction #UDs if 0x66 prefix is present. +#define ND_FLAG_SIBMEM 0x0000000008000000 // The instruction uses sibmem addressing (Intel AMX instructions). +#define ND_FLAG_I67 0x0000000010000000 // Ignore the 0x67 prefix in 64 bit mode (Intel MPX instructions). +#define ND_FLAG_IER 0x0000000020000000 // Ignore EVEX embedded rounding. +#define ND_FLAG_IWO64 0x0000000040000000 // Ignore VEX/EVEX.W outside 64 bit mode. It behaves as if it's 0. +#define ND_FLAG_NOREX2 0x0000000080000000 // The instruction #UDs if REX2 is present. +#define ND_FLAG_NOREP 0x0000000100000000 // The instruction #UDs if REP prefixes are present. +#define ND_FLAG_NO67 0x0000000200000000 // The instruction #UDs if 0x67 prefix is present. +#define ND_FLAG_NOV 0x0000000400000000 // The instruction #UDs if XOP/VEX/EVEX.vvvv is not logical 0. +#define ND_FLAG_NOVP 0x0000000800000000 // The instruction #UDs if EVEX.v' is not logical 0. +#define ND_FLAG_SCALABLE 0x0000001000000000 // EVEX.pp can be 0 or 1, simulating the presence of 0x66 prefix. + + + +// +// Accepted prefixes map +// +#define ND_PREF_REP 0x0001 // The instruction supports REP prefix. +#define ND_PREF_REPC 0x0002 // The instruction supports REPZ/REPNZ prefixes. +#define ND_PREF_LOCK 0x0004 // The instruction supports LOCK prefix. +#define ND_PREF_HLE 0x0008 // The instruction supports XACQUIRE/XRELEASE prefixes. +#define ND_PREF_XACQUIRE 0x0010 // The instruction supports only XACQUIRE. +#define ND_PREF_XRELEASE 0x0020 // The instruction supports only XRELEASE. +#define ND_PREF_BND 0x0040 // The instruction supports BND prefix. +#define ND_PREF_BH 0x0080 // The instruction supports branch hints. +#define ND_PREF_BHINT ND_PREF_BH +#define ND_PREF_HLEWOL 0x0100 // HLE prefix is accepted without LOCK. +#define ND_PREF_HLE_WO_LOCK ND_PREF_HLEWOL +#define ND_PREF_DNT 0x0200 // The instruction supports the DNT (Do Not Track) CET prefix. + + +// +// Accepted decorators map. These are stored per-instruction. There are also per-operand indicators for +// each decorator, where applicable. +// +#define ND_DECO_ER 0x01 // Embedded rounding is accepted. +#define ND_DECO_SAE 0x02 // Suppress all Exceptions is accepted. +#define ND_DECO_ZERO 0x04 // Zeroing is accepted. +#define ND_DECO_MASK 0x08 // Masking is accepted. +#define ND_DECO_BROADCAST 0x10 // Memory broadcast is accepted. +#define ND_DECO_ND 0x20 // New-data destination specifier accepted. +#define ND_DECO_NF 0x40 // No-Flags specifier accepted. +#define ND_DECO_ZU 0x80 // Zero-Upper semantic accepted. + + +// +// Operand access flags. +// +#define ND_ACCESS_NONE 0x00 // The operand is not accessed. +#define ND_ACCESS_READ 0x01 // The operand is read. +#define ND_ACCESS_WRITE 0x02 // The operand is written. +#define ND_ACCESS_COND_READ 0x04 // The operand is read only if some conditions are met. +#define ND_ACCESS_COND_WRITE 0x08 // The operand is written only if some conditions are met (ie: CMOVcc). +#define ND_ACCESS_ANY_READ (ND_ACCESS_READ | ND_ACCESS_COND_READ) // Any read mask. +#define ND_ACCESS_ANY_WRITE (ND_ACCESS_WRITE | ND_ACCESS_COND_WRITE) // Any write mask. +#define ND_ACCESS_PREFETCH 0x10 // The operand is prefetched. + + +// +// Condition definitions. +// +#define ND_COND_OVERFLOW 0x0 // OF +#define ND_COND_CARRY 0x2 // CF +#define ND_COND_BELOW 0x2 // CF +#define ND_COND_NOT_ABOVE_OR_EQUAL 0x2 // CF +#define ND_COND_ZERO 0x4 // ZF +#define ND_COND_EQUAL 0x4 // ZF +#define ND_COND_BELOW_OR_EQUAL 0x6 // CF | ZF +#define ND_COND_NOT_ABOVE 0x6 // CF | ZF +#define ND_COND_SIGN 0x8 // SF +#define ND_COND_PARITY 0xA // PF +#define ND_COND_LESS 0xC // SF ^ OF +#define ND_COND_LESS_OR_EQUAL 0xE // (SF ^ OF) | ZF +#define ND_COND_NOT(p) ((p) | 0x1) // Negates the predicate. + + +// +// Valid CPU modes. +// +// Group 1: ring +#define ND_MOD_R0 0x00000001 // Instruction valid in ring 0. +#define ND_MOD_R1 0x00000002 // Instruction valid in ring 1. +#define ND_MOD_R2 0x00000004 // Instruction valid in ring 2. +#define ND_MOD_R3 0x00000008 // Instruction valid in ring 3. + +// Group 2: operating mode. +#define ND_MOD_REAL 0x00000010 // Instruction valid in real mode. +#define ND_MOD_V8086 0x00000020 // Instruction valid in virtual 8086 mode. +#define ND_MOD_PROT 0x00000040 // Instruction valid in protected mode. +#define ND_MOD_COMPAT 0x00000080 // Instruction valid in compatibility mode. +#define ND_MOD_LONG 0x00000100 // Instruction valid in long mode. + +// Group 3: misc modes. +#define ND_MOD_SMM 0x00001000 // Instruction valid in System-Management Mode. +#define ND_MOD_SMM_OFF 0x00002000 // Instruction valid outside SMM. +#define ND_MOD_SGX 0x00004000 // Instruction valid in SGX enclaves. +#define ND_MOD_SGX_OFF 0x00008000 // Instruction valid outside SGX enclaves. +#define ND_MOD_TSX 0x00010000 // Instruction valid in TSX transactional regions. +#define ND_MOD_TSX_OFF 0x00020000 // Instruction valid outside TSX. + + +// Group 4: VMX +#define ND_MOD_VMXR 0x00040000 // Instruction valid in VMX Root mode. +#define ND_MOD_VMXN 0x00080000 // Instruction valid in VMX non-root mode. +#define ND_MOD_VMXR_SEAM 0x00100000 // Instruction valid in VMX root Secure Arbitration Mode. +#define ND_MOD_VMXN_SEAM 0x00200000 // Instruction valid in VMX non-root Secure Arbitration Mode. +#define ND_MOD_VMX_OFF 0x00400000 // Instruction valid outside VMX operation. + +#define ND_MOD_RING_MASK 0x0000000F // Valid ring mask. +#define ND_MOD_MODE_MASK 0x000001F0 // Valid mode mask. +#define ND_MOD_OTHER_MASK 0x0003F000 // Misc mask. +#define ND_MOD_VMX_MASK 0x007C0000 // VMX mask. + +// For instructions valid in any operating mode. +#define ND_MOD_ANY 0xFFFFFFFF // Instruction valid in any mode. + + +// +// Misc constants +// +#define ND_MAX_INSTRUCTION_LENGTH 15 // 15 bytes is the maximum instruction length supported by the x86 arch. +#define ND_MAX_MNEMONIC_LENGTH 32 // Should do for now. +#define ND_MIN_BUF_SIZE 128 // Textual disassembly minimal buffer size. +#define ND_MAX_OPERAND 10 // No more than 10 operands/instruction, but I'm generous. +#define ND_MAX_REGISTER_SIZE 64 // Maximum register size - 64 bytes. +#define ND_MAX_GPR_REGS 32 // Max number of GPRs. +#define ND_MAX_SEG_REGS 8 // Max number of segment registers. +#define ND_MAX_FPU_REGS 8 // Max number of FPU registers. +#define ND_MAX_MMX_REGS 8 // Max number of MMX registers. +#define ND_MAX_SSE_REGS 32 // Max number of SSE registers. +#define ND_MAX_CR_REGS 32 // Max number of control registers. +#define ND_MAX_DR_REGS 32 // Max number of debug registers. +#define ND_MAX_TR_REGS 16 // Max number of test registers. +#define ND_MAX_MSK_REGS 8 // Max number of mask registers. +#define ND_MAX_BND_REGS 4 // Max number of bound registers. +#define ND_MAX_SYS_REGS 8 // Max number of system registers. +#define ND_MAX_X87_REGS 8 // Max number of x87 state/control registers registers. +#define ND_MAX_TILE_REGS 8 // Max number of tile registers. + + + +// +// Misc macros. +// + +// Sign extend 8 bit to 64 bit. +#define ND_SIGN_EX_8(x) (((x) & 0x00000080) ? (0xFFFFFFFFFFFFFF00 | (x)) : ((x) & 0xFF)) +// Sign extend 16 bit to 64 bit. +#define ND_SIGN_EX_16(x) (((x) & 0x00008000) ? (0xFFFFFFFFFFFF0000 | (x)) : ((x) & 0xFFFF)) +// Sign extend 32 bit to 64 bit. +#define ND_SIGN_EX_32(x) (((x) & 0x80000000) ? (0xFFFFFFFF00000000 | (x)) : ((x) & 0xFFFFFFFF)) +// Wrapper for for ND_SIGN_EX_8/ND_SIGN_EX_16/ND_SIGN_EX_32. Sign extend sz bytes to 64 bits. +#define ND_SIGN_EX(sz, x) ((sz) == 1 ? ND_SIGN_EX_8(x) : (sz) == 2 ? ND_SIGN_EX_16(x) : \ + (sz) == 4 ? ND_SIGN_EX_32(x) : (x)) +// Trim 64 bits to sz bytes. +#define ND_TRIM(sz, x) ((sz) == 1 ? (x) & 0xFF : (sz) == 2 ? (x) & 0xFFFF : \ + (sz) == 4 ? (x) & 0xFFFFFFFF : (x)) +// Returns most significant bit, given size in bytes sz. +#define ND_MSB(sz, x) ((sz) == 1 ? ((x) >> 7) & 1 : (sz) == 2 ? ((x) >> 15) & 1 : \ + (sz) == 4 ? ((x) >> 31) & 1 : ((x) >> 63) & 1) +// Returns least significant bit. +#define ND_LSB(sz, x) ((x) & 1) +// Convert a size in bytes to a bitmask. +#define ND_SIZE_TO_MASK(sz) (((sz) < 8) ? ((1ULL << ((sz) * 8)) - 1) : (0xFFFFFFFFFFFFFFFF)) +// Get bit at position bit from x. +#define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1) +// Return the sign of sz bytes long value x. +#define ND_GET_SIGN(sz, x) ND_MSB(sz, x) +// Sets the sign of the sz bytes long value x. +#define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x) + +#ifdef BIG_ENDIAN +#define ND_FETCH_64(b) ((ND_UINT64)ND_FETCH_32((char *)b) | ((ND_UINT64)ND_FETCH_32((char *)b + 4) << 32)) +#define ND_FETCH_32(b) ((ND_UINT32)ND_FETCH_16((char *)b) | ((ND_UINT32)ND_FETCH_16((char *)b + 2) << 16)) +#define ND_FETCH_16(b) ((((char *)b)[0]) | (((char *)b)[1] << 8)) +#define ND_FETCH_8(b) (*((char *)b)) +#else +#define ND_FETCH_64(b) (*((ND_UINT64 *)(b))) +#define ND_FETCH_32(b) (*((ND_UINT32 *)(b))) +#define ND_FETCH_16(b) (*((ND_UINT16 *)(b))) +#define ND_FETCH_8(b) (*((ND_UINT8 *)(b))) +#endif + + +// +// Helper macros which simply test the presence of various ND_FLAG_* in the instruction attributes. +// +#define ND_IS_3DNOW(ix) (!!((ix)->Attributes & ND_FLAG_3DNOW)) +#define ND_HAS_CONDITION(ix) (!!((ix)->Attributes & ND_FLAG_COND)) +#define ND_HAS_MODRM(ix) (!!((ix)->Attributes & ND_FLAG_MODRM)) +#define ND_HAS_VSIB(ix) (!!((ix)->Attributes & ND_FLAG_VSIB)) +#define ND_HAS_MIB(ix) (!!((ix)->Attributes & ND_FLAG_MIB)) +#define ND_HAS_VECTOR(ix) (!!((ix)->Attributes & ND_FLAG_VECTOR)) +#define ND_HAS_BITBASE(ix) (!!((ix)->Attributes & ND_FLAG_BITBASE)) +#define ND_HAS_AG(ix) (!!((ix)->Attributes & ND_FLAG_AG)) +#define ND_HAS_SIBMEM(ix) (!!((ix)->Attributes & ND_FLAG_SIBMEM)) +#define ND_HAS_SHS(ix) (!!((ix)->Attributes & ND_FLAG_SHS)) +#define ND_HAS_CETT(ix) (!!((ix)->Attributes & ND_FLAG_CETT)) + +// +// Supported prefixes macros. +// +#define ND_REP_SUPPORT(ix) (!!((ix)->ValidPrefixes.Rep)) +#define ND_REPC_SUPPORT(ix) (!!((ix)->ValidPrefixes.RepCond)) +#define ND_LOCK_SUPPORT(ix) (!!((ix)->ValidPrefixes.Lock)) +#define ND_HLE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Hle)) +#define ND_XACQUIRE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xacquire)) +#define ND_XRELEASE_SUPPORT(ix) (!!((ix)->ValidPrefixes.Xrelease)) +#define ND_BND_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bnd)) +#define ND_BHINT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Bhint)) +#define ND_DNT_SUPPORT(ix) (!!((ix)->ValidPrefixes.Dnt)) + +// +// Decorators map macros. +// +#define ND_DECORATOR_SUPPORT(ix) ((ix)->ValidDecorators.Raw != 0) +#define ND_MASK_SUPPORT(ix) (!!((ix)->ValidDecorators.Mask)) +#define ND_ZERO_SUPPORT(ix) (!!((ix)->ValidDecorators.Zero)) +#define ND_ER_SUPPORT(ix) (!!((ix)->ValidDecorators.Er)) +#define ND_SAE_SUPPORT(ix) (!!((ix)->ValidDecorators.Sae)) +#define ND_BROADCAST_SUPPORT(ix) (!!((ix)->ValidDecorators.Broadcast)) + +// Generates a unique ID per register type, size and reg. The layout is the following: +// - bits [63, 60] (4 bits) - the operand type (ND_OP_REG) +// - bits [59, 52] (8 bits) - the register type +// - bits [51, 36] (16 bits) - the register size, in bytes +// - bits [35, 30] (6 bits) - the number of registers accessed starting with this reg (for block addressing) +// - bits [29, 9] (21 bits) - reserved +// - bit 8 - High8 indicator: indicates whether the reg is AH/CH/DH/BH +// - bits [7, 0] (8 bits) - the register ID +#define ND_OP_REG_ID(op) (((ND_UINT64)((op)->Type & 0xF) << 60) | \ + ((ND_UINT64)((op)->Info.Register.Type & 0xFF) << 52) | \ + ((ND_UINT64)((op)->Info.Register.Size & 0xFFFF) << 36) | \ + ((ND_UINT64)((op)->Info.Register.Count & 0x3F) << 30) | \ + ((ND_UINT64)((op)->Info.Register.IsHigh8 & 0x1) << 8) | \ + ((ND_UINT64)((op)->Info.Register.Reg))) + +// Example: ND_IS_OP_REG(op, ND_REG_GPR, 4, REG_ESP) +// Example: ND_IS_OP_REG(op, ND_REG_CR, 8, REG_CR3) +// Example: ND_IS_OP_REG(op, ND_REG_RIP, 8, 0) + +// Checks if the indicated operand op is a register of type t, with size s and index r. +#define ND_IS_OP_REG(op, t, s, r) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \ + ((ND_UINT64)((t) & 0xFF) << 52) | \ + ((ND_UINT64)((s) & 0xFFFF) << 36) | \ + ((ND_UINT64)(1) << 30) | \ + ((ND_UINT64)(r)))) + +// Checks if the indicated operand op is a register of type t, with size s and index r. +#define ND_IS_OP_REG_EX(op, t, s, r, b, h) (ND_OP_REG_ID(op) == (((ND_UINT64)(ND_OP_REG) << 60) | \ + ((ND_UINT64)((t) & 0xFF) << 52) | \ + ((ND_UINT64)((s) & 0xFFFF) << 36) | \ + ((ND_UINT64)((b) & 0x3F) << 30) | \ + ((ND_UINT64)((h) & 0x1) << 8) | \ + ((ND_UINT64)(r)))) + +// Checjs if the indicated operand is the stack. +#define ND_IS_OP_STACK(op) ((op)->Type == ND_OP_MEM && (op)->Info.Memory.IsStack) + + +// +// Operand types. +// +typedef enum _ND_OPERAND_TYPE +{ + ND_OP_NOT_PRESENT, // Indicates the absence of any operand. + ND_OP_REG, // The operand is a register. + ND_OP_MEM, // The operand is located in memory. + ND_OP_IMM, // The operand is an immediate. + ND_OP_OFFS, // The operand is a relative offset. + ND_OP_ADDR, // The operand is an absolute far address, in the form seg:offset. + ND_OP_ADDR_FAR = ND_OP_ADDR, + ND_OP_ADDR_NEAR, // The operand is an absolute near address, in the form target64. + ND_OP_CONST, // The operand is an implicit constant. + ND_OP_BANK, // An entire bank/set of registers are being accessed. Used in PUSHA/POPA/XSAVE/LOADALL. + ND_OP_DFV, // The operand is dfv (default flags value). +} ND_OPERAND_TYPE; + + +// +// Register types. +// +typedef enum _ND_REG_TYPE +{ + ND_REG_NOT_PRESENT, + ND_REG_GPR, // The register is a 8/16/32/64 bit general purpose register. + ND_REG_SEG, // The register is a segment register. + ND_REG_FPU, // The register is a 80-bit FPU register. + ND_REG_MMX, // The register is a 64-bit MMX register. + ND_REG_SSE, // The register is a 128/256/512 bit SSE vector register. + ND_REG_CR, // The register is a control register. + ND_REG_DR, // The register is a debug register. + ND_REG_TR, // The register is a test register. + ND_REG_BND, // The register is a bound register. + ND_REG_MSK, // The register is a mask register. + ND_REG_TILE, // The register is a tile register. + ND_REG_MSR, // The register is a model specific register. + ND_REG_XCR, // The register is a extended control register. + ND_REG_SYS, // The register is a system register. + ND_REG_X87, // The register is a x87 status/control register. + ND_REG_MXCSR, // The register is the MXCSR register. + ND_REG_PKRU, // The register is the PKRU register. + ND_REG_SSP, // The register is the SSP (Shadow Stack Pointer) register. + ND_REG_FLG, // The register is the FLAGS register. + ND_REG_RIP, // The register is the instruction pointer register. + ND_REG_UIF, // The register is the User Interrupt Flag. +} ND_REG_TYPE; + + +// +// Operand encoding types. +// +typedef enum _ND_OPERAND_ENCODING +{ + ND_OPE_NP, // No encoding present. + ND_OPE_R, // Operand encoded in modrm.reg. + ND_OPE_M, // Operand encoded in modrm.rm. + ND_OPE_V, // Operand encoded in Xop/Vex/Evex/Mvex.(v')vvvv + ND_OPE_D, // Operand is encoded inside subsequent instruction bytes. + ND_OPE_O, // Operand is encoded in low 3 bit of the opcode. + ND_OPE_I, // Operand is an immediate. + ND_OPE_C, // Operand is CL. + ND_OPE_1, // Operand is 1. + ND_OPE_L, // Operand is reg encoded in immediate. + ND_OPE_A, // Operand is encoded in Evex.aaa. + ND_OPE_E, // Operand is a MSR or XCR encoded in ECX register. + ND_OPE_S, // Operand is implicit/suppressed. Not encoded anywhere. +} ND_OPERAND_ENCODING; + + +// +// Instruction tuple type; used to determine compressed displacement size for disp8 EVEX instructions. Note that +// most of the EVEX encoded instructions use the compressed displacement addressing scheme. +// +typedef enum _ND_TUPLE +{ + ND_TUPLE_None, + ND_TUPLE_FV, // Full Vector + ND_TUPLE_HV, // Half Vector + ND_TUPLE_QV, // Quarter Vector + ND_TUPLE_T1S8, // Tuple1 scalar, size 8 bit + ND_TUPLE_T1S16, // Tuple1 scalar, size 16 bit + ND_TUPLE_T1S, // Tuple1 scalar, size 32/64 bit + ND_TUPLE_T1F, // Tuple1 float, size 32/64 bit + ND_TUPLE_T2, // Tuple2, 64/128 bit + ND_TUPLE_T4, // Tuple4, 128/256 bit + ND_TUPLE_T8, // Tuple8, 256 bit + ND_TUPLE_FVM, // Full Vector Memory + ND_TUPLE_HVM, // Half Vector Memory + ND_TUPLE_QVM, // Quarter Vector Memory + ND_TUPLE_OVM, // Oct Vector Memory + ND_TUPLE_M128, // M128, 128 bit + ND_TUPLE_DUP, // DUP (VMOVDDUP) + ND_TUPLE_T1_4X, // 4 x 32 bit Memory Elements are referenced +} ND_TUPLE; + + +// +// EVEX rounding control. +// +typedef enum _ND_ROUNDING +{ + ND_RND_RNE, // Round to nearest equal. + ND_RND_RD, // Round down. + ND_RND_RU, // Round up. + ND_RND_RZ, // round to zero. +} ND_ROUNDING; + +// +// Exception types. +// +typedef enum _ND_EX_TYPE +{ + ND_EXT_None, + + // SSE/AVX exceptions. + ND_EXT_1, + ND_EXT_2, + ND_EXT_3, + ND_EXT_4, + ND_EXT_5, + ND_EXT_6, + ND_EXT_7, + ND_EXT_8, + ND_EXT_9, + ND_EXT_10, + ND_EXT_11, + ND_EXT_12, + ND_EXT_13, + ND_EXT_14, + + // Opmask exceptios. + ND_EXT_K20, + ND_EXT_K21, + + // EVEX exceptions. + ND_EXT_E1, + ND_EXT_E1NF, + ND_EXT_E2, + ND_EXT_E3, + ND_EXT_E3NF, + ND_EXT_E4, + ND_EXT_E4S, // E4, with an additional case: if (dst == src1) or (dst == src2) + ND_EXT_E4nb, + ND_EXT_E4NF, + ND_EXT_E4NFnb, + ND_EXT_E5, + ND_EXT_E5NF, + ND_EXT_E6, + ND_EXT_E6NF, + ND_EXT_E7NM, + ND_EXT_E9, + ND_EXT_E9NF, + ND_EXT_E10, + ND_EXT_E10S, // E10, with an additional case: if (dst == src1) or (dst == src2) + ND_EXT_E10NF, + ND_EXT_E11, + ND_EXT_E12, + ND_EXT_E12NP, + + // AMX exceptions. + ND_EXT_AMX_E1, + ND_EXT_AMX_E2, + ND_EXT_AMX_E3, + ND_EXT_AMX_E4, + ND_EXT_AMX_E5, + ND_EXT_AMX_E6, + + // AMX-EVEX exceptions. + ND_EXT_AMX_EVEX_E1, + ND_EXT_AMX_EVEX_E2, + ND_EXT_AMX_EVEX_E3, + + // APX-EVEX exceptions. + ND_EXT_APX_EVEX_BMI, + ND_EXT_APX_EVEX_CCMP, + ND_EXT_APX_EVEX_WRSS, + ND_EXT_APX_EVEX_WRUSS, + ND_EXT_APX_EVEX_CFCMOV, + ND_EXT_APX_EVEX_CMPCCXADD, + ND_EXT_APX_EVEX_ENQCMD, + ND_EXT_APX_EVEX_INT, + ND_EXT_APX_EVEX_INVEPT, + ND_EXT_APX_EVEX_INVPCID, + ND_EXT_APX_EVEX_INVVPID, + ND_EXT_APX_EVEX_KEYLOCKER, + ND_EXT_APX_EVEX_KMOV, + ND_EXT_APX_EVEX_PP2, + ND_EXT_APX_EVEX_RAOINT, + ND_EXT_APX_EVEX_SHA, + ND_EXT_APX_EVEX_USER_MSR, +} ND_EX_TYPE; + + +// +// Operand access mode. +// +typedef union _ND_OPERAND_ACCESS +{ + ND_UINT8 Access; + struct + { + ND_UINT8 Read : 1; // The operand is read. + ND_UINT8 Write : 1; // The operand is written. + ND_UINT8 CondRead : 1; // The operand is read only under some conditions. + ND_UINT8 CondWrite : 1; // The operand is written only under some conditions. + ND_UINT8 Prefetch : 1; // The operand is prefetched. + }; +} ND_OPERAND_ACCESS; + + +// +// Operand flags. +// +typedef union _ND_OPERAND_FLAGS +{ + ND_UINT8 Flags; + struct + { + ND_UINT8 IsDefault : 1; // 1 if the operand is default. This also applies to implicit ops. + ND_UINT8 SignExtendedOp1 : 1; // 1 if the operand is sign extended to the first operands' size. + ND_UINT8 SignExtendedDws : 1; // 1 if the operand is sign extended to the default word size. + }; +} ND_OPERAND_FLAGS; + + +// +// Constant operand. +// +typedef struct _ND_OPDESC_CONSTANT +{ + ND_UINT64 Const; // Instruction constant, ie ROL reg, 1. +} ND_OPDESC_CONSTANT; + + +// +// Immediate operand. +// +typedef struct _ND_OPDESC_IMMEDIATE +{ + ND_UINT64 Imm; // Immediate. Only Size bytes are valid. The rest are undefined. + ND_UINT8 RawSize; // Raw size (how many bytes are encoded in the instruction). +} ND_OPDESC_IMMEDIATE; + + +// +// Relative offset operand. +// +typedef struct _ND_OPDESC_REL_OFFSET +{ + ND_UINT64 Rel; // Relative offset (relative to the current RIP). Sign extended. + ND_UINT8 RawSize; // Raw size (how many bytes are encoded in the instruction). +} ND_OPDESC_RELOFFSET; + + +// +// Describes a register operand. Count registers are used starting with Reg. +// +typedef struct _ND_OPDESC_REGISTER +{ + ND_REG_TYPE Type; // The register type. See enum ND_REG_TYPE. + ND_REG_SIZE Size; // Indicates the register size. This may not be equal to the Size + // field, as a smaller amount of data may be processed from a + // register (especially if we have a SSE register or a mask register). + // Also note that as of now, 64 bytes is the maximum register size. + ND_UINT32 Reg; // The register number/ID. + ND_UINT8 Count; // The number of registers accessed, starting with Reg. + + ND_UINT8 IsHigh8:1; // TRUE if this is AH, CH, DH or BH register. + ND_UINT8 IsBlock:1; // TRUE if this is a block register addressing. + ND_UINT8 IsZeroUpper:1; // TRUE if the upper register is zeroed. +} ND_OPDESC_REGISTER; + + +// +// Describes a seg:offset absolute effective address. +// +typedef struct _ND_OPDESC_ADDRESS +{ + // Size is the size of the address. Usually 4 (16 bit mode) or 6 (32 bit mode) or 10 (64 bit). + ND_UINT64 Offset; // Offset inside the segment. + ND_UINT16 BaseSeg; // Base segment selector of the address. +} ND_OPDESC_ADDRESS, ND_OPDESC_ADDRESS_FAR; + + +// +// Describes a 64-bit absolute effective address. +// +typedef struct _ND_OPDESC_ADDRESS_NEAR +{ + ND_UINT64 Target; // Absolue 64-bit target address. +} ND_OPDESC_ADDRESS_NEAR; + + +// +// Shadow stack access types. +// +typedef enum _ND_SHSTK_ACCESS +{ + ND_SHSTK_NONE = 0, + ND_SHSTK_EXPLICIT, // Explicit memory operand accessed as shadow stack. + ND_SHSTK_SSP_LD_ST, // Shadow Stack Pointer (SSP) used as base for addressing using conventional load/store. + ND_SHSTK_SSP_PUSH_POP, // Shadow Stack Pointer (SSP) used as base for addressing using push/pop. + ND_SHSTK_PL0_SSP, // Privilege 0 SSP (IA32_PL0_SSP) used (SETSSBSY). +} ND_SHSTK_ACCESS; + + +// +// Describes a memory operand. +// +typedef struct _ND_OPDESC_MEMORY +{ + ND_BOOL HasSeg:1; // TRUE if segment is present & used. + ND_BOOL HasBase:1; // TRUE if base register is present. + ND_BOOL HasIndex:1; // TRUE if index & scale are present. + ND_BOOL HasDisp:1; // TRUE if displacement is present. + ND_BOOL HasCompDisp:1; // TRUE if compressed disp8 is used (EVEX instructions). + ND_BOOL HasBroadcast:1; // TRUE if the memory operand is a broadcast operand. + + ND_BOOL IsRipRel:1; // TRUE if this is a rip-relative addressing. Base, Index, Scale are + // all ignored. + ND_BOOL IsStack:1; // TRUE if this is a stack op. Note that explicit stack accesses are not + // included (eg: mov eax, [rsp] will NOT set IsStack). + ND_BOOL IsString:1; // TRUE for [RSI] and [RDI] operands inside string operations. + ND_BOOL IsShadowStack:1; // TRUE if this is a shadow stack access. Check out ShStkType for more info. + ND_BOOL IsDirect:1; // TRUE if direct addressing (MOV [...], EAX, 0xA3). + ND_BOOL IsBitbase:1; // TRUE if this is a bit base. Used for BT* instructions. The bitbase + // stored in the second operand must be added to the linear address. + ND_BOOL IsAG:1; // TRUE if the memory operand is address generation and no mem access is + // made. + ND_BOOL IsMib:1; // TRUE if MIB addressing is used (MPX instructions). + ND_BOOL IsVsib:1; // TRUE if the index register selects a vector register. + ND_BOOL IsSibMem:1; // TRUE if the addressing uses sibmem (AMX instructions). + + ND_UINT8 BaseSize; // Base size, in bytes. Max 8 bytes. + ND_UINT8 IndexSize; // Ditto for index size. Max 64 bytes for VSIB. + ND_UINT8 DispSize; // Displacement size. Max 4 bytes. + ND_UINT8 CompDispSize; // Compressed displacement size - 1, 2, 4, 8, 16, 32, 64. + + ND_UINT8 ShStkType; // Shadow stack access type. Check out ND_SHSTK_ACCESS. + + union + { + struct + { + ND_UINT8 IndexSize; // VSIB index size. + ND_UINT8 ElemSize; // VSIB element size. + ND_UINT8 ElemCount; // Number of elements scattered/gathered/prefetched. + } Vsib; // Valid if HasVsib is set. + + struct + { + ND_UINT8 Count; // Number of times to broadcast the element. + ND_UINT8 Size; // Size of one element. + } Broadcast; // Valid if HasBroadcast is set. + }; + + ND_UINT8 Seg:3; // Base segment used to address the memory. 0 = es, 1 = cs, etc. + ND_UINT8 Base:5; // Base register. Can only be a GPR. + ND_UINT8 Index; // Index register. Can be a vector reg (ZMM0-ZMM31). + ND_UINT8 Scale:4; // Scale: 1, 2, 4 or 8. Always present if Index is present. + + ND_UINT64 Disp; // Sign extended displacement. + +} ND_OPDESC_MEMORY; + + +// +// Describes a Default Flags Value operand. +// +typedef struct _ND_OPDESC_DEFAULT_FLAGS +{ + ND_UINT8 CF:1; + ND_UINT8 ZF:1; + ND_UINT8 SF:1; + ND_UINT8 OF:1; +} ND_OPDESC_DEFAULT_FLAGS; + + +// +// Describes a decorator that applies to an operand. +// +typedef struct _ND_OPERAND_DECORATOR +{ + ND_BOOL HasMask:1; // TRUE if mask is present, 0 otherwise. + ND_BOOL HasZero:1; // TRUE if zeroing will be made, 0 if merging will be made. + ND_BOOL HasBroadcast:1; // TRUE if broadcasting is being made. Valid only for memory operands. + + // Mask register specifier. + ND_UINT8 Msk:3; // Mask register used. Only k0-k7 can be encoded. + +} ND_OPERAND_DECORATOR; + + +// +// Extended operand information. +// +typedef struct _ND_OPERAND +{ + ND_UINT8 Type:4; // Operand type. One of ND_OPERAND_TYPE enumerations. + ND_UINT8 Encoding:4; // Where is the operand encoded. One of ND_OPERAND_ENCODING enumerations. + ND_OPERAND_ACCESS Access; // Access mode (read, write, read-write, etc.) + ND_OPERAND_FLAGS Flags; // Misc operand flags. + ND_OPERAND_DECORATOR Decorator; // Decorator information. + ND_OPERAND_SIZE Size; // Operand size in bytes. This should be used when operating with + // the operand. It includes sign-extension or zero-extensions. + // Note that the Size field indicates the actual amount of data + // used for processing. If the operand type is a register, it MAY NOT + // indicate the register size. Use the Info.Register.Size + // field to get the actual register size. + + // Depending in the Type field, one of these subfields contains information about the operand. + // Althoug Immediate, RelativeOffset & Address are all immediate payloads, they are kept separate, due + // the slightly different semantic: + // 1. Immediate is a plain immediate quantity + // 2. RelativeOffset is an immediate added to the instruction pointer + // 3. Address is an mmediate formed formed of a segment:offset pair + union + { + ND_OPDESC_REGISTER Register; // Register, if operand type if ND_OP_REG. + ND_OPDESC_MEMORY Memory; // Memory, if operand type is ND_OP_MEM. + ND_OPDESC_IMMEDIATE Immediate; // Immediate, if operand type is ND_OP_IMM. + ND_OPDESC_RELOFFSET RelativeOffset; // Relative offset, if operand type is ND_OP_REL_OFFS. + ND_OPDESC_ADDRESS_FAR Address; // Address, seg:offset form, if operand type is ND_OP_ADDR. + ND_OPDESC_ADDRESS_NEAR AddressNear; // Address, target64 form, if operand type is ND_OP_ADDR_NEAR. + ND_OPDESC_CONSTANT Constant; // Constant, if operand type is ND_OP_CONST. + ND_OPDESC_DEFAULT_FLAGS DefaultFlags; // Default flags value, if operand type is ND_OP_DFV. + } Info; + +} ND_OPERAND, *PND_OPERAND; + + +// +// REX prefix. +// +typedef union _ND_REX +{ + ND_UINT8 Rex; + struct + { + ND_UINT8 b : 1; // b (rm or low opcode) extension field. + ND_UINT8 x : 1; // x (index) extension field. + ND_UINT8 r : 1; // r (reg) extension field. + ND_UINT8 w : 1; // w (size) extension field. Promotes to 64 bit. + }; +} ND_REX; + +// +// REX2 prefix. +// +typedef union _ND_REX2 +{ + ND_UINT8 Rex2[2]; + struct + { + ND_UINT8 op; // 0xD5 + + ND_UINT8 b3 : 1; // B3 (rm or low opcode) extension field. + ND_UINT8 x3 : 1; // X3 (index) extension field. + ND_UINT8 r3 : 1; // R3 (reg) extension field. + ND_UINT8 w : 1; // W (size) extension field. Promotes to 64 bit. + ND_UINT8 b4 : 1; // B4 (rm or low opcode) extension field. + ND_UINT8 x4 : 1; // X4 (index) extension field. + ND_UINT8 r4 : 1; // R4 (reg) extension field. + ND_UINT8 m0 : 1; // M0 map ID. + }; +} ND_REX2; + +// +// Mod R/M byte. +// +typedef union _ND_MODRM +{ + ND_UINT8 ModRm; + struct + { + ND_UINT8 rm : 3; // rm field. + ND_UINT8 reg : 3; // reg field. + ND_UINT8 mod : 2; // mod field. Indicates memory access (0, 1 or 2), or register access (3). + }; +} ND_MODRM; + +// +// SIB byte. +// +typedef union _ND_SIB +{ + ND_UINT8 Sib; + struct + { + ND_UINT8 base : 3; // Base register. + ND_UINT8 index : 3; // Index register. + ND_UINT8 scale : 2; // Scale. + }; +} ND_SIB; + +// +// 2-bytes VEX. Exactly as Intel defined it. +// +typedef union _ND_VEX2 +{ + ND_UINT8 Vex[2]; + struct + { + ND_UINT8 op; // 0xC5 + + ND_UINT8 p : 2; // p0, p1 + ND_UINT8 l : 1; // L + ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 + ND_UINT8 r : 1; // ~R + }; +} ND_VEX2; + + +// +// 3-bytes VEX. Exactly as Intel defined it. +// +typedef union _ND_VEX3 +{ + ND_UINT8 Vex[3]; + struct + { + ND_UINT8 op; // 0xC4 + + ND_UINT8 m : 5; // m0, m1, m2, m3, m4 + ND_UINT8 b : 1; // ~B + ND_UINT8 x : 1; // ~X + ND_UINT8 r : 1; // ~R + + ND_UINT8 p : 2; // p0, p1 + ND_UINT8 l : 1; // L + ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 + ND_UINT8 w : 1; // W + }; +} ND_VEX3; + + +// +// XOP. Exactly as AMD defined it. +// +typedef union _ND_XOP +{ + ND_UINT8 Xop[3]; + struct + { + ND_UINT8 op; // 0x8F + + ND_UINT8 m : 5; // m0, m1, m2, m3, m4 + ND_UINT8 b : 1; // ~B + ND_UINT8 x : 1; // ~X + ND_UINT8 r : 1; // ~R + + ND_UINT8 p : 2; // p0, p1 + ND_UINT8 l : 1; // L + ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 + ND_UINT8 w : 1; // W + }; +} ND_XOP; + + +// +// EVEX prefix. Exactly as Intel defined it. +// +typedef union _ND_EVEX +{ + ND_UINT8 Evex[4]; + struct + { + ND_UINT8 op; // 0x62 + + ND_UINT8 m : 3; // m0, m1, m2. Indicates opcode map. + ND_UINT8 b4 : 1; // B4 (repurposed from a hard-coded 0 bit). + ND_UINT8 rp : 1; // ~R' or ~R4 + ND_UINT8 b : 1; // ~B or ~B3 + ND_UINT8 x : 1; // ~X or ~X3 + ND_UINT8 r : 1; // ~R or ~R3 + + ND_UINT8 p : 2; // p0, p1 + ND_UINT8 x4 : 1; // ~X4 (repurposed from a hard-coded 1 bit). + ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3 + ND_UINT8 w : 1; // W + + ND_UINT8 a : 3; // a0, a1, a2 + ND_UINT8 vp : 1; // ~V' + ND_UINT8 bm : 1; // b + ND_UINT8 l : 2; // L'L + ND_UINT8 z : 1; // z + }; +} ND_EVEX; + + +// +// Describes the CPUID leaf, sub-leaf, register & bit that indicate whether an instruction is supported or not. +// If Leaf == ND_CFF_NO_LEAF, the instruction is supported on any CPU, and no CPUID flag exists. +// If SubLeaf == ND_CFF_NO_SUBLEAF, there is no subleaf to check. +// +typedef union _ND_CPUID_FLAG +{ + ND_UINT64 Flag; + struct + { + ND_UINT32 Leaf; // CPUID leaf. ND_CFF_NO_LEAF if not applicable. + ND_UINT32 SubLeaf : 24; // CPUID sub-leaf. ND_CFF_NO_SUBLEAF if not applicable. + ND_UINT32 Reg : 3; // The register that contains info regarding the instruction. + ND_UINT32 Bit : 5; // Bit inside the register that indicates whether the instruction is present. + }; +} ND_CPUID_FLAG; + + +// +// Each instruction may accept one or more prefixes. This structure indicates which prefixes are valid for the +// given instruction. +// +typedef union _ND_VALID_PREFIXES +{ + ND_UINT16 Raw; + struct + { + ND_UINT16 Rep : 1; // The instruction supports REP prefix. + ND_UINT16 RepCond : 1; // The instruction supports REPZ/REPNZ prefixes. + ND_UINT16 Lock : 1; // The instruction supports LOCK prefix. + ND_UINT16 Hle : 1; // The instruction supports XACQUIRE/XRELEASE prefixes. + ND_UINT16 Xacquire : 1; // The instruction supports only XACQUIRE. + ND_UINT16 Xrelease : 1; // The instruction supports only XRELEASE. + ND_UINT16 Bnd : 1; // The instruction supports BND prefix. + ND_UINT16 Bhint : 1; // The instruction supports branch hints. + ND_UINT16 HleNoLock : 1; // HLE prefix is accepted without LOCK. + ND_UINT16 Dnt : 1; // The instruction supports the DNT (Do Not Track) CET prefix. + }; +} ND_VALID_PREFIXES, *PND_VALID_PREFIXES; + + +// +// Each instruction may accept several decorators. This instruction indicates which decorators are valid for the +// given instruction. +// +typedef union _ND_VALID_DECORATORS +{ + ND_UINT8 Raw; + struct + { + ND_UINT8 Er : 1; // The instruction supports embedded rounding mode. + ND_UINT8 Sae : 1; // The instruction supports suppress all exceptions mode. + ND_UINT8 Zero : 1; // The instruction supports zeroing. + ND_UINT8 Mask : 1; // The instruction supports mask registers. + ND_UINT8 Broadcast : 1; // The instruction supports broadcast. + ND_UINT8 Nd : 1; // The instruction supports new data destination. + ND_UINT8 Nf : 1; // The instruction supports no-flags update. + ND_UINT8 Zu : 1; // The instruction supports zero-upper semantic. + }; +} ND_VALID_DECORATORS, *PND_VALID_DECORATORS; + + +// +// Each instruction is valid or invalid in any certain mode. This indicates which modes the instruction is valid in. +// If the bit is set, the isntruction is valid in that given mode. +// +typedef union _ND_VALID_MODES +{ + ND_UINT32 Raw; + struct + { + // Group 1: privilege level. + ND_UINT32 Ring0 : 1; // The instruction is valid in ring 0. + ND_UINT32 Ring1 : 1; // The instruction is valid in ring 1. + ND_UINT32 Ring2 : 1; // The instruction is valid in ring 2. + ND_UINT32 Ring3 : 1; // The instruction is valid in ring 3. + + // Group 2: operating mode - the CPU can be on only one of these modes at any moment. + ND_UINT32 Real : 1; // The instruction is valid in real mode. + ND_UINT32 V8086 : 1; // The instruction is valid in Virtual 8086 mode. + ND_UINT32 Protected : 1; // The instruction is valid in protected mode (32 bit). + ND_UINT32 Compat : 1; // The instruction is valid in compatibility mode (32 bit in 64 bit). + ND_UINT32 Long : 1; // The instruction is valid in long mode. + + ND_UINT32 Reserved : 3; // Reserved for padding/future use. + + // Group 3: special modes - these may be active inside other modes (example: TSX in Long mode). + ND_UINT32 Smm : 1; // The instruction is valid in System Management Mode. + ND_UINT32 SmmOff : 1; // The instruction is valid outside SMM. + ND_UINT32 Sgx : 1; // The instruction is valid in SGX mode. + ND_UINT32 SgxOff : 1; // The instruction is valid outside SGX. + ND_UINT32 Tsx : 1; // The instruction is valid in transactional regions. + ND_UINT32 TsxOff : 1; // The instruction is valid outside TSX. + + // Group 4: VMX mode - they engulf all the other modes. + ND_UINT32 VmxRoot : 1; // The instruction is valid in VMX root mode. + ND_UINT32 VmxNonRoot : 1;// The instruction is valid in VMX non root mode. + ND_UINT32 VmxRootSeam : 1; // The instruction is valid in VMX root SEAM. + ND_UINT32 VmxNonRootSeam : 1;// The instruction is valid in VMX non-root SEAM. + ND_UINT32 VmxOff : 1; // The instruction is valid outside VMX operation. + + }; +} ND_VALID_MODES, *PND_VALID_MODES; + + +// +// RFLAGS register. This structure reflects the actual position of each flag insdide the RFLAGS register, so it can +// be used for direct processing. +// +typedef union _ND_RFLAGS +{ + ND_UINT32 Raw; + struct + { + ND_UINT32 CF : 1; // Carry flag. + ND_UINT32 Reserved1 : 1; // Reserved, must be 1. + ND_UINT32 PF : 1; // Parity flag. + ND_UINT32 Reserved2 : 1; // Reserved. + ND_UINT32 AF : 1; // Auxiliary flag. + ND_UINT32 Reserved3 : 1; // Reserved. + ND_UINT32 ZF : 1; // Zero flag. + ND_UINT32 SF : 1; // Sign flag. + ND_UINT32 TF : 1; // Trap flag. + ND_UINT32 IF : 1; // Interrupt flag. + ND_UINT32 DF : 1; // Direction flag. + ND_UINT32 OF : 1; // Overflow flag. + ND_UINT32 IOPL : 2; // I/O privilege level flag. + ND_UINT32 NT : 1; // Nested task flag. + ND_UINT32 Reserved4 : 1; // Reserved. + ND_UINT32 RF : 1; // Resume flag. + ND_UINT32 VM : 1; // Virtual mode flag. + ND_UINT32 AC : 1; // Alignment check flag. + ND_UINT32 VIF : 1; // Virtual interrupts flag. + ND_UINT32 VIP : 1; // Virtual interrupt pending flag. + ND_UINT32 ID : 1; // CPUID identification flag. + }; +} ND_RFLAGS, *PND_RFLAGS; + + +#define ND_FPU_FLAG_SET_0 0 // The FPU status flag is cleared to 0. +#define ND_FPU_FLAG_SET_1 1 // The FPU status flag is set to 1. +#define ND_FPU_FLAG_MODIFIED 2 // The FPU status flag is modified according to a result. +#define ND_FPU_FLAG_UNDEFINED 3 // The FPU status flag is undefined or unaffected. + +// +// FPU status flags. Each status flag can be one of ND_FPU_FLAG*. +// +typedef struct _ND_FPU_FLAGS +{ + ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*. + ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*. +} ND_FPU_FLAGS, *PND_FPU_FLAGS; + + +// +// Branch information. +// +typedef struct _ND_BRANCH_INFO +{ + ND_UINT8 IsBranch : 1; + ND_UINT8 IsConditional : 1; + ND_UINT8 IsIndirect : 1; + ND_UINT8 IsFar : 1; +} ND_BRANCH_INFO; + + + +// +// Describes a decoded instruction. All the possible information about the instruction is contained in this structure. +// You don't have to call any other APIs to gather any more info about it. +// +typedef struct _INSTRUX +{ + ND_UINT8 DefCode:2; // ND_CODE_*. Indicates disassembly mode. + ND_UINT8 DefData:2; // ND_DATA_*. Indicates default data size. + ND_UINT8 DefStack:2; // ND_STACK_*. Indicates default stack pointer width. + ND_UINT8 AddrMode:2; // ND_ADDR_*. Indicates addressing mode. + ND_UINT8 OpMode:2; // ND_OPSZ_*. Indicates operand mode/size. + ND_UINT8 EfOpMode:2; // ND_OPSZ_*. Indicates effective operand mode/size. + ND_UINT8 VecMode:2; // ND_VECM_*. Indicates vector length. Valid only for vector instructions. + ND_UINT8 EfVecMode:2; // ND_VECM_*. Indicates effective vector length. Valid only for vector instructions. + ND_UINT8 EncMode:4; // ND_ENCM_*. Indicates encoding mode. + ND_UINT8 VexMode:2; // ND_VEX_*. Indicates the VEX mode, if any. Valid only if HasVex set. + ND_UINT8 EvexMode:4; // ND_EVEX_*. Indicates EVEX extension, if any. Valid only if HasEvex set. + ND_UINT8 VendMode:4; // ND_VEND_*. Indicates vendor mode. + ND_UINT8 FeatMode; // ND_FEAT_*. Indicates which features are enabled. + + // Present prefixes. Note that even if a prefix is marked as being present in the encoding, it does not necessary mean + // that the prefix is actually used. Check Is*Enabled fields to check if the prefix is enabled & used. In some cases, + // prefixes are ignored, even if present. + ND_BOOL HasRex:1; // TRUE - REX is present. + ND_BOOL HasRex2:1; // TRUE - REX2 is present. + ND_BOOL HasVex:1; // TRUE - VEX is present. + ND_BOOL HasXop:1; // TRUE - XOP is present. + ND_BOOL HasEvex:1; // TRUE - EVEX is present. + ND_BOOL HasOpSize:1; // TRUE - 0x66 present. + ND_BOOL HasAddrSize:1; // TRUE - 0x67 present. + ND_BOOL HasLock:1; // TRUE - 0xF0 present. + ND_BOOL HasRepnzXacquireBnd:1; // TRUE - 0xF2 present. + ND_BOOL HasRepRepzXrelease:1; // TRUE - 0xF3 present. + ND_BOOL HasSeg:1; // TRUE - segment override present. + + // Present encoding components. + ND_BOOL HasModRm:1; // TRUE - we have valid MODRM. + ND_BOOL HasSib:1; // TRUE - we have valid SIB. + ND_BOOL HasDisp:1; // TRUE - the instruction has displacement. + ND_BOOL HasAddr:1; // TRUE - the instruction contains a direct far address (ie, CALL far 0x9A) + ND_BOOL HasAddrNear:1; // TRUE - the instruction contains a direct near address (ie, CALL far 0x9A) + ND_BOOL HasMoffset:1; // TRUE - the instruction contains a moffset (ie, MOV al, [mem], 0xA0) + ND_BOOL HasRelOffs:1; // TRUE - the instruction contains a relative offset (ie, Jcc 0x7x). + ND_BOOL HasImm1:1; // TRUE - immediate present. + ND_BOOL HasImm2:1; // TRUE - second immediate present. + ND_BOOL HasSseImm:1; // TRUE - SSE immediate that encodes additional registers is present. + + // Present decorators & EVEX info. + ND_BOOL HasCompDisp:1; // TRUE - the instruction uses compressed displacement. + ND_BOOL HasBroadcast:1; // TRUE - the instruction uses broadcast addressing. + ND_BOOL HasMask:1; // TRUE - the instruction has mask. + ND_BOOL HasZero:1; // TRUE - the instruction uses zeroing. + ND_BOOL HasEr:1; // TRUE - the instruction has embedded rounding. + ND_BOOL HasSae:1; // TRUE - the instruction has SAE. + ND_BOOL HasNd:1; // TRUE - the instruction uses New-Data Destination. + ND_BOOL HasNf:1; // TRUE - the instruction uses NoFlags update. + ND_BOOL HasZu:1; // TRUE - the instruction has ZeroUpper. + ND_BOOL HasIgnEr:1; // TRUE - the instruction ignores embedded rounding. + + // Mandatory prefixes. + ND_BOOL HasMandatory66:1; // 0x66 is mandatory prefix. Does not behave as size-changing prefix. + ND_BOOL HasMandatoryF2:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. + ND_BOOL HasMandatoryF3:1; // 0x66 is mandatory prefix. Does not behave as REP prefix. + + // Prefix activation. Use these fields to check whether a prefix is present & active for the instruction. + ND_BOOL IsLockEnabled:1; // TRUE - LOCK is present & used. + ND_BOOL IsRepEnabled:1; // TRUE - REP is present & used. + ND_BOOL IsRepcEnabled:1; // TRUE - REPZ/REPNZ is present & used. + ND_BOOL IsXacquireEnabled:1; // TRUE - the instruction is XACQUIRE enabled. + ND_BOOL IsXreleaseEnabled:1; // TRUE - the instruction is XRELEASE enabled. + ND_BOOL IsBhintEnabled:1; // TRUE - branch hints valid & used. + ND_BOOL IsBndEnabled:1; // TRUE - BND prefix valid & used. + ND_BOOL IsDntEnabled:1; // TRUE - DNT prefix valid & used. + ND_BOOL IsRepeated:1; // TRUE - the instruction is REPed up to RCX times. + ND_BOOL IsCetTracked:1; // TRUE - this is an indirect CALL/JMP that is CET tracked. + + // Misc. + ND_UINT8 IsRipRelative:1; // TRUE - the instruction uses RIP relative addressing. + ND_UINT8 RoundingMode:2; // EVEX rounding mode, if present. One of ND_ROUNDING. + + // Instruction components lengths. Will be 0 if the given field is not present. + ND_UINT8 Length; // 1-15 valid. Instructions longer than 15 bytes will cause #GP. + ND_UINT8 WordLength:4; // The length of the instruction word. 2, 4 or 8. + ND_UINT8 StackWords:4; // Number of words accessed on/from the stack. 0-15. + + ND_UINT8 PrefLength:4; // The total number of bytes consumed by prefixes. This will also be + // the offset to the first opcode. The primary opcode will always be + // the last one, so at offset PrefixesLength + OpcodeLength - 1 + ND_UINT8 OpLength:4; // Number of opcode bytes. Max 3. + ND_UINT8 DispLength:4; // Displacement length, in bytes. Maximum 4. + ND_UINT8 AddrLength:4; // Absolute address length, in bytes. Maximum 8 bytes. + ND_UINT8 MoffsetLength:4; // Memory offset length, in bytes. Maximum 8 bytes. + ND_UINT8 Imm1Length:4; // First immediate length, in bytes. Maximum 8 bytes. + ND_UINT8 Imm2Length:4; // Second immediate length, in bytes. Maximum 1 byte. + ND_UINT8 RelOffsLength:4; // Relative offset length, in bytes. Maximum 4 bytes. + + // Instruction components offsets. Will be 0 if the given field is not present. Prefixes ALWAYS start at offset 0. + ND_UINT8 OpOffset:4; // The offset of the first opcode, inside the instruction. + ND_UINT8 MainOpOffset:4; // The offset of the nominal opcode, inside the instruction. + ND_UINT8 DispOffset:4; // The offset of the displacement, inside the instruction + ND_UINT8 AddrOffset:4; // The offset of the hard-coded address. + ND_UINT8 MoffsetOffset:4; // The offset of the absolute address, inside the instruction + ND_UINT8 Imm1Offset:4; // The offset of the immediate, inside the instruction + ND_UINT8 Imm2Offset:4; // The offset of the second immediate, if any, inside the instruction + ND_UINT8 RelOffsOffset:4; // The offset of the relative offset used in instruction. + ND_UINT8 SseImmOffset:4; // The offset of the SSE immediate, if any, inside the instruction. + ND_UINT8 ModRmOffset:4; // The offset of the mod rm byte inside the instruction, if any. + // If SIB is also present, it will always be at ModRmOffset + 1. + + // This structures contains the fields extracted from either REX, REX2, XOP, VEX, or EVEX fields. + // They're globally placed here, in order to avoid testing for each kind of prefix each time. + // Instead, one can use the different fields directly from here, regardless the actual encoding mode. + struct + { + ND_UINT32 w:1; // REX/REX2/XOP/VEX/EVEX.W + ND_UINT32 r:1; // REX/REX2/XOP/VEX/EVEX.R3 (reg extension) + ND_UINT32 x:1; // REX/REX2/XOP/VEX/EVEX.X3 (index extension) + ND_UINT32 b:1; // REX/REX2/XOP/VEX/EVEX.B3 (base extension) + ND_UINT32 rp:1; // REX2/EVEX.R4 (reg extension, previously known as R') + ND_UINT32 x4:1; // REX2/EVEX.X4 (index extension) + ND_UINT32 b4:1; // REX2/EVEX.B4 (base extension) + ND_UINT32 p:2; // XOP/VEX/EVEX.pp (embedded prefix) + ND_UINT32 m:5; // XOP/VEX/EVEX.mmmmm (decoding table) + ND_UINT32 l:2; // XOP/VEX.L or EVEX.L'L (vector length) + ND_UINT32 v:4; // XOP/VEX/EVEX.VVVV (additional operand) + ND_UINT32 vp:1; // EVEX.V4 (vvvv extension, previously known as V') + ND_UINT32 bm:1; // EVEX.b (embedded broadcast) + ND_UINT32 z:1; // EVEX.z (zero) + ND_UINT32 k:3; // EVEX.aaa (mask registers) + ND_UINT32 nd:1; // EVEX.ND (new data destination) + ND_UINT32 nf:1; // EVEX.NF (no-flags) + ND_UINT32 sc:4; // EVEX.SC0,SC1,SC2,SC3 (standard condition). + } Exs; + + // Raw instruction components. + ND_UINT8 Rep; // The last rep/repz/repnz prefix. 0 if none. + ND_UINT8 Seg; // The last segment override prefix. 0 if none. FS/GS if 64 bit. + ND_MODRM ModRm; // ModRM byte. + ND_SIB Sib; // SIB byte. + + union + { + ND_REX Rex; // REX prefix. + ND_REX2 Rex2; // REX2 prefix. + ND_VEX2 Vex2; // VEX 2 prefix. + ND_VEX3 Vex3; // VEX 3 prefix. + ND_XOP Xop; // XOP prefix. + ND_EVEX Evex; // EVEX prefix. + }; + + // An Address, Moffset, Displacement or RelativeOffset cannot be present at the same time. + union + { + ND_UINT32 Displacement; // Displacement. Max 4 bytes. Used in ModRM instructions. + ND_UINT32 RelativeOffset; // Relative offset, used for branches. Max 4 bytes. + ND_UINT64 Moffset; // Offset. Used by 'O' operands. It's an absolute address. + ND_UINT64 AddressNear; // target64 near address. + struct + { + ND_UINT32 Ip; + ND_UINT16 Cs; + } Address; // seg:offset far address. + }; + ND_UINT64 Immediate1; // Can be 8 bytes on x64. + union + { + ND_UINT8 Immediate2; // For enter, mainly. Can only be 1 byte. + ND_UINT8 SseImmediate; // This immediate actually selects a register. + }; + + ND_UINT8 OperandsCount:4; // Number of operands (total). + ND_UINT8 ExpOperandsCount:4; // Number of explicit operands. Use this if you want to ignore + // implicit operands such as stack, flags, etc. + ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands. + + // EVEX information. + ND_UINT8 ExceptionType; // Exception type. One of ND_EX_TYPE. + ND_UINT8 TupleType; // EVEX tuple type, if EVEX. One of ND_TUPLE. + + // As extracted from the operands themselves. + ND_UINT8 CsAccess; // CS access mode (read/write). Includes only implicit CS accesses. + ND_UINT8 RipAccess; // RIP access mode (read/write). + ND_UINT8 RflAccess; // RFLAGS access mode (read/write), as per the entire register. + ND_UINT8 StackAccess; // Stack access mode (push/pop). + ND_UINT8 MemoryAccess; // Memory access mode (read/write, including stack or shadow stack). + ND_FPU_FLAGS FpuFlagsAccess; // FPU status word C0-C3 bits access. Valid only for FPU instructions! + ND_BRANCH_INFO BranchInfo; // Branch information. + + struct + { + ND_RFLAGS Tested; // Tested flags. + ND_RFLAGS Modified; // Modified (according to the result) flags. + ND_RFLAGS Set; // Flags that are always set to 1. + ND_RFLAGS Cleared; // Flags that are always cleared to 0. + ND_RFLAGS Undefined; // Undefined flags. + } FlagsAccess; + + // Stored inside the instruction entry as well. These are specific for an instruction and do not depend on + // encoding. Use the flags definitions (ND_FLAG_*, ND_PREF_*, ND_DECO_*, ND_EXOP_*) to access specific bits. + ND_UINT64 Attributes; // Instruction attributes/flags. A collection of ND_FLAG_*. + + // Instruction metadata. + ND_INS_CLASS Instruction; // One of the ND_INS_* + ND_INS_CATEGORY Category; // One of the ND_CAT_* + ND_INS_SET IsaSet; // One of the ND_SET_* + + ND_CPUID_FLAG CpuidFlag; // CPUID support flag. + ND_VALID_MODES ValidModes; // Valid CPU modes for the instruction. + ND_VALID_PREFIXES ValidPrefixes; // Indicates which prefixes are valid for this instruction. + ND_VALID_DECORATORS ValidDecorators; // What decorators are accepted by the instruction. + + // Instruction bytes & mnemonic. + union + { + ND_UINT8 PrimaryOpCode; // Main opcode. + ND_UINT8 Condition:4; // Condition code. Valid only if ND_FLAG_COND is set in Attributes. + // Aliased over low 4 bits inside the main opcode. + }; + + const char *Mnemonic; // Instruction mnemonic. + ND_UINT8 InstructionBytes[16]; // The entire instruction. + ND_UINT8 OpCodeBytes[3]; // Opcode bytes - escape codes and main opcode. + +} INSTRUX, *PINSTRUX; + + + +// +// Decoder context. Such a structure must be passed to the NdDecodeWithContext API. This structure must be initialized +// only once, and then it can be re-used across NdDecodeWithContext calls. +// +typedef struct _ND_CONTEXT +{ + ND_UINT64 DefCode : 4; // Decode mode - one of the ND_CODE_* values. + ND_UINT64 DefData : 4; // Data mode - one of the ND_DATA_* values. + ND_UINT64 DefStack : 4; // Stack mode - one of the ND_STACK_* values. + ND_UINT64 VendMode : 4; // Prefered vendor - one of the ND_VEND_* values. + ND_UINT64 FeatMode : 8; // Supported features mask. A combination of ND_FEAT_* values. + ND_UINT64 Reserved : 40; // Reserved for future use. + ND_UINT32 Options; // Decoding options. A combination of ND_OPTION_* values. +} ND_CONTEXT; + +/// Decode only explicit instruction operands. If this options is set, implicit operands, such as RIP or RFLAGS +/// will not be decoded. As a consequence, the following fields inside INSTRUX will be undefined: +/// CsAccess, RipAccess, RflAccess, StackAcces, MemoryAccess, BranchInfo. +#define ND_OPTION_ONLY_EXPLICIT_OPERANDS 0x00000001 + + +// +// Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack. +// Use NdGetFullAccessMap to populate this structure. +// +typedef struct _ND_ACCESS_MAP +{ + ND_UINT8 RipAccess; + ND_UINT8 FlagsAccess; + ND_UINT8 StackAccess; + ND_UINT8 MemAccess; + ND_UINT8 MxcsrAccess; + ND_UINT8 PkruAccess; + ND_UINT8 SspAccess; + ND_UINT8 GprAccess[ND_MAX_GPR_REGS]; + ND_UINT8 SegAccess[ND_MAX_SEG_REGS]; + ND_UINT8 FpuAccess[ND_MAX_FPU_REGS]; + ND_UINT8 MmxAccess[ND_MAX_MMX_REGS]; + ND_UINT8 SseAccess[ND_MAX_SSE_REGS]; + ND_UINT8 CrAccess [ND_MAX_CR_REGS ]; + ND_UINT8 DrAccess [ND_MAX_DR_REGS ]; + ND_UINT8 TrAccess [ND_MAX_TR_REGS ]; + ND_UINT8 BndAccess[ND_MAX_BND_REGS]; + ND_UINT8 MskAccess[ND_MAX_MSK_REGS]; + ND_UINT8 TmmAccess[ND_MAX_TILE_REGS]; + ND_UINT8 SysAccess[ND_MAX_SYS_REGS]; + ND_UINT8 X87Access[ND_MAX_X87_REGS]; +} ND_ACCESS_MAP, *PND_ACCESS_MAP; + + +// +// Operand reverse-lookup table. Each entry inside this structure contains the pointer to the relevant operand. +// Some rules govern this special structure: +// - It is not generated by default. The user must call NdGetOperandRlut manually to fill in this structure. +// - This structure holds pointers inside the INSTRUX provided to the NdGetOperandRlut function; please make sure +// you call NdGetOperandRlut again if the INSTRUX is relocated, as all the pointers will dangle. +// - Not all the operand types have a corresponding entry in ND_OPERAND_RLUT, only the usual ones. +// - Some operands may have multiple entries in ND_OPERAND_RLUT - for example, RMW (read-modify-write) instructions +// will have Dst1 and Src1 pointing to the same operand. +// - The implicit registers entries in ND_OPERAND_RLUT will point to the operand which is of that type, and implicit; +// for example, ND_OPERAND_RLUT.Rax will be NULL for `add rax, rcx`, since in this case, `rax` is not an implicit +// operand. For `cpuid`, however, ND_OPERAND_RLUT.Rax will point to the implicit `eax` register. +// Use NdGetOperandRlut to populate this structure. +// +typedef struct _ND_OPERAND_RLUT +{ + PND_OPERAND Dst1; // First destination operand. + PND_OPERAND Dst2; // Second destination operand. + PND_OPERAND Src1; // First source operand. + PND_OPERAND Src2; // Second source operand. + PND_OPERAND Src3; // Third source operand. + PND_OPERAND Src4; // Fourth source operand. + PND_OPERAND Mem1; // First memory operand. + PND_OPERAND Mem2; // Second memory operand. + PND_OPERAND Stack; // Stack operand. + PND_OPERAND Flags; // Flags register operand. + PND_OPERAND Rip; // Instruction Pointer register operand. + PND_OPERAND Cs; // Implicit CS operand. + PND_OPERAND Ss; // Implicit SS operand. + PND_OPERAND Rax; // Implicit accumulator register operand. + PND_OPERAND Rcx; // Implicit counter register operand. + PND_OPERAND Rdx; // Implicit data register operand + PND_OPERAND Rbx; // Implicit base address register operand. + PND_OPERAND Rsp; // Implicit stack pointer operand. + PND_OPERAND Rbp; // Implicit base pointer operand. + PND_OPERAND Rsi; // Implicit source index operand. + PND_OPERAND Rdi; // Implicit destination index operand. +} ND_OPERAND_RLUT; + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Returns the bddisasm version. +// +void +NdGetVersion( + ND_UINT32 *Major, + ND_UINT32 *Minor, + ND_UINT32 *Revision, + const char **BuildDate, + const char **BuildTime + ); + +// +// Decode one instruction. Note that this is equivalent to: +// NdDecodeEx(Instrux, Code, ND_MAX_INSTRUCTION_LEN, DefCode, DefData). +// This version should be used if the caller doesn't care about the length of the buffer. Otherwise, use the other +// decode API. +// +NDSTATUS +NdDecode( + INSTRUX *Instrux, // Output decoded instruction. + const ND_UINT8 *Code, // Buffer containing the instruction bytes. + ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. + ND_UINT8 DefData // Data mode - one of the ND_DATA_* value. + ); + +// +// Decode one instruction. Note that this is equivalent to: +// NdDecodeEx2(Instrux, Code, Size, DefCode, DefData, DefCode, ND_VEND_ANY). +// By default, the used vendor will be ND_VEND_ANY, so all instructions will be decoded. +// By default, the feature mode will be ND_FEAT_ALL, so all instructions will be decoded (but may yield error where +// otherwise a NOP would be encoded - use ND_FEAT_NONE in that case). +// +NDSTATUS +NdDecodeEx( + INSTRUX *Instrux, // Output decoded instruction. + const ND_UINT8 *Code, // Buffer containing the instruction bytes. + ND_SIZET Size, // Maximum size of the Code buffer. + ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. + ND_UINT8 DefData // Data mode - one of the ND_DATA_* value. + ); + +// +// Fills a ND_CONTEXT structure, and calls NdDecodeWithContext. The feature mode will be ND_FEAT_ALL by default. +// +NDSTATUS +NdDecodeEx2( + INSTRUX *Instrux, // Output decoded instruction. + const ND_UINT8 *Code, // Buffer containing the instruction bytes. + ND_SIZET Size, // Maximum size of the Code buffer. + ND_UINT8 DefCode, // Decode mode - one of the ND_CODE_* values. + ND_UINT8 DefData, // Data mode - one of the ND_DATA_* value. + ND_UINT8 DefStack, // Stack mode - one of the ND_STACK_* values. + ND_UINT8 PreferedVendor // Preferred vendor - one of the ND_VEND_* values. + ); + +// +// This API received a decode context, where it expects DefCode, DefData, DefStack, VendMode and FeatMode to be +// already initialized. The Context will not be modified by the decoder, so it can be reused across decode calls. +// The Context should initially be initialized using NdInitContext. This will ensure backwards compatibility +// by setting new fields to default values. +// Note that this is the base decoding API, and this ends up being called by all the other decoding APIs, after +// providing default arguments and filling them in the Context structure. For maximum speed, use this instead of +// the others. +// +NDSTATUS +NdDecodeWithContext( + INSTRUX *Instrux, // Output decoded instruction. + const ND_UINT8 *Code, // Buffer containing the instruction bytes. + ND_SIZET Size, // Maximum size of the Code buffer. + ND_CONTEXT *Context // Context describing decode mode, vendor mode and supported features. + ); + +// +// Convert the given instruction into textual representation (Intel syntax). +// +NDSTATUS +NdToText( + const INSTRUX *Instrux, + ND_UINT64 Rip, + ND_UINT32 BufferSize, + char *Buffer + ); + +// +// Returns true if the instruction is RIP relative. Note that this function is kept for backwards compatibility, since +// there already is a IsRipRelative field inside INSTRUX. +// +ND_BOOL +NdIsInstruxRipRelative( + const INSTRUX *Instrux + ); + +// +// Returns an access map that contains the access for each register. +// +NDSTATUS +NdGetFullAccessMap( + const INSTRUX *Instrux, + ND_ACCESS_MAP *AccessMap + ); + +// +// Returns an operand reverse-lookup. One can use the Rlut to quickly reference different kinds of operands in INSTRUX. +// +NDSTATUS +NdGetOperandRlut( + const INSTRUX *Instrux, + ND_OPERAND_RLUT *Rlut + ); + +// +// Initialize the decoder context. +// +void +NdInitContext( + ND_CONTEXT *Context + ); + +#ifdef __cplusplus +} +#endif + +// #pragma warning(default: 4214) // Bitfield in type other than int. +// #pragma warning(default: 4201) // Nonstandard extension used: nameless struct/union. +#ifdef _MSC_VER +#pragma warning(pop) +#endif + +#endif // BDX86_CORE_H diff --git a/inc/cpuidflags.h b/inc/bdx86_cpuidflags.h similarity index 97% rename from inc/cpuidflags.h rename to inc/bdx86_cpuidflags.h index 570c1df..dad9212 100644 --- a/inc/cpuidflags.h +++ b/inc/bdx86_cpuidflags.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020 Bitdefender + * Copyright (c) 2024 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ @@ -7,15 +7,14 @@ // This file was auto-generated by generate_tables.py. DO NOT MODIFY! // -#ifndef CPUID_FLAGS_H -#define CPUID_FLAGS_H +#ifndef BDX86_CPUID_FLAGS_H +#define BDX86_CPUID_FLAGS_H #define ND_CFF_NO_LEAF 0xFFFFFFFF #define ND_CFF_NO_SUBLEAF 0x00FFFFFF #define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59)) - #define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 0) #define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 5) #define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 8) @@ -114,6 +113,8 @@ #define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8) #define ND_CFF_AVXVNNIINT16 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 10) #define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14) +#define ND_CFF_USER_MSR ND_CFF(0x00000007, 0x00000001, NDR_EDX, 15) +#define ND_CFF_APX_F ND_CFF(0x00000007, 0x00000001, NDR_EDX, 21) #define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0) #define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1) #define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3) diff --git a/inc/registers.h b/inc/bdx86_registers.h similarity index 80% rename from inc/registers.h rename to inc/bdx86_registers.h index 22c12d9..07db581 100644 --- a/inc/registers.h +++ b/inc/bdx86_registers.h @@ -2,8 +2,8 @@ * Copyright (c) 2020 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ -#ifndef REGISTERS_H -#define REGISTERS_H +#ifndef BDX86_REGISTERS_H +#define BDX86_REGISTERS_H // // Registers enumerations @@ -12,18 +12,24 @@ enum { NDR_RAX, NDR_RCX, NDR_RDX, NDR_RBX, NDR_RSP, NDR_RBP, NDR_RSI, NDR_RDI, NDR_R8, NDR_R9, NDR_R10, NDR_R11, NDR_R12, NDR_R13, NDR_R14, NDR_R15, + NDR_R16, NDR_R17, NDR_R18, NDR_R19, NDR_R20, NDR_R21, NDR_R22, NDR_R23, + NDR_R24, NDR_R25, NDR_R26, NDR_R27, NDR_R28, NDR_R29, NDR_R30, NDR_R31, }; enum { NDR_EAX, NDR_ECX, NDR_EDX, NDR_EBX, NDR_ESP, NDR_EBP, NDR_ESI, NDR_EDI, NDR_R8D, NDR_R9D, NDR_R10D,NDR_R11D,NDR_R12D,NDR_R13D,NDR_R14D,NDR_R15D, + NDR_R16D, NDR_R17D, NDR_R18D, NDR_R19D, NDR_R20D, NDR_R21D, NDR_R22D, NDR_R23D, + NDR_R24D, NDR_R25D, NDR_R26D, NDR_R27D, NDR_R28D, NDR_R29D, NDR_R30D, NDR_R31D, }; enum { NDR_AX, NDR_CX, NDR_DX, NDR_BX, NDR_SP, NDR_BP, NDR_SI, NDR_DI, NDR_R8W, NDR_R9W, NDR_R10W,NDR_R11W,NDR_R12W,NDR_R13W,NDR_R14W,NDR_R15W, + NDR_R16W, NDR_R17W, NDR_R18W, NDR_R19W, NDR_R20W, NDR_R21W, NDR_R22W, NDR_R23W, + NDR_R24W, NDR_R25W, NDR_R26W, NDR_R27W, NDR_R28W, NDR_R29W, NDR_R30W, NDR_R31W, }; enum @@ -35,6 +41,8 @@ enum { NDR_AL64, NDR_CL64, NDR_DL64, NDR_BL64, NDR_SPL, NDR_BPL, NDR_SIL, NDR_DIL, NDR_R8L, NDR_R9L, NDR_R10L, NDR_R11L, NDR_R12L, NDR_R13L, NDR_R14L, NDR_R15L, + NDR_R16L, NDR_R17L, NDR_R18L, NDR_R19L, NDR_R20L, NDR_R21L, NDR_R22L, NDR_R23L, + NDR_R24L, NDR_R25L, NDR_R26L, NDR_R27L, NDR_R28L, NDR_R29L, NDR_R30L, NDR_R31L, }; enum @@ -46,12 +54,16 @@ enum { NDR_CR0, NDR_CR1, NDR_CR2, NDR_CR3, NDR_CR4, NDR_CR5, NDR_CR6, NDR_CR7, NDR_CR8, NDR_CR9, NDR_CR10, NDR_CR11, NDR_CR12, NDR_CR13, NDR_CR14, NDR_CR15, + NDR_CR16, NDR_CR17, NDR_CR18, NDR_CR19, NDR_CR20, NDR_CR21, NDR_CR22, NDR_CR23, + NDR_CR24, NDR_CR25, NDR_CR26, NDR_CR27, NDR_CR28, NDR_CR29, NDR_CR30, NDR_CR31 }; enum { NDR_DR0, NDR_DR1, NDR_DR2, NDR_DR3, NDR_DR4, NDR_DR5, NDR_DR6, NDR_DR7, NDR_DR8, NDR_DR9, NDR_DR10, NDR_DR11, NDR_DR12, NDR_DR13, NDR_DR14, NDR_DR15, + NDR_DR16, NDR_DR17, NDR_DR18, NDR_DR19, NDR_DR20, NDR_DR21, NDR_DR22, NDR_DR23, + NDR_DR24, NDR_DR25, NDR_DR26, NDR_DR27, NDR_DR28, NDR_DR29, NDR_DR30, NDR_DR31 }; enum diff --git a/inc/version.h b/inc/version.h deleted file mode 100644 index d6ade4c..0000000 --- a/inc/version.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 Bitdefender - * SPDX-License-Identifier: Apache-2.0 - */ -#ifndef DISASM_VER_H -#define DISASM_VER_H - -#define DISASM_VERSION_MAJOR 1 -#define DISASM_VERSION_MINOR 38 -#define DISASM_VERSION_REVISION 0 - -// bdshemu depends on bddisasm. It cannot be used without it. -#define SHEMU_VERSION_MAJOR 1 -#define SHEMU_VERSION_MINOR 1 -#define SHEMU_VERSION_REVISION 16 - -#endif // DISASM_VER_H diff --git a/isagenerator/CMakeLists.txt b/isagenerator/CMakeLists.txt index 144d3c3..2f22c67 100644 --- a/isagenerator/CMakeLists.txt +++ b/isagenerator/CMakeLists.txt @@ -1,4 +1,4 @@ -cmake_minimum_required(VERSION 3.12) +cmake_minimum_required(VERSION 3.16) project(isagenerator) @@ -7,7 +7,7 @@ include(FindPython3) find_package(Python3 COMPONENTS Interpreter) if (Python3_FOUND) add_custom_target( - isagenerator + isagenerator_x86 COMMAND Python3::Interpreter generate_tables.py instructions WORKING_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}" COMMENT "Generating instruction tables") diff --git a/isagenerator/disasmlib.py b/isagenerator/disasmlib.py index af3af0b..405bdfa 100644 --- a/isagenerator/disasmlib.py +++ b/isagenerator/disasmlib.py @@ -1,5 +1,6 @@ +#!/usr/bin/env python3 # -# Copyright (c) 2020 Bitdefender +# Copyright (c) 2024 Bitdefender # SPDX-License-Identifier: Apache-2.0 # import os @@ -8,51 +9,65 @@ import re import glob +# Instruction attributes. These values go with the 'a' metadata key. valid_attributes = { + # Misc instruction properties. 'MODRM', # Mod r/m is present. - 'II64', # Instruction invalid in 64 bit mode. - 'F64', # Operand size forced to 64 bit. - 'D64', # Operand size defaults to 64 bit. - 'O64', # Instruction valid only in 64 bit mode. - 'SSECONDB', # Instruction has condition byte. - 'COND', # Instruction has predicated encoded in lower 4 bit of the opcode. - 'VSIB', # Instruction uses VSIB addressing. - 'MIB', # Instruction uses MIB addressing. - 'LIG', # *vex.L is ignored. - 'WIG', # *vex.W is ignored. '3DNOW', # Instruction uses 3dnow encoding. - 'MMASK', # Instruction must have mask specified (mask cannot be k0). - 'NOMZ', # Zeroing not allowed with memory addressing. + 'COND', # Instruction has condition encoded in lower 4 bit of the opcode. 'LOCKSP', # Special lock - MOV CR on amd can use LOCK to access CR8 in 32 bit mode. - 'NOL0', # Vector length 128 not supported. - 'NOA16', # 16 bit addressing not supported. - 'NO66', # 0x66 prefix causes #UD. - 'NORIPREL', # RIP relative addressing not supported. - 'VECT', # Vector instruction. + 'VECTOR', # Vector instruction. 'S66', # 0x66 prefix changes length even if it is in special map (66, f2, f3). - 'BITBASE', # Instruction uses bitbase addressing. - 'AG', # Instruction uses address generation, no memory access. 'SHS', # Instruction accesses the shadow stack. 'MFR', # The Mod inside Mod R/M is forced to register. No SIB/disp present. 'CETT', # Instruction is CET tracked. + 'SERIAL', # Instruction is serializing. + 'SCALABLE', # EVEX.pp prefix can be 0 or 1, simulating the presence of 0x66 prefix. + + # 64-bit modifiers. + 'I64', # Instruction invalid in 64 bit mode. + 'O64', # Instruction valid only in 64 bit mode. + 'F64', # Operand size forced to 64 bit. + 'D64', # Operand size defaults to 64 bit. + + # Per operand indicators. 'OP1DEF', # Operand 1 is default (implicit). 'OP2DEF', # Operand 2 is default (implicit). - 'OP2SEXO1', # Operand 2 is sign-extended to the size of the first operand. - 'OP3SEXO1', # Operand 3 is sign-extended to the size of the first operand. - 'OP1SEXDW', # Operand 1 is sign-extended to the size of the default word. - 'PREFIX', # Prefix. - 'SERIAL', # Instruction is serializing. + 'OP2SIGNEXO1', # Operand 2 is sign-extended to the size of the first operand. + 'OP3SIGNEXO1', # Operand 3 is sign-extended to the size of the first operand. + 'OP1SIGNEXDW', # Operand 1 is sign-extended to the size of the default word. + + # Addressing flags. + 'AG', # Instruction uses address generation, no memory access. + 'BITBASE', # Instruction uses bitbase addressing. + 'VSIB', # Instruction uses VSIB addressing. + 'MIB', # Instruction uses MIB addressing. 'SIBMEM', # Instruction uses sibmem addressing (AMX instructions). + + # Ignored fields. + 'LIG', # *vex.L is ignored. + 'WIG', # *vex.W is ignored. 'I67', # Ignore the address size override (0x67) prefix in 64 bit mode. 'IER', # Ignore embedded rounding for the instruction. 'IWO64', # The VEX/EVEX.W field is ignored outside 64 bit mode, and behaves as if it's 0. + + # Restrictions - these fields being present leads to #UD. + 'MMASK', # Instruction must have mask specified (mask cannot be k0). + 'NOMZ', # Zeroing not allowed with memory addressing. + 'NOL0', # Vector length 128 not supported. + 'NOA16', # 16 bit addressing not supported. + 'NORIPREL', # RIP relative addressing not supported. + 'NO66', # 0x66 prefix causes #UD. + 'NO67', # 0x67 prefix causes #UD. + 'NOREP', # REP prefixes will cause #UD. + 'NOREX2', # REX2 prefix will cause #UD. + 'NOV', # XOP/VEX/EVEX.v will cause #UD if not logical 0. + 'NOVP', # EVEX.v' will cause #UD if not logical 0. } -# # Explicit operands types. -# -valid_optype = [ - 'A', # Direct addressing. Used by far branches. +valid_optypes = [ + 'A', # Direct addressing. Used by direct branches. 'B', # The vvvv field inside VEX/EVEX encodes a general purpose registr. 'C', # The reg field inside Mod R/M encodes a control register. 'D', # The reg field inside Mod R/M encodes a debug register. @@ -92,8 +107,10 @@ valid_optype = [ 'mT', # The rm field inside Mod R/M encodes a tile register (AMX extension). 'vT', # The vvvv field inside VEX/EVEX encodes a tile register (AMX extension). 'm2zI', # Bits [1,0] of the immediate byte which encodes the fourth register. + 'dfv', # The EVEX.VVVV encodes a default flags value (OF,SF,ZF,CF). ] + # Operand sizes. # Unless otherwise stated, where multiple sizes are given, the correct size is selected by the # operand size or vector length as follows: @@ -103,7 +120,7 @@ valid_optype = [ # If only two sizes are given, only 16-bit and 32-bit operand sizes are considered, unles otherwise # indicated. # If only a size is given, that is available in all modes and with all operand sizes. -valid_opsize = [ +valid_opsizes = [ 'a', # 2 x 16 bits (16-bit opsize) or 2 x 32 bits (32-bit opsize). # Fixed integer sizes. @@ -184,7 +201,7 @@ valid_opsize = [ '4096', # 4096 bits representing an MSR address/value table. ] -# Implicit/fixed operands. Self explanatory. +# Implicit/fixed operands. valid_impops = {# register size 'AH' : ('AH', 'b'), # AH register. 'AL' : ('rAX', 'b'), # AL register. @@ -231,8 +248,8 @@ valid_impops = {# register size 'XMM5' : ('XMM5', 'dq'), # XMM5 register. 'XMM6' : ('XMM6', 'dq'), # XMM6 register. 'XMM7' : ('XMM7', 'dq'), # XMM7 register. - 'ST(0)' : ('ST(0)', 'ft'), # ST(0) register. - 'ST(i)' : ('ST(i)', 'ft'), # ST(1) register. + 'ST(0)' : ('ST0', 'ft'), # ST(0) register. + 'ST(i)' : ('STi', 'ft'), # ST(1) register. 'CS' : ('CS', 'v'), # CS register. 'SS' : ('SS', 'v'), # SS register. 'DS' : ('DS', 'v'), # DS register. @@ -274,6 +291,7 @@ valid_impops = {# register size 'pBXALb' : ('pBXAL', 'b'), # Implicit [RBX + AL], as used by XLAT. 'pDIq' : ('pDI', 'q'), # Implicit qword [RDI]. 'pDIdq' : ('pDI', 'dq'), # Implicit xmmword [RDI]. + # Implicit shadow stack accesses. 'SHS' : ('SHS', 'q'), # Shadow stack (SSP) implicit access, 1 qword (use by CET instructions). 'SHS0' : ('SHS0', 'q'), # Shadow stack (IA32_PL0_SSP) implicit access, 1 qword (use by CET instructions). @@ -283,6 +301,7 @@ valid_impops = {# register size 'SHS2' : ('SHSP', 'v2'), # Shadow stack push/pop, 2 words. 'SHS3' : ('SHSP', 'v3'), # Shadow stack push/pop, 3 words. 'SHS4' : ('SHSP', 'v4'), # Shadow stack push/pop, 4 words. + # User Interrupt Flag. 'UIF' : ('UIF', 'b'), # User Interrupt Flag, stored with size of 1 byte, although it is 1 bit. } @@ -322,8 +341,11 @@ operand_encoding = { '1' : '1', # Constant 1. 'CL' : 'C', # CL register. 'ST(i)' : 'M', # Modrm.rm encoded FPU register. + 'm2zI' : 'L', # Immediate encodes a register. + 'dfv' : 'V', # EVEX.VVVV encodes a default flags value. } +# Accepted prefixes. These values go with the 'p' metadata key. valid_prefixes = [ 'REP', # Rep prefix is accepted. 'REPC', # Conditional rep prefix is accepted. @@ -337,6 +359,7 @@ valid_prefixes = [ 'DNT', # Do Not Track prefix accepted (CET). ] +# Accepted access types. These values go with the 'w' metadata key (operand access map). valid_access = [ 'N', # No access. 'P', # Prefetch access. @@ -350,6 +373,7 @@ valid_access = [ 'CRCW', # Conditional Read-Conditional Write. ] +# Valid flags. These values go with the 'f' metadata key. valid_flags = [ 'CF', # Carry. 'PF', # Parity. @@ -370,6 +394,7 @@ valid_flags = [ 'ID' # CPUID ID flag. ] +# Valid flags access. These values go with the 'f' metadata key. valid_flag_op = [ 'm', # modified. 't', # tested. @@ -379,6 +404,7 @@ valid_flag_op = [ 'n', # not accessed. ] +# Valid CPU modes. These values go with the 'm' metadata key. valid_cpu_modes = [ 'r0', # Ring 0. 'r1', # Ring 1. @@ -403,52 +429,52 @@ valid_cpu_modes = [ ] valid_mode_groups = [ - "ring", - "mode", - "vmx", - "other", + 'ring', + 'mode', + 'vmx', + 'other', ] valid_ring_modes = [ - "r0", - "r1", - "r2", - "r3", + 'r0', + 'r1', + 'r2', + 'r3', ] valid_mode_modes = [ - "real", - "v8086", - "prot", - "compat", - "long", + 'real', + 'v8086', + 'prot', + 'compat', + 'long', ] valid_vmx_modes = [ - "vmxr", - "vmxn", - "vmxr_seam", - "vmxn_seam", - "vmx_off", + 'vmxr', + 'vmxn', + 'vmxr_seam', + 'vmxn_seam', + 'vmx_off', ] valid_other_modes = [ - "smm", - "smm_off", - "sgx", - "sgx_off", - "tsx", - "tsx_off", + 'smm', + 'smm_off', + 'sgx', + 'sgx_off', + 'tsx', + 'tsx_off', ] valid_mode_map = { - "ring" : valid_ring_modes, - "mode" : valid_mode_modes, - "vmx" : valid_vmx_modes, - "other" : valid_other_modes, + 'ring' : valid_ring_modes, + 'mode' : valid_mode_modes, + 'vmx' : valid_vmx_modes, + 'other' : valid_other_modes, } - +# Valid decoratoras that can be present in either mnemonic or operand. valid_decorators = [ '{K}', # Masking support. '{z}', # Zeroing support. @@ -457,8 +483,37 @@ valid_decorators = [ '|B32', # Broadcast 32. '|B64', # Broadcast 64. '|B16', # Broadcast 16. + '{ND}', # New data destination. + '{NF}', # No flags. + '{ZU}', # Zero-upper. ] +# Maps decorator to global flags. +deco_flags = { + '{K}' : 'MASK', + '{z}' : 'ZERO', + '{sae}' : 'SAE', + '{er}' : 'ER', + '|B32' : 'BROADCAST', + '|B64' : 'BROADCAST', + '|B16' : 'BROADCAST', + '{ND}' : 'ND', + '{ZU}' : 'ZU', + '{NF}' : 'NF', +} + +# Maps decorator to operand flags. +deco_op_flags = { + '{K}' : 'MASK', + '{z}' : 'ZERO', + '{sae}' : 'SAE', + '{er}' : 'ER', + '|B32' : 'B32', + '|B64' : 'B64', + '|B16' : 'B16', +} + +# Valid EVEX tuples. These values go with the 'l' metadata key. valid_tuples = [ 'fv', # Full Vector, Load+Op (Full Vector Dword/Qword). 'hv', # Half Vector, Load+Op (Half Vector). @@ -479,28 +534,23 @@ valid_tuples = [ 't1_4x', ] -absent_op = ['n/a', 'nil'] - -class InvalidEncodingException(Exception): - def __init__(self, value): - self.value = value - - def __str__(self): - return repr(self.value) - -class ParseLineException(Exception): - def __init__(self, value): - self.value = value - - def __str__(self): - return repr(self.value) +# Valid EVEX modes. These values go with the 'v' metadata key. +valid_evex_mode = [ + 'none', # Legacy EVEX + 'vex', # EVEX extension for VEX + 'legacy', # EVEX extension for legacy instructions + 'cond', # EVEX extension for conditional instructons +] -def reverse_dict(d): - r = {} - for k in d: - r[d[k]] = k - return r +# Use one of these value to indicate absent operands. +absent_op = ['n/a', ''] + +# Global templates, extracted from template files. +template_flags = {} +template_cpuid = {} +template_modes = {} + def my_str(x): if x is None: @@ -509,25 +559,67 @@ def my_str(x): return str(x) -# -# CPUID feature flags. -# -class CpuidFeatureFlag(): - def __init__(self, finfo): - self.Name = finfo["name"] - self.Leaf = finfo["leaf"] - self.SubLeaf = finfo["subleaf"] - self.Reg = finfo["reg"] - self.Bit = finfo["bit"] +class InvalidSpecificationException(Exception): + def __init__(self, value): + self.value = value def __str__(self): - return "%s: %s, %s, %s, %s" % (self.Name, self.Leaf, self.SubLeaf, self.Reg, self.Bit) + return repr(self.value) + + +class CpuidFeatureFlag(): + """ + Describes a CPUID feature flag. + + Attributes + ---------- + Name: str + Feature name. + Leaf: str + Leaf number (the EAX input value). + SubLeaf: str + SubLeaf number (the ECX input value. '0xFFFFFFFF' if no subleaf present). + Reg: str + The output register that contains the feature indication. + Bit: str + The bit inside Reg that indicates whether the feature is present or not. + """ + def __init__(self, finfo): + self.Name = finfo['name'] + self.Leaf = finfo['leaf'] + self.SubLeaf = finfo['subleaf'] + self.Reg = finfo['reg'] + self.Bit = finfo['bit'] + + def __str__(self): + return '%s: %s, %s, %s, %s' % (self.Name, self.Leaf, self.SubLeaf, self.Reg, self.Bit) -# -# Operand description -# class Operand(): + """ + Describes an x86 instruction operand. + + Attributes + ---------- + Raw: str + Raw operand description (examples: 'Gv', or 'EAX'). + Type: str + Operand type. One of valid_optypes (example: 'G'). + Size: str + Operand size. One of valid_opsizes (example: 'v'). + Flags: list[str] + Operand flags (example: ['OPDEF']). + Decorators: list[str] + Operand decorators (example: ['MASK', 'ZERO']). Entries from deco_op_flags. + Access: str + Operand access mode (example: 'RW'). One of valid_access. + Block: int + Operand block register access. Usually 0. + Encoding: str + Operand encoding (example: 'R'). One of operand_encoding values. + Implicit: bool + Whether the operand is implicit or explicit. + """ def __init__(self, op, access, flags, imp = False): self.Raw = op self.Type = 0 @@ -561,7 +653,7 @@ class Operand(): # Found decorator. self.Decorators.append(dec) # Remove it from the opstring. - op = op.replace(dec, "") + op = op.replace(dec, '') # Handle hard-coded operators - those that are implicit/are not encoded anywhere. if op in valid_impops: @@ -569,20 +661,23 @@ class Operand(): # Now handle explicit operators. else: # Attempt a match inside the explicit operands map. - for opt in valid_optype: + for opt in valid_optypes: if op.startswith(opt): self.Type = opt - op = op.replace(opt, "") + op = op.replace(opt, '') break # Now the operand size. After parsing the decorator and the operand type, we should be left with # the operand size only. - if self.Type in ['rK', 'mK', 'vK', 'aK'] and not op in valid_opsize: + if self.Type in ['rK', 'mK', 'vK', 'aK'] and not op in valid_opsizes: self.Size = 'q' - elif op in valid_opsize: + elif self.Type in ['dfv']: + # No size for default flags value. + self.Size = '0' + elif op in valid_opsizes: self.Size = op else: - raise InvalidEncodingException('Invalid operand size specified: ' + orig) + raise InvalidSpecificationException("Invalid operand size specified: " + orig) if self.Type in operand_encoding: self.Encoding = operand_encoding[self.Type] @@ -595,520 +690,253 @@ class Operand(): self.Access = access def __str__(self): - if True: - return self.Raw + return self.Raw -# -# Prefixes. -# -class Prefix(): - def __init__(self, prefix): - self.Mnemonic = prefix["mnemonic"] - self.Encoding = prefix["encoding"] - - def __str__(self): - return self.Mnemonic - - -# -# Instructions. -# class Instruction(): - def __init__(self, iinfo): + """ + Describes an x86 instruction. + + Attributes + ---------- + Mnemonic: str + The instruction mnemonic. Decorators are not included. + RawExpOps: list[str] + Raw explicit operands, as supplied in the specification file (example: ['Gv', 'Ev']). + RawImpOps: list[str] + Raw implicit operands, as supplied in the specification file (example: ['Fv', 'rIP']). + RawEnc: str + Raw encoding, as supplied in the specification file (example: '0xBD /r'). + RawMeta: list[str] + Raw meta-data, as supplied in the specification file (example: ['a:MODRM', 'p:LOCK', 's:ABC']). + DecoFlags: list[str] + Decorator flags, extracted from mnemonic & operands. Indicates what decorators are accepted + by the instruction. + Xop: bool + True if instruction uses XOP encoding. + Vex: bool + True if instruction uses VEX encoding. + Evex: bool + True if instruction uses EVEX encoding. + ExpOps: list[Operand] + Processed explicit operands. A list of Operand objects. + ImpOps: list[Operand] + Processed implicit operands. A list of Operand objects. + Attributes: list[str] + A list of instruction attributes (example: ['MODRM', 'I64']). Each attriubute in this list + must be one of the values listed in valid_attributes. + Prefmap: list[str] + A list of accepted prefixes (example: ['LOCK', 'HLE']). Each prefix in this list must be one + of the values listed in valid_prefixes. + Set: str + Instruction set (example: 'ABCD'). + Category: str + Instruction category (example: 'XYZQ'). + Class: str + Instruction class. Usually the same as the mnemonic. Can be overridden, if it is explicitly + specified. + Rwm: list[str] + Operand access map (example: ['RW', 'W']). Length must be equal to len(ExpOps) + len(ImpOps). + Inside the Rwm list, the entry at position x indicates the access mode for operand x. + Id: str + CPUID feature flag, if any (example: 'AVX512VBMI2'). + Tuple: str + EVEX tuple, if any (example: 'fvm'). + ExType: str + Exception type, if any (example: '1', or 'EVEX_PP2'). + Rflags: dict + Flags access mode (example: {'m': ['CF'], 't': ['CF'], 'u': ['ZF'], '0': ['AF'], '1': ['OF']}). + A dictionary with keys 'm' (modified), 't' (tested), 'u' (undefined), '0' (cleared), '1' (set), + and each key pointing to a list of flags which are accessed in the indicated mode. + FpuFlags: list[str] + FPU flags access mode (example: ['u', 'u', 'u', 'u']). A list of 4 str elements, each one + indicating the access mode for flag Cx, where x is the position in the list. + Modes: list[str] + Valid operating modes for the indicated instruction. + Encoding: dict + A dictionary containing all the encoding components. + """ + def __init__(self, mnemonic, expops, impops, encoding, meta): # Fill in raw instruction information - self.Mnemonic = iinfo["mnemonic"] - self.RawEnc = iinfo["encoding"] - self.Flags = iinfo["flags"] - self.Prefmap = iinfo["prefixes"] - self.Set = iinfo["set"] - self.Category = iinfo["cat"] - self.Class = iinfo["class"] - self.Rwm = iinfo["rwm"] - self.Id = iinfo["cff"] or self.Set - self.Tuple = iinfo["tuple"] - self.ExClass = iinfo["exclass"] - self.RevFlagsAccess = iinfo["flgaccess"] - self.Modes = iinfo["modes"] - self.FpuFlags = iinfo["fpuflg"] + self.Mnemonic = mnemonic + self.RawExpOps = expops + self.RawImpOps = impops + self.RawEnc = encoding + self.RawMeta = meta + self.DecoFlags = [] - # First redirecton class: opcodes - self.Opcodes = [] - self.Prefixes = [] - self.DecoFlags = [] - # Second redirection class: Modrm - self.HasModrm = self.ModrmRedirAfterMpref = False - self.Mod = self.Reg = self.Rm = None - # Third redirection class: mandatory prefix. - self.Np = self.MustHave66 = self.MustHaveF2 = self.MustHaveF3 = False - # Fourth redirection class: operating mode - self.RedM16 = self.RedM32 = self.RedM64 = False - # Fifth redirection class: default operand size - self.RedDs16 = self.RedDs32 = self.RedDs64 = self.RedDDs64 = self.RedFDs64 = False - # Sixth redirection class: default address size - self.RedAs16 = self.RedAs32 = self.RedAs64 = False - # Seventh redirecton class: rex, rex.w, rep, repz, rip rel - self.RedRexB = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = self.RedRipRel = False - # Misc - vendor - self.Vendor = None - # Misc - feature. - self.Feature = None + # Assume no XOP/VEX/EVEX. + self.Xop = self.Vex = self.Evex = False - # XOP, VEX and EVEX classes. - self.Vex = self.Xop = self.Evex = self.Mvex = False - self.M = self.P = self.L = self.W = None + # Pre-process the mnemonic, which may contain decorators. + for vd in valid_decorators: + if vd in self.Mnemonic: + self.DecoFlags.append(deco_flags[vd]) + self.Mnemonic = self.Mnemonic.replace(vd, '') - # Now parse each info chunk and extract the actual data - for t in iinfo["encoding"].split(' '): - if '0x66' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): - self.Prefixes.append(0x66) - self.MustHave66 = True - elif '0xF3' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): - self.Prefixes.append(0xF3) - self.MustHaveF3 = True - elif '0xF2' == t and not self.Opcodes and not (self.Xop or self.Vex or self.Evex): - self.Prefixes.append(0xF2) - self.MustHaveF2 = True - elif 'NP' == t: - self.Np = True - elif 'a0xF3' == t: - self.Prefixes.append(0xF3) - self.RedF3 = True - elif 'o64' == t: - self.Red64 = True - elif 'rexw' == t: - self.RedRexW = True - elif 'rexb' == t: - self.RedRexB = True - elif 'rep' == t: - self.RedRep = True - elif 'riprel' == t: - self.RedRipRel = True - elif 'ds16' == t: - self.RedDs16 = True - elif 'ds32' == t: - self.RedDs32 = True - elif 'ds64' == t: - self.RedDs64 = True - elif 'dds64' == t: - self.RedDDs64 = True - elif 'fds64' == t: - self.RedFDs64 = True - elif 'as16' == t: - self.RedAs16 = True - elif 'as32' == t: - self.RedAs32 = True - elif 'as64' == t: - self.RedAs64 = True - elif t.startswith('/'): - self.HasModrm = True - self.Flags.append('MODRM') - if t.endswith(':mem'): - self.Mod = 'mem' - if t.endswith('reg'): - self.Mod = 'reg' - t = t.replace(':mem', '').replace(':reg', '') - for i in range(0, 8): - if '/%d' % i == t: - self.Reg = i - if re.match(r'0x[0-9a-fA-F]{2}', t[1:]): - mrm = int(t[1:], 16) - if 0xC0 == (mrm & 0xC0): - self.Mod = 'reg' - else: - self.Mod = 'mem' - self.Rm = mrm & 7 - self.Reg = (mrm >> 3) & 7 - elif 'modrm' == t: - self.HasModrm = True - self.Flags.append('MODRM') - elif t.startswith('mod:'): - self.Mod = t[4:] - if self.Mod not in ['mem', 'reg']: - raise InvalidEncodingException('Invalid encoding: illegal "mod" modifier') - elif t.startswith('reg:'): - self.Reg = t[4:] - if self.Reg not in ['0', '1', '2', '3', '4', '5', '6', '7']: - raise InvalidEncodingException('Invalid encoding: illegal "reg" value') - self.Reg = int(self.Reg) - elif t.startswith('rm:'): - self.Rm = t[3:] - if self.Rm not in ['0', '1', '2', '3', '4', '5', '6', '7']: - raise InvalidEncodingException('Invalid encoding: illegal "rm" value') - self.Rm = int(self.Rm) - elif t.startswith('modrmpmp'): - self.ModrmRedirAfterMpref = True - elif t == 'xop': - self.Xop = True - elif t == 'vex': - self.Vex = True - elif t == 'evex': - self.Evex = True - elif t == 'mvex': - self.Mvex = True - elif t.startswith('m:'): - self.M = t[2:] - if self.M not in ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C']: - raise InvalidEncodingException('Invalid encoding: illegal "mmmmm" value') - self.M = int(self.M, 16) - elif t.startswith('p:'): - self.P = t[2:] - if not self.P in ['0', '1', '2', '3']: - raise InvalidEncodingException('Invalid encoding: illegal "pp" value!') - self.P = int(self.P) - elif t.startswith('l:'): - self.L = t[2:] - if self.L == '128': - self.L = 0 - elif self.L == '256': - self.L = 1 - elif self.L == '512': - self.L = 2 - elif self.L == 'x': - self.L = None - elif self.L == 'i': - self.L = None - if 'LIG' not in self.Flags: - self.Flags.append('LIG') - elif self.L in ['0', '1', '2', '3']: - self.L = int(self.L) - else: - raise InvalidEncodingException('Invalid encoding: illegal "l" value!') - elif t.startswith('w:'): - self.W = self.RawW = t[2:] - if self.W == 'x': - self.W = None - elif self.W == 'i': - self.W = None - if 'WIG' not in self.Flags: - self.Flags.append('WIG') - elif self.W in ['0', '1']: - self.W = int(self.W) - else: - raise InvalidEncodingException('Invalid encoding: illegal "w" value!') - elif re.match(r'0x[0-9a-fA-F]{2}', t): - self.Opcodes.append(int(t, 16)) - elif t in ['intel', 'amd', 'via', 'cyrix']: - self.Vendor = t - elif t in ['mpx', 'cet', 'cldm', 'piti']: - self.Feature = t - elif 'vsib' == t: - self.HasVsib = True - if 'VSIB' not in self.Flags: - self.Flags.append('VSIB') - elif 'mib' == t: - self.HasMib = True - if 'MIB' not in self.Flags: - self.Flags.append('MIB') - elif 'bitbase' == t: - self.HasBitbase = True - if 'BITBASE' not in self.Flags: - self.Flags.append('BITBASE') - elif 'sibmem' == t: - self.HasSibMem = True - if 'SIBMEM' not in self.Flags: - self.Flags.append('SIBMEM') - elif t in ['ib', 'iw', 'iz', 'iv', 'id', 'cb', 'cz', 'cv', 'cp', 'is4']: - # Not used for now, but they must be specified, for a complete instruction encoding specification. - pass - elif t.startswith('evex.'): - tokens2 = t.split('.') - self.Evex = True - self.M = self.P = self.L = self.W = 0 - for t2 in tokens2[1:]: - # Handle the L specifier - if t2 == 'LIG': - self.L = None - if 'LIG' not in self.Flags: - self.Flags.append('LIG') - elif t2 == 'LANY': - self.L = None - elif t2 == '128' or t2 == 'LZ' or t2 == 'L0': - self.L = 0 - elif t2 == '256' or t2 == 'L1': - self.L = 1 - elif t2 == '512' or t2 == 'L2': - self.L = 2 - # Handle the W specifier - elif t2 == 'WIG': - self.W = None - if 'WIG' not in self.Flags: - self.Flags.append('WIG') - elif t2 == 'WANY': - self.W = None - elif t2 == 'W0': - self.W = 0 - elif t2 == 'W1': - self.W = 1 - # Handle compressed prefix - elif t2 == '66': - self.P = 1 - elif t2 == 'F3': - self.P = 2 - elif t2 == 'F2': - self.P = 3 - # Handle opcode map - elif t2 == '0F': - self.M = 1 - elif t2 == '0F38': - self.M = 2 - elif t2 == '0F3A': - self.M = 3 - elif t2 in ['NDS', 'NDD', 'DDS']: - pass - else: - raise InvalidEncodingException('Invalid encoding: unknown evex token: %s/%s' % (t, t2)) - else: - raise InvalidEncodingException('Invalid encoding: Unknown token: %s' % t) + # Parse meta-information. + if self.RawMeta: + self.process_meta() + + # Parse the instruction encoding. + if self.RawEnc: + self.process_encoding() + else: + raise InvalidSpecificationException("Instruction with no encoding specified: " + self.Mnemonic) # Pre-process the explicit operands. The mask register is contained as a decorator, but put it as a direct # operand as well. The access flag is already present in rwm. - if len(iinfo["expops"]) >= 1 and iinfo["expops"][0].find("{K") > 0: - iinfo["expops"].insert(1, 'aKq') + if len(self.RawExpOps) >= 1 and self.RawExpOps[0].find('{K') > 0: + self.RawExpOps.insert(1, 'aKq') # Parse the explicit instruction operands. - self.ExpOps = self.process_operands(iinfo["expops"], False) + self.ExpOps = self.process_operands(self.RawExpOps, False) # Parse the implicit instruction operands. - self.ImpOps = self.process_operands(iinfo["impops"], True) + self.ImpOps = self.process_operands(self.RawImpOps, True) # Post-process the operands. We fill up the flags with additional info based on the operands. + usesv = usesvp = False for op in self.ExpOps: for deco in op.Decorators: - self.DecoFlags.append({'{K}':'MASK', '{z}':'ZERO', '{sae}':'SAE', '{er}':'ER', '|B32':'BROADCAST', '|B64':'BROADCAST', '|B16':'BROADCAST'}[deco]) - if op.Type in ['U', 'V', 'W', 'H', 'L'] and 'VECT' not in self.Flags: - self.Flags.append('VECT') + self.DecoFlags.append(deco_flags[deco]) + if op.Type in ['U', 'V', 'W', 'H', 'L']: + self.add_attribute('VECTOR') + if op.Type in ['B', 'H', 'vK', 'vT', 'dfv']: + usesv = True + if self.Evex: + if op.Type in ['B', 'H']: + usesvp = True + if 'VSIB' in self.Attributes: + usesvp = True + if self.Encoding["sc"]: + usesvp = True + if self.Xop or self.Vex or self.Evex: + if not usesv: + self.add_attribute('NOV') + if self.Evex and not usesvp: + self.add_attribute('NOVP') - # VEX, XOP, EVEX and MVEX instructions are not valid in real or v8086 modes. - if self.Vex or self.Xop or self.Evex or self.Mvex: + + # VEX, XOP, EVEX instructions are not valid in real or v8086 modes. + if self.Vex or self.Xop or self.Evex: if 'real' in self.Modes: self.Modes.remove('real') if 'v8086' in self.Modes: self.Modes.remove('v8086') - if 'long' not in self.Modes and 'II64' not in self.Flags: - self.Flags.append('II64') - if 'long' in self.Modes and 'prot' not in self.Modes and 'O64' not in self.Flags: - self.Flags.append('O64') - - # Split the instruction into encoding entities. - e = self.split_encoding() - if self.Vex or self.Xop or self.Evex: - self.Spec = { - "mmmmm" : e[0], - "opcodes" : e[1], - "modrm" : e[2], - "pp" : e[3], - "l" : e[4], - "w" : e[5], - } - else: - self.Spec = { - "opcodes" : e[0], - "modrm" : e[1], - "mpre" : e[2], - "mode" : e[3], - "dsize" : e[4], - "asize" : e[5], - "opre" : e[6], - "vendor" : e[7], - "feature": e[8] - } - - def process_operands(self, ops, imp = False): - p = 1 - res = [] - for op in ops: - if op in absent_op: - break - flags = [] - if not imp: - for f in self.Flags: - if f.startswith('OP%d' % p): - flags.append('OP' + f[3:]) - self.Flags.remove(f) - else: - flags.append('OPDEF') - if not imp: - res.append(Operand(op, self.Rwm[p - 1], flags, imp)) - else: - res.append(Operand(op, self.Rwm[len(self.ExpOps) + p - 1], flags, imp)) - p += 1 - return res - - def split_encoding(self): - if self.Vex or self.Xop or self.Evex or self.Mvex: - return self.split_encoding_vex() - else: - return self.split_encoding_legacy() - - def split_encoding_vex(self): - # First, get the 'mmmmm' - VEX decoding table. - mmmmm = '%x' % self.M - # Now get the opcode. Should be only one. - opcodes = ['%02x' % x for x in self.Opcodes] - # Get the modrm redirections. - modrm = { "mod": self.Mod, "reg": my_str(self.Reg), "rm": my_str(self.Rm), "modpost": None } - # Get the pp, if any. - pp = my_str(self.P) - # Get the l, if any. - l = my_str(self.L) - # Get the w, if any. - w = my_str(self.W) - return (mmmmm, opcodes, modrm, pp, l, w) - - def split_encoding_legacy(self): - # First redirection class, the opcode. - opcodes = ['%02x' % x for x in self.Opcodes] - # Second redirection class, modrm - modrm = { "mod": self.Mod, "reg": my_str(self.Reg), "rm": my_str(self.Rm), "modpost": None } - # Third redirection class, mandatory prefixes - mprefixes = [] - if self.MustHaveF2: - mprefixes.append('F2') - if self.MustHaveF3: - mprefixes.append('F3') - if self.MustHave66: - mprefixes.append('66') - if self.Np: - mprefixes.append('NP') - if len(mprefixes) == 0 and (not (self.Xop or self.Vex or self.Evex or self.Mvex)) and\ - (self.Opcodes[0] == 0x0F and self.Opcodes[1] in [0x3A, 0x38]): - mprefixes.append(None) - # Fourth redirection class, operating mode. - mode = [] - if self.RedM16: - mode.append('m16') - elif self.RedM32: - mode.append('m32') - elif self.RedM64: - mode.append('m64') - # Fifth redirection class, default operand size. - dsize = [] - if self.RedDs16: - dsize.append('ds16') - elif self.RedDs32: - dsize.append('ds32') - elif self.RedDs64: - dsize.append('ds64') - elif self.RedDDs64: - dsize.append('dds64') - elif self.RedFDs64: - dsize.append('fds64') - # Sixth redirection class, default address size. - asize = [] - if self.RedAs16: - asize.append('as16') - elif self.RedAs32: - asize.append('as32') - elif self.RedAs64: - asize.append('as64') - # Seventh redirection class, REX prefix, REX.W, 64 bit mode, 0xF3, SIB. The important aspect here is that unlike - # the other classes, this is not exhaustive - if an instruction does not fit in any of the entries, it - # will default to index 0 (and it will not return invalid encoding, unless entry 0 is invalid). - oprefixes = [] - if self.RedRexB: - oprefixes.append('rexb') - if self.RedRexW: - oprefixes.append('rexw') - if self.Red64: - oprefixes.append('64') - if self.RedF3: - oprefixes.append('aF3') - if self.RedRep: - oprefixes.append('rep') - if self.RedRipRel: - oprefixes.append('riprel') - # Vendor redirection, if any. - return (opcodes, modrm, mprefixes, mode, dsize, asize, oprefixes, self.Vendor, self.Feature) + if 'long' not in self.Modes and 'I64' not in self.Attributes: + self.Attributes.append('I64') + if 'long' in self.Modes and 'prot' not in self.Modes and 'O64' not in self.Attributes: + self.Attributes.append('O64') - def __str__(self): - # Get the operands - ops = '' - for o in self.ExpOps: - ops += o.__str__() + ',' - ops = ops[:-1] + def process_meta(self): + """ + Extract all the meta-data from the instruction spec, and fill in class attributes. + """ + self.Attributes = [] + self.Prefmap = [] + self.Set = 'UNKNOWN' + self.Category = 'UNKNOWN' + self.Class = self.Mnemonic + self.Rwm = None + self.Id = self.Set + self.Tuple = None + self.ExType = None + self.EvexMode = None + self.Rflags = {'m': [], 't': [], '0': [], '1': [], 'u': []} + self.FpuFlags = ['u', 'u', 'u', 'u'] + self.Modes = valid_cpu_modes.copy() - # Return a text reprezentation of the encoding - return (self.Mnemonic + ' ' + ops).strip() + for y in self.RawMeta: + token, value = y.strip().split(':') - - -def parse_entry(entry, template_flags = {}, template_cpuid = {}, template_modes = {}): - # Make sure this is not a comment. Skip comments. - if entry.startswith('#') or len(entry) < 4: - return None - - # Preprocess: remove comments, CR/LF - entry = entry.replace('\x0D', '').replace('\x0A', '') - com = entry.find('#') - if -1 != com: x = entry[:com] - - try: - # Space can't be the first character. - if entry[0] == ' ': - raise ParseLineException('Space cannot be the first character!') - - components = entry.split(';') - if len(components) != 5: - raise ParseLineException('Expected 5 components per line, but found %d (missing semicolon?)!' % len(components)) - - mnemonic = components[0].strip() - expops = components[1].strip().split(',') - impops = components[2].strip().split(',') - encoding = components[3].strip() - misc = components[4].strip().split(',') - - if len(expops) == 1 and expops[0] in absent_op: - expops = [] - - if len(impops) == 1 and impops[0] in absent_op: - impops = [] - - # Extract the flags, class, set, category, encoding, prefmap - attributes = prefmap = isaset = category = iclass = adop = rwm = None - cff = tuple = flgaccess = modes = exclass = fpuflg = None - - for y in misc: - y = y.strip() - token, value = y.split(':') - - # parse token - if token == 'a': # Instruction attributes. - attributes = value.split('|') - elif token == 'p': # Accepted prefixes. - prefmap = value.split('|') - elif token == 's': # Instruction set - isaset = value - elif token == 't': # Instruction type - category = value - elif token == 'c': # Instruction class. Defaults to the mnemonic if not specified. - iclass = value - elif token == 'w': # Read/write map - rwm = value.split('|') - elif token == 'i': # CPUID. - cff = value - elif token == 'l': # tuple - tuple = value + if token == 'a': + # Instruction attributes. + self.Attributes = value.split('|') + for a in self.Attributes: + if a not in valid_attributes: + raise InvalidSpecificationException( + "Unknown attribute specifier '%s', expecting one of [%s]" % (a, ','.join(valid_attributes))) + elif token == 'p': + # Accepted prefixes. + self.Prefmap = value.split('|') + for p in self.Prefmap: + if p not in valid_prefixes: + raise InvalidSpecificationException( + "Unknown prefix specifier '%s', expecting one of [%s]" % (p, ','.join(valid_prefixes))) + elif token == 's': + # Instruction set. + self.Set = self.Id = value + elif token == 't': + # Instruction type. + self.Category = value + elif token == 'c': + # Instruction class. + self.Class = value + elif token == 'w': + # Operand access. + self.Rwm = value.split('|') + # The read/write map must have the same size as the number of operands. + if len(self.Rwm) < len(self.RawExpOps) + len(self.RawImpOps): + raise InvalidSpecificationException( + "Invalid number of operand access specifiers: provided %d, expecting %d" % + (len(self.Rwm), len(self.RawExpOps) + len(self.RawImpOps))) + for r in self.Rwm: + if r not in valid_access: + raise InvalidSpecificationException( + "Unknown operand access specifier '%s', expecting one of [%s]" % (r, ','.join(valid_access))) + elif token == 'i': + # CPUID flag. + self.Id = value + elif token == 'l': + # EVEX tuple. + self.Tuple = value + if self.Tuple not in valid_tuples: + raise InvalidSpecificationException( + "Unknown tuple specifier '%s', expecting one of [%s]" % (self.Tuple, ','.join(valid_tuples))) + elif token == 'v': + # EVEX mode. + self.EvexMode = value + if self.EvexMode not in valid_evex_mode: + raise InvalidSpecificationException("Unknown evex extension type '%s', expecting one of [%s]" % + (self.EvexMode, ','.join(valid_evex_mode))) elif token == 'e': - exclass = value - elif token == 'f': # Flags access + # VEX/EVEX exception type. + self.ExType = value + elif token == 'f': + # RFLAGS access. flgaccess = [] for v in value.split('|'): if v in template_flags: flgaccess += template_flags[v].split('|') else: flgaccess.append(v) + revflg = {} + for m in valid_flag_op: + revflg[m] = [] + for flg in flgaccess: + f, m = flg.split('=') + if m not in valid_flag_op: + raise InvalidSpecificationException( + "Unknown flag access specifier '%s', expecting one of [%s]" % (m, ','.join(valid_flag_op))) + if f not in valid_flags: + raise InvalidSpecificationException( + "Unknown flag specifier '%s', expecting one of [%s]" % (f, ','.join(valid_flags))) + revflg[m].append(f) + flgaccess = revflg + self.Rflags = flgaccess elif token == 'u': - fpuflg = ['u', 'u', 'u', 'u'] # each one is undefined. + # FPU flags access. + self.FpuFlags = ['u', 'u', 'u', 'u'] # each one is undefined. for v in value.split('|'): flg, acc = v.split('=') if flg not in ['C0', 'C1', 'C2', 'C3']: - raise ParseLineException('Unknown FPU flag: %s' % flg) + raise InvalidSpecificationException("Unknown FPU flag: %s" % flg) if acc not in ['0', '1', 'm', 'u']: - raise ParseLineException('Unknown FPU flag access: %s' % acc) - fpuflg[int(flg[1])] = acc - elif token == 'm': # CPU modes. + raise InvalidSpecificationException("Unknown FPU flag access: %s" % acc) + self.FpuFlags[int(flg[1])] = acc + elif token == 'm': # Example: m:ring=0,1,2,3|vmx=root,nonroot|mode=real,v8086,smm,prot,compat,long|other=sgx,tsx # Note: any group that is not specified is considered entirely valid # Note: any group that is specified overrides all the other fields in the group; example: @@ -1125,156 +953,330 @@ def parse_entry(entry, template_flags = {}, template_cpuid = {}, template_modes groups = {} for g in valid_mode_groups: groups[g] = {} - groups[g]["negated"] = False - groups[g]["specified"] = False - groups[g]["modes"] = [] + groups[g]['negated'] = False + groups[g]['specified'] = False + groups[g]['modes'] = [] for tm in tmodes: m, v = tm.split('=') for vx in v.split('+'): - negated = False if vx.startswith('!'): vx = vx[1:] - groups[m]["negated"] = True + groups[m]['negated'] = True if m not in valid_mode_groups: - raise ParseLineException('Unknown CPU mode group specified: %s' % m) + raise InvalidSpecificationException("Unknown CPU mode group specified: %s" % m) if vx not in valid_mode_map[m]: - raise ParseLineException('Mode %s is not valid for mode group %s; it can be one of [%s]' % - (vx, m, ','.join(valid_mode_map[m]))) - groups[m]["specified"] = True - groups[m]["modes"].append(vx) + raise InvalidSpecificationException("Mode %s is not valid for mode group %s; it can be one of [%s]" % + (vx, m, ','.join(valid_mode_map[m]))) + groups[m]['specified'] = True + groups[m]['modes'].append(vx) for g in groups: - if not groups[g]["specified"]: + if not groups[g]['specified']: modes += valid_mode_map[g] - elif not groups[g]["negated"]: - modes += groups[g]["modes"] + elif not groups[g]['negated']: + modes += groups[g]['modes'] else: - modes += [x for x in valid_mode_map[g] if x not in groups[g]["modes"]] + modes += [x for x in valid_mode_map[g] if x not in groups[g]['modes']] + + for m in modes: + if m.startswith('!'): + m = m[1:] + if m not in valid_cpu_modes: + raise InvalidSpecificationException("Unknown CPU mode specifier '%s', expecting one of [%s]" % + (m, ','.join(valid_cpu_modes))) + + self.Modes = modes else: - raise ParseLineException('Unknown token specified: %s' % token) + raise InvalidSpecificationException("Unknown token specified: %s" % token) - if attributes is None: - attributes = [] - if prefmap is None: - prefmap = [] - if isaset is None: - isaset = 'UNKNOWN' - if category is None: - category = 'UNKNOWN' - if iclass is None: - iclass = mnemonic - if rwm is None: - rwm = [] - if cff is None: - cff = None - if modes is None: - # No mode specified, assume validity in all modes. - modes = [] - modes += valid_cpu_modes - if flgaccess is None: - flgaccess = [] - if fpuflg is None: - # fpuflg[x] is for Cx (fpuflg[0] = C0, fpuflg[1] = C1, etc.) - # u = undefined, m = modified, 0 = cleared to 0, 1 = set to 1. - fpuflg = ['u', 'u', 'u', 'u'] - # Validate the tokens. - # The set can be anything. - # The type can be anything. - # The iclass can be missing, it will default to the mnemonic. - - # The read/write map must have the same size as the number of operands. - if len(rwm) < len(expops) + len(impops): - raise ParseLineException('Invalid number of operand access specifiers: provided %d, expecting %d' % - (len(rwm), len(expops) + len(impops))) - for r in rwm: - if r not in valid_access: - raise ParseLineException('Unknown operand access specifier "%s", expecting one of [%s]' % - (r, ','.join(valid_access))) - # The CPUID can be anything, even if it doesn't match something specified in cpuid.dat. - - # The modes must be one of the valid modes. - for m in modes: - if m.startswith('!'): - m = m[1:] - if m not in valid_cpu_modes: - raise ParseLineException('Unknown CPU mode specifier "%s", expecting one of [%s]' % - (m, ','.join(valid_cpu_modes))) - - # Validate the prefixes. - for p in prefmap: - if p not in valid_prefixes: - raise ParseLineException('Unknown prefix specifier "%s", expecting one of [%s]' % - (p, ','.join(valid_prefixes))) - - # Validate the tuples. - if tuple and tuple not in valid_tuples: - raise ParseLineException('Unknown tuple specifier "%s", expecting one of [%s]' % - (tuple, ','.join(valid_tuples))) - - # Validate the attributes. - for a in attributes: - if a not in valid_attributes: - raise ParseLineException('Unknown attribute specifier "%s", expecting one of [%s]' % - (a, ','.join(valid_attributes))) - - # Validate the flags. - revflg = {} - for m in valid_flag_op: - revflg[m] = [] - for flg in flgaccess: - f, m = flg.split('=') - if m not in valid_flag_op: - raise ParseLineException('Unknow flag access specifier "%s", expecting one of [%s]' % - (m, ','.join(valid_flag_op))) - if f not in valid_flags: - raise ParseLineException('Unknow flag specifier "%s", expecting one of [%s]' % - (f, ','.join(valid_flas))) - revflg[m].append(f) - flgaccess = revflg - - iinfo = { - "mnemonic" : mnemonic, # Mnemonic - "expops" : expops, # Explicit operands - "impops" : impops, # Implicit operands - "encoding" : encoding, # Encoding - "flags" : attributes, # Instruction attributes - "prefixes" : prefmap, # Accepted prefixes - "set" : isaset, # Instruction set - "cat" : category, # Instruction category - "class" : iclass, # Instruction class - "rwm" : rwm, # Read/write operands map - "cff" : cff, # CPUID feature flag - "tuple" : tuple, # Tuple type, for EVEX instruxtions - "exclass" : exclass, # Exception class, for SSE/VEX/EVEX instructions - "flgaccess" : flgaccess, # RFLAGS access - "modes" : modes, # Valid operating modes - "fpuflg" : fpuflg, # FPU flags access (C0, C1, C2, C3), valid for x87 instructions only + def process_encoding(self): + """ + Extract all the encoding fields from the instruction spec, and fill in the Encoding dictionary. + Once instruction grouping has been performed, the Encoding dictionary may be left with empty values. + This function can be called an arbitrary number of times to regenerate the Encoding dictionary. + """ + # The order of the entries in Encoding does not matter. When grouping instructions, whoemever does the grouping, + # can choose whatever order they wish. + self.Encoding = { + 'opcode' : [], # Opcode group + 'opcode_last' : [], # Opcode group, but opcode comes after ModR/M (3DNow! instructions) + 'vendor' : [], # Vendor grouping + 'feature' : [], # Feature grouping; generally useful for instructions which act like NOP if feature is off + 'prefix' : [], # Mandatory prefix grouping: NP, 0x66, 0xF3, 0xF2 + 'modrmreg' : [], # ModR/M.reg group + 'modrmmod' : [], # ModR/M.mod group (mem or reg) + 'modrmrm' : [], # ModR/M.rm group + 'mode' : [], # Operating mode group (16, 32, 64) + 'dsize' : [], # Data size group + 'asize' : [], # Address size group + 'auxiliary' : [], # Other grouping criteria + 'mmmmm' : [], # XOP/VEX/EVEX.map + 'pp' : [], # XOP/VEX/EVEX.pp, compressed prefix + 'l' : [], # XOP/VEX/EVEX.l, vector length + 'w' : [], # XOP/VEX/EVEX.w, width + 'wi' : [], # XOP/VEX/EVEX.w, width, but ignored if outside 64-bit + 'nd' : [], # EVEX.nd, new data destination + 'nf' : [], # EVEX.nf, no flags + 'sc' : [], # EVEX.sc, standard condition code } - if 'PREFIX' in attributes: - return None + had_modrm = False - try: - ins = Instruction(iinfo) - except: - raise - - except Exception as e: - raise - - return ins + # Now parse each info chunk and extract the actual data + for t in self.RawEnc.split(' '): + if not t: + continue # Skip empty tokens + if t == 'xop': + self.Xop = True + elif t == 'vex': + self.Vex = True + elif t == 'evex': + self.Evex = True + # Mandatory prefixes. + elif t in ['NP', '0x66', '0xF3', '0xF2'] and not self.Encoding['opcode'] and not (self.Xop or self.Vex or self.Evex): + self.Encoding['prefix'].append('P' + t) # Prefix with P, so we don't confuse this with an opcode. + # Auxiliary conditions. + elif t in ['repz', 'mo64', 'rexw', 'rexb', 'rep', 'riprel', 'rex2', 'rex2w']: + self.Encoding['auxiliary'].append(t) + # Data size. + elif t in ['ds16', 'ds32', 'ds64', 'dds64', 'fds64']: + self.Encoding['dsize'].append(t) + # Address size. + elif t in ['as16', 'as32', 'as64']: + self.Encoding['asize'].append(t) + # Vendor. + elif t in ['intel', 'amd']: + self.Encoding['vendor'].append(t) + # Feature. + elif t in ['mpx', 'cet', 'cldm', 'piti']: + self.Encoding['feature'].append(t) + # ModR/M. + elif t.startswith('/'): + had_modrm = True + self.add_attribute('MODRM') + if m := re.match(r'^/r$', t): + pass + elif m := re.match(r'^/r:(reg|mem)$', t): + # Modrm mod + self.Encoding['modrmmod'].append(m[1]) + elif m := re.match(r'^/([0-7])$', t): + # Modrm reg + self.Encoding['modrmreg'].append(str(m[1])) + elif m := re.match(r'^/([0-7]):(reg|mem)$', t): + # Modrm reg & mod + self.Encoding['modrmreg'].append(str(m[1])) + self.Encoding['modrmmod'].append(m[2]) + # Handle opcode-like ModR/M + elif m := re.match(r'^/(0x[0-9a-fA-F]{2})$', t): + mrm = int(m[1], 16) + if 0xC0 == (mrm & 0xC0): + self.Encoding['modrmmod'].append('reg') + else: + self.Encoding['modrmmod'].append('mem') + self.Encoding['modrmrm'].append(str(mrm & 7)) + self.Encoding['modrmreg'].append(str((mrm >> 3) & 7)) + else: + raise InvalidSpecificationException("Invalid encoding: modrm specification is invalid: '%s'!" % t) + # Modrm.rm value. + elif m := re.match(r'^rm:([0-7])$', t): + self.Encoding['modrmrm'].append(m[1]) + # Map field inside XOP/VEX/EVEX. + elif m := re.match(r'^m:([0-9A-C])$', t): + self.Encoding['mmmmm'].append(m[1]) + # Compressed prefix field inside XOP/VEX/EVEX. + elif m := re.match(r'^p:([0-3])$', t): + self.Encoding['pp'].append(m[1]) + # Vector length field inside XOP/VEX/EVEX. + elif m := re.match(r'^l:([x|i|0|1|2|3])$', t): + if m[1] == 'x': + pass + elif m[1] == 'i': + self.add_attribute('LIG') + else: + self.Encoding['l'].append(m[1]) + # W field inside XOP/VEX/EVEX/REX2. + elif m := re.match(r'^w:(x|i|0|1)$', t): + if m[1] == 'x': + pass + elif m[1] == 'i': + self.add_attribute('WIG') + else: + if 'IWO64' in self.Attributes: + self.Encoding['wi'].append(m[1]) + else: + self.Encoding['w'].append(m[1]) + # New Data Destination field inside EVEX. + elif m := re.match(r'^nd:(0|1)$', t): + self.Encoding['nd'].append(m[1]) + # No Flags field inside EVEX. + elif m := re.match(r'^nf:(0|1)$', t): + self.Encoding['nf'].append(m[1]) + # Standard Condition Code field inside EVEX. + elif m := re.match(r'^sc:([0-9A-F]{1})$', t): + self.Encoding['sc'].append(m[1]) + # Opcode. + elif re.match(r'^0x[0-9a-fA-F]{2}$', t): + if had_modrm: + self.Encoding['opcode_last'].append(t) + else: + self.Encoding['opcode'].append(t) + # Misc encoding & addressing + elif 'vsib' == t: + self.add_attribute('VSIB') + elif 'mib' == t: + self.add_attribute('MIB') + elif 'bitbase' == t: + self.add_attribute('BITBASE') + elif 'sibmem' == t: + self.add_attribute('SIBMEM') + # Misc immediates + elif t in ['ib', 'iw', 'iz', 'iv', 'id', 'cb', 'cz', 'cv', 'cp', 'cq', 'is4']: + # Not used for now, but they must be specified, for a complete instruction encoding specification. + pass + else: + raise InvalidSpecificationException(f"Invalid encoding: Unknown token: {t}") + def process_operands(self, ops, imp = False): + """ + Process the provided operands list, and generate a list of Operand objects. + """ + p, res = 1, [] + for op in ops: + if op in absent_op: + break + flags = [] + if not imp: + for f in self.Attributes: + if f.startswith('OP%d' % p): + flags.append('OP' + f[3:]) + self.Attributes.remove(f) + else: + flags.append('OPDEF') + if not imp: + res.append(Operand(op, self.Rwm[p - 1], flags, imp)) + else: + res.append(Operand(op, self.Rwm[len(self.ExpOps) + p - 1], flags, imp)) + p += 1 + return res -def parse_ins_file(fpath, template_flags = {}, template_cpuid = {}, template_modes = {}): + + def add_attribute(self, attribute): + if attribute not in self.Attributes: + self.Attributes.append(attribute) + + def __str__(self): + ops = '' + for o in self.ExpOps: + ops += o.__str__() + ',' + ops = ops[:-1] + + # Return a text reprezentation of the encoding + return (self.Mnemonic + ' ' + ops).strip() + + +def parse_entry( + entry: str + ) -> Instruction: + """ + Parse one instruction specification line, and return an Instruction object. + For examples on how an entry must look, check any entry inside table_* files. + An instruction specification must contain 5 elements: + 1. The mnemonic + 2. The explicit operands (n/a or empty if none is present) + 3. The implicit operands (n/a or empty if none is present) + 4. The encoding (mandatory, cannot be empty) + 5. Metadata + The instruction metadata includes several 'key:value' pairs; 'key' can be one of the following: + 1. 'a': instruction attributes + 2. 's': instruction set + 3. 'c': instruction class + 4. 'p': accepted prefixes + 5. 'w': operand access map + 6. 'i': CPUID feature flag; by default, the instruction set is used to look up a potential CPUID flag + 7. 'l': EVEX tuple type + 8. 'e': VEX/EVEX exception type + 9. 'v': EVEX mode (normal EVEX, extended VEX, extended legacy, conditional) + 10. 'f': flags access ('m': modified, 't': tested, 'u': undefined, '0': cleared, '1': set to 1) + 11. 'u': FPU flags access + 12. 'm': valid operating modes + + Raises + ------ + InvalidSpecificationException + - If the specification is incomplete + - If an unknwon operand type or size is used + - If an invalid encoding is specified + - If an unknown metadata key is specified + - If any metadata value is invalid/unknown + + Parameters + ---------- + entry: str + The instruction specification. + + Returns + ------- + An object representing the instruction. + """ + # Make sure this is not a comment. Skip comments. + if entry.startswith('#') or len(entry) < 4: + return None + + # Preprocess: remove comments, CR/LF + entry = entry.replace('\x0D', '').replace('\x0A', '') + com = entry.find('#') + if -1 != com: x = entry[:com] + + # Space can't be the first character. + if entry[0] == ' ': + raise InvalidSpecificationException("Space cannot be the first character!") + + components = entry.split(';') + if len(components) != 5: + raise InvalidSpecificationException("Expected 5 components per line, but found %d (missing semicolon?)!" % len(components)) + + mnemonic = components[0].strip() + expops = components[1].strip().split(',') + impops = components[2].strip().split(',') + encoding = components[3].strip() + meta = components[4].strip().split(',') + + if len(mnemonic) < 1: + raise InvalidSpecificationException("Mnemonic cannot be empty!") + + if len(expops) == 1 and expops[0] in absent_op: + expops = [] + + if len(impops) == 1 and impops[0] in absent_op: + impops = [] + + return Instruction(mnemonic, expops, impops, encoding, meta) + + +def parse_ins_file( + fpath: str + ) -> list[Instruction]: + """ + Parse an entire instruction specification file, and return a list of Instruction objects. + + Parameters + ---------- + fpath: str + The file containing multiple instruction specifications. + + Returns + ------- + A list containing Instruction objects generated from the specs inside the provided file. + """ instructions = [] lcount = 0 for line in open(fpath, 'rt'): lcount += 1 try: - ins = parse_entry(line, template_flags, template_cpuid, template_modes) + ins = parse_entry(line) if ins: instructions.append(ins) except Exception as e: print('ERROR: Parsing failed at %s:%d: %s' % (fpath, lcount, e)) @@ -1282,26 +1284,22 @@ def parse_ins_file(fpath, template_flags = {}, template_cpuid = {}, template_mod return instructions +def parse_cff_file( + fpath: str + ) -> list[CpuidFeatureFlag]: + """ + Parse the CPUID feature flags file, and return a list of CpuidFeatureFlag objects. -def parse_pre_file(fpath): - prefixes = [] - for line in open(fpath, 'rt'): - # Ignore comments. - if line.startswith('#'): - continue - res = re.findall(r'([^\s]+)\s*\[\s*(0x[0-9a-fA-F]+)\]', line) - if not res: - continue - res = res[0] - pref = {} - pref["mnemonic"] = res[0] - pref["encoding"] = res[1] - prefixes.append(Prefix(pref)) - return prefixes + Parameters + ---------- + fpath: str + The file containing multiple CPUID feature specifications. - - -def parse_cff_file(fpath): + Returns + ------- + A list containing CpuidFeatureFlag objects generated from the specs inside the provided file. + """ + global template_cpuid features = [] for line in open(fpath, 'rt'): if line.startswith('#'): @@ -1311,16 +1309,32 @@ def parse_cff_file(fpath): continue res = res[0] cffi = {} - cffi["name"] = res[0] - cffi["leaf"] = res[1] - cffi["subleaf"] = res[2] - cffi["reg"] = res[3] - cffi["bit"] = res[4] + cffi['name'] = res[0] + cffi['leaf'] = res[1] + cffi['subleaf'] = res[2] + cffi['reg'] = res[3] + cffi['bit'] = res[4] features.append(CpuidFeatureFlag(cffi)) + template_cpuid = features return features -def parse_flags_file(fpath): +def parse_flags_file( + fpath: str + ) -> dict: + """ + Parse the flags access file, and return a list of flags access templates. + + Parameters + ---------- + fpath: str + The file containing multiple flags access templates. + + Returns + ------- + A dictionary containing all the flags access templates in the provided file. + """ + global template_flags flags = {} for line in open(fpath, 'rt'): if line.startswith('#'): @@ -1330,10 +1344,26 @@ def parse_flags_file(fpath): continue res = res[0] flags[res[0]] = res[1].strip('\n\r ') + template_flags = flags return flags -def parse_modess_file(fpath): +def parse_modess_file( + fpath: str + ) -> dict: + """ + Parse the valid modes file, and return a dictionary of existing valid modes templates. + + Parameters + ---------- + fpath: str + The file containing multiple valid modes specifications. + + Returns + ------- + A dictionary containing all the valid modes templates in the provided file. + """ + global template_modes modes = {} for line in open(fpath, 'rt'): if line.startswith('#'): @@ -1343,6 +1373,7 @@ def parse_modess_file(fpath): continue res = res[0] modes[res[0]] = res[1].strip('\n\r ') + template_modes = modes return modes @@ -1357,24 +1388,24 @@ if __name__ == "__main__": sys.exit(-1) # Parse the flags file. - flags = parse_flags_file('%s/flags.dat' % sys.argv[1]) + template_flags = parse_flags_file('%s/flags.dat' % sys.argv[1]) # Parse the cpuid feature flags and extract each feature - features = parse_cff_file('%s/cpuid.dat' % sys.argv[1]) + template_cpuid = parse_cff_file('%s/cpuid.dat' % sys.argv[1]) # Parse the modes file. - modes = parse_modess_file('%s/modes.dat' % sys.argv[1]) + template_modes = parse_modess_file('%s/modes.dat' % sys.argv[1]) # Parse the instruction file and extract the instructions instructions = [] for fn in glob.glob('%s/table*.dat' % sys.argv[1]): - instructions += parse_ins_file(fn, flags, features, modes) + instructions += parse_ins_file(fn) # Sort the instructions. instructions = sorted(instructions, key = lambda x: x.Mnemonic) for i in range(0, len(instructions)): print(instructions[i]) - features = sorted(features, key = lambda x: x.Name) + features = sorted(template_cpuid, key = lambda x: x.Name) for i in range(0, len(features)): print(features[i]) diff --git a/isagenerator/generate_tables.py b/isagenerator/generate_tables.py index 4331ecb..3cb5366 100644 --- a/isagenerator/generate_tables.py +++ b/isagenerator/generate_tables.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 # -# Copyright (c) 2020 Bitdefender +# Copyright (c) 2024 Bitdefender # SPDX-License-Identifier: Apache-2.0 # import os @@ -11,7 +11,7 @@ import glob import disasmlib header = '''/* - * Copyright (c) 2020 Bitdefender + * Copyright (c) 2024 Bitdefender * SPDX-License-Identifier: Apache-2.0 */ @@ -21,447 +21,152 @@ header = '''/* ''' -flags = { - 'MODRM' : 'ND_FLAG_MODRM', - 'II64' : 'ND_FLAG_I64', - 'F64' : 'ND_FLAG_F64', - 'D64' : 'ND_FLAG_D64', - 'O64' : 'ND_FLAG_O64', - 'SSECONDB' : 'ND_FLAG_SSE_CONDB', - 'COND' : 'ND_FLAG_COND', - 'VSIB' : 'ND_FLAG_VSIB', - 'MIB' : 'ND_FLAG_MIB', - 'LIG' : 'ND_FLAG_LIG', - 'WIG' : 'ND_FLAG_WIG', - '3DNOW' : 'ND_FLAG_3DNOW', - 'MMASK' : 'ND_FLAG_MMASK', - 'NOMZ' : 'ND_FLAG_NOMZ', - 'LOCKSP' : 'ND_FLAG_LOCK_SPECIAL', - 'NOL0' : 'ND_FLAG_NOL0', - 'NOA16' : 'ND_FLAG_NOA16', - 'NO66' : 'ND_FLAG_NO66', - 'NORIPREL' : 'ND_FLAG_NO_RIP_REL', - 'VECT' : 'ND_FLAG_VECTOR', - 'S66' : 'ND_FLAG_S66', - 'BITBASE' : 'ND_FLAG_BITBASE', - 'AG' : 'ND_FLAG_AG', - 'SHS' : 'ND_FLAG_SHS', - 'MFR' : 'ND_FLAG_MFR', - 'CETT' : 'ND_FLAG_CETT', - 'SERIAL' : 'ND_FLAG_SERIAL', - 'SIBMEM' : 'ND_FLAG_SIBMEM', - 'I67' : 'ND_FLAG_I67', - 'IER' : 'ND_FLAG_IER', - 'IWO64' : 'ND_FLAG_IWO64', -} +# Set this to True to generate the instructions database with designated initializers format: +# ".FieldName = Value" +# Set this to False to generate the instructions database with aggregate initializers format: +# "/* FieldName */ Value" +# Designated initializers can be used when building as C code (recommended!) or C++ >= 20. +# Aggregate initializers must be used when building as C++ code (NOT recommended). +idbe_format_designated = True -prefixes_map = { - 'REP' : 'ND_PREF_REP', - 'REPC' : 'ND_PREF_REPC', - 'HLE' : 'ND_PREF_HLE', - 'BND' : 'ND_PREF_BND', - 'LOCK' : 'ND_PREF_LOCK', - 'BH' : 'ND_PREF_BHINT', - 'XACQUIRE' : 'ND_PREF_XACQUIRE', - 'XRELEASE' : 'ND_PREF_XRELEASE', - 'HLEWOL' : 'ND_PREF_HLE_WO_LOCK', - 'DNT' : 'ND_PREF_DNT', -} -decorators_map = { - 'MASK' : 'ND_DECO_MASK', - 'BROADCAST': 'ND_DECO_BROADCAST', - 'ZERO' : 'ND_DECO_ZERO', - 'SAE' : 'ND_DECO_SAE', - 'ER' : 'ND_DECO_ER', -} +# +# These are the encoding components used to group instructions. Important things to note: +# - The order here is important! The higher up (the lower the index) for a given component, the more priority it +# receives when grouping instructions +# - The first entry of each tuple is the component type/name +# - The second is a boolean indicating whether the component is mandatory for all or optional +# +# For example, "opcode" is mandatory for all instructions in a group, as we can't group them otherwise. However, +# the auxiliary entry is not mandatory - in a given group, some instructions may have such an entry, while other do +# not. Those that lack an optional component will be treated as "default" encoding. +# +# Example of optional component: +# 0x90 : NOP +# repz 0x90 : PAUSE +# In this case, the `repz` is an optional encoding component, meaning that its presence will cause PAUSE +# to be decoded, but its absence will cause NOP to be decoded. +# +# Example of mandatory component: +# 0x0F 0x00 /0:mem: SLDT Mw +# 0x0F 0x00 /0:reg: SLDT Rv +# In this case, all instructions must specify both the reg component (/0) and the mod (mem or reg). +# If any of them is present for one instruction but absent for another, will lead to an error. For example, the +# following spec will cause an error, since there's no grouping possible, because one of the instructions specifies +# mem mode, while the other does not specify anything: +# 0x0F 0x00 /0:mem : SLDT Mw +# 0x0F 0x00 /0 : SLDT Rv +# +components_legacy = [ + { 'type': 'opcode' , 'all': True }, + { 'type': 'opcode_last' , 'all': True }, + { 'type': 'vendor' , 'all': False }, + { 'type': 'feature' , 'all': False }, + { 'type': 'prefix' , 'all': True }, + { 'type': 'modrmreg' , 'all': True }, + { 'type': 'modrmmod' , 'all': True }, + { 'type': 'modrmrm' , 'all': True }, + { 'type': 'mode' , 'all': False }, + { 'type': 'dsize' , 'all': False }, + { 'type': 'asize' , 'all': False }, + { 'type': 'auxiliary' , 'all': False }, + { 'type': 'w' , 'all': True }, +] -# Per operand flags. -opflags = { - 'OPDEF' : 'ND_OPF_DEFAULT', # Default operand. Not encoded anywhere. - 'OPSEXO1' : 'ND_OPF_SEX_OP1', - 'OPSEXDW' : 'ND_OPF_SEX_DWS', -} +components_ex = [ + { 'type': 'mmmmm' , 'all': True }, + { 'type': 'opcode' , 'all': True }, + { 'type': 'pp' , 'all': True }, + { 'type': 'modrmreg' , 'all': True }, + { 'type': 'modrmmod' , 'all': True }, + { 'type': 'modrmrm' , 'all': True }, + { 'type': 'l' , 'all': True }, + { 'type': 'w' , 'all': True }, + { 'type': 'wi' , 'all': True }, + { 'type': 'nd' , 'all': True }, + { 'type': 'nf' , 'all': True }, + { 'type': 'sc' , 'all': True }, +] -# Explicit operands map. -optype = { - 'A' : 'ND_OPT_A', - 'B' : 'ND_OPT_B', - 'C' : 'ND_OPT_C', - 'D' : 'ND_OPT_D', - 'E' : 'ND_OPT_E', - 'F' : 'ND_OPT_F', - 'G' : 'ND_OPT_G', - 'H' : 'ND_OPT_H', - 'I' : 'ND_OPT_I', - 'J' : 'ND_OPT_J', - 'K' : 'ND_OPT_K', - 'L' : 'ND_OPT_L', - 'M' : 'ND_OPT_M', - 'N' : 'ND_OPT_N', - 'O' : 'ND_OPT_O', - 'P' : 'ND_OPT_P', - 'Q' : 'ND_OPT_Q', - 'R' : 'ND_OPT_R', - 'S' : 'ND_OPT_S', - 'T' : 'ND_OPT_T', - 'U' : 'ND_OPT_U', - 'V' : 'ND_OPT_V', - 'W' : 'ND_OPT_W', - 'X' : 'ND_OPT_X', - 'Y' : 'ND_OPT_Y', - 'Z' : 'ND_OPT_Z', - 'rB' : 'ND_OPT_rB', - 'mB' : 'ND_OPT_mB', - 'rK' : 'ND_OPT_rK', - 'vK' : 'ND_OPT_vK', - 'mK' : 'ND_OPT_mK', - 'aK' : 'ND_OPT_aK', - 'rM' : 'ND_OPT_rM', - 'mM' : 'ND_OPT_mM', - 'rT' : 'ND_OPT_rT', - 'mT' : 'ND_OPT_mT', - 'vT' : 'ND_OPT_vT', - # Implicit operands. - '1' : 'ND_OPT_CONST_1', - 'AH' : 'ND_OPT_GPR_AH', - 'rAX' : 'ND_OPT_GPR_rAX', - 'rCX' : 'ND_OPT_GPR_rCX', - 'rDX' : 'ND_OPT_GPR_rDX', - 'rBX' : 'ND_OPT_GPR_rBX', - 'rSP' : 'ND_OPT_GPR_rSP', - 'rBP' : 'ND_OPT_GPR_rBP', - 'rSI' : 'ND_OPT_GPR_rSI', - 'rDI' : 'ND_OPT_GPR_rDI', - 'rR8' : 'ND_OPT_GPR_rR8', - 'rR9' : 'ND_OPT_GPR_rR9', - 'rR11' : 'ND_OPT_GPR_rR11', - 'rIP' : 'ND_OPT_RIP', - 'CS' : 'ND_OPT_SEG_CS', - 'SS' : 'ND_OPT_SEG_SS', - 'DS' : 'ND_OPT_SEG_DS', - 'ES' : 'ND_OPT_SEG_ES', - 'FS' : 'ND_OPT_SEG_FS', - 'GS' : 'ND_OPT_SEG_GS', - 'ST(0)' : 'ND_OPT_FPU_ST0', - 'ST(i)' : 'ND_OPT_FPU_STX', - 'XMM0' : 'ND_OPT_SSE_XMM0', - 'XMM1' : 'ND_OPT_SSE_XMM1', - 'XMM2' : 'ND_OPT_SSE_XMM2', - 'XMM3' : 'ND_OPT_SSE_XMM3', - 'XMM4' : 'ND_OPT_SSE_XMM4', - 'XMM5' : 'ND_OPT_SSE_XMM5', - 'XMM6' : 'ND_OPT_SSE_XMM6', - 'XMM7' : 'ND_OPT_SSE_XMM7', - - # Memory operands - 'pAX' : 'ND_OPT_MEM_rAX', - 'pCX' : 'ND_OPT_MEM_rCX', - 'pBXAL' : 'ND_OPT_MEM_rBX_AL', - 'pDI' : 'ND_OPT_MEM_rDI', - 'SHS' : 'ND_OPT_MEM_SHS', - 'SHS0' : 'ND_OPT_MEM_SHS0', - 'SHSP' : 'ND_OPT_MEM_SHSP', - 'SMT' : 'ND_OPT_MEM_SMSRT', - 'DMT' : 'ND_OPT_MEM_DMSRT', - - # Special immediates. - 'm2zI' : 'ND_OPT_Im2z', - - # System registers, MSRs, XCRs, etc. - 'GDTR' : 'ND_OPT_SYS_GDTR', - 'IDTR' : 'ND_OPT_SYS_IDTR', - 'LDTR' : 'ND_OPT_SYS_LDTR', - 'TR' : 'ND_OPT_SYS_TR', - 'CR0' : 'ND_OPT_CR_0', - 'XCR' : 'ND_OPT_XCR', - 'XCR0' : 'ND_OPT_XCR_0', - 'MSR' : 'ND_OPT_MSR', - 'FSBASE' : 'ND_OPT_MSR_FSBASE', - 'GSBASE' : 'ND_OPT_MSR_GSBASE', - 'KGSBASE' : 'ND_OPT_MSR_KGSBASE', - 'SCS' : 'ND_OPT_MSR_SCS', - 'SEIP' : 'ND_OPT_MSR_SEIP', - 'SESP' : 'ND_OPT_MSR_SESP', - 'TSC' : 'ND_OPT_MSR_TSC', - 'TSCAUX' : 'ND_OPT_MSR_TSCAUX', - 'STAR' : 'ND_OPT_MSR_STAR', - 'LSTAR' : 'ND_OPT_MSR_LSTAR', - 'FMASK' : 'ND_OPT_MSR_FMASK', - 'BANK' : 'ND_OPT_REG_BANK', - 'X87CONTROL':'ND_OPT_X87_CONTROL', - 'X87TAG' : 'ND_OPT_X87_TAG', - 'X87STATUS': 'ND_OPT_X87_STATUS', - 'MXCSR' : 'ND_OPT_MXCSR', - 'PKRU' : 'ND_OPT_PKRU', - 'SSP' : 'ND_OPT_SSP', - 'UIF' : 'ND_OPT_UIF' -} - -opsize = { - 'a' : 'ND_OPS_a', - 'b' : 'ND_OPS_b', - 'c' : 'ND_OPS_c', - 'd' : 'ND_OPS_d', - 'dq' : 'ND_OPS_dq', - 'ev' : 'ND_OPS_ev', - 'qv' : 'ND_OPS_qv', - 'hv' : 'ND_OPS_hv', - 'fv' : 'ND_OPS_fv', - 'uv' : 'ND_OPS_uv', - 'vm32x' : 'ND_OPS_vm32x', - 'vm32y' : 'ND_OPS_vm32y', - 'vm32z' : 'ND_OPS_vm32z', - 'vm32h' : 'ND_OPS_vm32h', - 'vm32n' : 'ND_OPS_vm32n', - 'vm64x' : 'ND_OPS_vm64x', - 'vm64y' : 'ND_OPS_vm64y', - 'vm64z' : 'ND_OPS_vm64z', - 'vm64h' : 'ND_OPS_vm64h', - 'vm64n' : 'ND_OPS_vm64n', - 'mib' : 'ND_OPS_mib', - 'v2' : 'ND_OPS_v2', - 'v3' : 'ND_OPS_v3', - 'v4' : 'ND_OPS_v4', - 'v5' : 'ND_OPS_v5', - 'v8' : 'ND_OPS_v8', - 'oq' : 'ND_OPS_oq', - 'p' : 'ND_OPS_p', - 'pd' : 'ND_OPS_pd', - 'ps' : 'ND_OPS_ps', - 'ph' : 'ND_OPS_ph', - 'q' : 'ND_OPS_q', - 'qq' : 'ND_OPS_qq', - 's' : 'ND_OPS_s', - 'sd' : 'ND_OPS_sd', - 'ss' : 'ND_OPS_ss', - 'sh' : 'ND_OPS_sh', - 'v' : 'ND_OPS_v', - 'w' : 'ND_OPS_w', - 'x' : 'ND_OPS_x', - 'y' : 'ND_OPS_y', - 'yf' : 'ND_OPS_yf', - 'z' : 'ND_OPS_z', - '?' : 'ND_OPS_unknown', - '0' : 'ND_OPS_0', - 'asz' : 'ND_OPS_asz', - 'ssz' : 'ND_OPS_ssz', - 'fa' : 'ND_OPS_fa', - 'fw' : 'ND_OPS_fw', - 'fd' : 'ND_OPS_fd', - 'fq' : 'ND_OPS_fq', - 'ft' : 'ND_OPS_ft', - 'fe' : 'ND_OPS_fe', - 'fs' : 'ND_OPS_fs', - 'l' : 'ND_OPS_l', - 'rx' : 'ND_OPS_rx', - 'cl' : 'ND_OPS_cl', - '12' : 'ND_OPS_12', - 't' : 'ND_OPS_t', - '384' : 'ND_OPS_384', - '512' : 'ND_OPS_512', - '4096' : 'ND_OPS_4096', -} - -opdecorators = { - '{K}' : 'ND_OPD_MASK', - '{z}' : 'ND_OPD_Z', - '{sae}' : 'ND_OPD_SAE', - '{er}' : 'ND_OPD_ER', - '|B32' : 'ND_OPD_B32', - '|B64' : 'ND_OPD_B64', - '|B16' : 'ND_OPD_B16', -} - -accessmap = { - 'R' : 'ND_OPA_R', - 'W' : 'ND_OPA_W', - 'CR' : 'ND_OPA_CR', - 'CW' : 'ND_OPA_CW', - 'RW' : 'ND_OPA_RW', - 'RCW' : 'ND_OPA_RCW', - 'CRW' : 'ND_OPA_CRW', - 'CRCW' : 'ND_OPA_CRCW', - 'P' : 'ND_OPA_P', - 'N' : 'ND_OPA_N', -} - -tuples = { - None : '0', - 'fv' : 'ND_TUPLE_FV', - 'hv' : 'ND_TUPLE_HV', - 'qv' : 'ND_TUPLE_QV', - 'fvm' : 'ND_TUPLE_FVM', - 'hvm' : 'ND_TUPLE_HVM', - 'qvm' : 'ND_TUPLE_QVM', - 'ovm' : 'ND_TUPLE_OVM', - 'dup' : 'ND_TUPLE_DUP', - 'm128' : 'ND_TUPLE_M128', - 't1s8' : 'ND_TUPLE_T1S8', - 't1s16' : 'ND_TUPLE_T1S16', - 't1s' : 'ND_TUPLE_T1S', - 't1f' : 'ND_TUPLE_T1F', - 't2' : 'ND_TUPLE_T2', - 't4' : 'ND_TUPLE_T4', - 't8' : 'ND_TUPLE_T8', - 't1_4x' : 'ND_TUPLE_T1_4X', -} - -extype = { - None : '0', - - # SSE/AVX - '1' : 'ND_EXT_1', - '2' : 'ND_EXT_2', - '3' : 'ND_EXT_3', - '4' : 'ND_EXT_4', - '5' : 'ND_EXT_5', - '6' : 'ND_EXT_6', - '7' : 'ND_EXT_7', - '8' : 'ND_EXT_8', - '9' : 'ND_EXT_9', - '10' : 'ND_EXT_10', - '11' : 'ND_EXT_11', - '12' : 'ND_EXT_12', - '13' : 'ND_EXT_13', - '14' : 'ND_EXT_14', - - # EVEX - 'E1' : 'ND_EXT_E1', - 'E1NF' : 'ND_EXT_E1NF', - 'E2' : 'ND_EXT_E2', - 'E3' : 'ND_EXT_E3', - 'E3NF' : 'ND_EXT_E3NF', - 'E4' : 'ND_EXT_E4', - 'E4S' : 'ND_EXT_E4S', - 'E4nb' : 'ND_EXT_E4nb', - 'E4NF' : 'ND_EXT_E4NF', - 'E4NFnb': 'ND_EXT_E4NFnb', - 'E5' : 'ND_EXT_E5', - 'E5NF' : 'ND_EXT_E5NF', - 'E6' : 'ND_EXT_E6', - 'E6NF' : 'ND_EXT_E6NF', - 'E7NM' : 'ND_EXT_E7NM', - 'E9' : 'ND_EXT_E9', - 'E9NF' : 'ND_EXT_E9NF', - 'E10' : 'ND_EXT_E10', - 'E10S' : 'ND_EXT_E10S', - 'E10NF' : 'ND_EXT_E10NF', - 'E11' : 'ND_EXT_E11', - 'E12' : 'ND_EXT_E12', - 'E12NP' : 'ND_EXT_E12NP', - - # Opmask - 'K20' : 'ND_EXT_K20', - 'K21' : 'ND_EXT_K21', - - # AMX - 'AMX_E1': 'ND_EXT_AMX_E1', - 'AMX_E2': 'ND_EXT_AMX_E2', - 'AMX_E3': 'ND_EXT_AMX_E3', - 'AMX_E4': 'ND_EXT_AMX_E4', - 'AMX_E5': 'ND_EXT_AMX_E5', - 'AMX_E6': 'ND_EXT_AMX_E6', -} - -modes = { - 'r0' : 'ND_MOD_R0', - 'r1' : 'ND_MOD_R1', - 'r2' : 'ND_MOD_R2', - 'r3' : 'ND_MOD_R3', - 'real' : 'ND_MOD_REAL', - 'v8086' : 'ND_MOD_V8086', - 'prot' : 'ND_MOD_PROT', - 'compat' : 'ND_MOD_COMPAT', - 'long' : 'ND_MOD_LONG', - 'smm' : 'ND_MOD_SMM', - 'smm_off' : 'ND_MOD_SMM_OFF', - 'sgx' : 'ND_MOD_SGX', - 'sgx_off' : 'ND_MOD_SGX_OFF', - 'tsx' : 'ND_MOD_TSX', - 'tsx_off' : 'ND_MOD_TSX_OFF', - 'vmxr' : 'ND_MOD_VMXR', - 'vmxn' : 'ND_MOD_VMXN', - 'vmxr_seam' : 'ND_MOD_VMXR_SEAM', - 'vmxn_seam' : 'ND_MOD_VMXN_SEAM', - 'vmx_off' : 'ND_MOD_VMX_OFF', -} - -indexes = { - "root" : 0, - "None" : 0, +component_value_index = { None : 0, + 'None' : 0, # modrm.mod - "mem" : 0, - "reg" : 1, + 'mem' : 0, + 'reg' : 1, - # mandatory prefixes - "NP" : 0, - "66" : 1, - "F3" : 2, - "F2" : 3, + # mandatory prefixes; using 'P' prefix so they're not confused with an opcode + 'PNP' : 0, + 'P0x66' : 1, + 'P0xF3' : 2, + 'P0xF2' : 3, # other prefixes/redirection conditions - "rexb" : 1, - "rexw" : 2, - "64" : 3, - "aF3" : 4, - "rep" : 5, - "riprel": 6, + 'rexb' : 1, + 'rexw' : 2, + 'mo64' : 3, + 'repz' : 4, + 'rep' : 5, + 'riprel': 6, + 'rex2' : 7, + 'rex2w' : 8, # Mode - "m16" : 1, - "m32" : 2, - "m64" : 3, + 'm16' : 1, + 'm32' : 2, + 'm64' : 3, # Default data size - "ds16" : 1, - "ds32" : 2, - "ds64" : 3, - "dds64" : 4, - "fds64" : 5, + 'ds16' : 1, + 'ds32' : 2, + 'ds64' : 3, + 'dds64' : 4, + 'fds64' : 5, # Default address size - "as16" : 1, - "as32" : 2, - "as64" : 3, + 'as16' : 1, + 'as32' : 2, + 'as64' : 3, # Vendor redirection. - "any" : 0, - "intel" : 1, - "amd" : 2, - "geode" : 3, - "cyrix" : 4, + 'any' : 0, + 'intel' : 1, + 'amd' : 2, # Feature redirection. - "mpx" : 1, - "cet" : 2, - "cldm" : 3, - "piti" : 4, + 'mpx' : 1, + 'cet' : 2, + 'cldm' : 3, + 'piti' : 4, } -ilut = { - "root" : ("ND_ILUT_ROOT", 1, "ND_TABLE"), - "opcode" : ("ND_ILUT_OPCODE", 256, "ND_TABLE_OPCODE"), - "opcode_3dnow" : ("ND_ILUT_OPCODE_3DNOW", 256, "ND_TABLE_OPCODE"), - "modrmmod" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"), - "modrmmodpost" : ("ND_ILUT_MODRM_MOD", 2, "ND_TABLE_MODRM_MOD"), - "modrmreg" : ("ND_ILUT_MODRM_REG", 8, "ND_TABLE_MODRM_REG"), - "modrmrm" : ("ND_ILUT_MODRM_RM", 8, "ND_TABLE_MODRM_RM"), - "mprefix" : ("ND_ILUT_MAN_PREFIX", 4, "ND_TABLE_MPREFIX"), - "mode" : ("ND_ILUT_MODE", 4, "ND_TABLE_MODE"), - "dsize" : ("ND_ILUT_DSIZE", 6, "ND_TABLE_DSIZE"), - "asize" : ("ND_ILUT_ASIZE", 4, "ND_TABLE_ASIZE"), - "auxiliary" : ("ND_ILUT_AUXILIARY", 8, "ND_TABLE_AUXILIARY"), - "vendor" : ("ND_ILUT_VENDOR", 6, "ND_TABLE_VENDOR"), - "feature" : ("ND_ILUT_FEATURE", 8, "ND_TABLE_FEATURE"), - "mmmmm" : ("ND_ILUT_VEX_MMMMM", 32, "ND_TABLE_VEX_MMMMM"), - "pp" : ("ND_ILUT_VEX_PP", 4, "ND_TABLE_VEX_PP"), - "l" : ("ND_ILUT_VEX_L", 4, "ND_TABLE_VEX_L"), - "w" : ("ND_ILUT_VEX_W", 2, "ND_TABLE_VEX_W"), - "wi" : ("ND_ILUT_VEX_WI", 2, "ND_TABLE_VEX_W"), + +# +# This dictionary describes how the decoding tables look. Each decoding component has associated a C decoding table. +# +components_ilut = { + 'opcode' : { 'ilut': 'ND_ILUT_OPCODE', 'size': 256, 'type': 'ND_TABLE_OPCODE' }, + 'opcode_last' : { 'ilut': 'ND_ILUT_OPCODE_LAST', 'size': 256, 'type': 'ND_TABLE_OPCODE' }, + 'modrmmod' : { 'ilut': 'ND_ILUT_MODRM_MOD', 'size': 2, 'type': 'ND_TABLE_MODRM_MOD' }, + 'modrmreg' : { 'ilut': 'ND_ILUT_MODRM_REG', 'size': 8, 'type': 'ND_TABLE_MODRM_REG' }, + 'modrmrm' : { 'ilut': 'ND_ILUT_MODRM_RM', 'size': 8, 'type': 'ND_TABLE_MODRM_RM' }, + 'prefix' : { 'ilut': 'ND_ILUT_MAN_PREFIX', 'size': 4, 'type': 'ND_TABLE_MPREFIX' }, + 'mode' : { 'ilut': 'ND_ILUT_MODE', 'size': 4, 'type': 'ND_TABLE_MODE' }, + 'dsize' : { 'ilut': 'ND_ILUT_DSIZE', 'size': 6, 'type': 'ND_TABLE_DSIZE' }, + 'asize' : { 'ilut': 'ND_ILUT_ASIZE', 'size': 4, 'type': 'ND_TABLE_ASIZE' }, + 'auxiliary' : { 'ilut': 'ND_ILUT_AUXILIARY', 'size': 10, 'type': 'ND_TABLE_AUXILIARY' }, + 'vendor' : { 'ilut': 'ND_ILUT_VENDOR', 'size': 6, 'type': 'ND_TABLE_VENDOR' }, + 'feature' : { 'ilut': 'ND_ILUT_FEATURE', 'size': 8, 'type': 'ND_TABLE_FEATURE' }, + 'mmmmm' : { 'ilut': 'ND_ILUT_EX_M', 'size': 32, 'type': 'ND_TABLE_EX_M' }, + 'pp' : { 'ilut': 'ND_ILUT_EX_PP', 'size': 4, 'type': 'ND_TABLE_EX_PP' }, + 'l' : { 'ilut': 'ND_ILUT_EX_L', 'size': 4, 'type': 'ND_TABLE_EX_L' }, + 'w' : { 'ilut': 'ND_ILUT_EX_W', 'size': 2, 'type': 'ND_TABLE_EX_W' }, + 'wi' : { 'ilut': 'ND_ILUT_EX_WI', 'size': 2, 'type': 'ND_TABLE_EX_W' }, + 'nd' : { 'ilut': 'ND_ILUT_EX_ND', 'size': 2, 'type': 'ND_TABLE_EX_ND' }, + 'nf' : { 'ilut': 'ND_ILUT_EX_NF', 'size': 2, 'type': 'ND_TABLE_EX_NF' }, + 'sc' : { 'ilut': 'ND_ILUT_EX_SC', 'size': 16, 'type': 'ND_TABLE_EX_SC' }, } @@ -473,598 +178,593 @@ prefixes = [] features = [] -# -# Convert one operand into it's C/C++ representation. -# -def cdef_operand(self): - return "OP(%s, %s, %s, %s, %s, %d)" % (optype[self.Type], opsize[self.Size], \ - '|'.join([opflags[x] for x in self.Flags]) or '0', accessmap[self.Access], \ - '|'.join([opdecorators[x] for x in self.Decorators]) or 0, self.Block) +def instrux_to_idbe( + ins: disasmlib.Instruction + ) -> dict: + """ + Generates a dictionary equivalent to the ND_IDBE structure. Each dictionary key is equivalent + to a ND_IDBE structure field. Restrictions: + - The order of the keys must be identical to the order of fields inside ND_IDBE + - There must be no gaps; if a field is not used, just initialize it to some default value + - The names must be identical to field names inside ND_IDBE -disasmlib.Operand.cdef = cdef_operand + Parameters + ---------- + ins: disasmlib.Instruction + The instruction to be converted to a dictionary. + Returns + ------- + A dictionary representing the bddisasm C definition of this instrux. + """ + d = {} -# -# Convert one instruction into it's C/C++ representation. -# -def cdef_instruction(self): - c = '' - - c += ' // Pos:%d Instruction:"%s" Encoding:"%s"/"%s"\n' % \ - (self.Icount, self.__str__(), self.RawEnc, ''.join([x.Encoding for x in self.ExpOps]).replace('S', '')) - - c += ' {\n ' + # Instruction class + d['Instruction'] = 'ND_INS_' + ins.Class - # Add the instruction class - c += 'ND_INS_' + self.Class + ', ' - - # Add the instruction type - c += 'ND_CAT_' + self.Category + ', ' - - # Add the instruction set - c += 'ND_SET_' + self.Set + ', ' + # Instruction Category + d['Category'] = 'ND_CAT_' + ins.Category - # Add the mneomonic index. - c += '%d, ' % (mnemonics.index(self.Mnemonic)) - - c += '\n ' + # ISA Set + d['IsaSet'] = 'ND_SET_' + ins.Set - # Add the prefixes map. - c += '|'.join([prefixes_map[x] for x in self.Prefmap] or '0') + ', ' + # Mnemonic (index) + d['Mnemonic'] = '%d' % (mnemonics.index(ins.Mnemonic)) - c += '\n ' + # Accepted prefixes map + if ins.Prefmap: + d['ValidPrefixes'] = '|'.join(['ND_PREF_' + x.upper() for x in ins.Prefmap]) + else: + d['ValidPrefixes'] = '0' - # Add the valid modes map. + # Valid modes all = True - for m in modes: - if m not in self.Modes: + smodes = '' + for m in disasmlib.valid_cpu_modes: + if m not in ins.Modes: all = False if all: - c += 'ND_MOD_ANY, ' + smodes = 'ND_MOD_ANY' else: - c += '|'.join([modes[m] for m in self.Modes]) + ', ' + smodes = '|'.join(['ND_MOD_' + m.upper() for m in ins.Modes]) + d['ValidModes'] = smodes - c += '\n ' - - # Add the decorators map. - c += '|'.join([decorators_map[x] for x in self.DecoFlags] or '0') + ', ' - - # Add the tuple type and the explicit operands count. - c += 'ND_OPS_CNT(%d, %d), ' % (len(self.ExpOps), len(self.ImpOps)) - - exclass = None - if self.ExClass: - if self.ExClass in ['0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13']: - exclass = 'ND_EXC_SSE_AVX' - elif self.ExClass in ['K20', 'K21']: - exclass = 'ND_EXC_OPMASK' - elif self.ExClass.startswith('AMX_'): - exclass = 'ND_EXC_AMX' - else: - exclass = 'ND_EXC_EVEX' - - if self.Evex: - # EVEX encoded instructions, store the tuple type. - c += '%s, ' % (tuples[self.Tuple]) + # Valid decorators + if ins.DecoFlags: + d['ValidDecorators'] = '|'.join(['ND_DECO_' + x.upper() for x in ins.DecoFlags]) else: - c += '0, ' + d['ValidDecorators'] = '0' - # Store exception type & class, if any. - if exclass: - c += '%s, %s, ' % (extype[self.ExClass], exclass) + # Operand count + d['OpsCount'] = 'ND_OPS_CNT(%d, %d)' % (len(ins.ExpOps), len(ins.ImpOps)) + + # EVEX tuple type + if ins.Evex and ins.Tuple: + d['TupleType'] = 'ND_TUPLE_' + ins.Tuple.upper() else: - c += '0, 0, ' + d['TupleType'] = '0' - # Add the FPU flags access, if the instruction is fpu. - if self.Set == 'X87': + # Exception type + if ins.ExType: + d['ExcType'] = 'ND_EXT_' + ins.ExType + else: + d['ExcType'] = '0' + + # FpuFlags (x87 instructions only) + if ins.Set == 'X87': value = 0 acc = { '0': 0, '1': 1, 'm': 2, 'u': 3 } for i in range(0, 4): - value |= acc[self.FpuFlags[i]] << (i * 2) - c += '0x%02x, ' % value + value |= acc[ins.FpuFlags[i]] << (i * 2) + d['FpuFlags'] = '0x%02x' % value else: - c += '0, ' + d['FpuFlags'] = '0' - # The 2 reserved fields. - c += '0, 0, ' + # EVEX mode + if ins.EvexMode: + d['EvexMode'] = 'ND_EVEXM_' + ins.EvexMode.upper() + else: + d['EvexMode'] = '0' - # Add the instruction flags - fs = '|'.join([flags[x] for x in self.Flags if x != 'nil' and not x.startswith('OP1') and not x.startswith('OP2')\ - and not x.startswith('OP3') and not x.startswith('OP4')\ - and not x.startswith('OP5') and not x.startswith('OP6')\ - ]) or 0 - - c += '%s, ' % fs - - # Store the CPUID flag, if any - flg = "0" - for feat in features: - if feat.Name == self.Id: - flg = "ND_CFF_%s" % feat.Name - c += "%s, " % flg - - # Store the accessed flags, if any. + # Flags (tested, modified, set, cleared) for m in ['t', 'm', '1', '0']: - flg = "0" - dst = self.RevFlagsAccess[m] + flg = '0' + dst = ins.Rflags[m] if m == '1' or m == '0': - dst = dst + self.RevFlagsAccess['u'] + dst = dst + ins.Rflags['u'] for f in dst: flg += '|NDR_RFLAG_%s' % f.upper() - c += "\n %s," % flg - - # Add the instruction operands - allOps = self.ExpOps + self.ImpOps - c += "\n {" - if allOps: - for op in self.ExpOps + self.ImpOps: - c += "\n " + op.cdef() + ", " - else: - c += "\n 0 " - c += "\n }," + if m == 't': d['TestedFlags'] = flg + if m == 'm': d['ModifiedFlags'] = flg + if m == '1': d['SetFlags'] = flg + if m == '0': d['ClearedFlags'] = flg - c += '\n }' + # Instruction attributes + fs = '|'.join(['ND_FLAG_' + x.upper() for x in ins.Attributes + if x != 'nil' and not x.startswith('OP1') and not x.startswith('OP2') + and not x.startswith('OP3') and not x.startswith('OP4') + and not x.startswith('OP5') and not x.startswith('OP6') + ]) or '0' + d['Attributes'] = fs + + # CPUID flag + flg = '0' + for feat in features: + if feat.Name == ins.Id: + flg = 'ND_CFF_%s' % feat.Name + d['CpuidFlag'] = flg + + # List of instruction operands + d['Operands'] = [] + for op in ins.ExpOps + ins.ImpOps: + d['Operands'].append(cdef_operand(op)) + + return d + +def cdef_operand( + op: disasmlib.Operand + ) -> str: + """ + Generates a bddisasm C definition for the current operand. + + Parameters + ---------- + op: Operand + The operand to be converted in a C definition. + + Returns + ------- + A string representing the bddisasm C definition of this operand. + + Example + ------- + "OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0)" + """ + return 'OP(%s, %s, %s, %s, %s, %d)' % ( + 'ND_OPT_' + op.Type, + 'ND_OPS_' + (op.Size if op.Size != '?' else 'unknown'), + '|'.join(['ND_OPF_' + x for x in op.Flags]) or '0', + 'ND_OPA_' + op.Access, + '|'.join(['ND_OPD_' + disasmlib.deco_op_flags[x] for x in op.Decorators]) or 0, + op.Block) + +def cdef_instruction( + ins: disasmlib.Instruction + ) -> str: + """ + Generates a bddisasm C or CPP definition for the current instruction. + If C style definition is used, designated initializers are used. + If CPP definition is required, aggregate initialization is used. + + Parameters + ---------- + ins: Instruction + The instruction to be converted in a C structure. + + Returns + ------- + A multi-line string representing the bddisasm C or CPP definition of this instruction. + + Example + ------- + Designated initializer definition: + // Pos:3 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" + { + .Instruction = ND_INS_AADD, + .Category = ND_CAT_RAOINT, + .IsaSet = ND_SET_RAOINT, + .Mnemonic = 2, + .ValidPrefixes = 0, + .ValidModes = ND_MOD_ANY, + .ValidDecorators = 0, + .OpsCount = ND_OPS_CNT(2, 0), + .TupleType = 0, + .ExcType = 0, + .FpuFlags = 0, + .EvexMode = 0, + .TestedFlags = 0, + .ModifiedFlags = 0, + .SetFlags = 0, + .ClearedFlags = 0, + .Attributes = ND_FLAG_NOREX2|ND_FLAG_MODRM, + .CpuidFlag = ND_CFF_RAOINT, + .Operands = + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + + Aggregate initializer definition: + // Pos:3 Instruction:"AADD My,Gy" Encoding:"NP 0x0F 0x38 0xFC /r:mem"/"MR" + { + /* Instruction */ ND_INS_AADD, + /* Category */ ND_CAT_RAOINT, + /* IsaSet */ ND_SET_RAOINT, + /* Mnemonic */ 2, + /* ValidPrefixes */ 0, + /* ValidModes */ ND_MOD_ANY, + /* ValidDecorators */ 0, + /* OpsCount */ ND_OPS_CNT(2, 0), + /* TupleType */ 0, + /* ExcType */ 0, + /* FpuFlags */ 0, + /* EvexMode */ 0, + /* TestedFlags */ 0, + /* ModifiedFlags */ 0, + /* SetFlags */ 0, + /* ClearedFlags */ 0, + /* Attributes */ ND_FLAG_NOREX2|ND_FLAG_MODRM, + /* CpuidFlag */ ND_CFF_RAOINT, + /* Operands */ + { + OP(ND_OPT_M, ND_OPS_y, 0, ND_OPA_RW, 0, 0), + OP(ND_OPT_G, ND_OPS_y, 0, ND_OPA_R, 0, 0), + }, + }, + """ + idbe = instrux_to_idbe(ins) + + c = '' + + # Start with the position and encoding description. + c += ' // Pos:%d Instruction:"%s" Encoding:"%s"/"%s"\n' % ( + ins.Icount, + str(ins), + ins.RawEnc, + ''.join([x.Encoding for x in ins.ExpOps]).replace('S', '')) + + c += ' {\n' + + for field in idbe: + if idbe_format_designated: + c += ' .%s = ' % field + else: + c += ' /* %16s */ ' % field + + if type(idbe[field]) is list: + c += '\n' + c += ' {\n' + if len(idbe[field]) == 0: + c += ' 0\n' + else: + for entry in idbe[field]: + c += ' ' + entry + ',\n' + c += ' },\n' + else: + c += str(idbe[field]) + ',\n' + + c += ' }' return c -disasmlib.Instruction.cdef = cdef_instruction + +def compute_index( + value: str + ) -> int: + """ + Given a component value, convert it to an index inside te C decoding table. Values which are present inside the + component_value_index dict will be translated using that. All other values will be considered to be hex values, + so they will be int(value, 16). The returned index is used when decoding an instruction, in order to lookup the + next viable entry in the multi-way decode tree. + + Parameters + ---------- + value: str + The index to be converted to an integer index. + + Returns + ------- + An integer representing the index of the given decode component. + + Example + ------- + Input: + value: repz + Returns: + 4 + + Input: + value: 0xCC + Returns: + 204 + """ + if value in component_value_index: + return component_value_index[value] + return int(value, 16) -# -# Initially, t is an empty hash-table. -# -def group_instructions(ilist): - d = { } - is3dnow = False - priorities = ["opcode", "vendor", "feature", "modrmmod", "modrmreg", "modrmmodpost", "modrmrm", "mprefix", "mode", \ - "dsize", "asize", "auxiliary", "_"] +def group_find_component( + instructions: list[disasmlib.Instruction], + components: list[dict] + ) -> dict: + """ + Given a list of instructions and a list of decoding components, return the decoding component that covers all the + instructions in the list. For example, in an initial call to this function for the list of all legacy instructions + the "opcode" component would be returned. - for i in ilist: - if '3DNOW' in i.Flags: - is3dnow = True + Parameters + ---------- + instructions: list[disasmlib.Instruction] + The list of instructions to be grouped. + components: + The list of components used for grouping. + + Returns + ------- + A dict representing the decode component that can be used to cover all instructions in the list. + None if no such component could be found. + """ + for c in components: + if c['all']: + # Some components must be present for all instructions in the list - for example, opcode. + bad = False + for i in instructions: + if not i.Encoding[c['type']]: + bad = True + break else: - is3dnow = False - - if i.Spec["opcodes"]: - if is3dnow: - d["__TYPE__"] = "opcode_3dnow" - else: - d["__TYPE__"] = "opcode" - elif i.Spec["mpre"] and i.ModrmRedirAfterMpref: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]: - d["__TYPE__"] = "mprefix" - elif i.Spec["vendor"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-11:]: - d["__TYPE__"] = "vendor" - elif i.Spec["feature"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-10:]: - d["__TYPE__"] = "feature" - elif i.Spec["modrm"]["mod"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-9:]: - d["__TYPE__"] = "modrmmod" - elif i.Spec["modrm"]["reg"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-8:]: - d["__TYPE__"] = "modrmreg" - elif i.Spec["modrm"]["modpost"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-7:]: - d["__TYPE__"] = "modrmmodpost" - elif i.Spec["modrm"]["rm"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-6:]: - d["__TYPE__"] = "modrmrm" - elif i.Spec["mpre"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-5:]: - d["__TYPE__"] = "mprefix" - elif i.Spec["mode"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-4:]: - d["__TYPE__"] = "mode" - elif i.Spec["dsize"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-3:]: - d["__TYPE__"] = "dsize" - elif i.Spec["asize"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-2:]: - d["__TYPE__"] = "asize" - elif i.Spec["opre"]: - if "__TYPE__" not in d or d["__TYPE__"] in priorities[-1:]: - d["__TYPE__"] = "auxiliary" - elif len(ilist) == 1: - return ilist[0] - - - for i in ilist: - if d["__TYPE__"] in ["opcode", "opcode_3dnow"]: - # Opcode redirection, add the next opcode to the hash, and remove it from the spec. - if int(i.Spec["opcodes"][0], 16) not in d: - d[int(i.Spec["opcodes"][0], 16)] = [i] - else: - d[int(i.Spec["opcodes"][0], 16)].append(i) - - # Remove the opcode for this instruction. - del i.Spec["opcodes"][0] - elif d["__TYPE__"] == "modrmmod": - if not i.Spec["modrm"]["mod"]: - if "mem" not in d: - d["mem"] = [i] - else: - d["mem"].append(i) - - if "reg" not in d: - d["reg"] = [copy.deepcopy(i)] - else: - d["reg"].append(copy.deepcopy(i)) - else: - if i.Spec["modrm"]["mod"] not in d: - d[i.Spec["modrm"]["mod"]] = [i] - else: - d[i.Spec["modrm"]["mod"]].append(i) - # Remove the mod specifier. - i.Spec["modrm"]["mod"] = None - elif d["__TYPE__"] == "modrmreg": - if int(i.Spec["modrm"]["reg"]) not in d: - d[int(i.Spec["modrm"]["reg"])] = [i] - else: - d[int(i.Spec["modrm"]["reg"])].append(i) - # Remove the reg specifier - i.Spec["modrm"]["reg"] = None - elif d["__TYPE__"] == "modrmmodpost": - if not i.Spec["modrm"]["modpost"]: - if "mem" not in d: - d["mem"] = [i] - else: - d["mem"].append(i) - - if "reg" not in d: - d["reg"] = [copy.deepcopy(i)] - else: - d["reg"].append(copy.deepcopy(i)) - else: - if i.Spec["modrm"]["modpost"] not in d: - d[i.Spec["modrm"]["modpost"]] = [i] - else: - d[i.Spec["modrm"]["modpost"]].append(i) - # Remove the modpost specifier. - i.Spec["modrm"]["modpost"] = None - elif d["__TYPE__"] == "modrmrm": - if int(i.Spec["modrm"]["rm"]) not in d: - d[int(i.Spec["modrm"]["rm"])] = [i] - else: - d[int(i.Spec["modrm"]["rm"])].append(i) - # Remove the reg specifier - i.Spec["modrm"]["rm"] = None - elif d["__TYPE__"] == "mprefix": - if not i.Spec["mpre"]: - p = "None" - else: - p = i.Spec["mpre"][0] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the prefix from the list. - if p != "None": - del i.Spec["mpre"][0] - elif d["__TYPE__"] == "mode": - if not i.Spec["mode"]: - p = "None" - else: - p = i.Spec["mode"][0] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the auxiliary redirector - if p != "None": - del i.Spec["mode"][0] - elif d["__TYPE__"] == "dsize": - if not i.Spec["dsize"]: - p = "None" - else: - p = i.Spec["dsize"][0] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the auxiliary redirector - if p != "None": - del i.Spec["dsize"][0] - elif d["__TYPE__"] == "asize": - if not i.Spec["asize"]: - p = "None" - else: - p = i.Spec["asize"][0] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the auxiliary redirector - if p != "None": - del i.Spec["asize"][0] - elif d["__TYPE__"] == "auxiliary": - if not i.Spec["opre"]: - p = "None" - else: - p = i.Spec["opre"][0] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the auxiliary redirector - if p != "None": - del i.Spec["opre"][0] - elif d["__TYPE__"] == "vendor": - if not i.Spec["vendor"]: - p = "None" - else: - p = i.Spec["vendor"] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the vendor redirector - if p != "None": - i.Spec["vendor"] = None - elif d["__TYPE__"] == "feature": - if not i.Spec["feature"]: - p = "None" - else: - p = i.Spec["feature"] - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the vendor redirector - if p != "None": - i.Spec["feature"] = None - else: - print("Don't know what to do!") - raise Exception("Unknwon redirection type.") - - return d - - - -def group_instructions_vex_xop_evex(ilist): - d = { } - - for i in ilist: - if i.Spec["mmmmm"]: - d["__TYPE__"] = "mmmmm" - elif i.Spec["opcodes"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "pp", "modrmrm", "modrmmodpost", "modrmreg", \ - "modrmmod"]: - d["__TYPE__"] = "opcode" - elif i.Spec["pp"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]: - d["__TYPE__"] = "pp" - elif i.Spec["modrm"]["mod"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost", "modrmreg"]: - d["__TYPE__"] = "modrmmod" - elif i.Spec["modrm"]["reg"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm", "modrmmodpost"]: - d["__TYPE__"] = "modrmreg" - elif i.Spec["modrm"]["modpost"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l", "modrmrm"]: - d["__TYPE__"] = "modrmmodpost" - elif i.Spec["modrm"]["rm"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l"]: - d["__TYPE__"] = "modrmrm" - elif i.Spec["l"]: - if "__TYPE__" not in d or d["__TYPE__"] in ["w"]: - d["__TYPE__"] = "l" - elif i.Spec["w"]: - if "__TYPE__" not in d: - if 'IWO64' in i.Flags: - d["__TYPE__"] = "wi" - else: - d["__TYPE__"] = "w" - elif len(ilist) == 1: - return ilist[0] - - - for i in ilist: - if d["__TYPE__"] == "mmmmm": - if int(i.Spec["mmmmm"], 16) not in d: - d[int(i.Spec["mmmmm"], 16)] = [i] - else: - d[int(i.Spec["mmmmm"], 16)].append(i) - i.Spec["mmmmm"] = None - elif d["__TYPE__"] == "opcode": - # Opcode redirection, add the next opcode to the hash, and remove it from the spec. - if int(i.Spec["opcodes"][0], 16) not in d: - d[int(i.Spec["opcodes"][0], 16)] = [i] - else: - d[int(i.Spec["opcodes"][0], 16)].append(i) - # Remove the opcode for this instruction. - del i.Spec["opcodes"][0] - elif d["__TYPE__"] == "modrmmod": - if not i.Spec["modrm"]["mod"]: - if "mem" not in d: - d["mem"] = [i] - else: - d["mem"].append(i) - - if "reg" not in d: - d["reg"] = [copy.deepcopy(i)] - else: - d["reg"].append(copy.deepcopy(i)) - else: - if i.Spec["modrm"]["mod"] not in d: - d[i.Spec["modrm"]["mod"]] = [i] - else: - d[i.Spec["modrm"]["mod"]].append(i) - # Remove the mod specifier. - i.Spec["modrm"]["mod"] = None - elif d["__TYPE__"] == "modrmreg": - if int(i.Spec["modrm"]["reg"]) not in d: - d[int(i.Spec["modrm"]["reg"])] = [i] - else: - d[int(i.Spec["modrm"]["reg"])].append(i) - # Remove the reg specifier - i.Spec["modrm"]["reg"] = None - elif d["__TYPE__"] == "modrmmodpost": - if not i.Spec["modrm"]["modpost"]: - if "mem" not in d: - d["mem"] = [i] - else: - d["mem"].append(i) - - if "reg" not in d: - d["reg"] = [copy.deepcopy(i)] - else: - d["reg"].append(copy.deepcopy(i)) - else: - if i.Spec["modrm"]["modpost"] not in d: - d[i.Spec["modrm"]["modpost"]] = [i] - else: - d[i.Spec["modrm"]["modpost"]].append(i) - # Remove the modpost specifier. - i.Spec["modrm"]["modpost"] = None - elif d["__TYPE__"] == "modrmrm": - if int(i.Spec["modrm"]["rm"]) not in d: - d[int(i.Spec["modrm"]["rm"])] = [i] - else: - d[int(i.Spec["modrm"]["rm"])].append(i) - # Remove the reg specifier - i.Spec["modrm"]["rm"] = None - elif d["__TYPE__"] == "pp": - p = int(i.Spec["pp"]) - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the prefix from the list. - i.Spec["pp"] = None - elif d["__TYPE__"] == "l": - p = int(i.Spec["l"]) - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the prefix from the list. - i.Spec["l"] = None - elif d["__TYPE__"] in ["w", "wi"]: - p = int(i.Spec["w"]) - if p not in d: - d[p] = [i] - else: - d[p].append(i) - # Remove the prefix from the list. - i.Spec["w"] = None - else: - print("Don't know what to do!") - raise Exception("Unknown redirection type.") - - return d - - -def build_hash_tree2(t, cbk): - for k in t: - if type(disasmlib.Instruction) == type(t[k]): - # Instruction, leaf, we're done. + # Optional components need only be present for a single instruction in the list. + bad = True + for i in instructions: + if i.Encoding[c['type']]: + bad = False + break + if bad: continue - elif type([]) == type(t[k]): - # List, group the instructions, and recurse. - t[k] = cbk(t[k]) - - if type({}) == type(t[k]): - build_hash_tree2(t[k], cbk) + return c + return None - -def dump_hash_tree2(t, level = 0): - if type(t) == type({}): - for h in t: - if h == "__TYPE__": - continue - print("%s %s (type: %s)" % (" " * level, h, t["__TYPE__"])) - dump_hash_tree2(t[h], level + 1) - else: - print(" " * level, t) - -# -# -# -def generate_translations2(instructions): - table_st = [] - table_xop = [] - table_vex = [] - table_evex = [] +def group_instructions( + instructions: list[disasmlib.Instruction], + components: list[dict] + ) -> dict: + """ + Given a list of instructions and a list of decoding components, find the best grouping component, distribute all + instructions inside an array of children entries based on the identified grouping component, and recurse for all + children entries, until we are left with leaf entries only. A leaf entry is composed of a single Instruction + object. - hash_st = {} - hash_vex = {} - hash_xop = {} - hash_evex = {} + Parameters + ---------- + instructions: list[disasmlib.Instruction] + The list of instructions to be grouped. + components: + The list of components used for grouping. + + Returns + ------- + A dictionary containing two keys: + - "component": indicates the component type used for the current grouping. It is one of "components_legacy" + or "components_ex", depending on which was used for the grouping. + - "children": an array of N entries, where each entry of the array contains an array of instructions that can + be further grouped. The size N of the "children" array is given by the number of possible entries for the + given "component". For example, an "opcode" component can have up to 256 values, so "children" will have + 256 entries. A "modrmreg" component can have up to 8 values, so "children" will have 8 entries. + + Example + ------- + Consider the following list of (simplified) initial instructions (only opcode and reduced encoding shown): + [{"I1", "0xBD"}, {"I2", "0xCC"}, {"I4", "FF /1"}, {"I5", "FF /5"}] + + During the first call, "opcode" would be chosen to group the instructions, so we would end up with the following + result: + { + "component": "opcode", + "children": [ + ... + Pos 0xBD: [{"I1", "0xBD"}], + ... + Pos 0xCC: [{"I2", "0xCC"}], + ... + Pos 0xFF: [{"I4", "FF /1"}, {"I5", "FF /5"}] + ] + } + + We would then recurse for each child in the children array. Note that for opcodes 0xBD and 0xCC, we already have + leaf entries, so further grouping will not be required. + + For opcode 0xFF, further grouping is needed. At the next step, the "modrmreg" will be chosen for grouping, with + the following result: + { + "component": "modrmreg", + "children": [ + Pos 0: [] + Pos 1: [{"I4", "FF /1"}] + Pos 2: [] + Pos 3: [] + Pos 4: [] + Pos 5: [{"I5", "FF /5"}] + Pos 6: [] + Pos 7: [] + ] + } + + As in the previous example, we would recurse for each child, but we are already at leaf entries, so no more grouping + is required. + """ + group = { + 'component' : None, # Component type, used to decode children instructions + 'children' : None, # Array of sub-groups. Each entry is an array of instructions that will be further groupes. + } + + # Find a good grouping component for the current instruction list. + comp = group_find_component(instructions, components) + + # If no good component was found, we probably reached a leaf entry. + if not comp and len(instructions) == 1: + # Reached leaf entry, no more grouping needed. + group['component'] = 'leaf' + group['children'] = instructions[0] + return group + elif not comp: + # No grouping component found for multiple instructions - error. + print("ERROR: Cannot properly group the following instructions. Please review specs!") + for i in instructions: print(" -> ", i, " with encoding: ", i.RawEnc) + raise Exception("Grouping error: invalid/incomplete specification!") + + # Allocate the sub-group array, based on the number of entries in the current group. + group['component'] = comp['type'] + group['children'] = [] + glen = components_ilut[comp['type']]['size'] + + for i in range(0, glen): + group['children'].append([]) + + # Now go through every instruction in the current group, and distribute it on its position. + # Note that at each grouping step, we pop the used component from the instruction + # encoding array, so that it's not used again. + for i in instructions: + if len(i.Encoding[comp['type']]) > 0: + index = compute_index(i.Encoding[comp['type']].pop(0)) + else: + index = 0 + group['children'][index].append(i) + + # Now recurse, and group every sub-group of instructions. + for i in range(0, glen): + # Skip empty groups. + if not group['children'][i]: + continue + + # Recursively group instructions. + group['children'][i] = group_instructions(group['children'][i], components) + + return group + + +def group_dump( + group: map, + level: int = 0 + ): + """ + Dump the entire translation tree identified by the root "group". + """ + if group['component'] == 'leaf': + print(" " * level, group['children']) + return + for i in range(0, len(group['children'])): + if not group['children'][i]: + continue + print(" " * level, group['component'], '%02x' % i) + group_dump(group['children'][i], level + 1) + + +def dump_translation_tables( + instructions: list[disasmlib.Instruction] + ): + """ + Generate the instruction translation trees. + """ + table_legacy = [] + table_xop = [] + table_vex = [] + table_evex = [] + + group_legacy = {} + group_vex = {} + group_xop = {} + group_evex = {} # Distribute each instruction type into its own table. for i in instructions: - if i.Vex: - table_vex.append(i) - elif i.Xop: - table_xop.append(i) - elif i.Evex: - table_evex.append(i) - else: - table_st.append(i) + if i.Vex: table_vex.append(i) + elif i.Xop: table_xop.append(i) + elif i.Evex: table_evex.append(i) + else: table_legacy.append(i) - hash_st["__TYPE__"] = "root" - hash_st["root"] = table_st - build_hash_tree2(hash_st, group_instructions) + # + # Legacy map. + # + group_legacy = group_instructions(table_legacy, components_legacy) + group_cdef = group_generate_c_table(group_legacy, 'gLegacyMap_%s' % group_legacy['component']) - hash_vex["__TYPE__"] = "root" - hash_vex["root"] = table_vex - build_hash_tree2(hash_vex, group_instructions_vex_xop_evex) + print('Writing the bdx86_table_root.h file...') + with open(r'../bddisasm/include/bdx86_table_root.h', 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_TABLE_ROOT_H\n') + f.write('#define BDX86_TABLE_ROOT_H\n\n') + f.write(group_cdef) + f.write('\n#endif\n\n') - hash_xop["__TYPE__"] = "root" - hash_xop["root"] = table_xop - build_hash_tree2(hash_xop, group_instructions_vex_xop_evex) - hash_evex["__TYPE__"] = "root" - hash_evex["root"] = table_evex - build_hash_tree2(hash_evex, group_instructions_vex_xop_evex) + # + # VEX map. + # + group_vex = group_instructions(table_vex, components_ex) + group_cdef = group_generate_c_table(group_vex, 'gVexMap_%s' % group_vex['component']) - # Dump'em! - #print "###########################################################################################################" - #dump_hash_tree2(hash_st) - print('Writing the table_root.h file...') - f = open(r'../bddisasm/include/table_root.h', 'wt') - f.write(header) - f.write("#ifndef TABLE_ROOT_H\n") - f.write("#define TABLE_ROOT_H\n\n") - dump_translation_tree_c(hash_st, 'gRootTable', f) - f.write("\n#endif\n\n") - f.close() - #print "###########################################################################################################" - #dump_hash_tree2(hash_vex) - print('Writing the table_vex.h file...') - f = open(r'../bddisasm/include/table_vex.h', 'wt') - f.write(header) - f.write("#ifndef TABLE_VEX_H\n") - f.write("#define TABLE_VEX_H\n\n") - dump_translation_tree_c(hash_vex, 'gVexTable', f) - f.write("\n#endif\n\n") - f.close() - #print "###########################################################################################################" - #dump_hash_tree2(hash_xop) - print('Writing the table_xop.h file...') - f = open(r'../bddisasm/include/table_xop.h', 'wt') - f.write(header) - f.write("#ifndef TABLE_XOP_H\n") - f.write("#define TABLE_XOP_H\n\n") - dump_translation_tree_c(hash_xop, 'gXopTable', f) - f.write("\n#endif\n\n") - f.close() - #print "###########################################################################################################" - #dump_hash_tree2(hash_evex) - print('Writing the table_evex.h file...') - f = open(r'../bddisasm/include/table_evex.h', 'wt') - f.write(header) - f.write("#ifndef TABLE_EVEX_H\n") - f.write("#define TABLE_EVEX_H\n\n") - dump_translation_tree_c(hash_evex, 'gEvexTable', f) - f.write("\n#endif\n\n") - f.close() - #print "###########################################################################################################" + print('Writing the bdx86_table_vex.h file...') + with open(r'../bddisasm/include/bdx86_table_vex.h', 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_TABLE_VEX_H\n') + f.write('#define BDX86_TABLE_VEX_H\n\n') + f.write(group_cdef) + f.write('\n#endif\n\n') - return [hash_st, hash_vex, hash_xop, hash_evex] + + # + # XOP map. + # + group_xop = group_instructions(table_xop, components_ex) + group_cdef = group_generate_c_table(group_xop, 'gXopMap_%s' % group_xop['component']) + + print('Writing the bdx86_table_xop.h file...') + with open(r'../bddisasm/include/bdx86_table_xop.h', 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_TABLE_XOP_H\n') + f.write('#define BDX86_TABLE_XOP_H\n\n') + f.write(group_cdef) + f.write('\n#endif\n\n') + + + # + # EVEX map. + # + group_evex = group_instructions(table_evex, components_ex) + group_cdef = group_generate_c_table(group_evex, 'gEvexMap_%s' % group_evex['component']) + + print('Writing the bdx86_table_evex.h file...') + with open(r'../bddisasm/include/bdx86_table_evex.h', 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_TABLE_EVEX_H\n') + f.write('#define BDX86_TABLE_EVEX_H\n\n') + f.write(group_cdef) + f.write('\n#endif\n\n') + + +def group_generate_c_table( + group: map, + name: str + ) -> str: + """ + Generate the translation tree, in C format, for the decoding tree identified by group. + """ + if group['component'] != 'leaf': + current_table = '' + current_table += 'const %s %s = \n' % (components_ilut[group['component']]['type'], name) + current_table += '{\n' + current_table += ' %s,\n' % components_ilut[group['component']]['ilut'] + current_table += ' {\n' + for i in range(0, len(group['children'])): + if not group['children'][i]: + current_table += ' /* %02x */ (const void *)ND_NULL,\n' % (i) + else: + current_name = name + ('_%02x_%s' % (i, group['children'][i]['component'])) + current_table += ' /* %02x */ (const void *)&%s,\n' % (i, current_name) + current_table = group_generate_c_table(group['children'][i], current_name) + current_table + current_table += ' }\n' + current_table += '};\n\n' + return current_table + else: + # Instruction, construct a dummy table that directly points to the instruction. + res = 'const ND_TABLE_INSTRUCTION %s = \n' % name + res += '{\n' + res += ' ND_ILUT_INSTRUCTION,\n' + res += ' (const void *)&gInstructions[% 4d] // %s\n' % (group['children'].Icount, str(group['children'])) + res += '};\n\n' + return res def generate_mnemonics(instructions): @@ -1085,7 +785,7 @@ def generate_constants(lst, pre = False): constants.append('ND_INS_' + i.Class) return sorted(set(constants)) - + def generate_constants2(instructions): constants_sets, constants_types = [], [] @@ -1096,175 +796,96 @@ def generate_constants2(instructions): return sorted(set(constants_sets)), sorted(set(constants_types)) def dump_mnemonics(mnemonics, prefixes, fname): - f = open(fname, 'wt') - f.write(header) - f.write('#ifndef MNEMONICS_H\n') - f.write('#define MNEMONICS_H\n') - f.write('\n') - f.write('const char *gMnemonics[%d] = \n' % len(mnemonics)) - f.write('{\n') - f.write(' ') - - i = 0 - ln = 0 - for m in mnemonics: - f.write('"%s", ' % m) - ln += len(m) + 4 - i += 1 - if ln > 60: - ln = 0 - f.write('\n ') - - f.write('\n};\n\n\n') - - f.write('#endif\n\n') - f.close() - -def dump_constants(constants, prefixes, constants_sets, constants_types, fname): - f = open(fname, 'wt') - f.write(header) - f.write('#ifndef CONSTANTS_H\n') - f.write('#define CONSTANTS_H\n\n') - f.write('\n') - f.write('typedef enum _ND_INS_CLASS\n') - f.write('{\n') - f.write(' ND_INS_INVALID = 0,\n') - - for c in constants: - f.write(' %s,\n' % c) - - f.write('\n} ND_INS_CLASS;\n\n\n') - - # Now the instruction sets. - f.write('typedef enum _ND_INS_SET\n') - f.write('{\n') - f.write(' ND_SET_INVALID = 0,\n') - for c in constants_sets: - f.write(' %s,\n' % c) - f.write('\n} ND_INS_SET;\n\n\n') - - # Now the instruction types. - f.write('typedef enum _ND_INS_TYPE\n') - f.write('{\n') - f.write(' ND_CAT_INVALID = 0,\n') - for c in constants_types: - f.write(' %s,\n' % c) - f.write('\n} ND_INS_CATEGORY;\n\n\n') - - # Done! - f.write('\n#endif\n') - - f.close() - -def dump_tree(translations, level = 0): - if type(translations) != type([]): - print('%s%s' % (level * ' ', translations)) - else: - for i in range(0, len(translations), 1): - if len(translations) == 1: - dump_tree(translations[i], level + 1) - else: - dump_tree(translations[i], level + 2) - -def generate_master_table(instructions, fname): - f = open(fname, 'wt') - f.write(header) - f.write('#ifndef INSTRUCTIONS_H\n') - f.write('#define INSTRUCTIONS_H\n') - f.write('\n') - flags = [] - f.write('const ND_INSTRUCTION gInstructions[%s] = \n' % len(instructions)) - f.write('{\n') - for i in instructions: - f.write('%s, \n\n' % i.cdef()) - f.write('\n};\n') - f.write('\n#endif\n') - f.close() - - -def dump_translation_tree_c(t, hname, f): - if type(t) == type({}): - pointers = [] - - ttype = t["__TYPE__"] - - for x in range(0, ilut[ttype][1]): pointers.append(None) - - tname = '%s_%s' % (hname, ttype) - - res = 'const %s %s = \n' % (ilut[ttype][2], tname) - res += '{\n' - res += ' %s,\n' % ilut[ttype][0] - res += ' { \n' - - for h in t: - if h == "__TYPE__": - continue - - if type(0) == type(h): - name = dump_translation_tree_c(t[h], hname + '_%02x' % h, f) - else: - name = dump_translation_tree_c(t[h], hname + '_%s' % h, f) - - if ttype in ["opcode", "opcode_3dnow", "mmmmm", "pp", "l", "w", "wi", "modrmreg", "modrmrm"]: - index = h - else: - index = indexes[h] - - try: - pointers[index] = name - except: - print(index, name) - print("fail fail fail", index) + with open(fname, 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_MNEMONICS_H\n') + f.write('#define BDX86_MNEMONICS_H\n') + f.write('\n') + f.write('const char *gMnemonics[%d] = \n' % len(mnemonics)) + f.write('{\n') + f.write(' ') i = 0 - for p in pointers: - if not p: - res += ' /* %02x */ ND_NULL,\n' % i - else: - res += ' /* %02x */ (const void *)&%s,\n' % (i, p) + ln = 0 + for m in mnemonics: + f.write('"%s", ' % m) + ln += len(m) + 4 i += 1 + if ln > 60: + ln = 0 + f.write('\n ') - res += ' }\n' - res += '};\n\n' - - if ttype == "root": - f.write("const PND_TABLE %s = (const PND_TABLE)&%s;\n\n" % (hname, name)) - else: - f.write(res) + f.write('\n};\n\n\n') - return tname - else: - # Instruction, construct a dummy table that directly points to the instruction. - name = '%s_leaf' % hname - res = 'const ND_TABLE_INSTRUCTION %s = \n' % name - res += '{\n' - res += ' ND_ILUT_INSTRUCTION,\n' - res += ' (const void *)&gInstructions[%d]\n' % t.Icount - res += '};\n\n' - f.write(res) - return name + f.write('#endif\n\n') -def generate_features(features, fname): - f = open(fname, 'wt') - f.write(header) - f.write('#ifndef CPUID_FLAGS_H\n') - f.write('#define CPUID_FLAGS_H\n') +def dump_constants(constants, prefixes, constants_sets, constants_types, fname): + with open(fname, 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_CONSTANTS_H\n') + f.write('#define BDX86_CONSTANTS_H\n\n') + f.write('\n') + f.write('typedef enum _ND_INS_CLASS\n') + f.write('{\n') + f.write(' ND_INS_INVALID = 0,\n') - f.write('\n') - f.write('#define ND_CFF_NO_LEAF 0xFFFFFFFF\n') - f.write('#define ND_CFF_NO_SUBLEAF 0x00FFFFFF\n') - f.write('\n') - f.write('\n') - f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))\n') - f.write('\n') + for c in constants: + f.write(' %s,\n' % c) - for c in features: - f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'NDR_' + c.Reg, c.Bit)) + f.write('\n} ND_INS_CLASS;\n\n\n') - f.write('\n') + # Now the instruction sets. + f.write('typedef enum _ND_INS_SET\n') + f.write('{\n') + f.write(' ND_SET_INVALID = 0,\n') + for c in constants_sets: + f.write(' %s,\n' % c) + f.write('\n} ND_INS_SET;\n\n\n') + + # Now the instruction types. + f.write('typedef enum _ND_INS_TYPE\n') + f.write('{\n') + f.write(' ND_CAT_INVALID = 0,\n') + for c in constants_types: + f.write(' %s,\n' % c) + f.write('\n} ND_INS_CATEGORY;\n\n\n') + + # Done! + f.write('\n#endif\n') - f.write('#endif // CPUID_FLAGS_H\n') +def dump_master_table(instructions, fname): + with open(fname, 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_INSTRUCTIONS_H\n') + f.write('#define BDX86_INSTRUCTIONS_H\n') + f.write('\n') + flags = [] + f.write('const ND_IDBE gInstructions[%s] = \n' % len(instructions)) + f.write('{\n') + for i in instructions: + f.write('%s, \n\n' % cdef_instruction(i)) + f.write('\n};\n') + f.write('\n#endif\n') + +def dump_features(features, fname): + with open(fname, 'wt') as f: + f.write(header) + f.write('#ifndef BDX86_CPUID_FLAGS_H\n') + f.write('#define BDX86_CPUID_FLAGS_H\n') + + f.write('\n') + f.write('#define ND_CFF_NO_LEAF 0xFFFFFFFF\n') + f.write('#define ND_CFF_NO_SUBLEAF 0x00FFFFFF\n') + f.write('\n') + f.write('\n') + f.write('#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))\n') + + for c in features: + f.write('#define ND_CFF_%s%sND_CFF(%s, %s, %s, %s)\n' % (c.Name, ' ' * (25 - len(c.Name)), c.Leaf, c.SubLeaf, 'NDR_' + c.Reg, c.Bit)) + + f.write('\n') + + f.write('#endif // CPUID_FLAGS_H\n') # # ============================================================================= @@ -1273,12 +894,12 @@ def generate_features(features, fname): # if __name__ == "__main__": if len(sys.argv) < 2: - print('Usage: %s defs-file' % os.path.basename(sys.argv[0])) + print('Usage: %s defs-file-dir' % os.path.basename(sys.argv[0])) sys.exit(-1) # Extract the flags. print('Loading flags access templates...') - flagsaccess = disasmlib.parse_flags_file('%s/flags.dat' % sys.argv[1]) + disasmlib.parse_flags_file('%s/flags.dat' % sys.argv[1]) # Extact the CPUID features. print('Loading CPUID feature flags templates...') @@ -1291,16 +912,13 @@ if __name__ == "__main__": # Extract the instructions. for fn in glob.glob('%s/table*.dat' % sys.argv[1]): print('Loading instructions from %s...' % fn) - instructions = instructions + disasmlib.parse_ins_file(fn, flagsaccess, features, insmodes) + instructions = instructions + disasmlib.parse_ins_file(fn) # Sort the instructions. instructions = sorted(instructions, key = lambda x: x.Mnemonic) for i in range(0, len(instructions)): instructions[i].Icount = i - # Generate the translation tree - translations = generate_translations2(instructions) - # Generate the mnemonics mnemonics = generate_mnemonics(instructions) mnemonics_prefixes = generate_mnemonics(prefixes) @@ -1310,22 +928,29 @@ if __name__ == "__main__": constants_prefixes = generate_constants(prefixes, True) constants_sets, constants_types = generate_constants2(instructions) + # # Dump all data to files. # # Dump the mnemonics - print('Writing the mnemonics.h file...') - dump_mnemonics(mnemonics, mnemonics_prefixes, r'../bddisasm/include/mnemonics.h') + print('Writing the bdx86_mnemonics.h (instruction mnemonics) file...') + dump_mnemonics(mnemonics, mnemonics_prefixes, r'../bddisasm/include/bdx86_mnemonics.h') # Dump the instruction constants - print('Writing the constants.h (instruction definitions) file...') - dump_constants(constants, constants_prefixes, constants_sets, constants_types, r'../inc/constants.h') + print('Writing the bdx86_constants.h (instruction definitions) file...') + dump_constants(constants, constants_prefixes, constants_sets, constants_types, r'../inc/bdx86_constants.h') - print('Writing the instructions.h (main instruction database) file...') - generate_master_table(instructions, r'../bddisasm/include/instructions.h') + # Dump the CPUID feature flags. + print('Writing the bdx86_cpuidflags.h (CPUID feature flags) file...') + dump_features(features, r'../inc/bdx86_cpuidflags.h') - print('Writing the cpuidflags.h (CPUID feature flags) file...') - generate_features(features, r'../inc/cpuidflags.h') + # Dump the instruction database. + print('Writing the bdx86_instructions.h (main instruction database) file...') + dump_master_table(instructions, r'../bddisasm/include/bdx86_instructions.h') - print('Instruction succesfully parsed & header files generated!') + # Dump the translation tables. + print('Writing the translation tables...') + dump_translation_tables(instructions) + + print('Instruction successfully parsed & header files generated!') diff --git a/isagenerator/instructions/cpuid.dat b/isagenerator/instructions/cpuid.dat index 3e08584..3e982d4 100644 --- a/isagenerator/instructions/cpuid.dat +++ b/isagenerator/instructions/cpuid.dat @@ -117,6 +117,8 @@ AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5 AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8 AVXVNNIINT16 : 0x00000007, 0x00000001, EDX, 10 PREFETCHITI : 0x00000007, 0x00000001, EDX, 14 +USER_MSR : 0x00000007, 0x00000001, EDX, 15 +APX_F : 0x00000007, 0x00000001, EDX, 21 XSAVEOPT : 0x0000000D, 0x00000001, EAX, 0 diff --git a/isagenerator/instructions/table_0F_38.dat b/isagenerator/instructions/table_0F_38.dat deleted file mode 100644 index a127fe2..0000000 --- a/isagenerator/instructions/table_0F_38.dat +++ /dev/null @@ -1,148 +0,0 @@ -# -# Copyright (c) 2020 Bitdefender -# SPDX-License-Identifier: Apache-2.0 -# - -# 0x00 - 0x0F -PSHUFB ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x00 /r ; s:SSSE3, t:MMX, w:RW|R -PSHUFB ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x00 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHADDW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x01 /r ; s:SSSE3, t:MMX, w:RW|R -PHADDW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x01 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHADDD ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x02 /r ; s:SSSE3, t:MMX, w:RW|R -PHADDD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x02 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHADDSW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x03 /r ; s:SSSE3, t:MMX, w:RW|R -PHADDSW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x03 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PMADDUBSW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x04 /r ; s:SSSE3, t:MMX, w:RW|R -PMADDUBSW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x04 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHSUBW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x05 /r ; s:SSSE3, t:MMX, w:RW|R -PHSUBW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x05 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHSUBD ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x06 /r ; s:SSSE3, t:MMX, w:RW|R -PHSUBD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x06 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PHSUBSW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x07 /r ; s:SSSE3, t:MMX, w:RW|R -PHSUBSW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x07 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PSIGNB ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x08 /r ; s:SSSE3, t:MMX, w:RW|R -PSIGNB ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x08 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PSIGNW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x09 /r ; s:SSSE3, t:MMX, w:RW|R -PSIGNW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x09 /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PSIGND ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x0A /r ; s:SSSE3, t:MMX, w:RW|R -PSIGND ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x0A /r ; s:SSSE3, t:SSE, w:RW|R, e:4 -PMULHRSW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x0B /r ; s:SSSE3, t:MMX, w:RW|R -PMULHRSW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x0B /r ; s:SSSE3, t:SSE, w:RW|R, e:4 - -# 0x10 - 0x1F -PBLENDVB ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x10 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4 -BLENDVPS ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x14 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4 -BLENDVPD ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x15 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4 -PTEST ; Vdq,Wdq ; Fv ; 0x66 0x0F 0x38 0x17 /r ; s:SSE4, t:SSE, w:R|R|W, f:CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0, e:4 -PABSB ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x1C /r ; s:SSSE3, t:MMX, w:W|R -PABSB ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x1C /r ; s:SSSE3, t:SSE, w:W|R, e:4 -PABSW ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x1D /r ; s:SSSE3, t:MMX, w:W|R -PABSW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x1D /r ; s:SSSE3, t:SSE, w:W|R, e:4 -PABSD ; Pq,Qq ; n/a ; NP 0x0F 0x38 0x1E /r ; s:SSSE3, t:MMX, w:W|R -PABSD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x1E /r ; s:SSSE3, t:SSE, w:W|R, e:4 - -# 0x20 - 0x2F -PMOVSXBW ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x20 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVSXBD ; Vdq,Wd ; n/a ; 0x66 0x0F 0x38 0x21 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVSXBQ ; Vdq,Ww ; n/a ; 0x66 0x0F 0x38 0x22 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVSXWD ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x23 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVSXWQ ; Vdq,Wd ; n/a ; 0x66 0x0F 0x38 0x24 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVSXDQ ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x25 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMULDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x28 /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PCMPEQQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x29 /r ; s:SSE4, t:SSE, w:RW|R, e:4 -MOVNTDQA ; Vx,Mx ; n/a ; 0x66 0x0F 0x38 0x2A /r:mem ; s:SSE4, t:SSE, w:W|R, e:1 -PACKUSDW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x2B /r ; s:SSE4, t:SSE, w:RW|R, e:4 - - -# 0x30 - 0x3F -PMOVZXBW ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x30 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVZXBD ; Vdq,Wd ; n/a ; 0x66 0x0F 0x38 0x31 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVZXBQ ; Vdq,Ww ; n/a ; 0x66 0x0F 0x38 0x32 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVZXWD ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x33 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVZXWQ ; Vdq,Wd ; n/a ; 0x66 0x0F 0x38 0x34 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PMOVZXDQ ; Vdq,Wq ; n/a ; 0x66 0x0F 0x38 0x35 /r ; s:SSE4, t:SSE, w:W|R, e:5 -PCMPGTQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x37 /r ; s:SSE42, t:SSE, w:RW|R, e:4 -PMINSB ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x38 /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMINSD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x39 /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMINUW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3A /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMINUD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3B /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMAXSB ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3C /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMAXSD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3D /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMAXUW ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3E /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PMAXUD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x3F /r ; s:SSE4, t:SSE, w:RW|R, e:4 - -# 0x40 - 0x4F -PMULLD ; Vx,Wx ; n/a ; 0x66 0x0F 0x38 0x40 /r ; s:SSE4, t:SSE, w:RW|R, e:4 -PHMINPOSUW ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0x41 /r ; s:SSE4, t:SSE, w:W|R, e:4 - -# 0x50 - 0x5F - -# 0x60 - 0x6F - -# 0x70 - 0x7F - -# 0x80 - 0x8F -INVEPT ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x80 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT -INVVPID ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x81 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT -INVPCID ; Gy,Mdq ; n/a ; 0x66 0x0F 0x38 0x82 /r:mem ; s:INVPCID, t:MISC, w:R|R, a:F64, m:KERNEL|NOV86 - -# 0x90 - 0x9F - -# 0xA0 - 0xAF - -# 0xB0 - 0xBF - -# 0xC0 - 0xCF -SHA1NEXTE ; Vdq,Wdq ; n/a ; NP 0x0F 0x38 0xC8 /r ; s:SHA, t:SHA, w:RW|R, e:4 -SHA1MSG1 ; Vdq,Wdq ; n/a ; NP 0x0F 0x38 0xC9 /r ; s:SHA, t:SHA, w:RW|R, e:4 -SHA1MSG2 ; Vdq,Wdq ; n/a ; NP 0x0F 0x38 0xCA /r ; s:SHA, t:SHA, w:RW|R, e:4 -SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; NP 0x0F 0x38 0xCB /r ; s:SHA, t:SHA, w:RW|R|R, e:4 -SHA256MSG1 ; Vdq,Wdq ; n/a ; NP 0x0F 0x38 0xCC /r ; s:SHA, t:SHA, w:RW|R, e:4 -SHA256MSG2 ; Vdq,Wdq ; n/a ; NP 0x0F 0x38 0xCD /r ; s:SHA, t:SHA, w:RW|R, e:4 -GF2P8MULB ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xCF /r ; s:GFNI, t:GFNI, w:RW|R, e:4 - -# 0xD0 - 0xDF -AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /0:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL -AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /1:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL -AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /2:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL -AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /3:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL -AESIMC ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xDB /r ; s:AES, t:AES, w:W|R, e:4 -AESENC ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xDC /r ; s:AES, t:AES, w:RW|R, e:4 -AESENC128KL ; Vdq,M384 ; Fv ; 0xF3 0x0F 0x38 0xDC /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL -LOADIWKEY ; Vdq,Udq ; EAX,XMM0,Fv ; 0xF3 0x0F 0x38 0xDC /r:reg ; s:KL, t:KL, w:R|R|R|R|W, f:AESKL, m:KERNEL -AESENCLAST ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xDD /r ; s:AES, t:AES, w:RW|R, e:4 -AESDEC128KL ; Vdq,M384 ; Fv ; 0xF3 0x0F 0x38 0xDD /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL -AESDEC ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xDE /r ; s:AES, t:AES, w:RW|R, e:4 -AESENC256KL ; Vdq,M512 ; Fv ; 0xF3 0x0F 0x38 0xDE /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL -AESDECLAST ; Vdq,Wdq ; n/a ; 0x66 0x0F 0x38 0xDF /r ; s:AES, t:AES, w:RW|R, e:4 -AESDEC256KL ; Vdq,M512 ; Fv ; 0xF3 0x0F 0x38 0xDF /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL - -# 0xE0 - 0xEF - -# 0xF0 - 0xFF -MOVBE ; Gv,Mv ; n/a ; 0x0F 0x38 0xF0 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R -MOVBE ; Gv,Mv ; n/a ; 0x66 0x0F 0x38 0xF0 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:S66 -CRC32 ; Gy,Eb ; n/a ; 0xF2 0x0F 0x38 0xF0 /r ; s:SSE42, t:SSE, w:RW|R -CRC32 ; Gy,Eb ; n/a ; 0x66 0xF2 0x0F 0x38 0xF0 /r ; s:SSE42, t:SSE, w:RW|R, a:S66 -MOVBE ; Mv,Gv ; n/a ; 0x0F 0x38 0xF1 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R -MOVBE ; Mv,Gv ; n/a ; 0x66 0x0F 0x38 0xF1 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:S66 -CRC32 ; Gy,Ev ; n/a ; 0xF2 0x0F 0x38 0xF1 /r ; s:SSE42, t:SSE, w:RW|R -CRC32 ; Gy,Ev ; n/a ; 0x66 0xF2 0x0F 0x38 0xF1 /r ; s:SSE42, t:SSE, w:RW|R, a:S66 -WRUSSD ; My,Gy ; n/a ; 0x66 0x0F 0x38 0xF5 /r:mem ; s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R, m:KERNEL -WRUSSQ ; My,Gy ; n/a ; rexw 0x66 0x0F 0x38 0xF5 /r:mem ; s:CET_SS, t:CET, c:WRUSS, a:SHS, w:W|R, m:KERNEL -WRSSD ; My,Gy ; n/a ; NP 0x0F 0x38 0xF6 /r:mem ; s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R -WRSSQ ; My,Gy ; n/a ; rexw NP 0x0F 0x38 0xF6 /r:mem ; s:CET_SS, t:CET, c:WRSS, a:SHS, w:W|R -ADCX ; Gy,Ey ; Fv ; 0x66 0x0F 0x38 0xF6 /r ; s:ADX, t:ARITH, w:RW|R|RW, f:CF=m -ADOX ; Gy,Ey ; Fv ; 0xF3 0x0F 0x38 0xF6 /r ; s:ADX, t:ARITH, w:RW|R|RW, f:OF=m -MOVDIR64B ; rMoq,Moq ; n/a ; 0x66 0x0F 0x38 0xF8 /r:mem ; s:MOVDIR64B, t:MOVDIR64B, w:W|R -ENQCMD ; rM?,Moq ; Fv ; 0xF2 0x0F 0x38 0xF8 /r:mem ; s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD -ENQCMDS ; rM?,Moq ; Fv ; 0xF3 0x0F 0x38 0xF8 /r:mem ; s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD -MOVDIRI ; My,Gy ; n/a ; NP 0x0F 0x38 0xF9 /r:mem ; s:MOVDIRI, t:MOVDIRI, w:W|R - -ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; 0xF3 0x0F 0x38 0xFA /r:reg ; s:KL, t:AESKL, w:W|R|R|W|W|W, f:ZERO -ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; 0xF3 0x0F 0x38 0xFB /r:reg ; s:KL, t:AESKL, w:W|R|RW|W|W, f:ZERO - -AADD ; My,Gy ; n/a ; NP 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R -AAND ; My,Gy ; n/a ; 0x66 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R -AOR ; My,Gy ; n/a ; 0xF2 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R -AXOR ; My,Gy ; n/a ; 0xF3 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R diff --git a/isagenerator/instructions/table_0F_3A.dat b/isagenerator/instructions/table_0F_3A.dat deleted file mode 100644 index 6e985f4..0000000 --- a/isagenerator/instructions/table_0F_3A.dat +++ /dev/null @@ -1,74 +0,0 @@ -# -# Copyright (c) 2020 Bitdefender -# SPDX-License-Identifier: Apache-2.0 -# - -# 0x00 - 0x0F -ROUNDPS ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2 -ROUNDPD ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2 -ROUNDSS ; Vss,Wss,Ib ; n/a ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3 -ROUNDSD ; Vsd,Wsd,Ib ; n/a ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3 -BLENDPS ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x0C /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4 -BLENDPD ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x0D /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4 -PBLENDW ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x0E /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4 -PALIGNR ; Pq,Qq,Ib ; n/a ; NP 0x0F 0x3A 0x0F /r ib ; s:SSSE3, t:MMX, w:RW|R|R -PALIGNR ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x0F /r ib ; s:SSSE3, t:SSE, w:RW|R|R, e:4 - -# 0x10 - 0x1F -# TODO: for PEXTRx, a smaller size is accessed, in fact. -PEXTRB ; Mb,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x14 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRB ; Ry,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x14 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 -PEXTRW ; Mw,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x15 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRW ; Ry,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x15 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 -PEXTRD ; Md,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x16 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRD ; Ry,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x16 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64 -PEXTRQ ; Mq,Vdq,Ib ; n/a ; rexw 0x66 0x0F 0x3A 0x16 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5 -PEXTRQ ; Ry,Vdq,Ib ; n/a ; rexw 0x66 0x0F 0x3A 0x16 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5 -EXTRACTPS ; Ed,Vdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x17 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:5 - -# 0x20 - 0x2F -PINSRB ; Vdq,Mb,Ib ; n/a ; 0x66 0x0F 0x3A 0x20 /r:mem ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 -PINSRB ; Vdq,Ry,Ib ; n/a ; 0x66 0x0F 0x3A 0x20 /r:reg ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 -INSERTPS ; Vdq,Md,Ib ; n/a ; 0x66 0x0F 0x3A 0x21 /r:mem ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 -INSERTPS ; Vdq,Udq,Ib ; n/a ; 0x66 0x0F 0x3A 0x21 /r:reg ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 -PINSRD ; Vdq,Ed,Ib ; n/a ; 0x66 0x0F 0x3A 0x22 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 -PINSRQ ; Vdq,Eq,Ib ; n/a ; rexw 0x66 0x0F 0x3A 0x22 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:5 - -# 0x30 - 0x3F - -# 0x40 - 0x4F -DPPS ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2 -DPPD ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2 -MPSADBW ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x42 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4 -PCLMULQDQ ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0x44 /r ib ; s:PCLMULQDQ, t:PCLMULQDQ, w:RW|R|R, e:4 - -# 0x50 - 0x5F - -# 0x60 - 0x6F -PCMPESTRM ; Vdq,Wdq,Ib ; yAX,yDX,XMM0,Fv ; 0x66 0x0F 0x3A 0x60 /r ib ; s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 -PCMPESTRI ; Vdq,Wdq,Ib ; yAX,yDX,yCX,Fv ; 0x66 0x0F 0x3A 0x61 /r ib ; s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 -PCMPISTRM ; Vdq,Wdq,Ib ; XMM0,Fv ; 0x66 0x0F 0x3A 0x62 /r ib ; s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4 -PCMPISTRI ; Vdq,Wdq,Ib ; yCX,Fv ; 0x66 0x0F 0x3A 0x63 /r ib ; s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4 - -# 0x70 - 0x7F - -# 0x80 - 0x8F - -# 0x90 - 0x9F - -# 0xA0 - 0xAF - -# 0xB0 - 0xBF - -# 0xC0 - 0xCF -SHA1RNDS4 ; Vdq,Wdq,Ib ; n/a ; NP 0x0F 0x3A 0xCC /r ib ; s:SHA, t:SHA, w:RW|R|R, e:4 -GF2P8AFFINEQB ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0xCE /r ib ; s:GFNI, t:GFNI, w:RW|R|R, e:4 -GF2P8AFFINEINVQB ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0xCF /r ib ; s:GFNI, t:GFNI, w:RW|R|R, e:4 - -# 0xD0 - 0xDF -AESKEYGENASSIST ; Vdq,Wdq,Ib ; n/a ; 0x66 0x0F 0x3A 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4 - -# 0xE0 - 0xEF - -# 0xF0 - 0xFF -HRESET ; Ib ; EAX ; 0xF3 0x0F 0x3A 0xF0 /0xC0 ib ; s:HRESET, t:HRESET, w:N|R, m:KERNEL|NOV86|NOTSX diff --git a/isagenerator/instructions/table_3dnow.dat b/isagenerator/instructions/table_3dnow.dat index 3d861fb..034aa0e 100644 --- a/isagenerator/instructions/table_3dnow.dat +++ b/isagenerator/instructions/table_3dnow.dat @@ -3,29 +3,29 @@ # SPDX-License-Identifier: Apache-2.0 # -PI2FW ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x0C ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PI2FD ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x0D ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PF2IW ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x1C ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PF2ID ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x1D ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRCPV ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x86 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 -PFRSQRTV ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x87 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 -PFNACC ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x8A ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFPNACC ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x8E ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFCMPGE ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x90 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFMIN ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x94 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRCP ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x96 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRSQRT ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x97 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFSUB ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x9A ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFADD ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0x9E ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFCMPGT ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xA0 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFMAX ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xA4 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRCPIT1 ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xA6 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRSQIT1 ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xA7 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFSUBR ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xAA ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFACC ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xAE ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFCMPEQ ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xB0 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFMUL ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xB4 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PFRCPIT2 ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xB6 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PMULHRW ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xB7 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PSWAPD ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xBB ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW -PAVGUSB ; Pq,Qq ; n/a ; 0x0F 0x0F /r 0xBF ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PI2FW ; Pq,Qq ; ; 0x0F 0x0F /r 0x0C ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PI2FD ; Pq,Qq ; ; 0x0F 0x0F /r 0x0D ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PF2IW ; Pq,Qq ; ; 0x0F 0x0F /r 0x1C ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PF2ID ; Pq,Qq ; ; 0x0F 0x0F /r 0x1D ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPV ; Pq,Qq ; ; 0x0F 0x0F /r 0x86 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 +PFRSQRTV ; Pq,Qq ; ; 0x0F 0x0F /r 0x87 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW, m:NO64 +PFNACC ; Pq,Qq ; ; 0x0F 0x0F /r 0x8A ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFPNACC ; Pq,Qq ; ; 0x0F 0x0F /r 0x8E ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPGE ; Pq,Qq ; ; 0x0F 0x0F /r 0x90 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMIN ; Pq,Qq ; ; 0x0F 0x0F /r 0x94 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCP ; Pq,Qq ; ; 0x0F 0x0F /r 0x96 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRSQRT ; Pq,Qq ; ; 0x0F 0x0F /r 0x97 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFSUB ; Pq,Qq ; ; 0x0F 0x0F /r 0x9A ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFADD ; Pq,Qq ; ; 0x0F 0x0F /r 0x9E ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPGT ; Pq,Qq ; ; 0x0F 0x0F /r 0xA0 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMAX ; Pq,Qq ; ; 0x0F 0x0F /r 0xA4 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPIT1 ; Pq,Qq ; ; 0x0F 0x0F /r 0xA6 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRSQIT1 ; Pq,Qq ; ; 0x0F 0x0F /r 0xA7 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFSUBR ; Pq,Qq ; ; 0x0F 0x0F /r 0xAA ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFACC ; Pq,Qq ; ; 0x0F 0x0F /r 0xAE ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFCMPEQ ; Pq,Qq ; ; 0x0F 0x0F /r 0xB0 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFMUL ; Pq,Qq ; ; 0x0F 0x0F /r 0xB4 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PFRCPIT2 ; Pq,Qq ; ; 0x0F 0x0F /r 0xB6 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PMULHRW ; Pq,Qq ; ; 0x0F 0x0F /r 0xB7 ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PSWAPD ; Pq,Qq ; ; 0x0F 0x0F /r 0xBB ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW +PAVGUSB ; Pq,Qq ; ; 0x0F 0x0F /r 0xBF ; s:3DNOW, t:3DNOW, w:RW|R, a:3DNOW diff --git a/isagenerator/instructions/table_evex1.dat b/isagenerator/instructions/table_evex_1.dat similarity index 52% rename from isagenerator/instructions/table_evex1.dat rename to isagenerator/instructions/table_evex_1.dat index 0ea9a98..f89a3d2 100644 --- a/isagenerator/instructions/table_evex1.dat +++ b/isagenerator/instructions/table_evex_1.dat @@ -4,181 +4,181 @@ # # 0x10 - 0x1F -VMOVUPS ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:0 l:x w:0 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVUPD ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:1 l:x w:1 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVSS ; Vdq{K}{z},Mss ; n/a ; evex m:1 p:2 l:i w:0 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R -VMOVSS ; Vdq{K}{z},Hdq,Udq ; n/a ; evex m:1 p:2 l:i w:0 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R -VMOVSD ; Vdq{K}{z},Msd ; n/a ; evex m:1 p:3 l:i w:1 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R -VMOVSD ; Vdq{K}{z},Hdq,Udq ; n/a ; evex m:1 p:3 l:i w:1 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R -VMOVUPS ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:0 l:x w:0 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVUPD ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:1 l:x w:1 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVSS ; Mss{K},Vdq ; n/a ; evex m:1 p:2 l:i w:0 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R -VMOVSS ; Udq{K}{z},Hdq,Vdq ; n/a ; evex m:1 p:2 l:i w:0 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R -VMOVSD ; Msd{K},Vdq ; n/a ; evex m:1 p:3 l:i w:1 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R -VMOVSD ; Udq{K}{z},Hdq,Vdq ; n/a ; evex m:1 p:3 l:i w:1 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R -VMOVLPS ; Vdq,Hdq,Mq ; n/a ; evex m:1 p:0 l:0 w:0 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R -VMOVHLPS ; Vdq,Hdq,Udq ; n/a ; evex m:1 p:0 l:0 w:0 0x12 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R -VMOVLPD ; Vdq,Hdq,Mq ; n/a ; evex m:1 p:1 l:0 w:1 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R -VMOVSLDUP ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:2 l:x w:0 0x12 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R -VMOVDDUP ; Vdq{K}{z},Wq ; n/a ; evex m:1 p:3 l:0 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R -VMOVDDUP ; Vqq{K}{z},Wqq ; n/a ; evex m:1 p:3 l:1 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R -VMOVDDUP ; Voq{K}{z},Woq ; n/a ; evex m:1 p:3 l:2 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R -VMOVLPS ; Mq,Vdq ; n/a ; evex m:1 p:0 l:0 w:0 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R -VMOVLPD ; Mq,Vdq ; n/a ; evex m:1 p:1 l:0 w:1 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R -VUNPCKLPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VUNPCKLPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VUNPCKHPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VUNPCKHPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VMOVHPS ; Vdq,Hdq,Mq ; n/a ; evex m:1 p:0 l:0 w:0 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R -VMOVLHPS ; Vdq,Hdq,Udq ; n/a ; evex m:1 p:0 l:0 w:0 0x16 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R -VMOVHPD ; Vdq,Hdq,Mq ; n/a ; evex m:1 p:1 l:0 w:1 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R -VMOVSHDUP ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:2 l:x w:0 0x16 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R -VMOVHPS ; Mq,Vdq ; n/a ; evex m:1 p:0 l:0 w:0 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R -VMOVHPD ; Mq,Vdq ; n/a ; evex m:1 p:1 l:0 w:1 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVUPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVUPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x10 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVSS ; Vdq{K}{z},Mss ; ; evex m:1 p:2 l:i w:0 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSS ; Vdq{K}{z},Hdq,Udq ; ; evex m:1 p:2 l:i w:0 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVSD ; Vdq{K}{z},Msd ; ; evex m:1 p:3 l:i w:1 0x10 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSD ; Vdq{K}{z},Hdq,Udq ; ; evex m:1 p:3 l:i w:1 0x10 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVUPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVUPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x11 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVSS ; Mss{K},Vdq ; ; evex m:1 p:2 l:i w:0 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSS ; Udq{K}{z},Hdq,Vdq ; ; evex m:1 p:2 l:i w:0 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVSD ; Msd{K},Vdq ; ; evex m:1 p:3 l:i w:1 0x11 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R +VMOVSD ; Udq{K}{z},Hdq,Vdq ; ; evex m:1 p:3 l:i w:1 0x11 /r:reg ; s:AVX512F, t:DATAXFER, l:t1s, e:E10, w:W|R|R|R +VMOVLPS ; Vdq,Hdq,Mq ; ; evex m:1 p:0 l:0 w:0 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R +VMOVHLPS ; Vdq,Hdq,Udq ; ; evex m:1 p:0 l:0 w:0 0x12 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R +VMOVLPD ; Vdq,Hdq,Mq ; ; evex m:1 p:1 l:0 w:1 0x12 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R +VMOVSLDUP ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x12 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R +VMOVDDUP ; Vdq{K}{z},Wq ; ; evex m:1 p:3 l:0 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVDDUP ; Vqq{K}{z},Wqq ; ; evex m:1 p:3 l:1 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVDDUP ; Voq{K}{z},Woq ; ; evex m:1 p:3 l:2 w:1 0x12 /r ; s:AVX512F, t:DATAXFER, l:dup, e:E5NF, w:W|R|R +VMOVLPS ; Mq,Vdq ; ; evex m:1 p:0 l:0 w:0 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R +VMOVLPD ; Mq,Vdq ; ; evex m:1 p:1 l:0 w:1 0x13 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VUNPCKLPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKLPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKHPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VUNPCKHPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VMOVHPS ; Vdq,Hdq,Mq ; ; evex m:1 p:0 l:0 w:0 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R|R +VMOVLHPS ; Vdq,Hdq,Udq ; ; evex m:1 p:0 l:0 w:0 0x16 /r:reg ; s:AVX512F, t:DATAXFER, e:E7NM, w:W|R|R +VMOVHPD ; Vdq,Hdq,Mq ; ; evex m:1 p:1 l:0 w:1 0x16 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R|R +VMOVSHDUP ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x16 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4NFnb, w:W|R|R +VMOVHPS ; Mq,Vdq ; ; evex m:1 p:0 l:0 w:0 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t2, e:E9NF, w:W|R +VMOVHPD ; Mq,Vdq ; ; evex m:1 p:1 l:0 w:1 0x17 /r:mem ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R # 0x20 - 0x2F -VMOVAPS ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:0 l:x w:0 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVAPD ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVAPS ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:0 l:x w:0 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVAPD ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VCVTSI2SS ; Vdq,Hdq{er},Ey ; n/a ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VCVTSI2SD ; Vdq,Hdq,Ey ; n/a ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 -VCVTSI2SD ; Vdq,Hdq{er},Ey ; n/a ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VMOVNTPS ; Mfv,Vfv ; n/a ; evex m:1 p:0 l:x w:0 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R -VMOVNTPD ; Mfv,Vfv ; n/a ; evex m:1 p:1 l:x w:1 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R -VCVTTSS2SI ; Gy,Wss{sae} ; n/a ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTSD2SI ; Gy,Wsd{sae} ; n/a ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSS2SI ; Gy,Wss{er} ; n/a ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSD2SI ; Gy,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VMOVAPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVAPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 +VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 +VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 +VMOVNTPS ; Mfv,Vfv ; ; evex m:1 p:0 l:x w:0 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VMOVNTPD ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:1 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS # 0x50 - 0x5F -VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VANDPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VANDPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VANDNPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VANDNPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VXORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:0 l:x w:0 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VXORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R -VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; n/a ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R -VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R -VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; n/a ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; n/a ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; n/a ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; n/a ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; n/a ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; n/a ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; n/a ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; n/a ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VANDPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDNPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VANDNPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VXORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VXORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R +VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R +VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R +VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R # 0x60 - 0x6F -VPUNPCKLBW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:x 0x60 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPUNPCKLWD ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:x 0x61 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPUNPCKLDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0x62 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPACKSSWB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x63 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPCMPGTB ; rKq{K},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x64 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPCMPGTW ; rKq{K},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x65 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPCMPGTD ; rKq{K},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0x66 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPACKUSWB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x67 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPUNPCKHBW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x68 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPUNPCKHWD ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x69 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPUNPCKHDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0x6A /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPACKSSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0x6B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPUNPCKLQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x6C /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPUNPCKHQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0x6D /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VMOVD ; Vdq,Ed ; n/a ; evex m:1 p:1 l:0 w:0 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 -VMOVQ ; Vdq,Eq ; n/a ; evex m:1 p:1 l:0 w:1 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 -VMOVDQA32 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:1 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVDQA64 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:1 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVDQU32 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:2 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU64 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:2 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU8 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:3 l:x w:0 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU16 ; Vfv{K}{z},Wfv ; n/a ; evex m:1 p:3 l:x w:1 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VPUNPCKLBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x60 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKLWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x61 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKLDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x62 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPACKSSWB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x63 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPCMPGTB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x64 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPGTW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x65 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPGTD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x66 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPACKUSWB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x67 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x68 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x69 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPUNPCKHDQ ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x6A /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPACKSSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0x6B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPUNPCKLQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x6C /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPUNPCKHQDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x6D /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VMOVD ; Vdq,Ed ; ; evex m:1 p:1 l:0 w:0 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 +VMOVQ ; Vdq,Eq ; ; evex m:1 p:1 l:0 w:1 0x6E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 +VMOVDQA32 ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQA64 ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQU32 ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:0 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU64 ; Vfv{K}{z},Wfv ; ; evex m:1 p:2 l:x w:1 0x6F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU8 ; Vfv{K}{z},Wfv ; ; evex m:1 p:3 l:x w:0 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU16 ; Vfv{K}{z},Wfv ; ; evex m:1 p:3 l:x w:1 0x6F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R # 0x70 - 0x7F -VPSHUFD ; Vfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x70 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPSHUFHW ; Vfv{K}{z},Wfv,Ib ; n/a ; evex m:1 p:2 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPSHUFLW ; Vfv{K}{z},Wfv,Ib ; n/a ; evex m:1 p:3 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPSRLW ; Hfv{K}{z},Wfv,Ib ; n/a ; evex m:1 p:1 l:x w:i 0x71 /2 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSRAW ; Hfv{K}{z},Wfv,Ib ; n/a ; evex m:1 p:1 l:x w:i 0x71 /4 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSLLW ; Hfv{K}{z},Wfv,Ib ; n/a ; evex m:1 p:1 l:x w:i 0x71 /6 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPRORD ; Hfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPRORQ ; Hfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPROLD ; Hfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPROLQ ; Hfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRLD ; Hfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x72 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRAD ; Hfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRAQ ; Hfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSLLD ; Hfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:1 p:1 l:x w:0 0x72 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRLQ ; Hfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0x73 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRLDQ ; Hfv,Wfv,Ib ; n/a ; evex m:1 p:1 l:x w:i 0x73 /3 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R -VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSLLDQ ; Hfv,Wfv,Ib ; n/a ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R -VPCMPEQB ; rKq{K},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPCMPEQW ; rKq{K},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; n/a ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; n/a ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; n/a ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; n/a ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTTSS2USI ; Gy,Wss{sae} ; n/a ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTSD2USI ; Gy,Wsd{sae} ; n/a ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; n/a ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; n/a ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTSS2USI ; Gy,Wss{er} ; n/a ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTSD2USI ; Gy,Wsd{er} ; n/a ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 -VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; n/a ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; n/a ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUDQ2PD ; Vfv{K}{z},Whv|B32 ; n/a ; evex m:1 p:2 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER -VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; n/a ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; n/a ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R -VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTUSI2SS ; Vss,Hss{er},Ey ; n/a ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VCVTUSI2SD ; Vdq,Hdq,Ey ; n/a ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 -VCVTUSI2SD ; Vdq,Hdq{er},Ey ; n/a ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 -VMOVD ; Ey,Vdq ; n/a ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 -VMOVQ ; Ey,Vdq ; n/a ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 -VMOVQ ; Vdq,Wq ; n/a ; evex m:1 p:2 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R -VMOVDQA32 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVDQA64 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R -VMOVDQU32 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:2 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU64 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:2 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU8 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:3 l:x w:0 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R -VMOVDQU16 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:3 l:x w:1 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VPSHUFD ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x70 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPSHUFHW ; Vfv{K}{z},Wfv,Ib ; ; evex m:1 p:2 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPSHUFLW ; Vfv{K}{z},Wfv,Ib ; ; evex m:1 p:3 l:x w:i 0x70 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPSRLW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /2 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSRAW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /4 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSLLW ; Hfv{K}{z},Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x71 /6 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPRORD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPRORQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /0 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /1 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x72 /4 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLD ; Hfv{K}{z},Wfv|B32,Ib ; ; evex m:1 p:1 l:x w:0 0x72 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /2 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /3 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64 +VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER +VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R +VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 +VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64 +VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64 +VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 +VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64 +VMOVQ ; Vdq,Wq ; ; evex m:1 p:2 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VMOVDQA32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQA64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R +VMOVDQU32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:2 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:2 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU8 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:0 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R +VMOVDQU16 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:1 0x7F /r ; s:AVX512BW, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R # 0x80 - 0x8F @@ -189,69 +189,91 @@ VMOVDQU16 ; Wfv{K}{z},Vfv ; n/a ; evex m:1 p:3 l:x w:1 # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; n/a ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; n/a ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; n/a ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; n/a ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VPINSRW ; Vdq,Hdq,Mw,Ib ; n/a ; evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R -VPINSRW ; Vdq,Hdq,Rv,Ib ; n/a ; evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R -VPEXTRW ; Gy,Udq,Ib ; n/a ; evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R -VSHUFPS ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; n/a ; evex m:1 p:0 l:x w:0 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R -VSHUFPD ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:1 p:1 l:x w:1 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VPINSRW ; Vdq,Hdq,Mw,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R +VPINSRW ; Vdq,Hdq,Rv,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R +VPEXTRW ; Gy,Udq,Ib ; ; evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VSHUFPS ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:1 p:0 l:x w:0 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFPD ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0xC6 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R # 0xD0 - 0xDF -VPSRLW ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R -VPSRLD ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:0 0xD2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPSRLQ ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:1 0xD3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPADDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xD4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMULLW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VMOVQ ; Wq,Vdq ; n/a ; evex m:1 p:1 l:0 w:1 0xD6 /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R -VPSUBUSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R -VPSUBUSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R -VPMINUB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xDA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPANDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPANDD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPADDUSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xDC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPADDUSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xDD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMAXUB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xDE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPANDND ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPANDNQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPSRLW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSRLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xD2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSRLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xD3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPADDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xD4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMULLW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VMOVQ ; Wq,Vdq ; ; evex m:1 p:1 l:0 w:1 0xD6 /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R +VPSUBUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPSUBUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPMINUB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPANDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPANDD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xDB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPADDUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXUB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xDE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPANDND ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPANDNQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xDF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R # 0xE0 - 0xEF -VPAVGB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE0 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSRAW ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:i 0xE1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R -VPSRAD ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:0 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPSRAQ ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:1 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPAVGW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMULHUW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMULHW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; n/a ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTDQ2PD ; Vfv{K}{z},Whv|B32 ; n/a ; evex m:1 p:2 l:x w:0 0xE6 /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER -VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R -VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; n/a ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R -VMOVNTDQ ; Mfv,Vfv ; n/a ; evex m:1 p:1 l:x w:0 0xE7 /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R -VPSUBSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSUBSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMINSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xEA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPORD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPADDSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xEC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPADDSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xED /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMAXSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xEE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPXORD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPXORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPAVGB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE0 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSRAW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xE1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSRAD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSRAQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xE2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPAVGW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMULHUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMULHW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0xE6 /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER +VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R +VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R +VMOVNTDQ ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:0 0xE7 /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VPSUBSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEA /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPORD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xEB /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPADDSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xED /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xEE /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPXORD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPXORQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xEF /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R # 0xF0 - 0xFF -VPSLLW ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:i 0xF1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R -VPSLLD ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:0 0xF2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPSLLQ ; Vfv{K}{z},Hfv,Wdq ; n/a ; evex m:1 p:1 l:x w:1 0xF3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R -VPMULUDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xF4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMADDWD ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xF5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSADBW ; Vfv,Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xF6 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R -VPSUBB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xF8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSUBW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xF9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSUBD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xFA /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSUBQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:1 p:1 l:x w:1 0xFB /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPADDB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xFC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPADDW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:1 p:1 l:x w:i 0xFD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPADDD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:1 p:1 l:x w:0 0xFE /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLW ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:i 0xF1 /r ; s:AVX512BW, t:AVX512, l:m128, e:E4nb, w:W|R|R|R +VPSLLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0 0xF2 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPSLLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xF3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R +VPMULUDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xF4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMADDWD ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSADBW ; Vfv,Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF6 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R +VPSUBB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xF9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSUBD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xFA /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSUBQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xFB /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPADDB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xFC /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xFD /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPADDD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:0 0xFE /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R + +# APX - KMOV instructions. +KMOVW ; rKw,Mw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVB ; rKb,Mb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVQ ; rKq,Mq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVD ; rKd,Md ; ; evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVW ; rKw,mKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVB ; rKb,mKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVQ ; rKq,mKq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVD ; rKd,mKd ; ; evex m:1 p:1 l:0 w:1 nf:0 0x90 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVW ; Mw,rKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVB ; Mb,rKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVQ ; Mq,rKq ; ; evex m:1 p:0 l:0 w:1 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVD ; Md,rKd ; ; evex m:1 p:1 l:0 w:1 nf:0 0x91 /r:mem ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVW ; rKw,Ry ; ; evex m:1 p:0 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVB ; rKb,Ry ; ; evex m:1 p:1 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVQ ; rKq,Ry ; ; evex m:1 p:3 l:0 w:1 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVD ; rKd,Ry ; ; evex m:1 p:3 l:0 w:0 nf:0 0x92 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVW ; Gy,mKw ; ; evex m:1 p:0 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVB ; Gy,mKb ; ; evex m:1 p:1 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVQ ; Gy,mKq ; ; evex m:1 p:3 l:0 w:1 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV +KMOVD ; Gy,mKd ; ; evex m:1 p:3 l:0 w:0 nf:0 0x93 /r:reg ; s:APX_F, t:KMASK, c:KMOV, w:W|R, v:vex, e:APX_EVEX_KMOV \ No newline at end of file diff --git a/isagenerator/instructions/table_evex2.dat b/isagenerator/instructions/table_evex_2.dat similarity index 50% rename from isagenerator/instructions/table_evex2.dat rename to isagenerator/instructions/table_evex_2.dat index 2059a06..fd70ef9 100644 --- a/isagenerator/instructions/table_evex2.dat +++ b/isagenerator/instructions/table_evex_2.dat @@ -4,342 +4,386 @@ # # 0x00 - 0x0F -VPSHUFB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x00 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPMADDUBSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x04 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R -VPMULHRSW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x0B /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPERMILPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x0C /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPERMILPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x0D /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPSHUFB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x00 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPMADDUBSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x04 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R +VPMULHRSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x0B /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPERMILPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x0C /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMILPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x0D /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R # 0x10 - 0x1F -VPSRLVW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x10 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPSRAVW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x11 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R -VPSLLVW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x12 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; n/a ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R -VPRORVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPRORVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPROLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPROLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPERMPS ; Vuv{K}{z},Huv,Wuv|B32 ; n/a ; evex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPERMPS ; Vuv{K}{z},Huv,Wuv|B32 ; n/a ; evex m:2 p:1 l:2 w:0 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPERMPD ; Vuv{K}{z},Huv,Wuv|B64 ; n/a ; evex m:2 p:1 l:1 w:1 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPERMPD ; Vuv{K}{z},Huv,Wuv|B64 ; n/a ; evex m:2 p:1 l:2 w:1 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPMOVUSWB ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x10 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMOVUSDB ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x11 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVUSQB ; Wev{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x12 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R -VPMOVUSDW ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x13 /r ; s:AVX512F, t:DATAXFER, l:hv, l:hvm, e:E6, w:W|R|R -VPMOVUSQW ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x14 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVUSQD ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x15 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VBROADCASTSS ; Vfv{K}{z},Wss ; n/a ; evex m:2 p:1 l:x w:0 0x18 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R -VBROADCASTF32X2 ; Vuv{K}{z},Wq ; n/a ; evex m:2 p:1 l:x w:0 0x19 /r ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R -VBROADCASTSD ; Vuv{K}{z},Wsd ; n/a ; evex m:2 p:1 l:x w:1 0x19 /r ; s:AVX512F, t:BROADCAST, a:NOL0, l:t1s, e:E6, w:W|R|R -VBROADCASTF32X4 ; Vuv{K}{z},Mdq ; n/a ; evex m:2 p:1 l:x w:0 0x1A /r:mem ; s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R -VBROADCASTF64X2 ; Vuv{K}{z},Mdq ; n/a ; evex m:2 p:1 l:x w:1 0x1A /r:mem ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R -VBROADCASTF32X8 ; Voq{K}{z},Mqq ; n/a ; evex m:2 p:1 l:2 w:0 0x1B /r:mem ; s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R -VBROADCASTF64X4 ; Voq{K}{z},Mqq ; n/a ; evex m:2 p:1 l:2 w:1 0x1B /r:mem ; s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R -VPABSB ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:x 0x1C /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R -VPABSW ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:x 0x1D /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R -VPABSD ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x1E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R -VPABSQ ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x1F /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VPSRLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x10 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPSRAVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x11 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R +VPSLLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x12 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R +VPRORVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPRORVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPROLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPERMPS ; Vuv{K}{z},Huv,Wuv|B32 ; ; evex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPS ; Vuv{K}{z},Huv,Wuv|B32 ; ; evex m:2 p:1 l:2 w:0 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPD ; Vuv{K}{z},Huv,Wuv|B64 ; ; evex m:2 p:1 l:1 w:1 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMPD ; Vuv{K}{z},Huv,Wuv|B64 ; ; evex m:2 p:1 l:2 w:1 0x16 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPMOVUSWB ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x10 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVUSDB ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x11 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVUSQB ; Wev{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x12 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVUSDW ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x13 /r ; s:AVX512F, t:DATAXFER, l:hv, l:hvm, e:E6, w:W|R|R +VPMOVUSQW ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x14 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVUSQD ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x15 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VBROADCASTSS ; Vfv{K}{z},Wss ; ; evex m:2 p:1 l:x w:0 0x18 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTF32X2 ; Vuv{K}{z},Wq ; ; evex m:2 p:1 l:x w:0 0x19 /r ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTSD ; Vuv{K}{z},Wsd ; ; evex m:2 p:1 l:x w:1 0x19 /r ; s:AVX512F, t:BROADCAST, a:NOL0, l:t1s, e:E6, w:W|R|R +VBROADCASTF32X4 ; Vuv{K}{z},Mdq ; ; evex m:2 p:1 l:x w:0 0x1A /r:mem ; s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R +VBROADCASTF64X2 ; Vuv{K}{z},Mdq ; ; evex m:2 p:1 l:x w:1 0x1A /r:mem ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTF32X8 ; Voq{K}{z},Mqq ; ; evex m:2 p:1 l:2 w:0 0x1B /r:mem ; s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R +VBROADCASTF64X4 ; Voq{K}{z},Mqq ; ; evex m:2 p:1 l:2 w:1 0x1B /r:mem ; s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R +VPABSB ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:x 0x1C /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R +VPABSW ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:x 0x1D /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R +VPABSD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x1E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VPABSQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x1F /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R # 0x20 - 0x2F -VPMOVSXBW ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:i 0x20 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPMOVSXBD ; Vfv{K}{z},Wqv ; n/a ; evex m:2 p:1 l:x w:i 0x21 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R -VPMOVSXBQ ; Vfv{K}{z},Wev ; n/a ; evex m:2 p:1 l:x w:i 0x22 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R -VPMOVSXWD ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:i 0x23 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPMOVSXWQ ; Vfv{K}{z},Wqv ; n/a ; evex m:2 p:1 l:x w:i 0x24 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R -VPMOVSXDQ ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:0 0x25 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPTESTMB ; rKq{K},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R -VPTESTMW ; rKq{K},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R -VPTESTMD ; rKq{K},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPTESTMQ ; rKq{K},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPMOVSWB ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x20 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMOVSDB ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x21 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVSQB ; Wev{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x22 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R -VPMOVSDW ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x23 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMOVSQW ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x24 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVSQD ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x25 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPTESTNMB ; rKq{K},Hfv,Wfv ; n/a ; evex m:2 p:2 l:x w:0 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R -VPTESTNMW ; rKq{K},Hfv,Wfv ; n/a ; evex m:2 p:2 l:x w:1 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R -VPTESTNMD ; rKq{K},Hfv,Wfv|B32 ; n/a ; evex m:2 p:2 l:x w:0 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPTESTNMQ ; rKq{K},Hfv,Wfv|B64 ; n/a ; evex m:2 p:2 l:x w:1 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R -VPMULDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPCMPEQQ ; rKq{K},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VMOVNTDQA ; Vfv,Mfv ; n/a ; evex m:2 p:1 l:x w:0 0x2A /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R -VPACKUSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x2B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VPMOVM2B ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:0 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R -VPMOVM2W ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:1 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R -VPMOVB2M ; rKq,Ufv ; n/a ; evex m:2 p:2 l:x w:0 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R -VPMOVW2M ; rKq,Ufv ; n/a ; evex m:2 p:2 l:x w:1 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R -VPBROADCASTMB2Q ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:1 0x2A /r:reg ; s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R +VPMOVSXBW ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:i 0x20 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVSXBD ; Vfv{K}{z},Wqv ; ; evex m:2 p:1 l:x w:i 0x21 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVSXBQ ; Vfv{K}{z},Wev ; ; evex m:2 p:1 l:x w:i 0x22 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R +VPMOVSXWD ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:i 0x23 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVSXWQ ; Vfv{K}{z},Wqv ; ; evex m:2 p:1 l:x w:i 0x24 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVSXDQ ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:0 0x25 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPTESTMB ; rKq{K},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTMW ; rKq{K},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTMD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPTESTMQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPMOVSWB ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x20 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVSDB ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x21 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVSQB ; Wev{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x22 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVSDW ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x23 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVSQW ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x24 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVSQD ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x25 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPTESTNMB ; rKq{K},Hfv,Wfv ; ; evex m:2 p:2 l:x w:0 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTNMW ; rKq{K},Hfv,Wfv ; ; evex m:2 p:2 l:x w:1 0x26 /r ; s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R +VPTESTNMD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPTESTNMQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:2 l:x w:1 0x27 /r ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R +VPMULDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPCMPEQQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VMOVNTDQA ; Vfv,Mfv ; ; evex m:2 p:1 l:x w:0 0x2A /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R +VPACKUSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x2B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VPMOVM2B ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVM2W ; Vfv,mKq ; ; evex m:2 p:2 l:x w:1 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVB2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:0 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPMOVW2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:1 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R +VPBROADCASTMB2Q ; Vfv,mKq ; ; evex m:2 p:2 l:x w:1 0x2A /r:reg ; s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R # 0x30 - 0x3F -VPMOVZXBW ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:i 0x30 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPMOVZXBD ; Vfv{K}{z},Wqv ; n/a ; evex m:2 p:1 l:x w:i 0x31 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R -VPMOVZXBQ ; Vfv{K}{z},Wev ; n/a ; evex m:2 p:1 l:x w:i 0x32 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R -VPMOVZXWD ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:i 0x33 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPMOVZXWQ ; Vfv{K}{z},Wqv ; n/a ; evex m:2 p:1 l:x w:i 0x34 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R -VPMOVZXDQ ; Vfv{K}{z},Whv ; n/a ; evex m:2 p:1 l:x w:0 0x35 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R -VPERMD ; Vuv{K}{z},Huv,Wuv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x36 /r ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R -VPERMQ ; Vuv{K}{z},Huv,Wuv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x36 /r ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R -VPCMPGTQ ; rKq{K},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x37 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMOVWB ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x30 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMOVDB ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x31 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVQB ; Wev{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x32 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R -VPMOVDW ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x33 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMOVQW ; Wqv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x34 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R -VPMOVQD ; Whv{K}{z},Vfv ; n/a ; evex m:2 p:2 l:x w:0 0x35 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R -VPMINSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x38 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMINSD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x39 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMINSQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x39 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMINUW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x3A /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMINUD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x3B /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMINUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x3B /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMAXSB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x3C /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMAXSD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x3D /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMAXSQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x3D /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMAXUW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0x3E /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R -VPMAXUD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x3F /r ; s:AVX512F, t:AVX512, l:fv, e:E4nb, w:W|R|R|R -VPMAXUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x3F /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMOVM2D ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:0 0x38 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R -VPMOVM2Q ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:1 0x38 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R -VPMOVD2M ; rKq,Ufv ; n/a ; evex m:2 p:2 l:x w:0 0x39 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R -VPMOVQ2M ; rKq,Ufv ; n/a ; evex m:2 p:2 l:x w:1 0x39 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R -VPBROADCASTMW2D ; Vfv,mKq ; n/a ; evex m:2 p:2 l:x w:0 0x3A /r:reg ; s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R +VPMOVZXBW ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:i 0x30 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVZXBD ; Vfv{K}{z},Wqv ; ; evex m:2 p:1 l:x w:i 0x31 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVZXBQ ; Vfv{K}{z},Wev ; ; evex m:2 p:1 l:x w:i 0x32 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E5, w:W|R|R +VPMOVZXWD ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:i 0x33 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPMOVZXWQ ; Vfv{K}{z},Wqv ; ; evex m:2 p:1 l:x w:i 0x34 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R +VPMOVZXDQ ; Vfv{K}{z},Whv ; ; evex m:2 p:1 l:x w:0 0x35 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R +VPERMD ; Vuv{K}{z},Huv,Wuv|B32 ; ; evex m:2 p:1 l:x w:0 0x36 /r ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPERMQ ; Vuv{K}{z},Huv,Wuv|B64 ; ; evex m:2 p:1 l:x w:1 0x36 /r ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPCMPGTQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x37 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMOVWB ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x30 /r ; s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVDB ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x31 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVQB ; Wev{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x32 /r ; s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R +VPMOVDW ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x33 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMOVQW ; Wqv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x34 /r ; s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R +VPMOVQD ; Whv{K}{z},Vfv ; ; evex m:2 p:2 l:x w:0 0x35 /r ; s:AVX512F, t:DATAXFER, l:hvm, e:E6, w:W|R|R +VPMINSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x38 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x39 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINSQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x39 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x3A /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMINUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x3B /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMINUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x3B /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x3C /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x3D /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXSQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x3D /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMAXUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0x3E /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R +VPMAXUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x3F /r ; s:AVX512F, t:AVX512, l:fv, e:E4nb, w:W|R|R|R +VPMAXUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x3F /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMOVM2D ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 0x38 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVM2Q ; Vfv,mKq ; ; evex m:2 p:2 l:x w:1 0x38 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVD2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:0 0x39 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPMOVQ2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:1 0x39 /r:reg ; s:AVX512DQ, t:DATAXFER, e:E7NM, w:W|R +VPBROADCASTMW2D ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 0x3A /r:reg ; s:AVX512CD, t:BROADCAST, e:E6NF, w:W|R # 0x40 - 0x4F -VPMULLD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x40 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPMULLQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x40 /r ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R -VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; n/a ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; n/a ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R -VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; n/a ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R -VPLZCNTD ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R -VPLZCNTQ ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R -VPSRLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRAVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSRAVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSLLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VPSLLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R -VRCP14PS ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R -VRCP14PD ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R -VRCP14SS ; Vdq{K}{z},Hdq,Wss ; n/a ; evex m:2 p:1 l:x w:0 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R -VRCP14SD ; Vdq{K}{z},Hdq,Wsd ; n/a ; evex m:2 p:1 l:x w:1 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R -VRSQRT14PS ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x4E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R -VRSQRT14PD ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x4E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R -VRSQRT14SS ; Vdq{K}{z},Hdq,Wss ; n/a ; evex m:2 p:1 l:x w:0 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R -VRSQRT14SD ; Vdq{K}{z},Hdq,Wsd ; n/a ; evex m:2 p:1 l:x w:1 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VPMULLD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x40 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPMULLQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x40 /r ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R +VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R +VPLZCNTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R +VPLZCNTQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R +VPSRLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSRAVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VPSLLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R +VRCP14PS ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRCP14PD ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRCP14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRCP14SD ; Vdq{K}{z},Hdq,Wsd ; ; evex m:2 p:1 l:x w:1 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRSQRT14PS ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x4E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRSQRT14PD ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x4E /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R +VRSQRT14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R +VRSQRT14SD ; Vdq{K}{z},Hdq,Wsd ; ; evex m:2 p:1 l:x w:1 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R # 0x50 - 0x5F -VPDPBUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x50 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R -VPDPBUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x51 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R -VPDPWSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x52 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R -VDPBF16PS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:2 l:x w:0 0x52 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R|R -VP4DPWSSD ; Voq{K}{z},Hoq+3,Mdq ; n/a ; evex m:2 p:3 l:2 w:0 0x52 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R -VPDPWSSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x53 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R -VP4DPWSSDS ; Voq{K}{z},Hoq+3,Mdq ; n/a ; evex m:2 p:3 l:2 w:0 0x53 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R -VPOPCNTB ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x54 /r ; s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R -VPOPCNTW ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x54 /r ; s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R -VPOPCNTD ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x55 /r ; s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R -VPOPCNTQ ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x55 /r ; s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R -VPBROADCASTD ; Vfv{K}{z},Wd ; n/a ; evex m:2 p:1 l:x w:0 0x58 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R -VBROADCASTI32X2 ; Vfv{K}{z},Wq ; n/a ; evex m:2 p:1 l:x w:0 0x59 /r ; s:AVX512DQ, t:BROADCAST, l:t2, e:E6, w:W|R|R -VPBROADCASTQ ; Vfv{K}{z},Wq ; n/a ; evex m:2 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R -VBROADCASTI32X4 ; Vuv{K}{z},Mdq ; n/a ; evex m:2 p:1 l:x w:0 0x5A /r:mem ; s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R -VBROADCASTI64X2 ; Vuv{K}{z},Mdq ; n/a ; evex m:2 p:1 l:x w:1 0x5A /r:mem ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R -VBROADCASTI32X8 ; Voq{K}{z},Mqq ; n/a ; evex m:2 p:1 l:2 w:0 0x5B /r:mem ; s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R -VBROADCASTI64X4 ; Voq{K}{z},Mqq ; n/a ; evex m:2 p:1 l:2 w:1 0x5B /r:mem ; s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R +VPDPBUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x50 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPBUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x51 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VPDPWSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x52 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VDPBF16PS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x52 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R|R +VP4DPWSSD ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x52 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R +VPDPWSSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x53 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R +VP4DPWSSDS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x53 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R +VPOPCNTB ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:0 0x54 /r ; s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R +VPOPCNTW ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:1 0x54 /r ; s:AVX512BITALG, t:VPOPCNT, l:fvm, e:E4, w:W|R|R +VPOPCNTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x55 /r ; s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R +VPOPCNTQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x55 /r ; s:AVX512VPOPCNTDQ, t:VPOPCNT, l:fv, e:E4, w:W|R|R +VPBROADCASTD ; Vfv{K}{z},Wd ; ; evex m:2 p:1 l:x w:0 0x58 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTI32X2 ; Vfv{K}{z},Wq ; ; evex m:2 p:1 l:x w:0 0x59 /r ; s:AVX512DQ, t:BROADCAST, l:t2, e:E6, w:W|R|R +VPBROADCASTQ ; Vfv{K}{z},Wq ; ; evex m:2 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:BROADCAST, l:t1s, e:E6, w:W|R|R +VBROADCASTI32X4 ; Vuv{K}{z},Mdq ; ; evex m:2 p:1 l:x w:0 0x5A /r:mem ; s:AVX512F, t:BROADCAST, a:NOL0, l:t4, e:E6, w:W|R|R +VBROADCASTI64X2 ; Vuv{K}{z},Mdq ; ; evex m:2 p:1 l:x w:1 0x5A /r:mem ; s:AVX512DQ, t:BROADCAST, a:NOL0, l:t2, e:E6, w:W|R|R +VBROADCASTI32X8 ; Voq{K}{z},Mqq ; ; evex m:2 p:1 l:2 w:0 0x5B /r:mem ; s:AVX512DQ, t:BROADCAST, l:t8, e:E6, w:W|R|R +VBROADCASTI64X4 ; Voq{K}{z},Mqq ; ; evex m:2 p:1 l:2 w:1 0x5B /r:mem ; s:AVX512F, t:BROADCAST, l:t4, e:E6, w:W|R|R # 0x60 - 0x6F -VPEXPANDB ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x62 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, e:E4, w:W|R|R -VPEXPANDW ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x62 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, e:E4, w:W|R|R -VPCOMPRESSB ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:0 0x63 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, a:NOMZ, e:E4, w:W|R|R -VPCOMPRESSW ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0x63 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, a:NOMZ, e:E4, w:W|R|R -VPBLENDMD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x64 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R -VPBLENDMQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x64 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R -VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R -VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R -VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R -VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R +VPEXPANDB ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:0 0x62 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, e:E4, w:W|R|R +VPEXPANDW ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:1 0x62 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, e:E4, w:W|R|R +VPCOMPRESSB ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:0 0x63 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s8, a:NOMZ, e:E4, w:W|R|R +VPCOMPRESSW ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:1 0x63 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:t1s16, a:NOMZ, e:E4, w:W|R|R +VPBLENDMD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x64 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VPBLENDMQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x64 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R +VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R +VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R -VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; n/a ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R -VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; n/a ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R +VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R +VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R # 0x70 - 0x7F -VPSHLDVW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x70 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R -VPSHLDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R -VPSHLDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R -VPSHRDVW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x72 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R -VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R -VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R -VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R -VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHLDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x70 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R +VPSHLDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHLDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHRDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x72 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R +VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R +VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R +VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R +VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R -VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R -VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R -VPERMI2D ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMI2Q ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMI2PS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x77 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMI2PD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x77 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPBROADCASTB ; Vfv{K}{z},Wb ; n/a ; evex m:2 p:1 l:x w:0 0x78 /r ; s:AVX512BW, t:BROADCAST, l:t1s8, e:E6, w:W|R|R -VPBROADCASTW ; Vfv{K}{z},Ww ; n/a ; evex m:2 p:1 l:x w:0 0x79 /r ; s:AVX512BW, t:BROADCAST, l:t1s16, e:E6, w:W|R|R -VPBROADCASTB ; Vfv{K}{z},Rb ; n/a ; evex m:2 p:1 l:x w:0 0x7A /r:reg ; s:AVX512BW, t:BROADCAST, l:t1s8, e:E7NM, w:W|R|R -VPBROADCASTW ; Vfv{K}{z},Rw ; n/a ; evex m:2 p:1 l:x w:0 0x7B /r:reg ; s:AVX512BW, t:BROADCAST, l:t1s16, e:E7NM, w:W|R|R -VPBROADCASTD ; Vfv{K}{z},Rd ; n/a ; evex m:2 p:1 l:x w:0 0x7C /r:reg ; s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64 -VPBROADCASTQ ; Vfv{K}{z},Rq ; n/a ; evex m:2 p:1 l:x w:1 0x7C /r:reg ; s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64 -VPERMT2B ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x7D /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R -VPERMT2W ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x7D /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R -VPERMT2D ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x7E /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMT2Q ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x7E /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMT2PS ; Vfv{K}{z},Hfv,Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R -VPERMT2PD ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMI2D ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2Q ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2PS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x77 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMI2PD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x77 /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPBROADCASTB ; Vfv{K}{z},Wb ; ; evex m:2 p:1 l:x w:0 0x78 /r ; s:AVX512BW, t:BROADCAST, l:t1s8, e:E6, w:W|R|R +VPBROADCASTW ; Vfv{K}{z},Ww ; ; evex m:2 p:1 l:x w:0 0x79 /r ; s:AVX512BW, t:BROADCAST, l:t1s16, e:E6, w:W|R|R +VPBROADCASTB ; Vfv{K}{z},Rb ; ; evex m:2 p:1 l:x w:0 0x7A /r:reg ; s:AVX512BW, t:BROADCAST, l:t1s8, e:E7NM, w:W|R|R +VPBROADCASTW ; Vfv{K}{z},Rw ; ; evex m:2 p:1 l:x w:0 0x7B /r:reg ; s:AVX512BW, t:BROADCAST, l:t1s16, e:E7NM, w:W|R|R +VPBROADCASTD ; Vfv{K}{z},Rd ; ; evex m:2 p:1 l:x w:0 0x7C /r:reg ; s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64 +VPBROADCASTQ ; Vfv{K}{z},Rq ; ; evex m:2 p:1 l:x w:1 0x7C /r:reg ; s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64 +VPERMT2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x7D /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMT2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x7D /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R +VPERMT2D ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x7E /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2Q ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x7E /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2PS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R +VPERMT2PD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R # 0x80 - 0x8F -VPMULTISHIFTQB ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0x83 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fv, e:E4NF, w:W|R|R|R -VEXPANDPS ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x88 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R -VEXPANDPD ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x88 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R -VPEXPANDD ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x89 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R -VPEXPANDQ ; Vfv{K}{z},Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x89 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R -VCOMPRESSPS ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:0 0x8A /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R -VCOMPRESSPD ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0x8A /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R -VPCOMPRESSD ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:0 0x8B /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R -VPCOMPRESSQ ; Wfv{K}{z},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0x8B /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R -VPERMB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x8D /r ; s:AVX512VBMI, t:AVX512VBMI, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R -VPERMW ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:1 0x8D /r ; s:AVX512BW, t:AVX512, l:fv, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R -VPSHUFBITQMB ; rK{K},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0x8F /r ; s:AVX512BITALG, t:AVX512VBMI, l:fvm, w:W|R|R|R +VPMULTISHIFTQB ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x83 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fv, e:E4NF, w:W|R|R|R +VEXPANDPS ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:0 0x88 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VEXPANDPD ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:1 0x88 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VPEXPANDD ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:0 0x89 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VPEXPANDQ ; Vfv{K}{z},Wfv ; ; evex m:2 p:1 l:x w:1 0x89 /r ; s:AVX512F, t:EXPAND, l:t1s, e:E4nb, w:W|R|R +VCOMPRESSPS ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:0 0x8A /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VCOMPRESSPD ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:1 0x8A /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPCOMPRESSD ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:0 0x8B /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPCOMPRESSQ ; Wfv{K}{z},Vfv ; ; evex m:2 p:1 l:x w:1 0x8B /r ; s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R +VPERMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x8D /r ; s:AVX512VBMI, t:AVX512VBMI, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R +VPERMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x8D /r ; s:AVX512BW, t:AVX512, l:fv, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R +VPSHUFBITQMB ; rK{K},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x8F /r ; s:AVX512BITALG, t:AVX512VBMI, l:fvm, w:W|R|R|R # 0x90 - 0x9F -VPGATHERDD ; Vfv{K},Mvm32n ; n/a ; evex m:2 p:1 l:x w:0 0x90 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPGATHERDQ ; Vfv{K},Mvm32h ; n/a ; evex m:2 p:1 l:x w:1 0x90 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPGATHERQD ; Vhv{K},Mvm64n ; n/a ; evex m:2 p:1 l:x w:0 0x91 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPGATHERQQ ; Vfv{K},Mvm64n ; n/a ; evex m:2 p:1 l:x w:1 0x91 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VGATHERDPS ; Vfv{K},Mvm32n ; n/a ; evex m:2 p:1 l:x w:0 0x92 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VGATHERDPD ; Vfv{K},Mvm32h ; n/a ; evex m:2 p:1 l:x w:1 0x92 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VGATHERQPS ; Vhv{K},Mvm64n ; n/a ; evex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VGATHERQPD ; Vfv{K},Mvm64n ; n/a ; evex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERDD ; Vfv{K},Mvm32n ; ; evex m:2 p:1 l:x w:0 0x90 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERDQ ; Vfv{K},Mvm32h ; ; evex m:2 p:1 l:x w:1 0x90 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERQD ; Vhv{K},Mvm64n ; ; evex m:2 p:1 l:x w:0 0x91 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPGATHERQQ ; Vfv{K},Mvm64n ; ; evex m:2 p:1 l:x w:1 0x91 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERDPS ; Vfv{K},Mvm32n ; ; evex m:2 p:1 l:x w:0 0x92 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERDPD ; Vfv{K},Mvm32h ; ; evex m:2 p:1 l:x w:1 0x92 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERQPS ; Vhv{K},Mvm64n ; ; evex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VGATHERQPD ; Vfv{K},Mvm64n ; ; evex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R -VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; n/a ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; n/a ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R -VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R +VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R +VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R # 0xA0 - 0xAF -VPSCATTERDD ; Mvm32n{K},Vfv ; n/a ; evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPSCATTERDQ ; Mvm32h{K},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPSCATTERQD ; Mvm64n{K},Vhv ; n/a ; evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VPSCATTERQQ ; Mvm64n{K},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERDPS ; Mvm32n{K},Vfv ; n/a ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERDPD ; Mvm32h{K},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERQPS ; Mvm64n{K},Vhv ; n/a ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VSCATTERQPD ; Mvm64n{K},Vfv ; n/a ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERDD ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERDQ ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERQD ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VPSCATTERQQ ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERDPS ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERDPD ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERQPS ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW +VSCATTERQPD ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW -VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; n/a ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; n/a ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R -VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R +VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R # 0xB0 - 0xBF -VPMADD52LUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0xB4 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R -VPMADD52HUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0xB5 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R -VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; n/a ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R -VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VPMADD52LUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB4 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R +VPMADD52HUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB5 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R +VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R +VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R +VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R # 0xC0 - 0xCF -VPCONFLICTD ; Vfv{K}{z},Wfv|B32 ; n/a ; evex m:2 p:1 l:x w:0 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R -VPCONFLICTQ ; Vfv{K}{z},Wfv|B64 ; n/a ; evex m:2 p:1 l:x w:1 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R -VGATHERPF0DPS ; Mvm32n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF0DPD ; Mvm32h{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF1DPS ; Mvm32n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF1DPD ; Mvm32h{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF0DPS ; Mvm32n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF0DPD ; Mvm32h{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF1DPS ; Mvm32n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF1DPD ; Mvm32h{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF0QPS ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF0QPD ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF1QPS ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VGATHERPF1QPD ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF0QPS ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF0QPD ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF1QPS ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VSCATTERPF1QPD ; Mvm64n{K} ; n/a ; evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VPCONFLICTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R +VPCONFLICTQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R +VGATHERPF0DPS ; Mvm32n{K} ; ; evex m:2 p:1 l:2 w:0 0xC6 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF0DPD ; Mvm32h{K} ; ; evex m:2 p:1 l:2 w:1 0xC6 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF1DPS ; Mvm32n{K} ; ; evex m:2 p:1 l:2 w:0 0xC6 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF1DPD ; Mvm32h{K} ; ; evex m:2 p:1 l:2 w:1 0xC6 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF0DPS ; Mvm32n{K} ; ; evex m:2 p:1 l:2 w:0 0xC6 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF0DPD ; Mvm32h{K} ; ; evex m:2 p:1 l:2 w:1 0xC6 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF1DPS ; Mvm32n{K} ; ; evex m:2 p:1 l:2 w:0 0xC6 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF1DPD ; Mvm32h{K} ; ; evex m:2 p:1 l:2 w:1 0xC6 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF0QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF0QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /1:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF1QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VGATHERPF1QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /2:mem vsib ; s:AVX512PF, t:GATHER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF0QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF0QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /5:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF1QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R +VSCATTERPF1QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R -VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; n/a ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; n/a ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; n/a ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; n/a ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; n/a ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; n/a ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; n/a ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R -VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; n/a ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; n/a ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R -VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R +VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R +VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R +VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R # 0xD0 - 0xDF -VAESENC ; Vfv,Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R -VAESENCLAST ; Vfv,Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R -VAESDEC ; Vfv,Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R -VAESDECLAST ; Vfv,Hfv,Wfv ; n/a ; evex m:2 p:1 l:x w:i 0xDF /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESENC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESENCLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESDEC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R +VAESDECLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDF /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R # 0xE0 - 0xEF -# 0xF0 - 0xFF + +# APX - AMX instructions +LDTILECFG ; Moq ; ; evex m:2 p:0 l:0 nf:0 w:0 0x49 /0:mem ; s:APX_F, t:AMX, w:R, m:NOTSX|O64, v:vex, e:AMX_EVEX_E1 +STTILECFG ; Moq ; ; evex m:2 p:1 l:0 nf:0 w:0 0x49 /0:mem ; s:APX_F, t:AMX, w:W, m:NOTSX|O64, v:vex, e:AMX_EVEX_E2 +TILELOADD ; rTt,Mt ; ; evex m:2 p:3 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem ; s:APX_F, t:AMX, w:W|R, m:NOTSX|O64, v:vex, e:AMX_EVEX_E3 +TILESTORED ; Mt,rTt ; ; evex m:2 p:2 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem ; s:APX_F, t:AMX, w:W|R, m:NOTSX|O64, v:vex, e:AMX_EVEX_E3 +TILELOADDT1 ; rTt,Mt ; ; evex m:2 p:1 l:0 nf:0 w:0 0x4B /r:mem rm:4 sibmem ; s:APX_F, t:AMX, w:W|R, m:NOTSX|O64, v:vex, e:AMX_EVEX_E3 + +# APX - CMPCC instructions +CMPOXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE0 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNOXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE1 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPCXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE2 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNCXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE3 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPZXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE4 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNZXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE5 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPBEXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE6 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNBEXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE7 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPSXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE8 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNSXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xE9 /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPPXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xEA /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNPXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xEB /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPLXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xEC /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNLXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xED /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPLEXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xEE /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD +CMPNLEXADD ; My,Gy,By ; Fv ; evex m:2 p:1 l:0 nf:0 0xEF /r:mem ; s:APX_F, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, v:vex, e:APX_EVEX_CMPCCXADD + +# APX - BMI instructions +ANDN ; Gy,By,Ey ; Fv ; evex m:2 p:0 l:0 nf:0 0xF2 /r ; s:APX_F, t:BMI1, w:W|R|R|W, v:vex, e:APX_EVEX_BMI, f:CF=0|PF=u|AF=u|ZF=m|SF=m|OF=0 +ANDN{NF} ; Gy,By,Ey ; ; evex m:2 p:0 l:0 nf:1 0xF2 /r ; s:APX_F, t:BMI1, w:W|R|R, v:vex, e:APX_EVEX_BMI +BLSI ; By,Ey ; Fv ; evex m:2 p:0 l:0 nf:0 0xF3 /3 ; s:APX_F, t:BMI1, w:W|R|W, v:vex, e:APX_EVEX_BMI, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0 +BLSI{NF} ; By,Ey ; ; evex m:2 p:0 l:0 nf:1 0xF3 /3 ; s:APX_F, t:BMI1, w:W|R, v:vex, e:APX_EVEX_BMI +BLSMSK ; By,Ey ; Fv ; evex m:2 p:0 l:0 nf:0 0xF3 /2 ; s:APX_F, t:BMI1, w:W|R|W, v:vex, e:APX_EVEX_BMI, f:CF=m|PF=u|AF=u|ZF=0|SF=m|OF=0 +BLSMSK{NF} ; By,Ey ; ; evex m:2 p:0 l:0 nf:1 0xF3 /2 ; s:APX_F, t:BMI1, w:W|R, v:vex, e:APX_EVEX_BMI +BLSR ; By,Ey ; Fv ; evex m:2 p:0 l:0 nf:0 0xF3 /1 ; s:APX_F, t:BMI1, w:W|R|W, v:vex, e:APX_EVEX_BMI, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0 +BLSR{NF} ; By,Ey ; ; evex m:2 p:0 l:0 nf:1 0xF3 /1 ; s:APX_F, t:BMI1, w:W|R, v:vex, e:APX_EVEX_BMI +BZHI ; Gy,Ey,By ; Fv ; evex m:2 p:0 l:0 nf:0 0xF5 /r ; s:APX_F, t:BMI2, w:W|R|R|W, v:vex, e:APX_EVEX_BMI, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0 +BZHI{NF} ; Gy,Ey,By ; ; evex m:2 p:0 l:0 nf:1 0xF5 /r ; s:APX_F, t:BMI2, w:W|R|R, v:vex, e:APX_EVEX_BMI +PEXT ; Gy,By,Ey ; ; evex m:2 p:2 l:0 nf:0 0xF5 /r ; s:APX_F, t:BMI2, w:W|R|R|W, v:vex, e:APX_EVEX_BMI +PDEP ; Gy,By,Ey ; ; evex m:2 p:3 l:0 nf:0 0xF5 /r ; s:APX_F, t:BMI2, w:W|R|R|W, v:vex, e:APX_EVEX_BMI +MULX ; Gy,By,Ey ; yDX ; evex m:2 p:3 l:0 nf:0 0xF6 /r ; s:APX_F, t:BMI2, w:W|W|R|R, v:vex, e:APX_EVEX_BMI +BEXTR ; Gy,Ey,By ; Fv ; evex m:2 p:0 l:0 nf:0 0xF7 /r ; s:APX_F, t:BMI1, w:W|R|R|W, v:vex, e:APX_EVEX_BMI, f:CF=0|PF=u|AF=u|ZF=m|SF=u|OF=0 +BEXTR{NF} ; Gy,Ey,By ; ; evex m:2 p:0 l:0 nf:1 0xF7 /r ; s:APX_F, t:BMI1, w:W|R|R, v:vex, e:APX_EVEX_BMI +SHLX ; Gy,Ey,By ; ; evex m:2 p:1 l:0 nf:0 0xF7 /r ; s:APX_F, t:BMI2, w:W|R|R, v:vex, e:APX_EVEX_BMI +SARX ; Gy,Ey,By ; ; evex m:2 p:2 l:0 nf:0 0xF7 /r ; s:APX_F, t:BMI2, w:W|R|R, v:vex, e:APX_EVEX_BMI +SHRX ; Gy,Ey,By ; ; evex m:2 p:3 l:0 nf:0 0xF7 /r ; s:APX_F, t:BMI2, w:W|R|R, v:vex, e:APX_EVEX_BMI diff --git a/isagenerator/instructions/table_evex3.dat b/isagenerator/instructions/table_evex_3.dat similarity index 57% rename from isagenerator/instructions/table_evex3.dat rename to isagenerator/instructions/table_evex_3.dat index 50b4349..926e21e 100644 --- a/isagenerator/instructions/table_evex3.dat +++ b/isagenerator/instructions/table_evex_3.dat @@ -4,114 +4,114 @@ # # 0x00 - 0x0F -VPERMQ ; Vuv{K}{z},Wuv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x00 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R -VPERMPD ; Vuv{K}{z},Wuv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x01 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R -VALIGND ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R -VALIGNQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R -VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R -VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; n/a ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; n/a ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; n/a ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; n/a ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; n/a ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VPALIGNR ; Vfv{K}{z},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R +VPERMQ ; Vuv{K}{z},Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x00 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VPERMPD ; Vuv{K}{z},Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x01 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R +VALIGND ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VALIGNQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R +VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R +VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VPALIGNR ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R # 0x10 - 0x1F -VPEXTRB ; Mb,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x14 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R -VPEXTRB ; Ry,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x14 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R, a:D64 -VPEXTRW ; Mw,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x15 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R -VPEXTRW ; Ry,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x15 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R, a:D64 -VPEXTRD ; Md,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:0 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 -VPEXTRD ; Ry,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:0 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64|D64 -VPEXTRQ ; Mq,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:1 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 -VPEXTRQ ; Ry,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:1 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 -VEXTRACTPS ; Md,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x17 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R -VEXTRACTPS ; Ry,Vdq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R -VINSERTF32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x18 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R -VINSERTF64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x18 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R -VEXTRACTF32X4 ; Wdq{K}{z},Vuv,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x19 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R -VEXTRACTF64X2 ; Wdq{K}{z},Vuv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x19 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R -VINSERTF32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; n/a ; evex m:3 p:1 l:2 w:0 0x1A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R -VINSERTF64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; n/a ; evex m:3 p:1 l:2 w:1 0x1A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R -VEXTRACTF32X8 ; Wqq{K}{z},Voq,Ib ; n/a ; evex m:3 p:1 l:2 w:0 0x1B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R -VEXTRACTF64X4 ; Wqq{K}{z},Voq,Ib ; n/a ; evex m:3 p:1 l:2 w:1 0x1B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R -VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R -VPCMPUD ; rKq{K},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R -VPCMPUQ ; rKq{K},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R -VPCMPD ; rKq{K},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R -VPCMPQ ; rKq{K},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPEXTRB ; Mb,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x14 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R +VPEXTRB ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x14 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R, a:D64 +VPEXTRW ; Mw,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x15 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R +VPEXTRW ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x15 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R, a:D64 +VPEXTRD ; Md,Vdq,Ib ; ; evex m:3 p:1 l:0 w:0 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VPEXTRD ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:0 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64|D64 +VPEXTRQ ; Mq,Vdq,Ib ; ; evex m:3 p:1 l:0 w:1 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VPEXTRQ ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:1 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64 +VEXTRACTPS ; Md,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x17 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VEXTRACTPS ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R +VINSERTF32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x18 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R +VINSERTF64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:1 0x18 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R +VEXTRACTF32X4 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:0 0x19 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R +VEXTRACTF64X2 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:1 0x19 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R +VINSERTF32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R +VINSERTF64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R +VEXTRACTF32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R +VEXTRACTF64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R +VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R +VPCMPUD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPUQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R +VPCMPQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R # 0x20 - 0x2F -VPINSRB ; Vdq,Hdq,Mb,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R -VPINSRB ; Vdq,Hdq,Rd,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x20 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R -VINSERTPS ; Vdq,Hdq,Md,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x21 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R -VINSERTPS ; Vdq,Hdq,Udq,Ib ; n/a ; evex m:3 p:1 l:0 w:i 0x21 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R -VPINSRD ; Vdq,Hdq,Ed,Ib ; n/a ; evex m:3 p:1 l:0 w:0 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64 -VPINSRQ ; Vdq,Hdq,Eq,Ib ; n/a ; evex m:3 p:1 l:0 w:1 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64 -VSHUFF32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R -VSHUFF64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R -VPTERNLOGD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R -VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R -VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; n/a ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; n/a ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R -VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; n/a ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; n/a ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R -VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; n/a ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R +VPINSRB ; Vdq,Hdq,Mb,Ib ; ; evex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R +VPINSRB ; Vdq,Hdq,Rd,Ib ; ; evex m:3 p:1 l:0 w:i 0x20 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R +VINSERTPS ; Vdq,Hdq,Md,Ib ; ; evex m:3 p:1 l:0 w:i 0x21 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VINSERTPS ; Vdq,Hdq,Udq,Ib ; ; evex m:3 p:1 l:0 w:i 0x21 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R +VPINSRD ; Vdq,Hdq,Ed,Ib ; ; evex m:3 p:1 l:0 w:0 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64 +VPINSRQ ; Vdq,Hdq,Eq,Ib ; ; evex m:3 p:1 l:0 w:1 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64 +VSHUFF32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFF64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VPTERNLOGD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R +VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R +VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R +VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R +VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R # 0x30 - 0x3F -VINSERTI32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x38 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R -VINSERTI64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x38 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R -VEXTRACTI32X4 ; Wdq{K}{z},Vuv,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x39 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R -VEXTRACTI64X2 ; Wdq{K}{z},Vuv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x39 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R -VINSERTI32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; n/a ; evex m:3 p:1 l:2 w:0 0x3A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R -VINSERTI64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; n/a ; evex m:3 p:1 l:2 w:1 0x3A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R -VEXTRACTI32X8 ; Wqq{K}{z},Voq,Ib ; n/a ; evex m:3 p:1 l:2 w:0 0x3B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R -VEXTRACTI64X4 ; Wqq{K}{z},Voq,Ib ; n/a ; evex m:3 p:1 l:2 w:1 0x3B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R -VPCMPUB ; rKq{K},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R -VPCMPUW ; rKq{K},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R -VPCMPB ; rKq{K},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R -VPCMPW ; rKq{K},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VINSERTI32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x38 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R +VINSERTI64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:1 0x38 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R +VEXTRACTI32X4 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:0 0x39 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R +VEXTRACTI64X2 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:1 0x39 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R +VINSERTI32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0 0x3A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R +VINSERTI64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x3A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R +VEXTRACTI32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x3B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R +VEXTRACTI64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x3B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R +VPCMPUB ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPUW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPB ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R +VPCMPW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R # 0x40 - 0x4F -VDBPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x42 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R -VSHUFI32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R -VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R -VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R +VDBPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x42 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R +VSHUFI32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R +VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R # 0x50 - 0x5F -VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; n/a ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R -VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; n/a ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; n/a ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R -VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; n/a ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R -VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; n/a ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R -VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; n/a ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R -VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; n/a ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; n/a ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R -VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; n/a ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R -VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; n/a ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; n/a ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R -VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; n/a ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R +VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R +VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R +VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R +VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R +VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R +VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R +VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R # 0x60 - 0x6F -VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; n/a ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R -VFPCLASSPS ; rKq{K},Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R -VFPCLASSPD ; rKq{K},Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R -VFPCLASSSH ; rKq{K},Wsh,Ib ; n/a ; evex m:3 p:0 l:i w:0 0x67 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R -VFPCLASSSS ; rKq{K},Wss,Ib ; n/a ; evex m:3 p:1 l:i w:0 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R -VFPCLASSSD ; rKq{K},Wsd,Ib ; n/a ; evex m:3 p:1 l:i w:1 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R +VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R +VFPCLASSPS ; rKq{K},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VFPCLASSPD ; rKq{K},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R +VFPCLASSSH ; rKq{K},Wsh,Ib ; ; evex m:3 p:0 l:i w:0 0x67 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R +VFPCLASSSS ; rKq{K},Wss,Ib ; ; evex m:3 p:1 l:i w:0 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R +VFPCLASSSD ; rKq{K},Wsd,Ib ; ; evex m:3 p:1 l:i w:1 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R # 0x70 - 0x7F -VPSHLDW ; Vfv{K}{z},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x70 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R -VPSHLDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R -VPSHLDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R -VPSHRDW ; Vfv{K}{z},Hfv,Wfv,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x72 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R -VPSHRDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; n/a ; evex m:3 p:1 l:x w:0 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R -VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHLDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x70 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R +VPSHLDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHLDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHRDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x72 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R +VPSHRDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R +VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R # 0x80 - 0x8F @@ -122,14 +122,18 @@ VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; n/a ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R -VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; n/a ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R +VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R +VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R -VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R -VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; n/a ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R +VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R +VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R # 0xD0 - 0xDF # 0xE0 - 0xEF # 0xF0 - 0xFF + + +# APX - RORX +RORX ; Gy,Ey,Ib ; ; evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib ; s:APX_F, t:BMI2, w:W|R|R, e:APX_EVEX_BMI, v:vex diff --git a/isagenerator/instructions/table_evex_4.dat b/isagenerator/instructions/table_evex_4.dat new file mode 100644 index 0000000..b0e04eb --- /dev/null +++ b/isagenerator/instructions/table_evex_4.dat @@ -0,0 +1,1342 @@ +# +# Copyright (c) 2024 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +# ADD +ADD ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x00 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x01 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x01 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x02 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x03 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x03 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /0 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /0 iz ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /0 iz ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /0 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /0 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{NF} ; Eb,Gb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x00 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +ADD{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x01 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x01 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Gb,Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x02 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +ADD{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x03 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x03 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x80 /0 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +ADD{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x81 /0 iz ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x81 /0 iz ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x83 /0 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x83 /0 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x00 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x01 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x01 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x02 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x03 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x03 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /0 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +ADD{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /0 iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /0 iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /0 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /0 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +ADD{ND}{NF} ; Bb,Eb,Gb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x00 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +ADD{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x01 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x01 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bb,Gb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x02 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +ADD{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x03 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x03 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x80 /0 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +ADD{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x81 /0 iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x81 /0 iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x83 /0 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ADD{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x83 /0 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SUB +SUB ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x28 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x29 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x29 /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x2A /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x2B /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x2B /r ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /5 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /5 iz ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /5 iz ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /5 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /5 ib ; s:APX_F, t:ARITH, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{NF} ; Eb,Gb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x28 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +SUB{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x29 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x29 /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Gb,Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x2A /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +SUB{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x2B /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x2B /r ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x80 /5 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT +SUB{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x81 /5 iz ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x81 /5 iz ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x83 /5 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x83 /5 ib ; s:APX_F, t:ARITH, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x28 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x29 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x29 /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x2A /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x2B /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x2B /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /5 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +SUB{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /5 iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /5 iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /5 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /5 ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH, a:SCALABLE +SUB{ND}{NF} ; Bb,Eb,Gb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x28 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +SUB{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x29 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x29 /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bb,Gb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x2A /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +SUB{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x2B /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x2B /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x80 /5 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT +SUB{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x81 /5 iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x81 /5 iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x83 /5 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SUB{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x83 /5 ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# AND +AND ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x20 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x21 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x21 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x22 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x23 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x23 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /4 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /4 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /4 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /4 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /4 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{NF} ; Eb,Gb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x20 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +AND{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x21 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x21 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Gb,Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x22 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +AND{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x23 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x23 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x80 /4 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +AND{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x81 /4 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x81 /4 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x83 /4 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x83 /4 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x20 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x21 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x21 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x22 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x23 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x23 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +AND{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /4 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /4 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +AND{ND}{NF} ; Bb,Eb,Gb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x20 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +AND{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x21 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x21 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bb,Gb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x22 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +AND{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x23 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x23 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x80 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +AND{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x81 /4 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x81 /4 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x83 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +AND{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x83 /4 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# OR +OR ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x08 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x09 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x09 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x0A /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x0B /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x0B /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /1 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /1 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /1 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /1 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /1 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{NF} ; Eb,Gb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x08 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +OR{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x09 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x09 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Gb,Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x0A /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +OR{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x0B /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x0B /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x80 /1 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +OR{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x81 /1 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x81 /1 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x83 /1 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x83 /1 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x08 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x09 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x09 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x0A /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x0B /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x0B /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +OR{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /1 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /1 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +OR{ND}{NF} ; Bb,Eb,Gb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x08 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +OR{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x09 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x09 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bb,Gb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x0A /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +OR{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x0B /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x0B /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x80 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +OR{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x81 /1 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x81 /1 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x83 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +OR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x83 /1 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# XOR +XOR ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x30 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x31 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x31 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x32 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x33 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x33 /r ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /6 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /6 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /6 iz ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /6 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /6 ib ; s:APX_F, t:LOGIC, w:RW|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{NF} ; Eb,Gb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x30 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +XOR{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x31 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x31 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Gb,Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x32 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +XOR{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x33 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x33 /r ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x80 /6 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT +XOR{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x81 /6 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x81 /6 iz ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x83 /6 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x83 /6 ib ; s:APX_F, t:LOGIC, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x30 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x31 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x31 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x32 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x33 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x33 /r ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC +XOR{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /6 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /6 iz ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, f:LOGIC, a:SCALABLE +XOR{ND}{NF} ; Bb,Eb,Gb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x30 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +XOR{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x31 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bv,Ev,Gv ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x31 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bb,Gb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x32 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +XOR{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x33 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x33 /r ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x80 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT +XOR{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x81 /6 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x81 /6 iz ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x83 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +XOR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x83 /6 ib ; s:APX_F, t:LOGIC, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# ADC +ADC ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x10 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x11 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x11 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x12 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x13 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x13 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /2 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /2 iz ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /2 iz ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /2 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /2 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x10 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x11 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x11 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x12 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x13 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x13 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /2 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +ADC{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /2 iz ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /2 iz ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /2 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +ADC{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /2 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE + + +# SBB +SBB ; Eb,Gb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x18 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x19 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Ev,Gv ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x19 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Gb,Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x1A /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x1B /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x1B /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x80 /3 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x81 /3 iz ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x81 /3 iz ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x83 /3 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x83 /3 ib ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bb,Eb,Gb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x18 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x19 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bv,Ev,Gv ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x19 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bb,Gb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x1A /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x1B /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x1B /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x80 /3 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC +SBB{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x81 /3 iz ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x81 /3 iz ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x83 /3 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE +SBB{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x83 /3 ib ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ARITHC, a:SCALABLE + + +# ROL +ROL ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /0 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /0 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /0 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /0 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /0 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROL{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /0 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /0 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# ROR +ROR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /1 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /1 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /1 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +ROR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /1 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT +ROR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /1 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROT, a:SCALABLE +ROR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /1 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +ROR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +ROR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /1 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# RCL +RCL ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /2 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /2 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /2 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /2 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /2 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCL{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /2 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /2 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# RCR +RCR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /3 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /3 ; s:APX_F, t:ROTATE, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /3 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT +RCR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /3 ; s:APX_F, t:ROTATE, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC +RCR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /3 ; s:APX_F, t:ROTATE, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:ROTC, a:SCALABLE +RCR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /3 ib ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT +RCR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +RCR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /3 ; s:APX_F, t:ROTATE, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SHL +SHL ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /4 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /4 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /4 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /4 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /4 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHL{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /4 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /4 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SHR +SHR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /5 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /5 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /5 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SHR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /5 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SHR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /5 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SHR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /5 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SHR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /5 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SAL +SAL ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /6 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /6 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /6 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /6 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /6 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAL{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /6 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAL{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /6 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SAR +SAR ; Eb,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC0 /7 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR ; Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR ; Eb,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD0 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD1 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR ; Ev,1 ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD1 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR ; Eb,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD2 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xD3 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR ; Ev,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xD3 /7 ; s:APX_F, t:SHIFT, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{NF} ; Eb,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC0 /7 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{NF} ; Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{NF} ; Eb,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD0 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD1 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{NF} ; Ev,1 ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD1 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{NF} ; Eb,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD2 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT +SAR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xD3 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{NF} ; Ev,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xD3 /7 ; s:APX_F, t:SHIFT, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND} ; Bb,Eb,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC0 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND} ; Bv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND} ; Bb,Eb,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD0 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD1 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND} ; Bv,Ev,1 ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD1 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND} ; Bb,Eb,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD2 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT +SAR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xD3 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND} ; Bv,Ev,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xD3 /7 ; s:APX_F, t:SHIFT, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:SHIFT, a:SCALABLE +SAR{ND}{NF} ; Bb,Eb,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC0 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND}{NF} ; Bv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xC1 /7 ib ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND}{NF} ; Bb,Eb,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD0 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD1 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND}{NF} ; Bv,Ev,1 ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD1 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND}{NF} ; Bb,Eb,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD2 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT +SAR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xD3 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SAR{ND}{NF} ; Bv,Ev,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xD3 /7 ; s:APX_F, t:SHIFT, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SHLD +SHLD ; Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x24 /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD ; Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xA5 /r ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD ; Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x24 /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD ; Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xA5 /r ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD{NF} ; Ev,Gv,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x24 /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{NF} ; Ev,Gv,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xA5 /r ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{NF} ; Ev,Gv,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x24 /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{NF} ; Ev,Gv,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xA5 /r ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{ND} ; Bv,Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x24 /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD{ND} ; Bv,Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xA5 /r ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD{ND} ; Bv,Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x24 /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD{ND} ; Bv,Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xA5 /r ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHLD{ND}{NF} ; Bv,Ev,Gv,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x24 /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{ND}{NF} ; Bv,Ev,Gv,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xA5 /r ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{ND}{NF} ; Bv,Ev,Gv,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x24 /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHLD{ND}{NF} ; Bv,Ev,Gv,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xA5 /r ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# SHRD +SHRD ; Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x2C /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD ; Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xAD /r ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD ; Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x2C /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD ; Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xAD /r ; s:APX_F, t:SHIFT, w:RCW|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD{NF} ; Ev,Gv,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x2C /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{NF} ; Ev,Gv,CL ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xAD /r ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{NF} ; Ev,Gv,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x2C /r ib ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{NF} ; Ev,Gv,CL ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xAD /r ; s:APX_F, t:SHIFT, w:RCW|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{ND} ; Bv,Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x2C /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD{ND} ; Bv,Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xAD /r ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD{ND} ; Bv,Ev,Gv,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x2C /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD{ND} ; Bv,Ev,Gv,CL ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xAD /r ; s:APX_F, t:SHIFT, w:W|R|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:SHIFTD +SHRD{ND}{NF} ; Bv,Ev,Gv,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x2C /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{ND}{NF} ; Bv,Ev,Gv,CL ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xAD /r ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{ND}{NF} ; Bv,Ev,Gv,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x2C /r ib ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +SHRD{ND}{NF} ; Bv,Ev,Gv,CL ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xAD /r ; s:APX_F, t:SHIFT, w:W|R|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# Misc +ADCX ; Gy,Ey ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x66 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:CF=t|CF=m +ADCX{ND} ; By,Gy,Ey ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x66 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:CF=t|CF=m +ADOX ; Gy,Ey ; Fv ; evex m:4 l:0 nd:0 nf:0 p:2 0x66 /r ; s:APX_F, t:ARITH, w:RW|R|RW, v:legacy, e:APX_EVEX_INT, f:CF=m +ADOX{ND} ; By,Gy,Ey ; Fv ; evex m:4 l:0 nd:1 nf:0 p:2 0x66 /r ; s:APX_F, t:ARITH, w:W|R|R|RW, v:legacy, e:APX_EVEX_INT, f:CF=m +CRC32 ; Gy,Eb ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xF0 /r ; s:APX_F, t:APX, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +CRC32 ; Gy,Ev ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xF1 /r ; s:APX_F, t:APX, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +CRC32 ; Gy,Ev ; ; evex m:4 l:0 nd:0 nf:0 p:1 0xF1 /r ; s:APX_F, t:APX, w:RW|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +MOVBE ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:0 p:0 0x60 /r ; s:APX_F, t:DATAXFER, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +MOVBE ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:0 p:1 0x60 /r ; s:APX_F, t:DATAXFER, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +MOVBE ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:0 p:0 0x61 /r ; s:APX_F, t:DATAXFER, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +MOVBE ; Ev,Gv ; ; evex m:4 l:0 nd:0 nf:0 p:1 0x61 /r ; s:APX_F, t:DATAXFER, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +POPCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x88 /r ; s:APX_F, t:APX, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +POPCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x88 /r ; s:APX_F, t:APX, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +POPCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x88 /r ; s:APX_F, t:APX, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +POPCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x88 /r ; s:APX_F, t:APX, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# LZCNT/TZCNT +TZCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF4 /r ; s:APX_F, t:BMI1, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +TZCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF4 /r ; s:APX_F, t:BMI1, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +TZCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xF4 /r ; s:APX_F, t:BMI1, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +TZCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xF4 /r ; s:APX_F, t:BMI1, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +LZCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF5 /r ; s:APX_F, t:LZCNT, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +LZCNT ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF5 /r ; s:APX_F, t:LZCNT, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +LZCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xF5 /r ; s:APX_F, t:LZCNT, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +LZCNT{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xF5 /r ; s:APX_F, t:LZCNT, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# MUL/IMUL +MUL ; Eb ; AL,AX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /4 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT, f:MUL +MUL ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /4 ; s:APX_F, t:ARITH, w:R|RW|W|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +MUL ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /4 ; s:APX_F, t:ARITH, w:R|RW|W|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +MUL{NF} ; Eb ; AL,AX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /4 ; s:APX_F, t:ARITH, w:R|R|W, v:legacy, e:APX_EVEX_INT +MUL{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /4 ; s:APX_F, t:ARITH, w:R|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE +MUL{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /4 ; s:APX_F, t:ARITH, w:R|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL ; Gv,Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Gv,Ev,Iz ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Gv,Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Gv,Ev,Ib ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{NF} ; Gv,Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Gv,Ev,Iz ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Gv,Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:0 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Gv,Ev,Ib ; ; evex m:4 l:0 nd:0 nf:1 p:1 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ZU} ; Gv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ZU} ; Gv,Ev,Iz ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ZU} ; Gv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ZU} ; Gv,Ev,Ib ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ZU}{NF} ; Gv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ZU}{NF} ; Gv,Ev,Iz ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x69 /r iz ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ZU}{NF} ; Gv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:0 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ZU}{NF} ; Gv,Ev,Ib ; ; evex m:4 l:0 nd:1 nf:1 p:1 0x6B /r ib ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xAF /r ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Gv,Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xAF /r ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Eb ; AL,AX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /5 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT, f:MUL +IMUL ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /5 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /5 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xAF /r ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Gv,Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xAF /r ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Eb ; AL,AX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /5 ; s:APX_F, t:ARITH, w:R|R|W, v:legacy, e:APX_EVEX_INT +IMUL{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /5 ; s:APX_F, t:ARITH, w:R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /5 ; s:APX_F, t:ARITH, w:R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xAF /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xAF /r ; s:APX_F, t:ARITH, w:W|R|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:MUL +IMUL{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xAF /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IMUL{ND}{NF} ; Bv,Gv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xAF /r ; s:APX_F, t:ARITH, w:W|R|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# DIV/IDIV +DIV ; Eb ; AX,AL,AH,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /6 ; s:APX_F, t:ARITH, w:R|R|W|W|W, v:legacy, e:APX_EVEX_INT, f:DIV +DIV ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /6 ; s:APX_F, t:ARITH, w:R|RW|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:DIV +DIV ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /6 ; s:APX_F, t:ARITH, w:R|RW|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:DIV +DIV{NF} ; Eb ; AX,AL,AH ; evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /6 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT +DIV{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /6 ; s:APX_F, t:ARITH, w:R|RW|RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +DIV{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /6 ; s:APX_F, t:ARITH, w:R|RW|RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IDIV ; Eb ; AX,AL,AH,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /7 ; s:APX_F, t:ARITH, w:R|R|W|W|W, v:legacy, e:APX_EVEX_INT, f:DIV +IDIV ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /7 ; s:APX_F, t:ARITH, w:R|RW|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:DIV +IDIV ; Ev ; rAX,rDX,Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /7 ; s:APX_F, t:ARITH, w:R|RW|RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:DIV +IDIV{NF} ; Eb ; AX,AL,AH ; evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /7 ; s:APX_F, t:ARITH, w:R|R|W|W, v:legacy, e:APX_EVEX_INT +IDIV{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /7 ; s:APX_F, t:ARITH, w:R|RW|RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +IDIV{NF} ; Ev ; rAX,rDX ; evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /7 ; s:APX_F, t:ARITH, w:R|RW|RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# INC/DEC +INC ; Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xFE /0 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC +INC ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xFF /0 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +INC ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xFF /0 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +INC{NF} ; Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xFE /0 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT +INC{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xFF /0 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +INC{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xFF /0 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +INC{ND} ; Bb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xFE /0 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC +INC{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xFF /0 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +INC{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xFF /0 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +INC{ND}{NF} ; Bb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xFE /0 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT +INC{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xFF /0 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +INC{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xFF /0 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +DEC ; Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xFE /1 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC +DEC ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xFF /1 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +DEC ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xFF /1 ; s:APX_F, t:ARITH, w:RW|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +DEC{NF} ; Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xFE /1 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT +DEC{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xFF /1 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +DEC{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xFF /1 ; s:APX_F, t:ARITH, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +DEC{ND} ; Bb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xFE /1 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC +DEC{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xFF /1 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +DEC{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xFF /1 ; s:APX_F, t:ARITH, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:INCDEC, a:SCALABLE +DEC{ND}{NF} ; Bb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xFE /1 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT +DEC{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xFF /1 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +DEC{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xFF /1 ; s:APX_F, t:ARITH, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# NOT/NEG +NOT ; Eb ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /2 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT +NOT ; Ev ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /2 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NOT ; Ev ; ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /2 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NOT{ND} ; Bb,Eb ; ; evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /2 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT +NOT{ND} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /2 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NOT{ND} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /2 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NEG ; Eb ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF6 /3 ; s:APX_F, t:LOGIC, w:RW|W, v:legacy, e:APX_EVEX_INT, f:ARITH +NEG ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:0 0xF7 /3 ; s:APX_F, t:LOGIC, w:RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:ARITH +NEG ; Ev ; Fv ; evex m:4 l:0 nd:0 nf:0 p:1 0xF7 /3 ; s:APX_F, t:LOGIC, w:RW|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:ARITH +NEG{NF} ; Eb ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xF6 /3 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT +NEG{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:0 0xF7 /3 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NEG{NF} ; Ev ; ; evex m:4 l:0 nd:0 nf:1 p:1 0xF7 /3 ; s:APX_F, t:LOGIC, w:RW, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NEG{ND} ; Bb,Eb ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xF6 /3 ; s:APX_F, t:LOGIC, w:W|R|W, v:legacy, e:APX_EVEX_INT, f:ARITH +NEG{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:0 0xF7 /3 ; s:APX_F, t:LOGIC, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:ARITH +NEG{ND} ; Bv,Ev ; Fv ; evex m:4 l:0 nd:1 nf:0 p:1 0xF7 /3 ; s:APX_F, t:LOGIC, w:W|R|W, v:legacy, e:APX_EVEX_INT, a:SCALABLE, f:ARITH +NEG{ND}{NF} ; Bb,Eb ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xF6 /3 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT +NEG{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:0 0xF7 /3 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE +NEG{ND}{NF} ; Bv,Ev ; ; evex m:4 l:0 nd:1 nf:1 p:1 0xF7 /3 ; s:APX_F, t:LOGIC, w:W|R, v:legacy, e:APX_EVEX_INT, a:SCALABLE + + +# PUSH2/POP2 instructions. +POP2 ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:0 0x8F /0:reg ; s:APX_F, t:POP, w:W|W|R, v:legacy, e:APX_EVEX_PP2, a:D64 +POP2P ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:1 0x8F /0:reg ; s:APX_F, t:POP, w:W|W|R, v:legacy, e:APX_EVEX_PP2, a:D64 +PUSH2 ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:0 0xFF /6:reg ; s:APX_F, t:PUSH, w:R|R|W, v:legacy, e:APX_EVEX_PP2, a:D64 +PUSH2P ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg ; s:APX_F, t:PUSH, w:R|R|W, v:legacy, e:APX_EVEX_PP2, a:D64 + + +# AES instructions. +ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg ; s:APX_F, t:AESKL, w:W|R|R|W|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy +ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg ; s:APX_F, t:AESKL, w:W|R|RW|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy +AESDEC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESDEC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESENC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy +AESENC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy + + +# SHA instructions. +SHA1RNDS4 ; Vdq,Wdq,Ib ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy +SHA1NEXTE ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +SHA1MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +SHA1MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +SHA256MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +SHA256MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy +SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy + + +# INVEPT, INVPCID, INVVPID +INVEPT ; Gy,Mdq ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xF0 /r:mem ; s:APX_F, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT, v:legacy, e:APX_EVEX_INVEPT +INVVPID ; Gy,Mdq ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xF1 /r:mem ; s:APX_F, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL, m:VMXROOT, v:legacy, e:APX_EVEX_INVVPID +INVPCID ; Gy,Mdq ; ; evex m:4 l:0 p:2 nd:0 nf:0 0xF2 /r:mem ; s:APX_F, t:MISC, w:R|R, a:F64, m:KERNEL|NOV86, v:legacy, e:APX_EVEX_INVPCID + + +# ENQCMD, ENQCMDS +ENQCMDS ; rM?,Moq ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xF8 /r:mem ; s:APX_F, t:ENQCMD, w:W|R|W, f:ENQCMD, v:legacy, e:APX_EVEX_ENQCMD +ENQCMD ; rM?,Moq ; Fv ; evex m:4 l:0 p:3 nd:0 nf:0 0xF8 /r:mem ; s:APX_F, t:ENQCMD, w:W|R|W, f:ENQCMD, v:legacy, e:APX_EVEX_ENQCMD + + +# MOVDIR +MOVDIR64B ; rMoq,Moq ; ; evex m:4 l:0 nd:0 nf:0 p:1 0xF8 /r:mem ; s:APX_F, t:MOVDIR64B, w:W|R, e:APX_EVEX_INT, v:legacy +UWRMSR ; Gq,Eq ; ; evex m:4 l:0 nd:0 nf:0 p:2 w:0 0xF8 /r:reg ; s:APX_F, t:USER_MSR, w:R|R, e:APX_EVEX_USER_MSR, v:legacy +URDMSR ; Eq,Gq ; ; evex m:4 l:0 nd:0 nf:0 p:3 w:0 0xF8 /r:reg ; s:APX_F, t:USER_MSR, w:W|R, e:APX_EVEX_USER_MSR, v:legacy +MOVDIRI ; My,Gy ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xF9 /r:mem ; s:APX_F, t:MOVDIRI, w:W|R, e:APX_EVEX_INT, v:legacy + + +# CET SS +WRUSSD ; My,Gy ; ; evex m:4 l:0 p:1 w:0 nd:0 nf:0 0x65 /r:mem ; s:APX_F, t:CET, c:WRUSS, a:SHS, w:W|R, v:legacy, e:APX_EVEX_WRUSS, m:KERNEL +WRUSSQ ; My,Gy ; ; evex m:4 l:0 p:1 w:1 nd:0 nf:0 0x65 /r:mem ; s:APX_F, t:CET, c:WRUSS, a:SHS, w:W|R, v:legacy, e:APX_EVEX_WRUSS, m:KERNEL +WRSSD ; My,Gy ; ; evex m:4 l:0 p:0 w:0 nd:0 nf:0 0x66 /r:mem ; s:APX_F, t:CET, c:WRSS, a:SHS, w:W|R, v:legacy, e:APX_EVEX_WRSS +WRSSQ ; My,Gy ; ; evex m:4 l:0 p:0 w:1 nd:0 nf:0 0x66 /r:mem ; s:APX_F, t:CET, c:WRSS, a:SHS, w:W|R, v:legacy, e:APX_EVEX_WRSS + + +# RAO-INT +AADD ; My,Gy ; ; evex m:4 l:0 nd:0 nf:0 p:0 0xFC /r:mem ; s:APX_F, t:RAOINT, w:RW|R, v:legacy, e:APX_EVEX_RAOINT +AAND ; My,Gy ; ; evex m:4 l:0 nd:0 nf:0 p:1 0xFC /r:mem ; s:APX_F, t:RAOINT, w:RW|R, v:legacy, e:APX_EVEX_RAOINT +AXOR ; My,Gy ; ; evex m:4 l:0 nd:0 nf:0 p:2 0xFC /r:mem ; s:APX_F, t:RAOINT, w:RW|R, v:legacy, e:APX_EVEX_RAOINT +AOR ; My,Gy ; ; evex m:4 l:0 nd:0 nf:0 p:3 0xFC /r:mem ; s:APX_F, t:RAOINT, w:RW|R, v:legacy, e:APX_EVEX_RAOINT + + +# CCMPSCC +CCMPO ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CCMPO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CCMPO ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CCMPO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPO ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CCMPNO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CCMPNO ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CCMPNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNO ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CCMPC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CCMPC ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CCMPC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPC ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CCMPNC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CCMPNC ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CCMPNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNC ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CCMPZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CCMPZ ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CCMPZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPZ ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CCMPNZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CCMPNZ ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CCMPNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNZ ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CCMPBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CCMPBE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CCMPBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPBE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CCMPNBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CCMPNBE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CCMPNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNBE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CCMPS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CCMPS ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CCMPS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPS ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CCMPNS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CCMPNS ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CCMPNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNS ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPT ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPT ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPT ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPF ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPF ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CCMPF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPF ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CCMPL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CCMPL ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CCMPL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPL ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CCMPNL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CCMPNL ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CCMPNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNL ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CCMPLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CCMPLE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CCMPLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPLE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x38 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CCMPNLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0x39 /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Gb,Eb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x3A /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CCMPNLE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Gv,Ev,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0x3B /r ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x80 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CCMPNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0x81 /7 iz ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CCMPNLE ; Ev,Ib,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0x83 /7 ib ; s:APX_F, t:APX, c:CCMP, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE + + +# CTESTSCC +CTESTO ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CTESTO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CTESTO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP +CTESTO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:0 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:0 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CTESTNO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CTESTNO ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP +CTESTNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:1 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNO ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:1 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNO, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CTESTC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CTESTC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP +CTESTC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:2 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:2 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CTESTNC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CTESTNC ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP +CTESTNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:3 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNC ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:3 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNC, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CTESTZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CTESTZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP +CTESTZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:4 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:4 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CTESTNZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CTESTNZ ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP +CTESTNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:5 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNZ ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:5 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNZ, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CTESTBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CTESTBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP +CTESTBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:6 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:6 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CTESTNBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CTESTNBE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP +CTESTNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:7 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNBE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:7 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNBE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CTESTS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CTESTS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP +CTESTS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:8 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:8 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CTESTNS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CTESTNS ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP +CTESTNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:9 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNS ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:9 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNS, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTT ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTT ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:A 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTT ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:A 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTF ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTF ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP +CTESTF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:B 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTF ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:B 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CTESTL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CTESTL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP +CTESTL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:C 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:C 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CTESTNL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CTESTNL ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP +CTESTNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:D 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNL ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:D 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNL, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTLE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CTESTLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CTESTLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CTESTLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP +CTESTLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:E 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:E 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Eb,Gb,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x84 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CTESTNLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Ev,Gv,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0x85 /r ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /0 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CTESTNLE ; Eb,Ib,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0xF6 /1 ib ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP +CTESTNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /0 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:0 nd:0 sc:F 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE +CTESTNLE ; Ev,Iz,dfv ; Fv ; evex m:4 l:0 p:1 nd:0 sc:F 0xF7 /1 iz ; s:APX_F, t:APX, c:CTEST, w:R|R|R|W, f:CNLE, v:cond, e:APX_EVEX_CCMP, a:SCALABLE + + +# CMOVCC +CMOVO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x40 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CO, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x41 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNO, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x40 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CO, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x41 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNO, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x42 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CC, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x43 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNC, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x42 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CC, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x43 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNC, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x44 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CZ, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x45 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNZ, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x44 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CZ, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x45 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNZ, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x46 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CBE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x47 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNBE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x46 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CBE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x47 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNBE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x48 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CS, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x49 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNS, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x48 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CS, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x49 /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNS, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4A /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CP, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4B /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNP, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4A /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CP, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4B /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNP, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4C /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CL, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4D /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNL, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4C /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CL, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4D /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNL, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4E /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CLE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:0 0x4F /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNLE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4E /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CLE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE +CMOVNLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:0 0x4F /r ; s:APX_F, t:APX, c:CMOVcc, w:W|R|R|R, f:CNLE, v:legacy, e:APX_EVEX_INT, a:COND|SCALABLE + + +# CFCMOVCC +CFCMOVO ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x40 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x40 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x40 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x40 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x41 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x41 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x41 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x41 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x42 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x42 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x42 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x42 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x43 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x43 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x43 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x43 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x44 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x44 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x44 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x44 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x45 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x45 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x45 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x45 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x46 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x46 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x46 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x46 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x47 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x47 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x47 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x47 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x48 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x48 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x48 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x48 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x49 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x49 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x49 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x49 /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4A /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4A /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4A /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4A /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4B /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4B /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4B /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4B /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4C /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4C /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4C /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4C /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4D /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4D /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4D /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4D /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4E /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4E /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4E /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4E /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:0 nf:0 0x4F /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Rv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Mv,Gv ; Fv ; evex m:4 l:0 p:0 nd:0 nf:1 0x4F /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:0 nf:0 0x4F /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Rv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:reg ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE ; Mv,Gv ; Fv ; evex m:4 l:0 p:1 nd:0 nf:1 0x4F /r:mem ; s:APX_F, t:APX, c:CFCMOV, w:CW|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x40 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x40 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x41 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNO{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x41 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNO, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x42 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x42 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x43 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNC{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x43 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNC, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x44 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x44 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x45 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNZ{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x45 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNZ, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x46 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x46 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x47 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNBE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x47 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNBE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x48 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x48 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x49 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNS{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x49 /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNS, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4A /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4A /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4B /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNP{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4B /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNP, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4C /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4C /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4D /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNL{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4D /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNL, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4E /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4E /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:0 nd:1 nf:1 0x4F /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE +CFCMOVNLE{ND} ; Bv,Gv,Ev ; Fv ; evex m:4 l:0 p:1 nd:1 nf:1 0x4F /r ; s:APX_F, t:APX, c:CFCMOV, w:W|R|R|R, f:CNLE, v:legacy, e:APX_EVEX_CFCMOV, a:COND|SCALABLE + + +# SETcc{ZU} +SETO{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x40 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CO, a:COND, v:legacy, e:APX_EVEX_INT +SETNO{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x41 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNO, a:COND, v:legacy, e:APX_EVEX_INT +SETC{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x42 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CC, a:COND, v:legacy, e:APX_EVEX_INT +SETNC{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x43 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNC, a:COND, v:legacy, e:APX_EVEX_INT +SETZ{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x44 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CZ, a:COND, v:legacy, e:APX_EVEX_INT +SETNZ{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x45 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNZ, a:COND, v:legacy, e:APX_EVEX_INT +SETBE{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x46 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CBE, a:COND, v:legacy, e:APX_EVEX_INT +SETNBE{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x47 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNBE, a:COND, v:legacy, e:APX_EVEX_INT +SETS{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x48 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CS, a:COND, v:legacy, e:APX_EVEX_INT +SETNS{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x49 /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNS, a:COND, v:legacy, e:APX_EVEX_INT +SETP{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4A /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CP, a:COND, v:legacy, e:APX_EVEX_INT +SETNP{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4B /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNP, a:COND, v:legacy, e:APX_EVEX_INT +SETL{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4C /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CL, a:COND, v:legacy, e:APX_EVEX_INT +SETNL{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4D /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNL, a:COND, v:legacy, e:APX_EVEX_INT +SETLE{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4E /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CLE, a:COND, v:legacy, e:APX_EVEX_INT +SETNLE{ZU} ; Eb ; Fv ; evex m:4 l:0 nf:0 p:3 0x4F /r ; s:APX_F, t:BITBYTE, c:SETcc, w:W|R, f:CNLE, a:COND, v:legacy, e:APX_EVEX_INT diff --git a/isagenerator/instructions/table_evex5.dat b/isagenerator/instructions/table_evex_5.dat similarity index 60% rename from isagenerator/instructions/table_evex5.dat rename to isagenerator/instructions/table_evex_5.dat index 28ceb2b..477dfa7 100644 --- a/isagenerator/instructions/table_evex5.dat +++ b/isagenerator/instructions/table_evex_5.dat @@ -4,65 +4,65 @@ # # 0x10 - 0x1F -VMOVSH ; Vdq{K}{z},Wsh ; n/a ; evex m:5 p:2 l:i w:0 0x10 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R -VMOVSH ; Vdq{K}{z},Hdq,Wsh ; n/a ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R -VMOVSH ; Wsh{K},Vdq ; n/a ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R -VMOVSH ; Wsh{K}{z},Hdq,Vdq ; n/a ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R -VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; n/a ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; n/a ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R +VMOVSH ; Vdq{K}{z},Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R +VMOVSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R +VMOVSH ; Wsh{K},Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R +VMOVSH ; Wsh{K}{z},Hdq,Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R +VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R # 0x20 - 0x2F -VCVTSI2SH ; Vdq,Hdq,Ey ; n/a ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 -VCVTTSH2SI ; Gy,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTSH2SI ; Gy,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 +VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 +VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 +VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0 # 0x50 - 0x5F -VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; n/a ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; n/a ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R -VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; n/a ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; n/a ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; n/a ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; n/a ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R +VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R +VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R # 0x60 - 0x6F -VMOVW ; Vdq,Mw ; n/a ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R -VMOVW ; Vdq,Rd ; n/a ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VMOVW ; Vdq,Mw ; ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VMOVW ; Vdq,Rd ; ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R # 0x70 - 0x7F -VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; n/a ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTTSH2USI ; Gy,Wsh{sae} ; n/a ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R -VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; n/a ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTSH2USI ; Gy,Wsh{er} ; n/a ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 -VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; n/a ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; n/a ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; n/a ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; n/a ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R -VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; n/a ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 -VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; n/a ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; n/a ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; n/a ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; n/a ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; n/a ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; n/a ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VMOVW ; Mw,Vdq ; n/a ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R -VMOVW ; Rd,Vdq ; n/a ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R +VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 +VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R +VCVTSH2USI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64 +VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R +VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R +VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64 +VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VMOVW ; Mw,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R +VMOVW ; Rd,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R diff --git a/isagenerator/instructions/table_evex6.dat b/isagenerator/instructions/table_evex_6.dat similarity index 59% rename from isagenerator/instructions/table_evex6.dat rename to isagenerator/instructions/table_evex_6.dat index e67348c..625294a 100644 --- a/isagenerator/instructions/table_evex6.dat +++ b/isagenerator/instructions/table_evex_6.dat @@ -4,65 +4,65 @@ # # 0x10 - 0x1F -VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; n/a ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R +VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R # 0x20 - 0x2F -VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R -VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R +VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R # 0x40 - 0x4F -VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; n/a ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R -VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; n/a ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R -VRCPPH ; Vfv{K}{z},Wfv|B16 ; n/a ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R -VRCPSH ; Vdq{K}{z},Hdq,Wsh ; n/a ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R -VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; n/a ; evex m:6 p:1 l:x w:0 0x4E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R -VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; n/a ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R +VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R +VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R +VRCPPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R +VRCPSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R +VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R +VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R # 0x50 - 0x5F -VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R -VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R -VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R -VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R +VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R +VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R +VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R +VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R # 0x90 - 0x9F -VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R # 0xA0 - 0xAF -VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R # 0xB0 - 0xBF -VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R -VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; n/a ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R -VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; n/a ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R +VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R +VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R # 0xD0 - 0xD7 -VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R -VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; n/a ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R -VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R -VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; n/a ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R +VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R +VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R +VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R +VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R diff --git a/isagenerator/instructions/table_evex_7.dat b/isagenerator/instructions/table_evex_7.dat new file mode 100644 index 0000000..a5c3d94 --- /dev/null +++ b/isagenerator/instructions/table_evex_7.dat @@ -0,0 +1,7 @@ +# +# Copyright (c) 2024 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +UWRMSR ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:R|R|W, m:O64, v:vex +URDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:W|R|R, m:O64, v:vex diff --git a/isagenerator/instructions/table_base.dat b/isagenerator/instructions/table_legacy_0.dat similarity index 71% rename from isagenerator/instructions/table_base.dat rename to isagenerator/instructions/table_legacy_0.dat index de396de..bea4117 100644 --- a/isagenerator/instructions/table_base.dat +++ b/isagenerator/instructions/table_legacy_0.dat @@ -9,7 +9,7 @@ ADD ; Ev,Gv ; Fv ; 0x01 /r ; s:I ADD ; Gb,Eb ; Fv ; 0x02 /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH ADD ; Gv,Ev ; Fv ; 0x03 /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH ADD ; AL,Ib ; Fv ; 0x04 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH -ADD ; rAX,Iz ; Fv ; 0x05 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1 +ADD ; rAX,Iz ; Fv ; 0x05 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1 PUSH ; ES ; Kv ; 0x06 ; s:I86, t:PUSH, w:R|W, m:NO64|NOSGX POP ; ES ; Kv ; 0x07 ; s:I86, t:POP, w:W|R, m:NO64|NOSGX OR ; Eb,Gb ; Fv ; 0x08 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK @@ -17,7 +17,7 @@ OR ; Ev,Gv ; Fv ; 0x09 /r ; s:I OR ; Gb,Eb ; Fv ; 0x0A /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC OR ; Gv,Ev ; Fv ; 0x0B /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC OR ; AL,Ib ; Fv ; 0x0C ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC -OR ; rAX,Iz ; Fv ; 0x0D iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 +OR ; rAX,Iz ; Fv ; 0x0D iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1 PUSH ; CS ; Kv ; 0x0E ; s:I86, t:PUSH, w:R|W, m:NO64|NOSGX # 0x10 - 0x1F @@ -26,7 +26,7 @@ ADC ; Ev,Gv ; Fv ; 0x11 /r ; s:I ADC ; Gb,Eb ; Fv ; 0x12 /r ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC ADC ; Gv,Ev ; Fv ; 0x13 /r ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC ADC ; AL,Ib ; Fv ; 0x14 ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC -ADC ; rAX,Iz ; Fv ; 0x15 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1 +ADC ; rAX,Iz ; Fv ; 0x15 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1 PUSH ; SS ; Kv ; 0x16 ; s:I86, t:PUSH, w:R|W, m:NO64|NOSGX POP ; SS ; Kv ; 0x17 ; s:I86, t:POP, w:W|R, m:NO64|NOSGX SBB ; Eb,Gb ; Fv ; 0x18 /r ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, p:HLE|LOCK @@ -34,7 +34,7 @@ SBB ; Ev,Gv ; Fv ; 0x19 /r ; s:I SBB ; Gb,Eb ; Fv ; 0x1A /r ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC SBB ; Gv,Ev ; Fv ; 0x1B /r ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC SBB ; AL,Ib ; Fv ; 0x1C ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC -SBB ; rAX,Iz ; Fv ; 0x1D iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1 +SBB ; rAX,Iz ; Fv ; 0x1D iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1 PUSH ; DS ; Kv ; 0x1E ; s:I86, t:PUSH, w:R|W, m:NO64|NOSGX POP ; DS ; Kv ; 0x1F ; s:I86, t:POP, w:W|R, m:NO64|NOSGX @@ -44,18 +44,15 @@ AND ; Ev,Gv ; Fv ; 0x21 /r ; s:I AND ; Gb,Eb ; Fv ; 0x22 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC AND ; Gv,Ev ; Fv ; 0x23 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC AND ; AL,Ib ; Fv ; 0x24 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC -AND ; rAX,Iz ; Fv ; 0x25 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 -es ; n/a ; n/a ; 0x26 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -DAA ; n/a ; AL,Fv ; 0x27 ; s:I86, t:DECIMAL, w:RW|RW, f:DAAS, m:NO64 +AND ; rAX,Iz ; Fv ; 0x25 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1 +DAA ; ; AL,Fv ; 0x27 ; s:I86, t:DECIMAL, w:RW|RW, f:DAAS, m:NO64 SUB ; Eb,Gb ; Fv ; 0x28 /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK SUB ; Ev,Gv ; Fv ; 0x29 /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK SUB ; Gb,Eb ; Fv ; 0x2A /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH SUB ; Gv,Ev ; Fv ; 0x2B /r ; s:I86, t:ARITH, w:RW|R|W, f:ARITH SUB ; AL,Ib ; Fv ; 0x2C ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH -SUB ; rAX,Iz ; Fv ; 0x2D iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1 -cs ; n/a ; n/a ; 0x2E ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -BHNT ; n/a ; n/a ; 0x2E ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -DAS ; n/a ; AL,Fv ; 0x2F ; s:I86, t:DECIMAL, w:RW|RW, f:DAAS|SF=m, m:NO64 +SUB ; rAX,Iz ; Fv ; 0x2D iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1 +DAS ; ; AL,Fv ; 0x2F ; s:I86, t:DECIMAL, w:RW|RW, f:DAAS|SF=m, m:NO64 # 0x30 - 0x3F XOR ; Eb,Gb ; Fv ; 0x30 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK @@ -63,36 +60,33 @@ XOR ; Ev,Gv ; Fv ; 0x31 /r ; s:I XOR ; Gb,Eb ; Fv ; 0x32 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC XOR ; Gv,Ev ; Fv ; 0x33 /r ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC XOR ; AL,Ib ; Fv ; 0x34 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC -XOR ; rAX,Iz ; Fv ; 0x35 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1 -ss ; n/a ; n/a ; 0x36 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -AAA ; n/a ; AH,AL,Fv ; 0x37 ; s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 +XOR ; rAX,Iz ; Fv ; 0x35 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1 +AAA ; ; AH,AL,Fv ; 0x37 ; s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 CMP ; Eb,Gb ; Fv ; 0x38 /r ; s:I86, t:ARITH, w:R|R|W, f:ARITH CMP ; Ev,Gv ; Fv ; 0x39 /r ; s:I86, t:ARITH, w:R|R|W, f:ARITH CMP ; Gb,Eb ; Fv ; 0x3A /r ; s:I86, t:ARITH, w:R|R|W, f:ARITH CMP ; Gv,Ev ; Fv ; 0x3B /r ; s:I86, t:ARITH, w:R|R|W, f:ARITH CMP ; AL,Ib ; Fv ; 0x3C ib ; s:I86, t:ARITH, w:R|R|W, f:ARITH -CMP ; rAX,Iz ; Fv ; 0x3D iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 -ds ; n/a ; n/a ; 0x3E ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -BHT ; n/a ; n/a ; 0x3E ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -AAS ; n/a ; AH,AL,Fv ; 0x3F ; s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 +CMP ; rAX,Iz ; Fv ; 0x3D iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SIGNEXO1 +AAS ; ; AH,AL,Fv ; 0x3F ; s:I86, t:DECIMAL, w:RW|RW|RW, f:AAAS, m:NO64 # 0x40 - 0x4F -INC ; Zv ; Fv ; 0x40 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x41 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x42 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x43 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x44 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x45 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x46 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -INC ; Zv ; Fv ; 0x47 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x48 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x49 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4A ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4B ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4C ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4D ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4E ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 -DEC ; Zv ; Fv ; 0x4F ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64 +INC ; Zv ; Fv ; 0x40 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x41 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x42 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x43 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x44 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x45 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x46 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +INC ; Zv ; Fv ; 0x47 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x48 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x49 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4A ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4B ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4C ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4D ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4E ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 +DEC ; Zv ; Fv ; 0x4F ; s:I86, t:ARITH, w:RW|W, f:INCDEC, m:NO64, a:NOREX2 # 0x50 - 0x5F PUSH ; Zv ; Kv ; 0x50 ; s:I86, t:PUSH, w:R|W, a:D64 @@ -111,24 +105,35 @@ POP ; Zv ; Kv ; 0x5C ; s:I POP ; Zv ; Kv ; 0x5D ; s:I86, t:POP, w:W|R, a:D64 POP ; Zv ; Kv ; 0x5E ; s:I86, t:POP, w:W|R, a:D64 POP ; Zv ; Kv ; 0x5F ; s:I86, t:POP, w:W|R, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x50 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x51 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x52 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x53 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x54 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x55 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x56 ; s:APX_F, t:PUSH, w:R|W, a:D64 +PUSHP ; Zv ; Kv ; rex2w 0x57 ; s:APX_F, t:PUSH, w:R|W, a:D64 +POPP ; Zv ; Kv ; rex2w 0x58 ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x59 ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5A ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5B ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5C ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5D ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5E ; s:APX_F, t:POP, w:W|R, a:D64 +POPP ; Zv ; Kv ; rex2w 0x5F ; s:APX_F, t:POP, w:W|R, a:D64 # 0x60 - 0x6F -PUSHA ; n/a ; BANK,Kv8 ; ds16 0x60 ; s:I386, t:PUSH, w:R|W, m:NO64 -PUSHAD ; n/a ; BANK,Kv8 ; ds32 0x60 ; s:I386, t:PUSH, w:R|W, m:NO64 -POPA ; n/a ; BANK,Kv8 ; ds16 0x61 ; s:I386, t:POP, w:W|R, m:NO64 -POPAD ; n/a ; BANK,Kv8 ; ds32 0x61 ; s:I386, t:POP, w:W|R, m:NO64 -BOUND ; Gv,Ma ; n/a ; 0x62 /r:mem ; s:I186, t:INTERRUPT, w:R|R, m:NO64 +PUSHA ; ; BANK,Kv8 ; ds16 0x60 ; s:I386, t:PUSH, w:R|W, m:NO64 +PUSHAD ; ; BANK,Kv8 ; ds32 0x60 ; s:I386, t:PUSH, w:R|W, m:NO64 +POPA ; ; BANK,Kv8 ; ds16 0x61 ; s:I386, t:POP, w:W|R, m:NO64 +POPAD ; ; BANK,Kv8 ; ds32 0x61 ; s:I386, t:POP, w:W|R, m:NO64 +BOUND ; Gv,Ma ; ; 0x62 /r:mem ; s:I186, t:INTERRUPT, w:R|R, m:NO64 ARPL ; Ew,Gw ; Fv ; 0x63 /r ; s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL|NO64 -MOVSXD ; Gv,Ez ; n/a ; o64 0x63 /r ; s:LONGMODE, t:DATAXFER, w:W|R, m:O64 -fs ; n/a ; n/a ; 0x64 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -BHALT ; n/a ; n/a ; 0x64 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -gs ; n/a ; n/a ; 0x65 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -size ; n/a ; n/a ; 0x66 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -addr ; n/a ; n/a ; 0x67 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -PUSH ; Iz ; Kv ; 0x68 iz ; s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW -IMUL ; Gv,Ev,Iz ; Fv ; 0x69 /r iz ; s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1 -PUSH ; Ib ; Kv ; 0x6A ib ; s:I86, t:PUSH, w:R|W, a:D64|OP1SEXDW -IMUL ; Gv,Ev,Ib ; Fv ; 0x6B /r ib ; s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SEXO1 +MOVSXD ; Gv,Ez ; ; mo64 0x63 /r ; s:LONGMODE, t:DATAXFER, w:W|R, m:O64 +PUSH ; Iz ; Kv ; 0x68 iz ; s:I86, t:PUSH, w:R|W, a:D64|OP1SIGNEXDW +IMUL ; Gv,Ev,Iz ; Fv ; 0x69 /r iz ; s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SIGNEXO1 +PUSH ; Ib ; Kv ; 0x6A ib ; s:I86, t:PUSH, w:R|W, a:D64|OP1SIGNEXDW +IMUL ; Gv,Ev,Ib ; Fv ; 0x6B /r ib ; s:I86, t:ARITH, w:W|R|R|W, f:MUL, a:OP3SIGNEXO1 INSB ; Yb,DX ; aDI,Fv ; 0x6C ; s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX INSB ; Yb,DX ; aCX,aDI,Fv ; rep 0x6C ; s:I86, t:IOSTRINGOP, c:INS, w:CW|R|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX INSW ; Yz,DX ; aDI,Fv ; ds16 0x6D ; s:I86, t:IOSTRINGOP, c:INS, w:W|R|RW|R, f:IOS, a:OP1DEF|OP2DEF, p:REP, m:NOSGX @@ -143,22 +148,22 @@ OUTSD ; DX,Xz ; aSI,Fv ; 0x6F ; s:I OUTSD ; DX,Xz ; aCX,aSI,Fv ; rep 0x6F ; s:I86, t:IOSTRINGOP, c:OUTS, w:R|CR|RCW|RCW|R, f:IOS, a:OP1DEF|OP2DEF|SERIAL, p:REP, m:NOSGX # 0x70 - 0x7F -JO ; Jb ; rIP,Fv ; 0x70 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CO, a:F64|COND, p:BND|BH -JNO ; Jb ; rIP,Fv ; 0x71 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNO, a:F64|COND, p:BND|BH -JC ; Jb ; rIP,Fv ; 0x72 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CC, a:F64|COND, p:BND|BH -JNC ; Jb ; rIP,Fv ; 0x73 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNC, a:F64|COND, p:BND|BH -JZ ; Jb ; rIP,Fv ; 0x74 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CZ, a:F64|COND, p:BND|BH -JNZ ; Jb ; rIP,Fv ; 0x75 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNZ, a:F64|COND, p:BND|BH -JBE ; Jb ; rIP,Fv ; 0x76 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CBE, a:F64|COND, p:BND|BH -JNBE ; Jb ; rIP,Fv ; 0x77 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNBE, a:F64|COND, p:BND|BH -JS ; Jb ; rIP,Fv ; 0x78 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CS, a:F64|COND, p:BND|BH -JNS ; Jb ; rIP,Fv ; 0x79 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNS, a:F64|COND, p:BND|BH -JP ; Jb ; rIP,Fv ; 0x7A cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CP, a:F64|COND, p:BND|BH -JNP ; Jb ; rIP,Fv ; 0x7B cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNP, a:F64|COND, p:BND|BH -JL ; Jb ; rIP,Fv ; 0x7C cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CL, a:F64|COND, p:BND|BH -JNL ; Jb ; rIP,Fv ; 0x7D cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNL, a:F64|COND, p:BND|BH -JLE ; Jb ; rIP,Fv ; 0x7E cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CLE, a:F64|COND, p:BND|BH -JNLE ; Jb ; rIP,Fv ; 0x7F cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNLE, a:F64|COND, p:BND|BH +JO ; Jb ; rIP,Fv ; 0x70 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CO, a:F64|COND|NOREX2, p:BND|BH +JNO ; Jb ; rIP,Fv ; 0x71 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNO, a:F64|COND|NOREX2, p:BND|BH +JC ; Jb ; rIP,Fv ; 0x72 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CC, a:F64|COND|NOREX2, p:BND|BH +JNC ; Jb ; rIP,Fv ; 0x73 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNC, a:F64|COND|NOREX2, p:BND|BH +JZ ; Jb ; rIP,Fv ; 0x74 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CZ, a:F64|COND|NOREX2, p:BND|BH +JNZ ; Jb ; rIP,Fv ; 0x75 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNZ, a:F64|COND|NOREX2, p:BND|BH +JBE ; Jb ; rIP,Fv ; 0x76 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CBE, a:F64|COND|NOREX2, p:BND|BH +JNBE ; Jb ; rIP,Fv ; 0x77 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNBE, a:F64|COND|NOREX2, p:BND|BH +JS ; Jb ; rIP,Fv ; 0x78 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CS, a:F64|COND|NOREX2, p:BND|BH +JNS ; Jb ; rIP,Fv ; 0x79 cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNS, a:F64|COND|NOREX2, p:BND|BH +JP ; Jb ; rIP,Fv ; 0x7A cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CP, a:F64|COND|NOREX2, p:BND|BH +JNP ; Jb ; rIP,Fv ; 0x7B cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNP, a:F64|COND|NOREX2, p:BND|BH +JL ; Jb ; rIP,Fv ; 0x7C cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CL, a:F64|COND|NOREX2, p:BND|BH +JNL ; Jb ; rIP,Fv ; 0x7D cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNL, a:F64|COND|NOREX2, p:BND|BH +JLE ; Jb ; rIP,Fv ; 0x7E cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CLE, a:F64|COND|NOREX2, p:BND|BH +JNLE ; Jb ; rIP,Fv ; 0x7F cb ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNLE, a:F64|COND|NOREX2, p:BND|BH # 0x80 - 0x8F ADD ; Eb,Ib ; Fv ; 0x80 /0 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, p:HLE|LOCK @@ -170,147 +175,148 @@ SUB ; Eb,Ib ; Fv ; 0x80 /5 ib ; s:I XOR ; Eb,Ib ; Fv ; 0x80 /6 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, p:HLE|LOCK CMP ; Eb,Ib ; Fv ; 0x80 /7 ib ; s:I86, t:ARITH, w:R|R|W, f:ARITH -ADD ; Ev,Iz ; Fv ; 0x81 /0 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK -OR ; Ev,Iz ; Fv ; 0x81 /1 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -ADC ; Ev,Iz ; Fv ; 0x81 /2 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK -SBB ; Ev,Iz ; Fv ; 0x81 /3 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK -AND ; Ev,Iz ; Fv ; 0x81 /4 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -SUB ; Ev,Iz ; Fv ; 0x81 /5 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK -XOR ; Ev,Iz ; Fv ; 0x81 /6 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -CMP ; Ev,Iz ; Fv ; 0x81 /7 iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 +ADD ; Ev,Iz ; Fv ; 0x81 /0 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, p:HLE|LOCK +OR ; Ev,Iz ; Fv ; 0x81 /1 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +ADC ; Ev,Iz ; Fv ; 0x81 /2 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, p:HLE|LOCK +SBB ; Ev,Iz ; Fv ; 0x81 /3 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, p:HLE|LOCK +AND ; Ev,Iz ; Fv ; 0x81 /4 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +SUB ; Ev,Iz ; Fv ; 0x81 /5 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, p:HLE|LOCK +XOR ; Ev,Iz ; Fv ; 0x81 /6 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +CMP ; Ev,Iz ; Fv ; 0x81 /7 iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SIGNEXO1 -ADD ; Eb,Ib ; Fv ; 0x82 /0 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK -OR ; Eb,Ib ; Fv ; 0x82 /1 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK -ADC ; Eb,Ib ; Fv ; 0x82 /2 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK -SBB ; Eb,Ib ; Fv ; 0x82 /3 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, m:NO64, p:HLE|LOCK -AND ; Eb,Ib ; Fv ; 0x82 /4 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK -SUB ; Eb,Ib ; Fv ; 0x82 /5 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, m:NO64, p:HLE|LOCK -XOR ; Eb,Ib ; Fv ; 0x82 /6 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, m:NO64, p:HLE|LOCK -CMP ; Eb,Ib ; Fv ; 0x82 /7 iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1, m:NO64 +ADD ; Eb,Ib ; Fv ; 0x82 /0 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +OR ; Eb,Ib ; Fv ; 0x82 /1 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +ADC ; Eb,Ib ; Fv ; 0x82 /2 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +SBB ; Eb,Ib ; Fv ; 0x82 /3 iz ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +AND ; Eb,Ib ; Fv ; 0x82 /4 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +SUB ; Eb,Ib ; Fv ; 0x82 /5 iz ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +XOR ; Eb,Ib ; Fv ; 0x82 /6 iz ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, m:NO64, p:HLE|LOCK +CMP ; Eb,Ib ; Fv ; 0x82 /7 iz ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SIGNEXO1, m:NO64 -ADD ; Ev,Ib ; Fv ; 0x83 /0 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK -OR ; Ev,Ib ; Fv ; 0x83 /1 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -ADC ; Ev,Ib ; Fv ; 0x83 /2 ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK -SBB ; Ev,Ib ; Fv ; 0x83 /3 ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SEXO1, p:HLE|LOCK -AND ; Ev,Ib ; Fv ; 0x83 /4 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -SUB ; Ev,Ib ; Fv ; 0x83 /5 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SEXO1, p:HLE|LOCK -XOR ; Ev,Ib ; Fv ; 0x83 /6 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SEXO1, p:HLE|LOCK -CMP ; Ev,Ib ; Fv ; 0x83 /7 ib ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SEXO1 +ADD ; Ev,Ib ; Fv ; 0x83 /0 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, p:HLE|LOCK +OR ; Ev,Ib ; Fv ; 0x83 /1 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +ADC ; Ev,Ib ; Fv ; 0x83 /2 ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, p:HLE|LOCK +SBB ; Ev,Ib ; Fv ; 0x83 /3 ib ; s:I86, t:ARITH, w:RW|R|RW, f:ARITHC, a:OP2SIGNEXO1, p:HLE|LOCK +AND ; Ev,Ib ; Fv ; 0x83 /4 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +SUB ; Ev,Ib ; Fv ; 0x83 /5 ib ; s:I86, t:ARITH, w:RW|R|W, f:ARITH, a:OP2SIGNEXO1, p:HLE|LOCK +XOR ; Ev,Ib ; Fv ; 0x83 /6 ib ; s:I86, t:LOGIC, w:RW|R|W, f:LOGIC, a:OP2SIGNEXO1, p:HLE|LOCK +CMP ; Ev,Ib ; Fv ; 0x83 /7 ib ; s:I86, t:ARITH, w:R|R|W, f:ARITH, a:OP2SIGNEXO1 TEST ; Eb,Gb ; Fv ; 0x84 /r ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC TEST ; Ev,Gv ; Fv ; 0x85 /r ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC -XCHG ; Eb,Gb ; n/a ; 0x86 /r ; s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL -XCHG ; Ev,Gv ; n/a ; 0x87 /r ; s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL -MOV ; Eb,Gb ; n/a ; 0x88 /r ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL -MOV ; Ev,Gv ; n/a ; 0x89 /r ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL -MOV ; Gb,Eb ; n/a ; 0x8A /r ; s:I86, t:DATAXFER, w:W|R -MOV ; Gv,Ev ; n/a ; 0x8B /r ; s:I86, t:DATAXFER, w:W|R -MOV ; Mw,Sw ; n/a ; 0x8C /r:mem ; s:I86, t:DATAXFER, w:W|R -MOV ; Rv,Sw ; n/a ; 0x8C /r:reg ; s:I86, t:DATAXFER, w:W|R -LEA ; Gv,M0 ; n/a ; 0x8D /r:mem ; s:I86, t:MISC, w:W|N, a:AG -MOV ; Sw,Mw ; n/a ; 0x8E /r:mem ; s:I86, t:DATAXFER, w:W|R -MOV ; Sw,Rv ; n/a ; 0x8E /r:reg ; s:I86, t:DATAXFER, w:W|R +XCHG ; Eb,Gb ; ; 0x86 /r ; s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL +XCHG ; Ev,Gv ; ; 0x87 /r ; s:I86, t:DATAXFER, w:RW|RW, p:HLE|LOCK|HLEWOL +MOV ; Eb,Gb ; ; 0x88 /r ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +MOV ; Ev,Gv ; ; 0x89 /r ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +MOV ; Gb,Eb ; ; 0x8A /r ; s:I86, t:DATAXFER, w:W|R +MOV ; Gv,Ev ; ; 0x8B /r ; s:I86, t:DATAXFER, w:W|R +MOV ; Mw,Sw ; ; 0x8C /r:mem ; s:I86, t:DATAXFER, w:W|R +MOV ; Rv,Sw ; ; 0x8C /r:reg ; s:I86, t:DATAXFER, w:W|R +LEA ; Gv,M0 ; ; 0x8D /r:mem ; s:I86, t:MISC, w:W|N, a:AG +MOV ; Sw,Mw ; ; 0x8E /r:mem ; s:I86, t:DATAXFER, w:W|R +MOV ; Sw,Rv ; ; 0x8E /r:reg ; s:I86, t:DATAXFER, w:W|R POP ; Ev ; Kv ; 0x8F /0 ; s:I86, t:POP, w:W|R, a:D64 # 0x90 - 0x9F -NOP ; n/a ; n/a ; 0x90 ; s:I86, t:NOP -PAUSE ; n/a ; n/a ; a0xF3 0x90 ; s:PAUSE, t:MISC, m:NOTSX -XCHG ; Zv,rAX ; n/a ; rexb 0x90 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x91 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x92 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x93 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x94 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x95 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x96 ; s:I86, t:DATAXFER, w:RW|RW -XCHG ; Zv,rAX ; n/a ; 0x97 ; s:I86, t:DATAXFER, w:RW|RW -CBW ; n/a ; AX,AL ; ds16 0x98 ; s:I386, t:CONVERT, w:W|R -CWDE ; n/a ; EAX,AX ; ds32 0x98 ; s:I386, t:CONVERT, w:W|R -CDQE ; n/a ; RAX,EAX ; ds64 0x98 ; s:I386, t:CONVERT, w:W|R -CWD ; n/a ; DX,AX ; ds16 0x99 ; s:I386, t:CONVERT, w:W|R -CDQ ; n/a ; EDX,EAX ; ds32 0x99 ; s:I386, t:CONVERT, w:W|R -CQO ; n/a ; RDX,RAX ; ds64 0x99 ; s:I386, t:CONVERT, w:W|R +NOP ; ; ; 0x90 ; s:I86, t:NOP +PAUSE ; ; ; repz 0x90 ; s:PAUSE, t:MISC, m:NOTSX +XCHG ; Zv,rAX ; ; rexb 0x90 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x91 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x92 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x93 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x94 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x95 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x96 ; s:I86, t:DATAXFER, w:RW|RW +XCHG ; Zv,rAX ; ; 0x97 ; s:I86, t:DATAXFER, w:RW|RW +CBW ; ; AX,AL ; ds16 0x98 ; s:I386, t:CONVERT, w:W|R +CWDE ; ; EAX,AX ; ds32 0x98 ; s:I386, t:CONVERT, w:W|R +CDQE ; ; RAX,EAX ; ds64 0x98 ; s:I386, t:CONVERT, w:W|R +CWD ; ; DX,AX ; ds16 0x99 ; s:I386, t:CONVERT, w:W|R +CDQ ; ; EDX,EAX ; ds32 0x99 ; s:I386, t:CONVERT, w:W|R +CQO ; ; RDX,RAX ; ds64 0x99 ; s:I386, t:CONVERT, w:W|R CALLF ; Ap ; CS,rIP,Kv2,SHS2 ; 0x9A cp ; s:I86, t:CALL, c:CALLFD, w:R|RW|W|W|W, m:NO64|NOSGX -WAIT ; n/a ; n/a ; 0x9B ; s:X87, t:X87_ALU +WAIT ; ; ; 0x9B ; s:X87, t:X87_ALU PUSHFW ; Fv ; Kv ; ds16 0x9C ; s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 PUSHFD ; Fv ; Kv ; ds32 0x9C ; s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 PUSHFQ ; Fv ; Kv ; dds64 0x9C ; s:I86, t:PUSH, c:PUSHF, w:R|W, a:D64 POPFW ; Fv ; Kv ; ds16 0x9D ; s:I86, t:POP, c:POPF, w:W|R , a:D64 POPFD ; Fv ; Kv ; ds32 0x9D ; s:I86, t:POP, c:POPF, w:W|R , a:D64 POPFQ ; Fv ; Kv ; dds64 0x9D ; s:I86, t:POP, c:POPF, w:W|R , a:D64 -SAHF ; n/a ; AH,Fv ; 0x9E ; s:I86, t:FLAGOP, w:R|W, f:CF=m|PF=m|AF=m|ZF=m|SF=m -LAHF ; n/a ; AH,Fv ; 0x9F ; s:I86, t:FLAGOP, w:W|R, f:CF=t|PF=t|AF=t|ZF=t|SF=t +SAHF ; ; AH,Fv ; 0x9E ; s:I86, t:FLAGOP, w:R|W, f:CF=m|PF=m|AF=m|ZF=m|SF=m +LAHF ; ; AH,Fv ; 0x9F ; s:I86, t:FLAGOP, w:W|R, f:CF=t|PF=t|AF=t|ZF=t|SF=t # 0xA0 - 0xAF -MOV ; AL,Ob ; n/a ; 0xA0 ; s:I86, t:DATAXFER, w:W|R -MOV ; rAX,Ov ; n/a ; 0xA1 ; s:I86, t:DATAXFER, w:W|R -MOV ; Ob,AL ; n/a ; 0xA2 ; s:I86, t:DATAXFER, w:W|R -MOV ; Ov,rAX ; n/a ; 0xA3 ; s:I86, t:DATAXFER, w:W|R +MOV ; AL,Ob ; ; 0xA0 ; s:I86, t:DATAXFER, w:W|R, a:NOREX2 +MOV ; rAX,Ov ; ; 0xA1 ; s:I86, t:DATAXFER, w:W|R, a:NOREX2 +MOV ; Ob,AL ; ; 0xA2 ; s:I86, t:DATAXFER, w:W|R, a:NOREX2 +MOV ; Ov,rAX ; ; 0xA3 ; s:I86, t:DATAXFER, w:W|R, a:NOREX2 +JMPABS ; Aq ; rIP ; rex2 w:0 0xA1 cq ; s:APX_F, t:UNCOND_BR, w:R|W, a:NO66|NO67|NOREP -MOVSB ; Yb,Xb ; aSI,aDI,Fv ; 0xA4 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSB ; Yb,Xb ; aCX,aSI,aDI,Fv ; rep 0xA4 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSW ; Yv,Xv ; aSI,aDI,Fv ; ds16 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSW ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds16 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSD ; Yv,Xv ; aSI,aDI,Fv ; ds32 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSD ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds32 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSQ ; Yv,Xv ; aSI,aDI,Fv ; ds64 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF, p:REP -MOVSQ ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds64 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +MOVSB ; Yb,Xb ; aSI,aDI,Fv ; 0xA4 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSB ; Yb,Xb ; aCX,aSI,aDI,Fv ; rep 0xA4 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSW ; Yv,Xv ; aSI,aDI,Fv ; ds16 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSW ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds16 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSD ; Yv,Xv ; aSI,aDI,Fv ; ds32 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSD ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds32 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSQ ; Yv,Xv ; aSI,aDI,Fv ; ds64 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:W|R|RW|RW|R, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +MOVSQ ; Yv,Xv ; aCX,aSI,aDI,Fv ; rep ds64 0xA5 ; s:I86, t:STRINGOP, c:MOVS, w:CW|CR|RCW|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP -CMPSB ; Xb,Yb ; aSI,aDI,Fv ; 0xA6 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSB ; Xb,Yb ; aCX,aSI,aDI,Fv ; rep 0xA6 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSW ; Xv,Yv ; aSI,aDI,Fv ; ds16 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSW ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds16 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSD ; Xv,Yv ; aSI,aDI,Fv ; ds32 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSD ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds32 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSQ ; Xv,Yv ; aSI,aDI,Fv ; ds64 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -CMPSQ ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds64 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +CMPSB ; Xb,Yb ; aSI,aDI,Fv ; 0xA6 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSB ; Xb,Yb ; aCX,aSI,aDI,Fv ; rep 0xA6 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSW ; Xv,Yv ; aSI,aDI,Fv ; ds16 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSW ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds16 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSD ; Xv,Yv ; aSI,aDI,Fv ; ds32 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSD ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds32 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSQ ; Xv,Yv ; aSI,aDI,Fv ; ds64 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:R|R|RW|RW|R, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +CMPSQ ; Xv,Yv ; aCX,aSI,aDI,Fv ; rep ds64 0xA7 ; s:I86, t:STRINGOP, c:CMPS, w:CR|CR|RCW|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC -TEST ; AL,Ib ; Fv ; 0xA8 ib ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC -TEST ; rAX,Iz ; Fv ; 0xA9 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 +TEST ; AL,Ib ; Fv ; 0xA8 ib ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:NOREX2 +TEST ; rAX,Iz ; Fv ; 0xA9 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:NOREX2|OP2SIGNEXO1 -STOSB ; Yb,AL ; aDI,Fv ; 0xAA ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSB ; Yb,AL ; aCX,aDI,Fv ; rep 0xAA ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSW ; Yv,AX ; aDI,Fv ; ds16 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSW ; Yv,AX ; aCX,aDI,Fv ; rep ds16 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSD ; Yv,EAX ; aDI,Fv ; ds32 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSD ; Yv,EAX ; aCX,aDI,Fv ; rep ds32 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSQ ; Yv,RAX ; aDI,Fv ; ds64 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -STOSQ ; Yv,RAX ; aCX,aDI,Fv ; rep ds64 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF, p:REP +STOSB ; Yb,AL ; aDI,Fv ; 0xAA ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSB ; Yb,AL ; aCX,aDI,Fv ; rep 0xAA ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSW ; Yv,AX ; aDI,Fv ; ds16 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSW ; Yv,AX ; aCX,aDI,Fv ; rep ds16 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSD ; Yv,EAX ; aDI,Fv ; ds32 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSD ; Yv,EAX ; aCX,aDI,Fv ; rep ds32 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSQ ; Yv,RAX ; aDI,Fv ; ds64 0xAB ; s:I86, t:STRINGOP, c:STOS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +STOSQ ; Yv,RAX ; aCX,aDI,Fv ; rep ds64 0xAB ; s:I86, t:STRINGOP, c:STOS, w:CW|R|RCW|RCW|RW, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP -LODSB ; AL,Xb ; aSI,Fv ; 0xAC ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -LODSB ; AL,Xb ; aCX,aSI,Fv ; rep 0xAC ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -LODSW ; AX,Xv ; aSI,Fv ; ds16 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -LODSW ; AX,Xv ; aCX,aSI,Fv ; rep ds16 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -LODSD ; EAX,Xv ; aSI,Fv ; ds32 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -LODSD ; EAX,Xv ; aCX,aSI,Fv ; rep ds32 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP -LODSQ ; RAX,Xv ; aSI,Fv ; ds64 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF, p:REP -LODSQ ; RAX,Xv ; aCX,aSI,Fv ; rep ds64 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF, p:REP +LODSB ; AL,Xb ; aSI,Fv ; 0xAC ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSB ; AL,Xb ; aCX,aSI,Fv ; rep 0xAC ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSW ; AX,Xv ; aSI,Fv ; ds16 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSW ; AX,Xv ; aCX,aSI,Fv ; rep ds16 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSD ; EAX,Xv ; aSI,Fv ; ds32 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSD ; EAX,Xv ; aCX,aSI,Fv ; rep ds32 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSQ ; RAX,Xv ; aSI,Fv ; ds64 0xAD ; s:I86, t:STRINGOP, c:LODS, w:W|R|RW|R, f:DF=t , a:OP1DEF|OP2DEF|NOREX2, p:REP +LODSQ ; RAX,Xv ; aCX,aSI,Fv ; rep ds64 0xAD ; s:I86, t:STRINGOP, c:LODS, w:CW|CR|RCW|RCW|RW, f:DF=t, a:OP1DEF|OP2DEF|NOREX2, p:REP -SCASB ; AL,Yb ; aDI,Fv ; 0xAE ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -SCASB ; AL,Yb ; aCX,aDI,Fv ; rep 0xAE ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -SCASW ; AX,Yv ; aDI,Fv ; ds16 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -SCASW ; AX,Yv ; aCX,aDI,Fv ; rep ds16 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -SCASD ; EAX,Yv ; aDI,Fv ; ds32 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -SCASD ; EAX,Yv ; aCX,aDI,Fv ; rep ds32 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC -SCASQ ; RAX,Yv ; aDI,Fv ; ds64 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF, p:REPC -SCASQ ; RAX,Yv ; aCX,aDI,Fv ; rep ds64 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF, p:REPC +SCASB ; AL,Yb ; aDI,Fv ; 0xAE ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASB ; AL,Yb ; aCX,aDI,Fv ; rep 0xAE ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASW ; AX,Yv ; aDI,Fv ; ds16 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASW ; AX,Yv ; aCX,aDI,Fv ; rep ds16 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASD ; EAX,Yv ; aDI,Fv ; ds32 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASD ; EAX,Yv ; aCX,aDI,Fv ; rep ds32 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASQ ; RAX,Yv ; aDI,Fv ; ds64 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|R|RW|RW, f:CMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC +SCASQ ; RAX,Yv ; aCX,aDI,Fv ; rep ds64 0xAF ; s:I86, t:STRINGOP, c:SCAS, w:R|CR|RCW|RCW|RW, f:REPCMPS, a:OP1DEF|OP2DEF|NOREX2, p:REPC # 0xB0 - 0xBF -MOV ; Zb,Ib ; n/a ; 0xB0 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB1 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB2 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB3 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB4 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB5 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB6 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zb,Ib ; n/a ; 0xB7 ib ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xB8 iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xB9 iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBA iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBB iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBC iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBD iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBE iv ; s:I86, t:DATAXFER, w:W|R -MOV ; Zv,Iv ; n/a ; 0xBF iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB0 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB1 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB2 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB3 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB4 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB5 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB6 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zb,Ib ; ; 0xB7 ib ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xB8 iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xB9 iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBA iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBB iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBC iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBD iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBE iv ; s:I86, t:DATAXFER, w:W|R +MOV ; Zv,Iv ; ; 0xBF iv ; s:I86, t:DATAXFER, w:W|R # 0xC0 - 0xCF ROL ; Eb,Ib ; Fv ; 0xC0 /0 ib ; s:I86, t:ROTATE, w:RW|R|W, f:ROT @@ -330,23 +336,23 @@ SHR ; Ev,Ib ; Fv ; 0xC1 /5 ib ; s:I SAL ; Ev,Ib ; Fv ; 0xC1 /6 ib ; s:I86, t:SHIFT, w:RW|R|W, f:SHIFT SAR ; Ev,Ib ; Fv ; 0xC1 /7 ib ; s:I86, t:SHIFT, w:RW|R|W, f:SHIFT RETN ; Iw ; rIP,sSP,Kv,SHS1 ; 0xC2 iw ; s:I86, t:RET, w:R|W|W|R|R, a:F64, p:BND -RETN ; n/a ; rIP,Kv,SHS1 ; 0xC3 ; s:I86, t:RET, w:W|R|R, a:F64, p:BND +RETN ; ; rIP,Kv,SHS1 ; 0xC3 ; s:I86, t:RET, w:W|R|R, a:F64, p:BND LES ; Gz,Mp ; ES ; 0xC4 /r:mem ; s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX LDS ; Gz,Mp ; DS ; 0xC5 /r:mem ; s:I86, t:SEGOP, w:W|R|W, m:NO64|NOSGX -MOV ; Eb,Ib ; n/a ; 0xC6 /0 ib ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL +MOV ; Eb,Ib ; ; 0xC6 /0 ib ; s:I86, t:DATAXFER, w:W|R, p:XRELEASE|HLEWOL XABORT ; Ib ; yIP,EAX ; 0xC6 /0xF8 ib ; s:TSX, t:UNCOND_BR, w:R|W|RCW, i:RTM -MOV ; Ev,Iz ; n/a ; 0xC7 /0 iz ; s:I86, t:DATAXFER, w:W|R, a:OP2SEXO1, p:XRELEASE|HLEWOL +MOV ; Ev,Iz ; ; 0xC7 /0 iz ; s:I86, t:DATAXFER, w:W|R, a:OP2SIGNEXO1, p:XRELEASE|HLEWOL XBEGIN ; Jz ; yIP,EAX ; 0xC7 /0xF8 cz ; s:TSX, t:COND_BR, w:R|RCW|CW, i:RTM ENTER ; Iw,Ib ; rBP,sSP,Kv ; 0xC8 iw ib ; s:I186, t:MISC, w:R|R|RW|RW|W, a:D64 -LEAVE ; n/a ; sBP,rBP,rSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64 +LEAVE ; ; sBP,rBP,rSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64 RETF ; Iw ; CS,rIP,Kv2,SHS2 ; 0xCA iw ; s:I86, t:RET, w:R|W|W|R|R -RETF ; n/a ; CS,rIP,Kv2,SHS2 ; 0xCB ; s:I86, t:RET, w:W|W|R|R -INT3 ; n/a ; CS,rIP,Kv3,Fv,SHS3 ; 0xCC ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX +RETF ; ; CS,rIP,Kv2,SHS2 ; 0xCB ; s:I86, t:RET, w:W|W|R|R +INT3 ; ; CS,rIP,Kv3,Fv,SHS3 ; 0xCC ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX INT ; Ib ; CS,rIP,Kv3,Fv,SHS3 ; 0xCD ib ; s:I86, t:INTERRUPT, w:R|RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX -INTO ; n/a ; CS,rIP,Kv3,Fv,SHS3 ; 0xCE ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NO64|NOSGX -IRETW ; n/a ; CS,rIP,Kv3,Fv,SHS3 ; ds16 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL -IRETD ; n/a ; CS,rIP,Kv3,Fv,SHS3 ; ds32 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL -IRETQ ; n/a ; CS,rIP,Kv3,Fv,SHS3 ; ds64 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL +INTO ; ; CS,rIP,Kv3,Fv,SHS3 ; 0xCE ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NO64|NOSGX +IRETW ; ; CS,rIP,Kv3,Fv,SHS3 ; ds16 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL +IRETD ; ; CS,rIP,Kv3,Fv,SHS3 ; ds32 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL +IRETQ ; ; CS,rIP,Kv3,Fv,SHS3 ; ds64 0xCF ; s:I86, t:RET, c:IRET, w:RW|W|R|RW|RW, a:SERIAL # 0xD0 - 0xDF ROL ; Eb,1 ; Fv ; 0xD0 /0 ; s:I86, t:ROTATE, w:RW|R|W, f:ROT @@ -383,62 +389,55 @@ SAL ; Ev,CL ; Fv ; 0xD3 /6 ; s:I SAR ; Ev,CL ; Fv ; 0xD3 /7 ; s:I86, t:SHIFT, w:RW|R|W, f:SHIFT AAM ; Ib ; AL,AH,Fv ; 0xD4 ib ; s:I86, t:DECIMAL, w:R|RW|W|W, f:AADM, m:NO64 AAD ; Ib ; AL,AH,Fv ; 0xD5 ib ; s:I86, t:DECIMAL, w:R|RW|RW|W, f:AADM, m:NO64 -SALC ; n/a ; AL,Fv ; 0xD6 ; s:I86, t:FLAGOP, w:W|R, f:CF=t -XLATB ; n/a ; AL,pBXALb ; 0xD7 ; s:I86, t:MISC, w:W|R +SALC ; ; AL,Fv ; 0xD6 ; s:I86, t:FLAGOP, w:W|R, f:CF=t +XLATB ; ; AL,pBXALb ; 0xD7 ; s:I86, t:MISC, w:W|R # 0xE0 - 0xEF -LOOPNZ ; Jb ; aCX,rIP,Fv ; 0xE0 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64 -LOOPZ ; Jb ; aCX,rIP,Fv ; 0xE1 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64 -LOOP ; Jb ; aCX,rIP,Fv ; 0xE2 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, a:F64 -JCXZ ; Jb ; aCX,rIP ; as16 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64 -JECXZ ; Jb ; aCX,rIP ; as32 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64 -JRCXZ ; Jb ; aCX,rIP ; as64 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64 -IN ; AL,Ib ; Fv ; 0xE4 ib ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX -IN ; eAX,Ib ; Fv ; 0xE5 ib ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX -OUT ; Ib,AL ; Fv ; 0xE6 ib ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX -OUT ; Ib,eAX ; Fv ; 0xE7 ib ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX -CALL ; Jz ; rIP,Kv,SHS1 ; 0xE8 cz ; s:I86, t:CALL, c:CALLNR, w:R|RW|W|W, a:F64, p:BND -JMP ; Jz ; rIP ; 0xE9 cz ; s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND +LOOPNZ ; Jb ; aCX,rIP,Fv ; 0xE0 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64|NOREX2 +LOOPZ ; Jb ; aCX,rIP,Fv ; 0xE1 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, f:ZF=t, a:F64|NOREX2 +LOOP ; Jb ; aCX,rIP,Fv ; 0xE2 cb ; s:I86, t:COND_BR, w:R|RW|CRCW|R, a:F64|NOREX2 +JCXZ ; Jb ; aCX,rIP ; as16 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64|NOREX2 +JECXZ ; Jb ; aCX,rIP ; as32 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64|NOREX2 +JRCXZ ; Jb ; aCX,rIP ; as64 0xE3 cb ; s:I86, t:COND_BR, c:JrCXZ, w:R|R|CRCW, a:F64|NOREX2 +IN ; AL,Ib ; Fv ; 0xE4 ib ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX, a:NOREX2 +IN ; eAX,Ib ; Fv ; 0xE5 ib ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX, a:NOREX2 +OUT ; Ib,AL ; Fv ; 0xE6 ib ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL|NOREX2, m:NOSGX +OUT ; Ib,eAX ; Fv ; 0xE7 ib ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL|NOREX2, m:NOSGX +CALL ; Jz ; rIP,Kv,SHS1 ; 0xE8 cz ; s:I86, t:CALL, c:CALLNR, w:R|RW|W|W, a:F64|NOREX2, p:BND +JMP ; Jz ; rIP ; 0xE9 cz ; s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64|NOREX2, p:BND JMPF ; Ap ; CS,rIP ; 0xEA cp ; s:I86, t:UNCOND_BR, c:JMPFD, w:R|W|W, m:NO64|NOSGX -JMP ; Jb ; rIP ; 0xEB cb ; s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64, p:BND -IN ; AL,DX ; Fv ; 0xEC ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX -IN ; eAX,DX ; Fv ; 0xED ; s:I86, t:IO, w:W|R|R, f:IO, m:NOSGX -OUT ; DX,AL ; Fv ; 0xEE ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX -OUT ; DX,eAX ; Fv ; 0xEF ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL, m:NOSGX +JMP ; Jb ; rIP ; 0xEB cb ; s:I86, t:UNCOND_BR, c:JMPNR, w:R|RW, a:F64|NOREX2, p:BND +IN ; AL,DX ; Fv ; 0xEC ; s:I86, t:IO, w:W|R|R, f:IO, a:NOREX2, m:NOSGX +IN ; eAX,DX ; Fv ; 0xED ; s:I86, t:IO, w:W|R|R, f:IO, a:NOREX2, m:NOSGX +OUT ; DX,AL ; Fv ; 0xEE ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL|NOREX2, m:NOSGX +OUT ; DX,eAX ; Fv ; 0xEF ; s:I86, t:IO, w:R|R|R, f:IO, a:SERIAL|NOREX2, m:NOSGX # 0xF0 - 0xFF -LOCK ; n/a ; n/a ; 0xF0 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -REPNZ ; n/a ; n/a ; 0xF2 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -XACQUIRE ; n/a ; n/a ; 0xF2 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -BND ; n/a ; n/a ; 0xF2 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -REPZ ; n/a ; n/a ; 0xF3 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX -XRELEASE ; n/a ; n/a ; 0xF2 ; s:UNKNOWN, t:UNKNOWN, a:PREFIX - -INT1 ; n/a ; CS,rIP,Kv3,Fv ; 0xF1 ; s:I86, t:INTERRUPT, w:RW|RW|RW|W, f:INT, m:NOSGX -HLT ; n/a ; n/a ; 0xF4 ; s:I86, t:SYSTEM, m:KERNEL -CMC ; n/a ; Fv ; 0xF5 ; s:I86, t:FLAGOP, w:RW, f:CF=m +INT1 ; ; CS,rIP,Kv3,Fv ; 0xF1 ; s:I86, t:INTERRUPT, w:RW|RW|RW|W, f:INT, m:NOSGX +HLT ; ; ; 0xF4 ; s:I86, t:SYSTEM, m:KERNEL +CMC ; ; Fv ; 0xF5 ; s:I86, t:FLAGOP, w:RW, f:CF=m TEST ; Eb,Ib ; Fv ; 0xF6 /0 ib ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC TEST ; Eb,Ib ; Fv ; 0xF6 /1 ib ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC -NOT ; Eb ; n/a ; 0xF6 /2 ; s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK +NOT ; Eb ; ; 0xF6 /2 ; s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK NEG ; Eb ; Fv ; 0xF6 /3 ; s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK MUL ; Eb ; AL,AX,Fv ; 0xF6 /4 ; s:I86, t:ARITH, w:R|R|W|W, f:MUL IMUL ; Eb ; AL,AX,Fv ; 0xF6 /5 ; s:I86, t:ARITH, w:R|R|W|W, f:MUL DIV ; Eb ; AX,AL,AH,Fv ; 0xF6 /6 ; s:I86, t:ARITH, w:R|R|W|W|W, f:DIV IDIV ; Eb ; AX,AL,AH,Fv ; 0xF6 /7 ; s:I86, t:ARITH, w:R|R|W|W|W, f:DIV -TEST ; Ev,Iz ; Fv ; 0xF7 /0 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 -TEST ; Ev,Iz ; Fv ; 0xF7 /1 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SEXO1 -NOT ; Ev ; n/a ; 0xF7 /2 ; s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK +TEST ; Ev,Iz ; Fv ; 0xF7 /0 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SIGNEXO1 +TEST ; Ev,Iz ; Fv ; 0xF7 /1 iz ; s:I86, t:LOGIC, w:R|R|W, f:LOGIC, a:OP2SIGNEXO1 +NOT ; Ev ; ; 0xF7 /2 ; s:I86, t:LOGIC, w:RW|W, p:HLE|LOCK NEG ; Ev ; Fv ; 0xF7 /3 ; s:I86, t:LOGIC, w:RW|W, f:ARITH, p:HLE|LOCK MUL ; Ev ; rAX,rDX,Fv ; 0xF7 /4 ; s:I86, t:ARITH, w:R|RW|W|W, f:MUL IMUL ; Ev ; rAX,rDX,Fv ; 0xF7 /5 ; s:I86, t:ARITH, w:R|RW|W|W, f:MUL DIV ; Ev ; rAX,rDX,Fv ; 0xF7 /6 ; s:I86, t:ARITH, w:R|RW|RW|W, f:DIV IDIV ; Ev ; rAX,rDX,Fv ; 0xF7 /7 ; s:I86, t:ARITH, w:R|RW|RW|W, f:DIV -CLC ; n/a ; Fv ; 0xF8 ; s:I86, t:FLAGOP, w:W, f:CF=0 -STC ; n/a ; Fv ; 0xF9 ; s:I86, t:FLAGOP, w:W, f:CF=1 -CLI ; n/a ; Fv ; 0xFA ; s:I86, t:FLAGOP, w:RW, f:IF=0 -STI ; n/a ; Fv ; 0xFB ; s:I86, t:FLAGOP, w:RW, f:IF=1 -CLD ; n/a ; Fv ; 0xFC ; s:I86, t:FLAGOP, w:W, f:DF=0 -STD ; n/a ; Fv ; 0xFD ; s:I86, t:FLAGOP, w:W, f:DF=1 +CLC ; ; Fv ; 0xF8 ; s:I86, t:FLAGOP, w:W, f:CF=0 +STC ; ; Fv ; 0xF9 ; s:I86, t:FLAGOP, w:W, f:CF=1 +CLI ; ; Fv ; 0xFA ; s:I86, t:FLAGOP, w:RW, f:IF=0 +STI ; ; Fv ; 0xFB ; s:I86, t:FLAGOP, w:RW, f:IF=1 +CLD ; ; Fv ; 0xFC ; s:I86, t:FLAGOP, w:W, f:DF=0 +STD ; ; Fv ; 0xFD ; s:I86, t:FLAGOP, w:W, f:DF=1 INC ; Eb ; Fv ; 0xFE /0 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK DEC ; Eb ; Fv ; 0xFE /1 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK INC ; Ev ; Fv ; 0xFF /0 ; s:I86, t:ARITH, w:RW|W, f:INCDEC, p:HLE|LOCK diff --git a/isagenerator/instructions/table_0F.dat b/isagenerator/instructions/table_legacy_1.dat similarity index 54% rename from isagenerator/instructions/table_0F.dat rename to isagenerator/instructions/table_legacy_1.dat index de25e91..fb527af 100644 --- a/isagenerator/instructions/table_0F.dat +++ b/isagenerator/instructions/table_legacy_1.dat @@ -22,276 +22,276 @@ LIDT ; Ms ; IDTR ; 0x0F 0x01 /3:m SMSW ; Mw ; CR0 ; 0x0F 0x01 /4:mem ; s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX SMSW ; Rv ; CR0 ; 0x0F 0x01 /4:reg ; s:I286REAL, t:SYSTEM, w:W|R, m:NOSGX LMSW ; Ew ; CR0 ; 0x0F 0x01 /6 ; s:I286REAL, t:SYSTEM, w:R|W, a:SERIAL, m:KERNEL -INVLPG ; Mb ; n/a ; 0x0F 0x01 /7:mem ; s:I486REAL, t:SYSTEM, w:R, a:AG, m:KERNEL|NOV86 +INVLPG ; Mb ; ; 0x0F 0x01 /7:mem ; s:I486REAL, t:SYSTEM, w:R, a:AG, m:KERNEL|NOV86 RSTORSSP ; Mq ; SSP ; 0xF3 0x0F 0x01 /5:mem ; s:CET_SS, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0 -ENCLV ; n/a ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xC0 ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX|VMX -VMCALL ; n/a ; n/a ; NP 0x0F 0x01 /0xC1 ; s:VTX, t:VTX, m:VMX|NOTSX|NOSGX -VMLAUNCH ; n/a ; Fv ; NP 0x0F 0x01 /0xC2 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT -VMRESUME ; n/a ; Fv ; NP 0x0F 0x01 /0xC3 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT -VMXOFF ; n/a ; Fv ; NP 0x0F 0x01 /0xC4 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT -PCONFIG ; n/a ; EAX,RBX,RCX,RDX,Fv ; NP 0x0F 0x01 /0xC5 ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW|W, m:KERNEL, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0 -WRMSRNS ; n/a ; EAX,EDX,ECX,MSR ; NP 0x0F 0x01 /0xC6 ; s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL -WRMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF3 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64 -RDMSRLIST ; n/a ; SMT,DMT,ECX ; 0xF2 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64 -PBNDKB ; n/a ; EAX,RBX,RCX,Fv ; NP 0x0F 0x01 /0xC7 ; s:TSE, t:SYSTEM, w:W|R|R|W, m:KERNEL|O64, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0 -MONITOR ; n/a ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xC8 ; s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86 -MWAIT ; n/a ; EAX,ECX ; NP 0x0F 0x01 /0xC9 ; s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86 -CLAC ; n/a ; Fv ; NP 0x0F 0x01 /0xCA ; s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86 -ERETU ; n/a ; rIP,Fv,rSP,CS,SS,Kv5,SSP,GSBASE,KGSBASE ;0xF3 0x0F 0x01 /0xCA; s:FRED, t:RET, w:W|W|W|W|W|R|CRCW|RW|RW, m:KERNEL|O64|NOTSX, a:F64 -ERETS ; n/a ; rIP,Fv,rSP,Kv5,SSP ; 0xF2 0x0F 0x01 /0xCA ; s:FRED, t:RET, w:W|W|W|R|CRCW, m:KERNEL|O64|NOTSX, a:F64 -STAC ; n/a ; Fv ; NP 0x0F 0x01 /0xCB ; s:SMAP, t:SMAP, w:W, f:AC=1, m:KERNEL|NOV86 -TDCALL ; n/a ; n/a ; 0x66 0x0F 0x01 /0xCC ; s:TDX, t:TDX, m:KERNEL|VMXNROOT -SEAMRET ; n/a ; n/a ; 0x66 0x0F 0x01 /0xCD ; s:TDX, t:TDX, f:VMX, m:SEAMR -SEAMOPS ; n/a ; RAX,RCX,RDX,R8,R9 ; 0x66 0x0F 0x01 /0xCE ; s:TDX, t:TDX, w:RW|R|R|R|R, m:SEAMR -SEAMCALL ; n/a ; RAX ; 0x66 0x0F 0x01 /0xCF ; s:TDX, t:TDX, w:R, f:VMX, m:SEAMN -ENCLS ; n/a ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xCF ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX -XGETBV ; n/a ; ECX,EDX,EAX,XCR ; NP 0x0F 0x01 /0xD0 ; s:XSAVE, t:XSAVE, w:R|W|W|R -XSETBV ; n/a ; ECX,EDX,EAX,XCR ; NP 0x0F 0x01 /0xD1 ; s:XSAVE, t:XSAVE, w:R|R|R|W, m:KERNEL -VMFUNC ; n/a ; n/a ; NP 0x0F 0x01 /0xD4 ; s:VTX, t:VTX, m:VMX|NOSGX -XEND ; n/a ; yIP ; NP 0x0F 0x01 /0xD5 ; s:TSX, t:COND_BR, w:CW, i:RTM -XTEST ; n/a ; Fv ; NP 0x0F 0x01 /0xD6 ; s:TSX, t:LOGIC, w:W, i:RTM, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 -ENCLU ; n/a ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xD7 ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:USER|NOSMM|NOTSX -VMRUN ; n/a ; rAX ; 0x0F 0x01 /0xD8 ; s:SVM, t:SYSTEM, w:R, m:VMXROOT -VMMCALL ; n/a ; n/a ; 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX -VMMCALL ; n/a ; n/a ; 0x66 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX -VMGEXIT ; n/a ; n/a ; 0xF3 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX -VMGEXIT ; n/a ; n/a ; 0xF2 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX -VMLOAD ; n/a ; rAX ; 0x0F 0x01 /0xDA ; s:SVM, t:SYSTEM, w:R, m:VMXROOT -VMSAVE ; n/a ; n/a ; 0x0F 0x01 /0xDB ; s:SVM, t:SYSTEM, m:VMXROOT -STGI ; n/a ; n/a ; 0x0F 0x01 /0xDC ; s:SVM, t:SYSTEM, m:VMXROOT -CLGI ; n/a ; n/a ; 0x0F 0x01 /0xDD ; s:SVM, t:SYSTEM, m:VMXROOT -SKINIT ; n/a ; EAX ; 0x0F 0x01 /0xDE ; s:SVM, t:SYSTEM, w:R, m:VMXROOT -INVLPGA ; n/a ; rAX,ECX ; 0x0F 0x01 /0xDF ; s:SVM, t:SYSTEM, w:R|R, m:VMXROOT -SERIALIZE ; n/a ; n/a ; NP 0x0F 0x01 /0xE8 ; s:SERIALIZE, t:MISC, a:SERIAL -SETSSBSY ; n/a ; SHS0,SSP ; 0xF3 0x0F 0x01 /0xE8 ; s:CET_SS, t:CET, a:SHS, w:RW|RW -XSUSLDTRK ; n/a ; n/a ; 0xF2 0x0F 0x01 /0xE8 ; s:TSXLDTRK, t:MISC -XRESLDTRK ; n/a ; n/a ; 0xF2 0x0F 0x01 /0xE9 ; s:TSXLDTRK, t:MISC -SAVEPREVSSP ; n/a ; SHSS,SSP ; 0xF3 0x0F 0x01 /0xEA ; s:CET_SS, t:CET, w:RW|R, f:CF=t -UIRET ; n/a ; rIP,Fv,sSP,UIF,Kv3,SHS1 ; 0xF3 0x0F 0x01 /0xEC ; s:UINTR, t:RET, a:F64, w:W|W|W|W|R|R, m:O64|NOTSX|NOSGX -TESTUI ; n/a ; UIF,Fv ; 0xF3 0x0F 0x01 /0xED ; s:UINTR, t:UINTR, w:R|W, f:UINTR, m:O64|NOSGX -RDPKRU ; n/a ; EDX,EAX,ECX,PKRU ; NP 0x0F 0x01 /0xEE ; s:PKU, t:MISC, w:W|W|R|R -CLUI ; n/a ; UIF ; 0xF3 0x0F 0x01 /0xEE ; s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX -WRPKRU ; n/a ; EDX,EAX,ECX,PKRU ; NP 0x0F 0x01 /0xEF ; s:PKU, t:MISC, w:R|R|R|W -STUI ; n/a ; UIF ; 0xF3 0x0F 0x01 /0xEF ; s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX -SWAPGS ; n/a ; GSBASE,KGSBASE ; 0x0F 0x01 /0xF8 ; s:LONGMODE, t:SYSTEM, w:RW|RW, m:KERNEL|O64 -RDTSCP ; n/a ; EAX,EDX,ECX,TSC,TSCAUX ; 0x0F 0x01 /0xF9 ; s:RDTSCP, t:SYSTEM, w:W|W|W|R|R -MONITORX ; n/a ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xFA ; s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 -MCOMMIT ; n/a ; Fv ; 0xF3 0x0F 0x01 /0xFA ; s:MCOMMIT, t:MISC, w:W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 -MWAITX ; n/a ; EAX,ECX,EBX ; NP 0x0F 0x01 /0xFB ; s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 -CLZERO ; n/a ; rAX ; 0x0F 0x01 /0xFC ; s:CLZERO, t:MISC, w:R -RDPRU ; n/a ; EAX,EDX,ECX,Fv ; 0x0F 0x01 /0xFD ; s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 -RMPQUERY ; n/a ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:R|RW|W|RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPQUERY -INVLPGB ; n/a ; rAX,ECX,EDX ; 0x0F 0x01 /0xFE ; s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL -RMPADJUST ; n/a ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:R|RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL -RMPUPDATE ; n/a ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL -TLBSYNC ; n/a ; n/a ; 0x0F 0x01 /0xFF ; s:INVLPGB, t:SYSTEM, m:NOREAL|KERNEL -PSMASH ; n/a ; RAX,Fv ; 0xF3 0x0F 0x01 /0xFF ; s:SNP, t:SYSTEM, w:RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL -PVALIDATE ; n/a ; rAX,ECX,EDX,Fv ; 0xF2 0x0F 0x01 /0xFF ; s:SNP, t:SYSTEM, w:RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m|CF=m, m:KERNEL +ENCLV ; ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xC0 ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX|VMX +VMCALL ; ; ; NP 0x0F 0x01 /0xC1 ; s:VTX, t:VTX, m:VMX|NOTSX|NOSGX +VMLAUNCH ; ; Fv ; NP 0x0F 0x01 /0xC2 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +VMRESUME ; ; Fv ; NP 0x0F 0x01 /0xC3 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +VMXOFF ; ; Fv ; NP 0x0F 0x01 /0xC4 ; s:VTX, t:VTX, w:W, f:VMX, m:VMXROOT +PCONFIG ; ; EAX,RBX,RCX,RDX,Fv ; NP 0x0F 0x01 /0xC5 ; s:PCONFIG, t:PCONFIG, w:R|RW|RW|RW|W, m:KERNEL, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0 +WRMSRNS ; ; EAX,EDX,ECX,MSR ; NP 0x0F 0x01 /0xC6 ; s:WRMSRNS, t:SYSTEM, w:R|R|R|W, m:KERNEL +WRMSRLIST ; ; SMT,DMT,ECX ; 0xF3 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|R|RW, m:KERNEL|O64 +RDMSRLIST ; ; SMT,DMT,ECX ; 0xF2 0x0F 0x01 /0xC6 ; s:MSRLIST, t:SYSTEM, w:R|W|RW, m:KERNEL|O64 +PBNDKB ; ; EAX,RBX,RCX,Fv ; NP 0x0F 0x01 /0xC7 ; s:TSE, t:SYSTEM, w:W|R|R|W, m:KERNEL|O64, f:CF=0|ZF=m|PF=0|AF=0|OF=0|SF=0 +MONITOR ; ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xC8 ; s:SSE3, t:MISC, w:R|R|R, i:MONITOR, m:KERNEL|NOV86 +MWAIT ; ; EAX,ECX ; NP 0x0F 0x01 /0xC9 ; s:SSE3, t:MISC, w:RW|R, i:MONITOR, m:KERNEL|NOV86 +CLAC ; ; Fv ; NP 0x0F 0x01 /0xCA ; s:SMAP, t:SMAP, w:W, f:AC=0, m:KERNEL|NOV86 +ERETU ; ; CS,rIP,Fv,SS,rSP,Kv5,SSP,GSBASE,KGSBASE ;0xF3 0x0F 0x01 /0xCA; s:FRED, t:RET, w:W|W|W|W|W|R|CRCW|RW|RW, m:KERNEL|O64|NOTSX, a:F64 +ERETS ; ; rIP,Fv,rSP,Kv5,SSP ; 0xF2 0x0F 0x01 /0xCA ; s:FRED, t:RET, w:W|W|W|R|CRCW, m:KERNEL|O64|NOTSX, a:F64 +STAC ; ; Fv ; NP 0x0F 0x01 /0xCB ; s:SMAP, t:SMAP, w:W, f:AC=1, m:KERNEL|NOV86 +TDCALL ; ; ; 0x66 0x0F 0x01 /0xCC ; s:TDX, t:TDX, m:KERNEL|VMXNROOT +SEAMRET ; ; ; 0x66 0x0F 0x01 /0xCD ; s:TDX, t:TDX, f:VMX, m:SEAMR +SEAMOPS ; ; RAX,RCX,RDX,R8,R9 ; 0x66 0x0F 0x01 /0xCE ; s:TDX, t:TDX, w:RW|R|R|R|R, m:SEAMR +SEAMCALL ; ; RAX ; 0x66 0x0F 0x01 /0xCF ; s:TDX, t:TDX, w:R, f:VMX, m:SEAMN +ENCLS ; ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xCF ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:KERNEL|NOSMM|NOTSX +XGETBV ; ; ECX,EDX,EAX,XCR ; NP 0x0F 0x01 /0xD0 ; s:XSAVE, t:XSAVE, w:R|W|W|R +XSETBV ; ; ECX,EDX,EAX,XCR ; NP 0x0F 0x01 /0xD1 ; s:XSAVE, t:XSAVE, w:R|R|R|W, m:KERNEL +VMFUNC ; ; ; NP 0x0F 0x01 /0xD4 ; s:VTX, t:VTX, m:VMX|NOSGX +XEND ; ; yIP ; NP 0x0F 0x01 /0xD5 ; s:TSX, t:COND_BR, w:CW, i:RTM +XTEST ; ; Fv ; NP 0x0F 0x01 /0xD6 ; s:TSX, t:LOGIC, w:W, i:RTM, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +ENCLU ; ; EAX,RBX,RCX,RDX ; NP 0x0F 0x01 /0xD7 ; s:SGX, t:SGX, w:R|CRW|CRW|CRW, m:USER|NOSMM|NOTSX +VMRUN ; ; rAX ; 0x0F 0x01 /0xD8 ; s:SVM, t:SYSTEM, w:R, m:VMXROOT +VMMCALL ; ; ; NP 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX +VMMCALL ; ; ; 0x66 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX +VMGEXIT ; ; ; 0xF3 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX +VMGEXIT ; ; ; 0xF2 0x0F 0x01 /0xD9 ; s:SVM, t:SYSTEM, m:VMX +VMLOAD ; ; rAX ; 0x0F 0x01 /0xDA ; s:SVM, t:SYSTEM, w:R, m:VMXROOT +VMSAVE ; ; ; 0x0F 0x01 /0xDB ; s:SVM, t:SYSTEM, m:VMXROOT +STGI ; ; ; 0x0F 0x01 /0xDC ; s:SVM, t:SYSTEM, m:VMXROOT +CLGI ; ; ; 0x0F 0x01 /0xDD ; s:SVM, t:SYSTEM, m:VMXROOT +SKINIT ; ; EAX ; 0x0F 0x01 /0xDE ; s:SVM, t:SYSTEM, w:R, m:VMXROOT +INVLPGA ; ; rAX,ECX ; 0x0F 0x01 /0xDF ; s:SVM, t:SYSTEM, w:R|R, m:VMXROOT +SERIALIZE ; ; ; NP 0x0F 0x01 /0xE8 ; s:SERIALIZE, t:MISC, a:SERIAL +SETSSBSY ; ; SHS0,SSP ; 0xF3 0x0F 0x01 /0xE8 ; s:CET_SS, t:CET, a:SHS, w:RW|RW +XSUSLDTRK ; ; ; 0xF2 0x0F 0x01 /0xE8 ; s:TSXLDTRK, t:MISC +XRESLDTRK ; ; ; 0xF2 0x0F 0x01 /0xE9 ; s:TSXLDTRK, t:MISC +SAVEPREVSSP ; ; SHSS,SSP ; 0xF3 0x0F 0x01 /0xEA ; s:CET_SS, t:CET, w:RW|R, f:CF=t +UIRET ; ; rIP,Fv,sSP,UIF,Kv3,SHS1 ; 0xF3 0x0F 0x01 /0xEC ; s:UINTR, t:RET, a:F64, w:W|W|W|W|R|R, m:O64|NOTSX|NOSGX +TESTUI ; ; UIF,Fv ; 0xF3 0x0F 0x01 /0xED ; s:UINTR, t:UINTR, w:R|W, f:UINTR, m:O64|NOSGX +RDPKRU ; ; EDX,EAX,ECX,PKRU ; NP 0x0F 0x01 /0xEE ; s:PKU, t:MISC, w:W|W|R|R +CLUI ; ; UIF ; 0xF3 0x0F 0x01 /0xEE ; s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX +WRPKRU ; ; EDX,EAX,ECX,PKRU ; NP 0x0F 0x01 /0xEF ; s:PKU, t:MISC, w:R|R|R|W +STUI ; ; UIF ; 0xF3 0x0F 0x01 /0xEF ; s:UINTR, t:UINTR, w:W, m:O64|NOTSX|NOSGX +SWAPGS ; ; GSBASE,KGSBASE ; 0x0F 0x01 /0xF8 ; s:LONGMODE, t:SYSTEM, w:RW|RW, m:KERNEL|O64 +RDTSCP ; ; EAX,EDX,ECX,TSC,TSCAUX ; 0x0F 0x01 /0xF9 ; s:RDTSCP, t:SYSTEM, w:W|W|W|R|R +MONITORX ; ; pAXb,ECX,EDX ; NP 0x0F 0x01 /0xFA ; s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 +MCOMMIT ; ; Fv ; 0xF3 0x0F 0x01 /0xFA ; s:MCOMMIT, t:MISC, w:W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +MWAITX ; ; EAX,ECX,EBX ; NP 0x0F 0x01 /0xFB ; s:MWAITT, t:SYSTEM, w:R|R|R, m:KERNEL|NOV86 +CLZERO ; ; rAX ; 0x0F 0x01 /0xFC ; s:CLZERO, t:MISC, w:R +RDPRU ; ; EAX,EDX,ECX,Fv ; NP 0x0F 0x01 /0xFD ; s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RMPQUERY ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:R|RW|W|RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPQUERY +INVLPGB ; ; rAX,ECX,EDX ; NP 0x0F 0x01 /0xFE ; s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL +RMPADJUST ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:R|RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL +RMPUPDATE ; ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL +TLBSYNC ; ; ; NP 0x0F 0x01 /0xFF ; s:INVLPGB, t:SYSTEM, m:NOREAL|KERNEL +PSMASH ; ; RAX,Fv ; 0xF3 0x0F 0x01 /0xFF ; s:SNP, t:SYSTEM, w:RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, m:O64|KERNEL +PVALIDATE ; ; rAX,ECX,EDX,Fv ; 0xF2 0x0F 0x01 /0xFF ; s:SNP, t:SYSTEM, w:RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m|CF=m, m:KERNEL LAR ; Gv,Mw ; Fv ; 0x0F 0x02 /r:mem ; s:I286PROT, t:SYSTEM, w:CW|R|W, f:ZF=m, m:NOREAL LAR ; Gv,Rz ; Fv ; 0x0F 0x02 /r:reg ; s:I286PROT, t:SYSTEM, w:CW|R|W, f:ZF=m, m:NOREAL LSL ; Gv,Mw ; Fv ; 0x0F 0x03 /r:mem ; s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL LSL ; Gv,Rz ; Fv ; 0x0F 0x03 /r:reg ; s:I286PROT, t:SYSTEM, w:RW|R|W, f:ZF=m, m:NOREAL -#LOADALL ; n/a ; BANK ; 0x0F 0x05 ; s:I486REAL, t:UNDOC, w:R -SYSCALL ; n/a ; STAR,LSTAR,FMASK,SS,RCX,R11,CS,rIP,Fv,SSP ; 0x0F 0x05 ; s:AMD, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW|RW, a:F64|CETT, i:FSC, m:NOSGX -CLTS ; n/a ; CR0 ; 0x0F 0x06 ; s:I286REAL, t:SYSTEM, w:W, m:KERNEL|NOV86 -#LOADALLD ; n/a ; BANK ; 0x0F 0x07 ; s:I486REAL, t:UNDOC, w:R -SYSRET ; n/a ; STAR,SS,rCX,R11,CS,rIP,Fv,SSP ; 0x0F 0x07 ; s:AMD, t:SYSRET, w:R|W|R|R|W|W|W|W, i:FSC, m:KERNEL -INVD ; n/a ; n/a ; 0x0F 0x08 ; s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 -WBINVD ; n/a ; n/a ; 0x0F 0x09 ; s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 -WBNOINVD ; n/a ; n/a ; a0xF3 0x0F 0x09 ; s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86 -# Not supported by regulat x86 CPUs. -#CL1INVMB ; n/a ; n/a ; 0x0F 0x0A ; s:SCC, t:SYSTEM, m:NO64 -UD2 ; n/a ; n/a ; 0x0F 0x0B ; s:PPRO, t:MISC -PREFETCHE ; Mb ; n/a ; 0x0F 0x0D /0:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /0:reg ; s:PPRO, t:NOP, w:N|N -PREFETCHW ; Mb ; n/a ; 0x0F 0x0D /1:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /1:reg ; s:PPRO, t:NOP, w:N|N -PREFETCHWT1 ; Mb ; n/a ; 0x0F 0x0D /2:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /2:reg ; s:PPRO, t:NOP, w:N|N -PREFETCHM ; Mb ; n/a ; 0x0F 0x0D /3:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /3:reg ; s:PPRO, t:NOP, w:N|N -PREFETCH ; Mb ; n/a ; 0x0F 0x0D /4:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /4:reg ; s:PPRO, t:NOP, w:N|N -PREFETCH ; Mb ; n/a ; 0x0F 0x0D /5:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /5:reg ; s:PPRO, t:NOP, w:N|N -PREFETCH ; Mb ; n/a ; 0x0F 0x0D /6:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /6:reg ; s:PPRO, t:NOP, w:N|N -PREFETCH ; Mb ; n/a ; 0x0F 0x0D /7:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P -NOP ; Ev,Gv ; n/a ; 0x0F 0x0D /7:reg ; s:PPRO, t:NOP, w:N|N +#LOADALL ; ; BANK ; 0x0F 0x05 ; s:I486REAL, t:UNDOC, w:R +SYSCALL ; ; STAR,LSTAR,FMASK,SS,RCX,R11,CS,rIP,Fv,SSP ; 0x0F 0x05 ; s:AMD, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW|RW, a:F64|CETT, i:FSC, m:NOSGX +CLTS ; ; CR0 ; 0x0F 0x06 ; s:I286REAL, t:SYSTEM, w:W, m:KERNEL|NOV86 +#LOADALLD ; ; BANK ; 0x0F 0x07 ; s:I486REAL, t:UNDOC, w:R +SYSRET ; ; STAR,SS,rCX,R11,CS,rIP,Fv,SSP ; 0x0F 0x07 ; s:AMD, t:SYSRET, w:R|W|R|R|W|W|W|W, i:FSC, m:KERNEL +INVD ; ; ; 0x0F 0x08 ; s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 +WBINVD ; ; ; 0x0F 0x09 ; s:I486REAL, t:SYSTEM, a:SERIAL, m:KERNEL|NOV86 +WBNOINVD ; ; ; repz 0x0F 0x09 ; s:WBNOINVD, t:WBNOINVD, m:KERNEL|NOV86 +# Not supported by regular x86 CPUs. +#CL1INVMB ; ; ; 0x0F 0x0A ; s:SCC, t:SYSTEM, m:NO64 +UD2 ; ; ; 0x0F 0x0B ; s:PPRO, t:MISC +PREFETCHE ; Mb ; ; 0x0F 0x0D /0:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /0:reg ; s:PPRO, t:NOP, w:N|N +PREFETCHW ; Mb ; ; 0x0F 0x0D /1:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /1:reg ; s:PPRO, t:NOP, w:N|N +PREFETCHWT1 ; Mb ; ; 0x0F 0x0D /2:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /2:reg ; s:PPRO, t:NOP, w:N|N +PREFETCHM ; Mb ; ; 0x0F 0x0D /3:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /3:reg ; s:PPRO, t:NOP, w:N|N +PREFETCH ; Mb ; ; 0x0F 0x0D /4:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /4:reg ; s:PPRO, t:NOP, w:N|N +PREFETCH ; Mb ; ; 0x0F 0x0D /5:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /5:reg ; s:PPRO, t:NOP, w:N|N +PREFETCH ; Mb ; ; 0x0F 0x0D /6:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /6:reg ; s:PPRO, t:NOP, w:N|N +PREFETCH ; Mb ; ; 0x0F 0x0D /7:mem ; s:PREFETCH_NOP, t:PREFETCH, w:P +NOP ; Ev,Gv ; ; 0x0F 0x0D /7:reg ; s:PPRO, t:NOP, w:N|N -FEMMS ; n/a ; n/a ; 0x0F 0x0E ; s:3DNOW, t:MMX, c:FEMMS +FEMMS ; ; ; 0x0F 0x0E ; s:3DNOW, t:MMX, c:FEMMS # 0x10 - 0x1F -MOVUPS ; Vps,Wps ; n/a ; NP 0x0F 0x10 /r ; s:SSE, t:DATAXFER, w:W|R, e:4 -MOVUPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x10 /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 -MOVSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x10 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x10 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVUPS ; Wps,Vps ; n/a ; NP 0x0F 0x11 /r ; s:SSE, t:DATAXFER, w:W|R, e:4 -MOVUPD ; Wpd,Vpd ; n/a ; 0x66 0x0F 0x11 /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 -MOVSS ; Wss,Vss ; n/a ; 0xF3 0x0F 0x11 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVSD ; Wsd,Vsd ; n/a ; 0xF2 0x0F 0x11 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVHLPS ; Vq,Wq ; n/a ; NP 0x0F 0x12 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVLPD ; Vsd,Mq ; n/a ; 0x66 0x0F 0x12 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVSLDUP ; Vx,Wx ; n/a ; 0xF3 0x0F 0x12 /r ; s:SSE3, t:DATAXFER, w:W|R, e:4 -MOVDDUP ; Vdq,Wq ; n/a ; 0xF2 0x0F 0x12 /r ; s:SSE3, t:DATAXFER, w:W|R, e:5 -MOVLPS ; Mq,Vps ; n/a ; NP 0x0F 0x13 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVLPD ; Mq,Vpd ; n/a ; 0x66 0x0F 0x13 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 -UNPCKLPS ; Vx,Wx ; n/a ; NP 0x0F 0x14 /r ; s:SSE, t:SSE, w:RW|R, e:4 -UNPCKLPD ; Vx,Wx ; n/a ; 0x66 0x0F 0x14 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -UNPCKHPS ; Vx,Wx ; n/a ; NP 0x0F 0x15 /r ; s:SSE, t:SSE, w:RW|R, e:4 -UNPCKHPD ; Vx,Wx ; n/a ; 0x66 0x0F 0x15 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -MOVHPS ; Vq,Mq ; n/a ; NP 0x0F 0x16 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVLHPS ; Vq,Uq ; n/a ; NP 0x0F 0x16 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7 -MOVHPD ; Vq,Mq ; n/a ; 0x66 0x0F 0x16 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVSHDUP ; Vx,Wx ; n/a ; 0xF3 0x0F 0x16 /r ; s:SSE3, t:DATAXFER, w:W|R, e:4 -MOVHPS ; Mq,Vq ; n/a ; NP 0x0F 0x17 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 -MOVHPD ; Mq,Vq ; n/a ; 0x66 0x0F 0x17 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVUPS ; Vps,Wps ; ; NP 0x0F 0x10 /r ; s:SSE, t:DATAXFER, w:W|R, e:4 +MOVUPD ; Vpd,Wpd ; ; 0x66 0x0F 0x10 /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 +MOVSS ; Vss,Wss ; ; 0xF3 0x0F 0x10 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x10 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVUPS ; Wps,Vps ; ; NP 0x0F 0x11 /r ; s:SSE, t:DATAXFER, w:W|R, e:4 +MOVUPD ; Wpd,Vpd ; ; 0x66 0x0F 0x11 /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 +MOVSS ; Wss,Vss ; ; 0xF3 0x0F 0x11 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVSD ; Wsd,Vsd ; ; 0xF2 0x0F 0x11 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVHLPS ; Vq,Wq ; ; NP 0x0F 0x12 /r ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLPD ; Vsd,Mq ; ; 0x66 0x0F 0x12 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVSLDUP ; Vx,Wx ; ; 0xF3 0x0F 0x12 /r ; s:SSE3, t:DATAXFER, w:W|R, e:4 +MOVDDUP ; Vdq,Wq ; ; 0xF2 0x0F 0x12 /r ; s:SSE3, t:DATAXFER, w:W|R, e:5 +MOVLPS ; Mq,Vps ; ; NP 0x0F 0x13 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLPD ; Mq,Vpd ; ; 0x66 0x0F 0x13 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 +UNPCKLPS ; Vx,Wx ; ; NP 0x0F 0x14 /r ; s:SSE, t:SSE, w:RW|R, e:4 +UNPCKLPD ; Vx,Wx ; ; 0x66 0x0F 0x14 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +UNPCKHPS ; Vx,Wx ; ; NP 0x0F 0x15 /r ; s:SSE, t:SSE, w:RW|R, e:4 +UNPCKHPD ; Vx,Wx ; ; 0x66 0x0F 0x15 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +MOVHPS ; Vq,Mq ; ; NP 0x0F 0x16 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVLHPS ; Vq,Uq ; ; NP 0x0F 0x16 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7 +MOVHPD ; Vq,Mq ; ; 0x66 0x0F 0x16 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVSHDUP ; Vx,Wx ; ; 0xF3 0x0F 0x16 /r ; s:SSE3, t:DATAXFER, w:W|R, e:4 +MOVHPS ; Mq,Vq ; ; NP 0x0F 0x17 /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:5 +MOVHPD ; Mq,Vq ; ; 0x66 0x0F 0x17 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:5 # Default wide-nops/PREFETCH instructions. -PREFETCHNTA ; Mb ; n/a ; 0x0F 0x18 /0:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; 0x0F 0x18 /0:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT0 ; Mb ; n/a ; 0x0F 0x18 /1:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; 0x0F 0x18 /1:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT1 ; Mb ; n/a ; 0x0F 0x18 /2:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT2 ; Mb ; n/a ; 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; 0x0F 0x18 /6 ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; 0x0F 0x18 /7 ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; 0x0F 0x19 /r ; s:PPRO, t:WIDENOP, w:N +PREFETCHNTA ; Mb ; ; 0x0F 0x18 /0:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; 0x0F 0x18 /0:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT0 ; Mb ; ; 0x0F 0x18 /1:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; 0x0F 0x18 /1:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT1 ; Mb ; ; 0x0F 0x18 /2:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT2 ; Mb ; ; 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; 0x0F 0x18 /6 ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; 0x0F 0x18 /7 ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; 0x0F 0x19 /r ; s:PPRO, t:WIDENOP, w:N # PREFETCHITI instructions. Most of them duplicates of the above, since they are also present when the PREFETCHIT feature # is enabled (which applies to the entire opcode). -PREFETCHNTA ; Mb ; n/a ; piti 0x0F 0x18 /0:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; piti 0x0F 0x18 /0:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT0 ; Mb ; n/a ; piti 0x0F 0x18 /1:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; piti 0x0F 0x18 /1:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT1 ; Mb ; n/a ; piti 0x0F 0x18 /2:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; piti 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHT2 ; Mb ; n/a ; piti 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P -NOP ; Ev ; n/a ; piti 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; piti 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; piti 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N -PREFETCHIT1 ; Mb ; n/a ;piti riprel 0x0F 0x18 /6:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64 -NOP ; Ev ; n/a ; piti 0x0F 0x18 /6:mem ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; piti 0x0F 0x18 /6:reg ; s:PPRO, t:WIDENOP, w:N -PREFETCHIT0 ; Mb ; n/a ;piti riprel 0x0F 0x18 /7:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64 -NOP ; Ev ; n/a ; piti 0x0F 0x18 /7:mem ; s:PPRO, t:WIDENOP, w:N -NOP ; Ev ; n/a ; piti 0x0F 0x18 /7:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHNTA ; Mb ; ; piti 0x0F 0x18 /0:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; piti 0x0F 0x18 /0:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT0 ; Mb ; ; piti 0x0F 0x18 /1:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; piti 0x0F 0x18 /1:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT1 ; Mb ; ; piti 0x0F 0x18 /2:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; piti 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHT2 ; Mb ; ; piti 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P +NOP ; Ev ; ; piti 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; piti 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; piti 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N +PREFETCHIT1 ; Mb ; ;piti riprel 0x0F 0x18 /6:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64 +NOP ; Ev ; ; piti 0x0F 0x18 /6:mem ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; piti 0x0F 0x18 /6:reg ; s:PPRO, t:WIDENOP, w:N +PREFETCHIT0 ; Mb ; ;piti riprel 0x0F 0x18 /7:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64 +NOP ; Ev ; ; piti 0x0F 0x18 /7:mem ; s:PPRO, t:WIDENOP, w:N +NOP ; Ev ; ; piti 0x0F 0x18 /7:reg ; s:PPRO, t:WIDENOP, w:N # MPX instructions. According to the SDM, MPX instructions have 64 bit op & address size in 64 bit mode, no matter # if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here. -# MPX not used, these guys are wide NOPs. -NOP ; Ev,Gv ; n/a ; 0x0F 0x1A /r ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Gv,Ev ; n/a ; 0x0F 0x1B /r ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; 0x0F 0x1C /r ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; 0x0F 0x1D /r ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; 0x0F 0x1E /r ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; 0x0F 0x1F /r ; s:PPRO, t:WIDENOP, w:N|N +# NOP instructions. Decode by default if MPX, CLDEMODE or CET is not enabled. +NOP ; Ev,Gv ; ; 0x0F 0x1A /r ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Gv,Ev ; ; 0x0F 0x1B /r ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; 0x0F 0x1C /r ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; 0x0F 0x1D /r ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; 0x0F 0x1E /r ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; 0x0F 0x1F /r ; s:PPRO, t:WIDENOP, w:N|N # Features that are mapped onto wide NOPs. -# MPX -BNDLDX ; rBl,Mmib ; n/a ; mpx 0x0F 0x1A /r:mem mib ; s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67 -NOP ; Gv,Ev ; n/a ; mpx 0x0F 0x1A /r:reg ; s:PPRO, t:WIDENOP, w:N|N -BNDMOV ; rBl,mBl ; n/a ; mpx 0x66 0x0F 0x1A /r ; s:MPX, t:MPX, w:W|R, a:NOA16|I67 -BNDCL ; rBl,Ey ; n/a ; mpx 0xF3 0x0F 0x1A /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67 -BNDCU ; rBl,Ey ; n/a ; mpx 0xF2 0x0F 0x1A /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67 -BNDSTX ; Mmib,rBl ; n/a ; mpx 0x0F 0x1B /r:mem mib ; s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67 -NOP ; Gv,Ev ; n/a ; mpx 0x0F 0x1B /r:reg ; s:PPRO, t:WIDENOP, w:N|N -BNDMOV ; mBl,rBl ; n/a ; mpx 0x66 0x0F 0x1B /r ; s:MPX, t:MPX, w:W|R, a:NOA16|I67 -BNDMK ; rBl,My ; n/a ; mpx 0xF3 0x0F 0x1B /r:mem ; s:MPX, t:MPX, w:W|R, a:F64|NOA16|NORIPREL|I67 -NOP ; Gv,Ev ; n/a ; mpx 0xF3 0x0F 0x1B /r:reg ; s:PPRO, t:WIDENOP, w:N|N -BNDCN ; rBl,Ey ; n/a ; mpx 0xF2 0x0F 0x1B /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67 +# MPX instructions. +BNDLDX ; rBl,Mmib ; ; mpx NP 0x0F 0x1A /r:mem mib ; s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67|NOREX2 +NOP ; Gv,Ev ; ; mpx NP 0x0F 0x1A /r:reg ; s:PPRO, t:WIDENOP, w:N|N +BNDMOV ; rBl,mBl ; ; mpx 0x66 0x0F 0x1A /r ; s:MPX, t:MPX, w:W|R, a:NOA16|I67|NOREX2 +BNDCL ; rBl,Ey ; ; mpx 0xF3 0x0F 0x1A /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67|NOREX2 +BNDCU ; rBl,Ey ; ; mpx 0xF2 0x0F 0x1A /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67|NOREX2 +BNDSTX ; Mmib,rBl ; ; mpx NP 0x0F 0x1B /r:mem mib ; s:MPX, t:MPX, w:W|R, a:AG|NOA16|NORIPREL|I67|NOREX2 +NOP ; Gv,Ev ; ; mpx NP 0x0F 0x1B /r:reg ; s:PPRO, t:WIDENOP, w:N|N +BNDMOV ; mBl,rBl ; ; mpx 0x66 0x0F 0x1B /r ; s:MPX, t:MPX, w:W|R, a:NOA16|I67|NOREX2 +BNDMK ; rBl,My ; ; mpx 0xF3 0x0F 0x1B /r:mem ; s:MPX, t:MPX, w:W|R, a:F64|NOA16|NORIPREL|I67|NOREX2 +NOP ; Gv,Ev ; ; mpx 0xF3 0x0F 0x1B /r:reg ; s:PPRO, t:WIDENOP, w:N|N +BNDCN ; rBl,Ey ; ; mpx 0xF2 0x0F 0x1B /r ; s:MPX, t:MPX, w:R|R, a:AG|F64|I67|NOREX2 -# CLDEMOTE -CLDEMOTE ; Mb ; n/a ; cldm NP 0x0F 0x1C /0:mem ; s:CLDEMOTE, t:CLDEMOTE, w:P -NOP ; Ev,Gv ; n/a ; cldm 0x66 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0xF3 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0xF2 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /0:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /1 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /2 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /3 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /4 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /5 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /6 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Ev,Gv ; n/a ; cldm 0x0F 0x1C /7 ; s:PPRO, t:WIDENOP, w:N|N +# CLDEMOTE instruction. +CLDEMOTE ; Mb ; ; cldm NP 0x0F 0x1C /0:mem ; s:CLDEMOTE, t:CLDEMOTE, w:P +NOP ; Ev,Gv ; ; cldm 0x66 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0xF3 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0xF2 0x0F 0x1C /0:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /0:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /1 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /2 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /3 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /4 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /5 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /6 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Ev,Gv ; ; cldm 0x0F 0x1C /7 ; s:PPRO, t:WIDENOP, w:N|N -# CET -NOP ; Mv,Gv ; n/a ; cet 0x0F 0x1E /r:mem ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /1:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet rexw 0x0F 0x1E /1:reg ; s:PPRO, t:WIDENOP, w:N|N -RDSSPD ; Rd ; SSP ; cet a0xF3 0x0F 0x1E /1:reg ; s:CET_SS, t:CET, c:RSSSP, w:W|R -RDSSPQ ; Rq ; SSP ;cet a0xF3 rexw 0x0F 0x1E /1:reg ; s:CET_SS, t:CET, c:RSSSP, w:W|R -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /2:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /3:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /4:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /5:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /6:reg ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xF8 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xF9 ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFA ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFB ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFC ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFD ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFE ; s:PPRO, t:WIDENOP, w:N|N -NOP ; Rv,Gv ; n/a ; cet 0x0F 0x1E /0xFF ; s:PPRO, t:WIDENOP, w:N|N -ENDBR64 ; n/a ; n/a ; cet a0xF3 0x0F 0x1E /0xFA ; s:CET_IBT, t:CET, c:ENDBR -ENDBR32 ; n/a ; n/a ; cet a0xF3 0x0F 0x1E /0xFB ; s:CET_IBT, t:CET, c:ENDBR +# CET instructions. +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /0:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /1:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /1:reg ; s:PPRO, t:WIDENOP, w:N|N +RDSSPD ; Rd ; SSP ; cet repz 0x0F 0x1E /1:reg ; s:CET_SS, t:CET, c:RSSSP, w:W|R +RDSSPQ ; Rq ; SSP ; cet repz rexw 0x0F 0x1E /1:reg ; s:CET_SS, t:CET, c:RSSSP, w:W|R +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /2:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /2:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /3:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /3:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /4:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /4:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /5:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /5:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /6:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /6:reg ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Mv,Gv ; ; cet 0x0F 0x1E /7:mem ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xF8 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xF9 ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFA ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFB ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFC ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFD ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFE ; s:PPRO, t:WIDENOP, w:N|N +NOP ; Rv,Gv ; ; cet 0x0F 0x1E /0xFF ; s:PPRO, t:WIDENOP, w:N|N +ENDBR64 ; ; ; cet repz 0x0F 0x1E /0xFA ; s:CET_IBT, t:CET, c:ENDBR +ENDBR32 ; ; ; cet repz 0x0F 0x1E /0xFB ; s:CET_IBT, t:CET, c:ENDBR # 0x20 - 0x2F -MOV ; Ry,Cy ; n/a ; 0x0F 0x20 /r ; s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64, m:KERNEL|NOV86 -MOV ; Ry,Dy ; n/a ; 0x0F 0x21 /r ; s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64, m:KERNEL|NOV86 -MOV ; Cy,Ry ; n/a ; 0x0F 0x22 /r ; s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64|SERIAL, m:KERNEL|NOV86 -MOV ; Dy,Ry ; n/a ; 0x0F 0x23 /r ; s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64|SERIAL, m:KERNEL|NOV86 -MOV ; Ry,Ty ; n/a ; 0x0F 0x24 /r ; s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86|NO64 -MOV ; Ty,Ry ; n/a ; 0x0F 0x26 /r ; s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86|NO64 -MOVAPS ; Vps,Wps ; n/a ; NP 0x0F 0x28 /r ; s:SSE, t:DATAXFER, w:W|R, e:1 -MOVAPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x28 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 -MOVAPS ; Wps,Vps ; n/a ; NP 0x0F 0x29 /r ; s:SSE, t:DATAXFER, w:W|R, e:1 -MOVAPD ; Wpd,Vpd ; n/a ; 0x66 0x0F 0x29 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 -CVTPI2PS ; Vq,Qq ; n/a ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R -CVTPI2PD ; Vpd,Qq ; n/a ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R -CVTSI2SS ; Vss,Ey ; n/a ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTSI2SD ; Vsd,Ey ; n/a ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -MOVNTPS ; Mps,Vps ; n/a ; NP 0x0F 0x2B /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:1 -MOVNTPD ; Mpd,Vpd ; n/a ; 0x66 0x0F 0x2B /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 -MOVNTSS ; Mss,Vss ; n/a ; 0xF3 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R -MOVNTSD ; Msd,Vsd ; n/a ; 0xF2 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R -CVTTPS2PI ; Pq,Wq ; n/a ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R -CVTTPD2PI ; Pq,Wpd ; n/a ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R -CVTTSS2SI ; Gy,Wss ; n/a ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTTSD2SI ; Gy,Wsd ; n/a ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTPS2PI ; Pq,Wq ; n/a ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R -CVTPD2PI ; Pq,Wpd ; n/a ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R -CVTSS2SI ; Gy,Wss ; n/a ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3 -CVTSD2SI ; Gy,Wsd ; n/a ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +MOV ; Ry,Cy ; ; 0x0F 0x20 /r ; s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64, m:KERNEL|NOV86 +MOV ; Ry,Dy ; ; 0x0F 0x21 /r ; s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64, m:KERNEL|NOV86 +MOV ; Cy,Ry ; ; 0x0F 0x22 /r ; s:I86, t:DATAXFER, c:MOV_CR, w:W|R, a:LOCKSP|MFR|F64|SERIAL, m:KERNEL|NOV86 +MOV ; Dy,Ry ; ; 0x0F 0x23 /r ; s:I86, t:DATAXFER, c:MOV_DR, w:W|R, a:MFR|F64|SERIAL, m:KERNEL|NOV86 +MOV ; Ry,Ty ; ; 0x0F 0x24 /r ; s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86|NO64 +MOV ; Ty,Ry ; ; 0x0F 0x26 /r ; s:I86, t:DATAXFER, c:MOV_TR, w:W|R, a:MFR|F64, m:KERNEL|NOV86|NO64 +MOVAPS ; Vps,Wps ; ; NP 0x0F 0x28 /r ; s:SSE, t:DATAXFER, w:W|R, e:1 +MOVAPD ; Vpd,Wpd ; ; 0x66 0x0F 0x28 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVAPS ; Wps,Vps ; ; NP 0x0F 0x29 /r ; s:SSE, t:DATAXFER, w:W|R, e:1 +MOVAPD ; Wpd,Vpd ; ; 0x66 0x0F 0x29 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 +CVTPI2PS ; Vq,Qq ; ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R +CVTPI2PD ; Vpd,Qq ; ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R +CVTSI2SS ; Vss,Ey ; ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3 +CVTSI2SD ; Vsd,Ey ; ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +MOVNTPS ; Mps,Vps ; ; NP 0x0F 0x2B /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:1 +MOVNTPD ; Mpd,Vpd ; ; 0x66 0x0F 0x2B /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVNTSS ; Mss,Vss ; ; 0xF3 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R +MOVNTSD ; Msd,Vsd ; ; 0xF2 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R +CVTTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R +CVTTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R +CVTTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3 +CVTTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +CVTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R +CVTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R +CVTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3 +CVTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3 UCOMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2E /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS UCOMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2E /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 COMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2F /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3 COMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2F /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3 # 0x30 - 0x3F -WRMSR ; n/a ; EAX,EDX,ECX,MSR ; 0x0F 0x30 ; s:PENTIUMREAL, t:SYSTEM, w:R|R|R|W, a:SERIAL, m:KERNEL|NOV86, i:MSR -RDTSC ; n/a ; EAX,EDX,TSC ; 0x0F 0x31 ; s:PENTIUMREAL, t:SYSTEM, w:W|W|R -RDMSR ; n/a ; EAX,EDX,ECX,MSR ; 0x0F 0x32 ; s:PENTIUMREAL, t:SYSTEM, w:W|W|R|R, m:KERNEL|NOV86, i:MSR -RDPMC ; n/a ; EAX,EDX,ECX,MSR ; 0x0F 0x33 ; s:RDPMC, t:SYSTEM, w:W|W|R|R, m:NOSGX -SYSENTER ; n/a ; SCS,SESP,SEIP,SS,sSP,CS,rIP,Fv,SSP ; 0x0F 0x34 ; s:PPRO, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW, a:CETT, i:SEP, f:IF=0, m:NOREAL|NOSGX -SYSEXIT ; n/a ; SS,sSP,CS,rIP,SSP ; 0x0F 0x35 ; s:PPRO, t:SYSRET, w:W|W|W|W|W|W, a:F64, i:SEP, m:KERNEL|NOREAL -RDSHR ; Ed ; n/a ; cyrix 0x0F 0x36 /r ; s:CYRIX, t:SYSTEM, w:R -GETSEC ; n/a ; EAX,EBX ; NP 0x0F 0x37 ; s:SMX, t:SYSTEM, w:RCW|R, m:KERNEL|NOREAL|NOSGX -WRSHR ; Ed ; n/a ; cyrix 0x0F 0x37 /r ; s:CYRIX, t:SYSTEM, w:W -DMINT ; n/a ; n/a ; 0x0F 0x39 ; s:CYRIX, t:SYSTEM, m:NO64 -CPU_WRITE ; n/a ; n/a ; 0x0F 0x3C ; s:CYRIX, t:SYSTEM -CPU_READ ; n/a ; n/a ; 0x0F 0x3D ; s:CYRIX, t:SYSTEM -ALTINST ; n/a ; n/a ; 0x0F 0x3F ; s:CYRIX, t:SYSTEM +WRMSR ; ; EAX,EDX,ECX,MSR ; 0x0F 0x30 ; s:PENTIUMREAL, t:SYSTEM, w:R|R|R|W, a:SERIAL|NOREX2, m:KERNEL|NOV86, i:MSR +RDTSC ; ; EAX,EDX,TSC ; 0x0F 0x31 ; s:PENTIUMREAL, t:SYSTEM, w:W|W|R, a:NOREX2 +RDMSR ; ; EAX,EDX,ECX,MSR ; 0x0F 0x32 ; s:PENTIUMREAL, t:SYSTEM, w:W|W|R|R, m:KERNEL|NOV86, i:MSR, a:NOREX2 +RDPMC ; ; EAX,EDX,ECX,MSR ; 0x0F 0x33 ; s:RDPMC, t:SYSTEM, w:W|W|R|R, m:NOSGX, a:NOREX2 +SYSENTER ; ; SCS,SESP,SEIP,SS,sSP,CS,rIP,Fv,SSP ; 0x0F 0x34 ; s:PPRO, t:SYSCALL, w:R|R|R|W|W|W|W|W|RW, a:CETT|NOREX2, i:SEP, f:IF=0, m:NOREAL|NOSGX +SYSEXIT ; ; SS,sSP,CS,rIP,SSP ; 0x0F 0x35 ; s:PPRO, t:SYSRET, w:W|W|W|W|W|W, a:F64|NOREX2, i:SEP, m:KERNEL|NOREAL +GETSEC ; ; EAX,EBX ; NP 0x0F 0x37 ; s:SMX, t:SYSTEM, w:RCW|R, m:KERNEL|NOREAL|NOSGX, a:NOREX2 # 0x40 - 0x4F CMOVO ; Gv,Ev ; Fv ; 0x0F 0x40 /r ; s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CO, a:COND @@ -313,166 +313,157 @@ CMOVNLE ; Gv,Ev ; Fv ; 0x0F 0x4F /r # 0x50 - 0x5F # Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit). -MOVMSKPS ; Gy,Ups ; n/a ; NP 0x0F 0x50 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7, a:D64 -MOVMSKPD ; Gy,Upd ; n/a ; 0x66 0x0F 0x50 /r:reg ; s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64 -SQRTPS ; Vps,Wps ; n/a ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2 -SQRTPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2 -SQRTSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3 -SQRTSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3 -RSQRTPS ; Vps,Wps ; n/a ; NP 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:4 -RSQRTSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:5 -RCPPS ; Vps,Wps ; n/a ; NP 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:4 -RCPSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:5 -ANDPS ; Vps,Wps ; n/a ; NP 0x0F 0x54 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 -ANDPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x54 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 -ANDNPS ; Vps,Wps ; n/a ; NP 0x0F 0x55 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 -ANDNPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x55 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 -ORPS ; Vps,Wps ; n/a ; NP 0x0F 0x56 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 -ORPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x56 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 -XORPS ; Vps,Wps ; n/a ; NP 0x0F 0x57 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 -XORPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x57 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 -ADDPS ; Vps,Wps ; n/a ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2 -ADDPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2 -ADDSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3 -ADDSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MULPS ; Vps,Wps ; n/a ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2 -MULPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MULSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3 -MULSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3 -CVTPS2PD ; Vpd,Wq ; n/a ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTPD2PS ; Vps,Wpd ; n/a ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTSS2SD ; Vsd,Wss ; n/a ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTSD2SS ; Vss,Wsd ; n/a ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 -CVTDQ2PS ; Vps,Wdq ; n/a ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTPS2DQ ; Vdq,Wps ; n/a ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTTPS2DQ ; Vdq,Wps ; n/a ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -SUBPS ; Vps,Wps ; n/a ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2 -SUBPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2 -SUBSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3 -SUBSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MINPS ; Vps,Wps ; n/a ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2 -MINPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MINSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3 -MINSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3 -DIVPS ; Vps,Wps ; n/a ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2 -DIVPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2 -DIVSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3 -DIVSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3 -MAXPS ; Vps,Wps ; n/a ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2 -MAXPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2 -MAXSS ; Vss,Wss ; n/a ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3 -MAXSD ; Vsd,Wsd ; n/a ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3 +MOVMSKPS ; Gy,Ups ; ; NP 0x0F 0x50 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7, a:D64 +MOVMSKPD ; Gy,Upd ; ; 0x66 0x0F 0x50 /r:reg ; s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64 +SQRTPS ; Vps,Wps ; ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2 +SQRTPD ; Vpd,Wpd ; ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2 +SQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3 +SQRTSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3 +RSQRTPS ; Vps,Wps ; ; NP 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:4 +RSQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:5 +RCPPS ; Vps,Wps ; ; NP 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:4 +RCPSS ; Vss,Wss ; ; 0xF3 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:5 +ANDPS ; Vps,Wps ; ; NP 0x0F 0x54 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ANDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x54 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ANDNPS ; Vps,Wps ; ; NP 0x0F 0x55 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ANDNPD ; Vpd,Wpd ; ; 0x66 0x0F 0x55 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ORPS ; Vps,Wps ; ; NP 0x0F 0x56 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +ORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x56 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +XORPS ; Vps,Wps ; ; NP 0x0F 0x57 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4 +XORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x57 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4 +ADDPS ; Vps,Wps ; ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2 +ADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2 +ADDSS ; Vss,Wss ; ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3 +ADDSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3 +MULPS ; Vps,Wps ; ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2 +MULPD ; Vpd,Wpd ; ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2 +MULSS ; Vss,Wss ; ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3 +MULSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3 +CVTPS2PD ; Vpd,Wq ; ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +CVTPD2PS ; Vps,Wpd ; ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTSS2SD ; Vsd,Wss ; ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +CVTSD2SS ; Vss,Wsd ; ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3 +CVTDQ2PS ; Vps,Wdq ; ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTPS2DQ ; Vdq,Wps ; ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTTPS2DQ ; Vdq,Wps ; ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +SUBPS ; Vps,Wps ; ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2 +SUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2 +SUBSS ; Vss,Wss ; ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3 +SUBSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3 +MINPS ; Vps,Wps ; ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2 +MINPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2 +MINSS ; Vss,Wss ; ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3 +MINSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3 +DIVPS ; Vps,Wps ; ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2 +DIVPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2 +DIVSS ; Vss,Wss ; ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3 +DIVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3 +MAXPS ; Vps,Wps ; ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2 +MAXPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2 +MAXSS ; Vss,Wss ; ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3 +MAXSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3 # 0x60 - 0x6F -PUNPCKLBW ; Pq,Qd ; n/a ; NP 0x0F 0x60 /r ; s:MMX, t:MMX, w:RW|R -PUNPCKLBW ; Vx,Wx ; n/a ; 0x66 0x0F 0x60 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKLWD ; Pq,Qd ; n/a ; NP 0x0F 0x61 /r ; s:MMX, t:MMX, w:RW|R -PUNPCKLWD ; Vx,Wx ; n/a ; 0x66 0x0F 0x61 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKLDQ ; Pq,Qd ; n/a ; NP 0x0F 0x62 /r ; s:MMX, t:MMX, w:RW|R -PUNPCKLDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x62 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PACKSSWB ; Pq,Qq ; n/a ; NP 0x0F 0x63 /r ; s:MMX, t:MMX, w:RW|R -PACKSSWB ; Vx,Wx ; n/a ; 0x66 0x0F 0x63 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PCMPGTB ; Pq,Qq ; n/a ; NP 0x0F 0x64 /r ; s:MMX, t:MMX, w:RW|R -PCMPGTB ; Vx,Wx ; n/a ; 0x66 0x0F 0x64 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PCMPGTW ; Pq,Qq ; n/a ; NP 0x0F 0x65 /r ; s:MMX, t:MMX, w:RW|R -PCMPGTW ; Vx,Wx ; n/a ; 0x66 0x0F 0x65 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PCMPGTD ; Pq,Qq ; n/a ; NP 0x0F 0x66 /r ; s:MMX, t:MMX, w:RW|R -PCMPGTD ; Vx,Wx ; n/a ; 0x66 0x0F 0x66 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PACKUSWB ; Pq,Qq ; n/a ; NP 0x0F 0x67 /r ; s:MMX, t:MMX, w:RW|R -PACKUSWB ; Vx,Wx ; n/a ; 0x66 0x0F 0x67 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKHBW ; Pq,Qq ; n/a ; NP 0x0F 0x68 /r ; s:MMX, t:MMX, w:RW|R -PUNPCKHBW ; Vx,Wx ; n/a ; 0x66 0x0F 0x68 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKHWD ; Pq,Qq ; n/a ; NP 0x0F 0x69 /r ; s:MMX, t:MMX, w:RW|R -PUNPCKHWD ; Vx,Wx ; n/a ; 0x66 0x0F 0x69 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKHDQ ; Pq,Qq ; n/a ; NP 0x0F 0x6A /r ; s:MMX, t:MMX, w:RW|R -PUNPCKHDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x6A /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PACKSSDW ; Pq,Qq ; n/a ; NP 0x0F 0x6B /r ; s:MMX, t:MMX, w:RW|R -PACKSSDW ; Vx,Wx ; n/a ; 0x66 0x0F 0x6B /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKLQDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x6C /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PUNPCKHQDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0x6D /r ; s:SSE2, t:SSE, w:RW|R, e:4 -MOVD ; Pq,Ey ; n/a ; NP 0x0F 0x6E /r ; s:MMX, t:DATAXFER, w:W|R -MOVQ ; Pq,Ey ; n/a ; rexw NP 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVD ; Vdq,Ey ; n/a ; 0x66 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ ; Vdq,Ey ; n/a ; 0x66 rexw 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ ; Pq,Qq ; n/a ; NP 0x0F 0x6F /r ; s:MMX, t:DATAXFER, w:W|R -MOVDQA ; Vx,Wx ; n/a ; 0x66 0x0F 0x6F /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 -MOVDQU ; Vx,Wx ; n/a ; 0xF3 0x0F 0x6F /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 +PUNPCKLBW ; Pq,Qd ; ; NP 0x0F 0x60 /r ; s:MMX, t:MMX, w:RW|R +PUNPCKLBW ; Vx,Wx ; ; 0x66 0x0F 0x60 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLWD ; Pq,Qd ; ; NP 0x0F 0x61 /r ; s:MMX, t:MMX, w:RW|R +PUNPCKLWD ; Vx,Wx ; ; 0x66 0x0F 0x61 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLDQ ; Pq,Qd ; ; NP 0x0F 0x62 /r ; s:MMX, t:MMX, w:RW|R +PUNPCKLDQ ; Vx,Wx ; ; 0x66 0x0F 0x62 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PACKSSWB ; Pq,Qq ; ; NP 0x0F 0x63 /r ; s:MMX, t:MMX, w:RW|R +PACKSSWB ; Vx,Wx ; ; 0x66 0x0F 0x63 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTB ; Pq,Qq ; ; NP 0x0F 0x64 /r ; s:MMX, t:MMX, w:RW|R +PCMPGTB ; Vx,Wx ; ; 0x66 0x0F 0x64 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTW ; Pq,Qq ; ; NP 0x0F 0x65 /r ; s:MMX, t:MMX, w:RW|R +PCMPGTW ; Vx,Wx ; ; 0x66 0x0F 0x65 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PCMPGTD ; Pq,Qq ; ; NP 0x0F 0x66 /r ; s:MMX, t:MMX, w:RW|R +PCMPGTD ; Vx,Wx ; ; 0x66 0x0F 0x66 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PACKUSWB ; Pq,Qq ; ; NP 0x0F 0x67 /r ; s:MMX, t:MMX, w:RW|R +PACKUSWB ; Vx,Wx ; ; 0x66 0x0F 0x67 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHBW ; Pq,Qq ; ; NP 0x0F 0x68 /r ; s:MMX, t:MMX, w:RW|R +PUNPCKHBW ; Vx,Wx ; ; 0x66 0x0F 0x68 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHWD ; Pq,Qq ; ; NP 0x0F 0x69 /r ; s:MMX, t:MMX, w:RW|R +PUNPCKHWD ; Vx,Wx ; ; 0x66 0x0F 0x69 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHDQ ; Pq,Qq ; ; NP 0x0F 0x6A /r ; s:MMX, t:MMX, w:RW|R +PUNPCKHDQ ; Vx,Wx ; ; 0x66 0x0F 0x6A /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PACKSSDW ; Pq,Qq ; ; NP 0x0F 0x6B /r ; s:MMX, t:MMX, w:RW|R +PACKSSDW ; Vx,Wx ; ; 0x66 0x0F 0x6B /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKLQDQ ; Vx,Wx ; ; 0x66 0x0F 0x6C /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PUNPCKHQDQ ; Vx,Wx ; ; 0x66 0x0F 0x6D /r ; s:SSE2, t:SSE, w:RW|R, e:4 +MOVD ; Pq,Ey ; ; NP 0x0F 0x6E /r ; s:MMX, t:DATAXFER, w:W|R +MOVQ ; Pq,Ey ; ; rexw NP 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVD ; Vdq,Ey ; ; 0x66 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ ; Vdq,Ey ; ; 0x66 rexw 0x0F 0x6E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ ; Pq,Qq ; ; NP 0x0F 0x6F /r ; s:MMX, t:DATAXFER, w:W|R +MOVDQA ; Vx,Wx ; ; 0x66 0x0F 0x6F /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVDQU ; Vx,Wx ; ; 0xF3 0x0F 0x6F /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 # 0x70 - 0x7F -PSHUFW ; Pq,Qq,Ib ; n/a ; NP 0x0F 0x70 /r ib ; s:MMX, t:MMX, w:W|R|R -PSHUFD ; Vx,Wx,Ib ; n/a ; 0x66 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 -PSHUFHW ; Vx,Wx,Ib ; n/a ; 0xF3 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 -PSHUFLW ; Vx,Wx,Ib ; n/a ; 0xF2 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 -PSRLW ; Nq,Ib ; n/a ; NP 0x0F 0x71 /2:reg ib ; s:MMX, t:MMX, w:RW|R -PSRLW ; Ux,Ib ; n/a ; 0x66 0x0F 0x71 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRAW ; Nq,Ib ; n/a ; NP 0x0F 0x71 /4:reg ib ; s:MMX, t:MMX, w:RW|R -PSRAW ; Ux,Ib ; n/a ; 0x66 0x0F 0x71 /4:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSLLW ; Nq,Ib ; n/a ; NP 0x0F 0x71 /6:reg ib ; s:MMX, t:MMX, w:RW|R -PSLLW ; Ux,Ib ; n/a ; 0x66 0x0F 0x71 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRLD ; Nq,Ib ; n/a ; NP 0x0F 0x72 /2:reg ib ; s:MMX, t:MMX, w:RW|R -PSRLD ; Ux,Ib ; n/a ; 0x66 0x0F 0x72 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRAD ; Nq,Ib ; n/a ; NP 0x0F 0x72 /4:reg ib ; s:MMX, t:MMX, w:RW|R -PSRAD ; Ux,Ib ; n/a ; 0x66 0x0F 0x72 /4:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSLLD ; Nq,Ib ; n/a ; NP 0x0F 0x72 /6:reg ib ; s:MMX, t:MMX, w:RW|R -PSLLD ; Ux,Ib ; n/a ; 0x66 0x0F 0x72 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRLQ ; Nq,Ib ; n/a ; NP 0x0F 0x73 /2:reg ib ; s:MMX, t:MMX, w:RW|R -PSRLQ ; Ux,Ib ; n/a ; 0x66 0x0F 0x73 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRLDQ ; Ux,Ib ; n/a ; 0x66 0x0F 0x73 /3:reg ib ; s:SSE2, t:SSE, w:RW|R, e:7 -PSLLQ ; Nq,Ib ; n/a ; NP 0x0F 0x73 /6:reg ib ; s:MMX, t:MMX, w:RW|R -PSLLQ ; Ux,Ib ; n/a ; 0x66 0x0F 0x73 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 -PSLLDQ ; Ux,Ib ; n/a ; 0x66 0x0F 0x73 /7:reg ib ; s:SSE2, t:SSE, w:RW|R, e:7 -PCMPEQB ; Pq,Qq ; n/a ; NP 0x0F 0x74 /r ; s:MMX, t:MMX, w:RW|R -PCMPEQB ; Vx,Wx ; n/a ; 0x66 0x0F 0x74 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PCMPEQW ; Pq,Qq ; n/a ; NP 0x0F 0x75 /r ; s:MMX, t:MMX, w:RW|R -PCMPEQW ; Vx,Wx ; n/a ; 0x66 0x0F 0x75 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PCMPEQD ; Pq,Qq ; n/a ; NP 0x0F 0x76 /r ; s:MMX, t:MMX, w:RW|R -PCMPEQD ; Vx,Wx ; n/a ; 0x66 0x0F 0x76 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -EMMS ; n/a ; n/a ; NP 0x0F 0x77 ; s:MMX, t:MMX +PSHUFW ; Pq,Qq,Ib ; ; NP 0x0F 0x70 /r ib ; s:MMX, t:MMX, w:W|R|R +PSHUFD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 +PSHUFHW ; Vx,Wx,Ib ; ; 0xF3 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 +PSHUFLW ; Vx,Wx,Ib ; ; 0xF2 0x0F 0x70 /r ib ; s:SSE2, t:SSE, w:W|R|R, e:4 +PSRLW ; Nq,Ib ; ; NP 0x0F 0x71 /2:reg ib ; s:MMX, t:MMX, w:RW|R +PSRLW ; Ux,Ib ; ; 0x66 0x0F 0x71 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRAW ; Nq,Ib ; ; NP 0x0F 0x71 /4:reg ib ; s:MMX, t:MMX, w:RW|R +PSRAW ; Ux,Ib ; ; 0x66 0x0F 0x71 /4:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSLLW ; Nq,Ib ; ; NP 0x0F 0x71 /6:reg ib ; s:MMX, t:MMX, w:RW|R +PSLLW ; Ux,Ib ; ; 0x66 0x0F 0x71 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRLD ; Nq,Ib ; ; NP 0x0F 0x72 /2:reg ib ; s:MMX, t:MMX, w:RW|R +PSRLD ; Ux,Ib ; ; 0x66 0x0F 0x72 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRAD ; Nq,Ib ; ; NP 0x0F 0x72 /4:reg ib ; s:MMX, t:MMX, w:RW|R +PSRAD ; Ux,Ib ; ; 0x66 0x0F 0x72 /4:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSLLD ; Nq,Ib ; ; NP 0x0F 0x72 /6:reg ib ; s:MMX, t:MMX, w:RW|R +PSLLD ; Ux,Ib ; ; 0x66 0x0F 0x72 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRLQ ; Nq,Ib ; ; NP 0x0F 0x73 /2:reg ib ; s:MMX, t:MMX, w:RW|R +PSRLQ ; Ux,Ib ; ; 0x66 0x0F 0x73 /2:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRLDQ ; Ux,Ib ; ; 0x66 0x0F 0x73 /3:reg ib ; s:SSE2, t:SSE, w:RW|R, e:7 +PSLLQ ; Nq,Ib ; ; NP 0x0F 0x73 /6:reg ib ; s:MMX, t:MMX, w:RW|R +PSLLQ ; Ux,Ib ; ; 0x66 0x0F 0x73 /6:reg ib ; s:SSE2, t:SSE, w:RW|R, e:4 +PSLLDQ ; Ux,Ib ; ; 0x66 0x0F 0x73 /7:reg ib ; s:SSE2, t:SSE, w:RW|R, e:7 +PCMPEQB ; Pq,Qq ; ; NP 0x0F 0x74 /r ; s:MMX, t:MMX, w:RW|R +PCMPEQB ; Vx,Wx ; ; 0x66 0x0F 0x74 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PCMPEQW ; Pq,Qq ; ; NP 0x0F 0x75 /r ; s:MMX, t:MMX, w:RW|R +PCMPEQW ; Vx,Wx ; ; 0x66 0x0F 0x75 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PCMPEQD ; Pq,Qq ; ; NP 0x0F 0x76 /r ; s:MMX, t:MMX, w:RW|R +PCMPEQD ; Vx,Wx ; ; 0x66 0x0F 0x76 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +EMMS ; ; ; NP 0x0F 0x77 ; s:MMX, t:MMX VMREAD ; Ey,Gy ; Fv ; NP 0x0F 0x78 /r ; s:VTX, t:VTX, w:RW|R|W, f:VMX, a:F64, m:VMXROOT -INSERTQ ; Vdq,Udq,Ib,Ib ; n/a ; 0xF2 0x0F 0x78 /r ib ib ; s:SSE4A, t:BITBYTE, w:W|R|R|R -EXTRQ ; Uq,Ib,Ib ; n/a ; 0x66 0x0F 0x78 /0 modrmpmp ib ib ; s:SSE4A, t:BITBYTE, w:W|R|R +INSERTQ ; Vdq,Udq,Ib,Ib ; ; 0xF2 0x0F 0x78 /r ib ib ; s:SSE4A, t:BITBYTE, w:W|R|R|R +EXTRQ ; Uq,Ib,Ib ; ; 0x66 0x0F 0x78 /0 ib ib ; s:SSE4A, t:BITBYTE, w:W|R|R VMWRITE ; Gy,Ey ; Fv ; NP 0x0F 0x79 /r ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64, m:VMXROOT -EXTRQ ; Vdq,Uq ; n/a ; 0x66 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R -INSERTQ ; Vdq,Udq ; n/a ; 0xF2 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R -HADDPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HADDPS ; Vps,Wps ; n/a ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HSUBPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 -HSUBPS ; Vps,Wps ; n/a ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 -MOVD ; Ey,Pd ; n/a ; NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R -MOVQ ; Ey,Pq ; n/a ; rexw NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R -MOVD ; Ey,Vdq ; n/a ; 0x66 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ ; Ey,Vdq ; n/a ; 0x66 rexw 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ ; Vdq,Wq ; n/a ; 0xF3 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ ; Qq,Pq ; n/a ; NP 0x0F 0x7F /r ; s:MMX, t:DATAXFER, w:W|R -MOVDQA ; Wx,Vx ; n/a ; 0x66 0x0F 0x7F /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 -MOVDQU ; Wx,Vx ; n/a ; 0xF3 0x0F 0x7F /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 - -# SMM instructions on Cyrix CPUs. -SVDC ; Ms,Sw ; n/a ; cyrix 0x0F 0x78 /r:mem ; s:CYRIX_SMM, t:SEGOP, w:W|R -RSDC ; Sw,Ms ; n/a ; cyrix 0x0F 0x79 /r:mem ; s:CYRIX_SMM, t:SEGOP, w:R|R -SVLDT ; Ms ; n/a ; cyrix 0x0F 0x7A /r:mem ; s:CYRIX_SMM, t:SEGOP, w:W -RSLDT ; Ms ; n/a ; cyrix 0x0F 0x7B /r:mem ; s:CYRIX_SMM, t:SEGOP, w:R -SVTS ; Ms ; n/a ; cyrix 0x0F 0x7C /r:mem ; s:CYRIX_SMM, t:SEGOP, w:W -RSTS ; Ms ; n/a ; cyrix 0x0F 0x7D /r:mem ; s:CYRIX_SMM, t:SEGOP, w:R -SMINT ; n/a ; n/a ; cyrix 0x0F 0x7E ; s:CYRIX_SMM, t:SEGOP +EXTRQ ; Vdq,Uq ; ; 0x66 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R +INSERTQ ; Vdq,Udq ; ; 0xF2 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R +HADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 +HADDPS ; Vps,Wps ; ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2 +HSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 +HSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2 +MOVD ; Ey,Pd ; ; NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R +MOVQ ; Ey,Pq ; ; rexw NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R +MOVD ; Ey,Vdq ; ; 0x66 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ ; Ey,Vdq ; ; 0x66 rexw 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ ; Vdq,Wq ; ; 0xF3 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ ; Qq,Pq ; ; NP 0x0F 0x7F /r ; s:MMX, t:DATAXFER, w:W|R +MOVDQA ; Wx,Vx ; ; 0x66 0x0F 0x7F /r ; s:SSE2, t:DATAXFER, w:W|R, e:1 +MOVDQU ; Wx,Vx ; ; 0xF3 0x0F 0x7F /r ; s:SSE2, t:DATAXFER, w:W|R, e:4 # 0x80 - 0x8F -JO ; Jz ; rIP,Fv ; 0x0F 0x80 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CO, a:F64|COND, p:BND|BH -JNO ; Jz ; rIP,Fv ; 0x0F 0x81 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNO, a:F64|COND, p:BND|BH -JC ; Jz ; rIP,Fv ; 0x0F 0x82 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CC, a:F64|COND, p:BND|BH -JNC ; Jz ; rIP,Fv ; 0x0F 0x83 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNC, a:F64|COND, p:BND|BH -JZ ; Jz ; rIP,Fv ; 0x0F 0x84 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CZ, a:F64|COND, p:BND|BH -JNZ ; Jz ; rIP,Fv ; 0x0F 0x85 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNZ, a:F64|COND, p:BND|BH -JBE ; Jz ; rIP,Fv ; 0x0F 0x86 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CBE, a:F64|COND, p:BND|BH -JNBE ; Jz ; rIP,Fv ; 0x0F 0x87 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNBE, a:F64|COND, p:BND|BH -JS ; Jz ; rIP,Fv ; 0x0F 0x88 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CS, a:F64|COND, p:BND|BH -JNS ; Jz ; rIP,Fv ; 0x0F 0x89 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNS, a:F64|COND, p:BND|BH -JP ; Jz ; rIP,Fv ; 0x0F 0x8A cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CP, a:F64|COND, p:BND|BH -JNP ; Jz ; rIP,Fv ; 0x0F 0x8B cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNP, a:F64|COND, p:BND|BH -JL ; Jz ; rIP,Fv ; 0x0F 0x8C cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CL, a:F64|COND, p:BND|BH -JNL ; Jz ; rIP,Fv ; 0x0F 0x8D cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNL, a:F64|COND, p:BND|BH -JLE ; Jz ; rIP,Fv ; 0x0F 0x8E cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CLE, a:F64|COND, p:BND|BH -JNLE ; Jz ; rIP,Fv ; 0x0F 0x8F cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNLE, a:F64|COND, p:BND|BH +JO ; Jz ; rIP,Fv ; 0x0F 0x80 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CO, a:F64|COND|NOREX2, p:BND|BH +JNO ; Jz ; rIP,Fv ; 0x0F 0x81 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNO, a:F64|COND|NOREX2, p:BND|BH +JC ; Jz ; rIP,Fv ; 0x0F 0x82 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CC, a:F64|COND|NOREX2, p:BND|BH +JNC ; Jz ; rIP,Fv ; 0x0F 0x83 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNC, a:F64|COND|NOREX2, p:BND|BH +JZ ; Jz ; rIP,Fv ; 0x0F 0x84 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CZ, a:F64|COND|NOREX2, p:BND|BH +JNZ ; Jz ; rIP,Fv ; 0x0F 0x85 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNZ, a:F64|COND|NOREX2, p:BND|BH +JBE ; Jz ; rIP,Fv ; 0x0F 0x86 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CBE, a:F64|COND|NOREX2, p:BND|BH +JNBE ; Jz ; rIP,Fv ; 0x0F 0x87 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNBE, a:F64|COND|NOREX2, p:BND|BH +JS ; Jz ; rIP,Fv ; 0x0F 0x88 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CS, a:F64|COND|NOREX2, p:BND|BH +JNS ; Jz ; rIP,Fv ; 0x0F 0x89 cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNS, a:F64|COND|NOREX2, p:BND|BH +JP ; Jz ; rIP,Fv ; 0x0F 0x8A cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CP, a:F64|COND|NOREX2, p:BND|BH +JNP ; Jz ; rIP,Fv ; 0x0F 0x8B cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNP, a:F64|COND|NOREX2, p:BND|BH +JL ; Jz ; rIP,Fv ; 0x0F 0x8C cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CL, a:F64|COND|NOREX2, p:BND|BH +JNL ; Jz ; rIP,Fv ; 0x0F 0x8D cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNL, a:F64|COND|NOREX2, p:BND|BH +JLE ; Jz ; rIP,Fv ; 0x0F 0x8E cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CLE, a:F64|COND|NOREX2, p:BND|BH +JNLE ; Jz ; rIP,Fv ; 0x0F 0x8F cz ; s:I86, t:COND_BR, c:Jcc, w:R|CRCW|R, f:CNLE, a:F64|COND|NOREX2, p:BND|BH # 0x90 - 0x9F SETO ; Eb ; Fv ; 0x0F 0x90 /r ; s:I386, t:BITBYTE, c:SETcc, w:W|R, f:CO, a:COND @@ -495,26 +486,14 @@ SETNLE ; Eb ; Fv ; 0x0F 0x9F /r # 0xA0 - 0xAF PUSH ; FS ; Kv ; 0x0F 0xA0 ; s:I86, t:PUSH, w:R|W, a:D64, m:NOSGX POP ; FS ; Kv ; 0x0F 0xA1 ; s:I86, t:POP, w:W|R, a:D64, m:NOSGX -CPUID ; n/a ; EAX,EBX,ECX,EDX ; 0x0F 0xA2 ; s:I486REAL, t:MISC, w:RW|W|CRW|W, a:SERIAL, m:NOSGX|NOTSX +CPUID ; ; EAX,EBX,ECX,EDX ; 0x0F 0xA2 ; s:I486REAL, t:MISC, w:RW|W|CRW|W, a:SERIAL, m:NOSGX|NOTSX BT ; Ev,Gv ; Fv ; 0x0F 0xA3 /r bitbase ; s:I386, t:BITBYTE, w:R|R|W, f:BT SHLD ; Ev,Gv,Ib ; Fv ; 0x0F 0xA4 /r ib ; s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD SHLD ; Ev,Gv,CL ; Fv ; 0x0F 0xA5 /r ; s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD -# Cyrix security instructions. -MONTMUL ; n/a ; n/a ; 0xF3 0x0F 0xA6 /0xC0 ; s:CYRIX, t:PADLOCK, p:REP -XSHA1 ; n/a ; n/a ; 0xF3 0x0F 0xA6 /0xC8 ; s:CYRIX, t:PADLOCK, p:REP -XSHA256 ; n/a ; n/a ; 0xF3 0x0F 0xA6 /0xD0 ; s:CYRIX, t:PADLOCK, p:REP -XSTORE ; n/a ; n/a ; 0x0F 0xA7 /0xC0 ; s:CYRIX, t:PADLOCK -XSTORE ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xC0 ; s:CYRIX, t:PADLOCK, p:REP -XCRYPTECB ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xC8 ; s:CYRIX, t:PADLOCK, p:REP -XCRYPTCBC ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xD0 ; s:CYRIX, t:PADLOCK, p:REP -XCRYPTCTR ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xD8 ; s:CYRIX, t:PADLOCK, p:REP -XCRYPTCFB ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xE0 ; s:CYRIX, t:PADLOCK, p:REP -XCRYPTOFB ; n/a ; n/a ; 0xF3 0x0F 0xA7 /0xE8 ; s:CYRIX, t:PADLOCK, p:REP - PUSH ; GS ; Kv ; 0x0F 0xA8 ; s:I86, t:PUSH, w:R|W, a:D64, m:NOSGX POP ; GS ; Kv ; 0x0F 0xA9 ; s:I86, t:POP, w:W|R, a:D64, m:NOSGX -RSM ; n/a ; CS,rIP,Fv ; 0x0F 0xAA ; s:I486, t:SYSRET, w:W|W|W, a:SERIAL, m:SMM +RSM ; ; CS,rIP,Fv ; 0x0F 0xAA ; s:I486, t:SYSRET, w:W|W|W, a:SERIAL, m:SMM BTS ; Ev,Gv ; Fv ; 0x0F 0xAB /r bitbase ; s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:HLE|LOCK SHRD ; Ev,Gv,Ib ; Fv ; 0x0F 0xAC /r ib ; s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD SHRD ; Ev,Gv,CL ; Fv ; 0x0F 0xAD /r ; s:I386, t:SHIFT, w:RCW|R|R|W, f:SHIFTD @@ -525,33 +504,33 @@ FXRSTOR ; Mrx ; BANK ; NP 0x0F 0xAE /1:m FXRSTOR64 ; Mrx ; BANK ; rexw NP 0x0F 0xAE /1:mem ; s:FXSAVE, t:SSE, w:R|W LDMXCSR ; Md ; MXCSR ; NP 0x0F 0xAE /2:mem ; s:SSE, t:SSE, w:R|W STMXCSR ; Md ; MXCSR ; NP 0x0F 0xAE /3:mem ; s:SSE, t:SSE, w:W|R -XSAVE ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /4:mem ; s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R -XSAVE64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /4:mem ; s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R -XRSTOR ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /5:mem ; s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W -XRSTOR64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /5:mem ; s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W -XSAVEOPT ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /6:mem ; s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R -XSAVEOPT64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /6:mem ; s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R -CLWB ; Mb ; n/a ; 0x66 0x0F 0xAE /6:mem ; s:CLWB, t:MISC, w:R +XSAVE ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /4:mem ; s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R, a:NOREX2 +XSAVE64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /4:mem ; s:XSAVE, t:XSAVE, c:XSAVE, w:W|R|R|R|R, a:NOREX2 +XRSTOR ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /5:mem ; s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W, a:NOREX2 +XRSTOR64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /5:mem ; s:XSAVE, t:XSAVE, c:XRSTOR, w:R|R|R|R|W, a:NOREX2 +XSAVEOPT ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xAE /6:mem ; s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R, a:NOREX2 +XSAVEOPT64 ; M? ; EDX,EAX,XCR0,BANK ; rexw NP 0x0F 0xAE /6:mem ; s:XSAVE, t:XSAVE, c:XSAVEOPT, w:W|R|R|R|R, a:NOREX2 +CLWB ; Mb ; ; 0x66 0x0F 0xAE /6:mem ; s:CLWB, t:MISC, w:R CLRSSBSY ; Mq ; SSP ; 0xF3 0x0F 0xAE /6:mem ; s:CET_SS, t:CET, a:SHS, w:RW|RW, f:CF=m|ZF=0|PF=0|AF=0|OF=0|SF=0 -CLFLUSH ; Mb ; n/a ; NP 0x0F 0xAE /7:mem ; s:CLFSH, t:MISC, w:R -CLFLUSHOPT ; Mb ; n/a ; 0x66 0x0F 0xAE /7:mem ; s:CLFSHOPT, t:MISC, w:R +CLFLUSH ; Mb ; ; NP 0x0F 0xAE /7:mem ; s:CLFSH, t:MISC, w:R +CLFLUSHOPT ; Mb ; ; 0x66 0x0F 0xAE /7:mem ; s:CLFSHOPT, t:MISC, w:R -PTWRITE ; Ey ; n/a ; 0xF3 0x0F 0xAE /4 ; s:PTWRITE, t:PTWRITE, w:R, a:NO66 +PTWRITE ; Ey ; ; 0xF3 0x0F 0xAE /4 ; s:PTWRITE, t:PTWRITE, w:R, a:NO66 -RDFSBASE ; Ry ; FSBASE ; o64 0xF3 0x0F 0xAE /0:reg ; s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 -RDGSBASE ; Ry ; GSBASE ; o64 0xF3 0x0F 0xAE /1:reg ; s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 -WRFSBASE ; Ry ; FSBASE ; o64 0xF3 0x0F 0xAE /2:reg ; s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 -WRGSBASE ; Ry ; GSBASE ; o64 0xF3 0x0F 0xAE /3:reg ; s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 +RDFSBASE ; Ry ; FSBASE ; mo64 0xF3 0x0F 0xAE /0:reg ; s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 +RDGSBASE ; Ry ; GSBASE ; mo64 0xF3 0x0F 0xAE /1:reg ; s:RDWRFSGS, t:RDWRFSGS, w:W|R, m:O64 +WRFSBASE ; Ry ; FSBASE ; mo64 0xF3 0x0F 0xAE /2:reg ; s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 +WRGSBASE ; Ry ; GSBASE ; mo64 0xF3 0x0F 0xAE /3:reg ; s:RDWRFSGS, t:RDWRFSGS, w:R|W, m:O64 INCSSPD ; Rd ; SHSI,SSP ; 0xF3 0x0F 0xAE /5:reg ; s:CET_SS, t:CET, c:INCSSP, w:R|R|RW INCSSPQ ; Rq ; SHSI,SSP ; 0xF3 rexw 0x0F 0xAE /5:reg ; s:CET_SS, t:CET, c:INCSSP, w:R|R|RW -LFENCE ; n/a ; n/a ; NP 0x0F 0xAE /5:reg ; s:SSE2, t:MISC +LFENCE ; ; ; NP 0x0F 0xAE /5:reg ; s:SSE2, t:MISC UMONITOR ; mMb ; Fv ; 0xF3 0x0F 0xAE /6:reg ; s:WAITPKG, t:WAITPKG, w:R|W, f:WAITPKG, m:NOTSX UMWAIT ; Ry ; EDX,EAX ; 0xF2 0x0F 0xAE /6:reg ; s:WAITPKG, t:WAITPKG, w:R|R|R, m:NOTSX TPAUSE ; Ry ; EDX,EAX,Fv ; 0x66 0x0F 0xAE /6:reg ; s:WAITPKG, t:WAITPKG, w:R|R|R|W, f:WAITPKG -MFENCE ; n/a ; n/a ; NP 0x0F 0xAE /6:reg ; s:SSE2, t:MISC -SFENCE ; n/a ; n/a ; NP 0x0F 0xAE /7:reg ; s:SSE2, t:MISC +MFENCE ; ; ; NP 0x0F 0xAE /6:reg ; s:SSE2, t:MISC +SFENCE ; ; ; NP 0x0F 0xAE /7:reg ; s:SSE2, t:MISC # Intel dropped support for the PCOMMIT instruction before it was shipped in any CPU. The following instruction wil ALWAYS cause a #UD from now on. -#PCOMMIT ; n/a ; n/a ; 0x66 0x0F 0xAE /7:reg ; s:PCOMMIT, t:MISC +#PCOMMIT ; ; ; 0x66 0x0F 0xAE /7:reg ; s:PCOMMIT, t:MISC IMUL ; Gv,Ev ; Fv ; 0x0F 0xAF /r ; s:I86, t:ARITH, w:RW|R|W, f:MUL @@ -562,39 +541,39 @@ LSS ; Gv,Mp ; SS ; 0x0F 0xB2 /r:m BTR ; Ev,Gv ; Fv ; 0x0F 0xB3 /r bitbase ; s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE LFS ; Gv,Mp ; FS ; 0x0F 0xB4 /r:mem ; s:I386, t:SEGOP, w:W|R|W, m:NOSGX LGS ; Gv,Mp ; GS ; 0x0F 0xB5 /r:mem ; s:I386, t:SEGOP, w:W|R|W, m:NOSGX -MOVZX ; Gv,Eb ; n/a ; 0x0F 0xB6 /r ; s:I386, t:DATAXFER, w:W|R -MOVZX ; Gv,Ew ; n/a ; 0x0F 0xB7 /r ; s:I386, t:DATAXFER, w:W|R +MOVZX ; Gv,Eb ; ; 0x0F 0xB6 /r ; s:I386, t:DATAXFER, w:W|R +MOVZX ; Gv,Ew ; ; 0x0F 0xB7 /r ; s:I386, t:DATAXFER, w:W|R JMPE ; Jz ; rIP ; 0x0F 0xB8 cz ; s:I64, t:UNCOND_BR, w:R|W, m:NO64 -POPCNT ; Gv,Ev ; Fv ; a0xF3 0x0F 0xB8 /r ; s:POPCNT, t:SSE, w:W|R|W, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 -UD1 ; Gd,Ed ; n/a ; 0x0F 0xB9 /r ; s:UD, t:UD, w:R|R +POPCNT ; Gv,Ev ; Fv ; repz 0x0F 0xB8 /r ; s:POPCNT, t:SSE, w:W|R|W, f:CF=0|PF=0|AF=0|ZF=m|SF=0|OF=0 +UD1 ; Gd,Ed ; ; 0x0F 0xB9 /r ; s:UD, t:UD, w:R|R BT ; Ev,Ib ; Fv ; 0x0F 0xBA /4 ib ; s:I386, t:BITBYTE, w:R|R|W, f:BT BTS ; Ev,Ib ; Fv ; 0x0F 0xBA /5 ib ; s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE BTR ; Ev,Ib ; Fv ; 0x0F 0xBA /6 ib ; s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE BTC ; Ev,Ib ; Fv ; 0x0F 0xBA /7 ib ; s:I386, t:BITBYTE, w:RW|R|W, f:BT, p:LOCK|HLE BTC ; Ev,Gv ; Fv ; 0x0F 0xBB /r bitbase ; s:I386, t:I386, w:RW|R|W, f:BT, p:LOCK|HLE BSF ; Gv,Ev ; Fv ; 0x0F 0xBC /r ; s:I386, t:I386, w:CW|R|W, f:CF=u|PF=u|AF=u|ZF=m|SF=u|OF=u -TZCNT ; Gv,Ev ; Fv ; a0xF3 0x0F 0xBC /r ; s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +TZCNT ; Gv,Ev ; Fv ; repz 0x0F 0xBC /r ; s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u BSR ; Gv,Ev ; Fv ; 0x0F 0xBD /r ; s:I386, t:BITBYTE, w:CW|R|W, f:CF=u|PF=u|AF=u|ZF=m|SF=u|OF=u -LZCNT ; Gv,Ev ; Fv ; a0xF3 0x0F 0xBD /r ; s:LZCNT, t:LZCNT, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u -MOVSX ; Gv,Eb ; n/a ; 0x0F 0xBE /r ; s:I386, t:DATAXFER, w:W|R -MOVSX ; Gv,Ew ; n/a ; 0x0F 0xBF /r ; s:I386, t:DATAXFER, w:W|R +LZCNT ; Gv,Ev ; Fv ; repz 0x0F 0xBD /r ; s:LZCNT, t:LZCNT, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=u|OF=u +MOVSX ; Gv,Eb ; ; 0x0F 0xBE /r ; s:I386, t:DATAXFER, w:W|R +MOVSX ; Gv,Ew ; ; 0x0F 0xBF /r ; s:I386, t:DATAXFER, w:W|R # 0xC0 - 0xCF XADD ; Eb,Gb ; Fv ; 0x0F 0xC0 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE XADD ; Ev,Gv ; Fv ; 0x0F 0xC1 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE -CMPPS ; Vps,Wps,Ib ; n/a ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2 -CMPPD ; Vpd,Wpd,Ib ; n/a ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2 -CMPSS ; Vss,Wss,Ib ; n/a ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3 -CMPSD ; Vsd,Wsd,Ib ; n/a ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3 -MOVNTI ; My,Gy ; n/a ; NP 0x0F 0xC3 /r:mem ; s:SSE2, t:DATAXFER, w:W|R -PINSRW ; Pq,Rd,Ib ; n/a ; NP 0x0F 0xC4 /r:reg ib ; s:MMX, t:MMX, w:RW|R|R -PINSRW ; Pq,Mw,Ib ; n/a ; NP 0x0F 0xC4 /r:mem ib ; s:MMX, t:MMX, w:RW|R|R -PINSRW ; Vdq,Rd,Ib ; n/a ; 0x66 0x0F 0xC4 /r:reg ib ; s:SSE2, t:SSE, w:RW|R|R, e:5 -PINSRW ; Vdq,Mw,Ib ; n/a ; 0x66 0x0F 0xC4 /r:mem ib ; s:SSE2, t:SSE, w:RW|R|R, e:5 -PEXTRW ; Gy,Nq,Ib ; n/a ; NP 0x0F 0xC5 /r:reg ib ; s:MMX, t:MMX, w:W|R|R, a:D64 -PEXTRW ; Gy,Udq,Ib ; n/a ; 0x66 0x0F 0xC5 /r:reg ib ; s:SSE2, t:SSE, w:W|R|R, e:5, a:D64 -SHUFPS ; Vps,Wps,Ib ; n/a ; NP 0x0F 0xC6 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:4 -SHUFPD ; Vpd,Wpd,Ib ; n/a ; 0x66 0x0F 0xC6 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:4 +CMPPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2 +CMPPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2 +CMPSS ; Vss,Wss,Ib ; ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3 +CMPSD ; Vsd,Wsd,Ib ; ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3 +MOVNTI ; My,Gy ; ; NP 0x0F 0xC3 /r:mem ; s:SSE2, t:DATAXFER, w:W|R +PINSRW ; Pq,Rd,Ib ; ; NP 0x0F 0xC4 /r:reg ib ; s:MMX, t:MMX, w:RW|R|R +PINSRW ; Pq,Mw,Ib ; ; NP 0x0F 0xC4 /r:mem ib ; s:MMX, t:MMX, w:RW|R|R +PINSRW ; Vdq,Rd,Ib ; ; 0x66 0x0F 0xC4 /r:reg ib ; s:SSE2, t:SSE, w:RW|R|R, e:5 +PINSRW ; Vdq,Mw,Ib ; ; 0x66 0x0F 0xC4 /r:mem ib ; s:SSE2, t:SSE, w:RW|R|R, e:5 +PEXTRW ; Gy,Nq,Ib ; ; NP 0x0F 0xC5 /r:reg ib ; s:MMX, t:MMX, w:W|R|R, a:D64 +PEXTRW ; Gy,Udq,Ib ; ; 0x66 0x0F 0xC5 /r:reg ib ; s:SSE2, t:SSE, w:W|R|R, e:5, a:D64 +SHUFPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC6 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:4 +SHUFPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC6 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:4 CMPXCHG8B ; Mq ; EDX,EAX,ECX,EBX,Fv ; 0x0F 0xC7 /1:mem ; s:PENTIUMREAL, t:SEMAPHORE, w:RCW|RCW|RCW|R|R|W, i:CX8, f:ZF=m, p:LOCK|HLE CMPXCHG16B ; Mdq ; RDX,RAX,RCX,RBX,Fv ; rexw 0x0F 0xC7 /1:mem ; s:CMPXCHG16B, t:SEMAPHORE, w:RCW|RCW|RCW|R|R|W, i:CX8, f:ZF=m, p:LOCK|HLE XRSTORS ; M? ; EDX,EAX,XCR0,BANK ; NP 0x0F 0xC7 /3:mem ; s:XSAVES, t:XSAVE, c:XRSTORS, w:R|R|R|R|W @@ -607,120 +586,120 @@ VMPTRLD ; Mq ; Fv ; NP 0x0F 0xC7 /6:m VMCLEAR ; Mq ; Fv ; 0x66 0x0F 0xC7 /6:mem ; s:VTX, t:VTX, w:R|W, f:VMX, m:VMXROOT VMXON ; Mq ; Fv ; 0xF3 0x0F 0xC7 /6:mem ; s:VTX, t:VTX, w:R|W, f:VMX, m:VMXROOT VMPTRST ; Mq ; Fv ; NP 0x0F 0xC7 /7:mem ; s:VTX, t:VTX, w:W|W, f:VMX, m:VMXROOT -RDRAND ; Rv ; Fv ; 0x0F 0xC7 /6:reg ; s:RDRAND, t:RDRAND, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +RDRAND ; Rv ; Fv ; NP 0x0F 0xC7 /6:reg ; s:RDRAND, t:RDRAND, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDRAND ; Rv ; Fv ; 0x66 0x0F 0xC7 /6:reg ; s:RDRAND, t:RDRAND, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 -SENDUIPI ; Rq ; n/a ; 0xF3 0x0F 0xC7 /6:reg ; s:UINTR, t:UINTR, w:RW, m:O64|NOTSX|NOSGX -RDSEED ; Rv ; Fv ; 0x0F 0xC7 /7:reg ; s:RDSEED, t:RDSEED, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 +SENDUIPI ; Rq ; ; 0xF3 0x0F 0xC7 /6:reg ; s:UINTR, t:UINTR, w:RW, m:O64|NOTSX|NOSGX +RDSEED ; Rv ; Fv ; NP 0x0F 0xC7 /7:reg ; s:RDSEED, t:RDSEED, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDSEED ; Rv ; Fv ; 0x66 0x0F 0xC7 /7:reg ; s:RDSEED, t:RDSEED, a:S66, w:W|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0 RDPID ; Ryf ; TSCAUX ; 0xF3 0x0F 0xC7 /7:reg ; s:RDPID, t:RDPID, w:W|R -BSWAP ; Zv ; n/a ; 0x0F 0xC8 ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xC9 ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCA ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCB ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCC ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCD ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCE ; s:I486REAL, t:DATAXFER, w:RW -BSWAP ; Zv ; n/a ; 0x0F 0xCF ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xC8 ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xC9 ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCA ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCB ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCC ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCD ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCE ; s:I486REAL, t:DATAXFER, w:RW +BSWAP ; Zv ; ; 0x0F 0xCF ; s:I486REAL, t:DATAXFER, w:RW # 0xD0 - 0xDF -ADDSUBPD ; Vpd,Wpd ; n/a ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 -ADDSUBPS ; Vps,Wps ; n/a ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 -PSRLW ; Pq,Qq ; n/a ; NP 0x0F 0xD1 /r ; s:MMX, t:MMX, w:RW|R -PSRLW ; Vx,Wx ; n/a ; 0x66 0x0F 0xD1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRLD ; Pq,Qq ; n/a ; NP 0x0F 0xD2 /r ; s:MMX, t:MMX, w:RW|R -PSRLD ; Vx,Wx ; n/a ; 0x66 0x0F 0xD2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRLQ ; Pq,Qq ; n/a ; NP 0x0F 0xD3 /r ; s:MMX, t:MMX, w:RW|R -PSRLQ ; Vx,Wx ; n/a ; 0x66 0x0F 0xD3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDQ ; Pq,Qq ; n/a ; NP 0x0F 0xD4 /r ; s:SSE2, t:MMX, w:RW|R, e:4 -PADDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0xD4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMULLW ; Pq,Qq ; n/a ; NP 0x0F 0xD5 /r ; s:MMX, t:MMX, w:RW|R -PMULLW ; Vx,Wx ; n/a ; 0x66 0x0F 0xD5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -MOVQ ; Wq,Vq ; n/a ; 0x66 0x0F 0xD6 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 -MOVQ2DQ ; Vdq,Nq ; n/a ; 0xF3 0x0F 0xD6 /r:reg ; s:SSE2, t:DATAXFER, w:W|R -MOVDQ2Q ; Pq,Uq ; n/a ; 0xF2 0x0F 0xD6 /r:reg ; s:SSE2, t:DATAXFER, w:W|R -PMOVMSKB ; Gy,Nq ; n/a ; NP 0x0F 0xD7 /r:reg ; s:SSE, t:MMX, w:W|R, e:7, a:D64 -PMOVMSKB ; Gy,Ux ; n/a ; 0x66 0x0F 0xD7 /r:reg ; s:SSE2, t:SSE, w:W|R, e:7, a:D64 -PSUBUSB ; Pq,Qq ; n/a ; NP 0x0F 0xD8 /r ; s:MMX, t:MMX, w:RW|R -PSUBUSB ; Vx,Wx ; n/a ; 0x66 0x0F 0xD8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSUBUSW ; Pq,Qq ; n/a ; NP 0x0F 0xD9 /r ; s:MMX, t:MMX, w:RW|R -PSUBUSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xD9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMINUB ; Pq,Qq ; n/a ; NP 0x0F 0xDA /r ; s:MMX, t:MMX, w:RW|R -PMINUB ; Vx,Wx ; n/a ; 0x66 0x0F 0xDA /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PAND ; Pq,Qq ; n/a ; NP 0x0F 0xDB /r ; s:MMX, t:LOGICAL, w:RW|R -PAND ; Vx,Wx ; n/a ; 0x66 0x0F 0xDB /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 -PADDUSB ; Pq,Qq ; n/a ; NP 0x0F 0xDC /r ; s:MMX, t:MMX, w:RW|R -PADDUSB ; Vx,Wx ; n/a ; 0x66 0x0F 0xDC /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDUSW ; Pq,Qq ; n/a ; NP 0x0F 0xDD /r ; s:MMX, t:MMX, w:RW|R -PADDUSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xDD /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMAXUB ; Pq,Qq ; n/a ; NP 0x0F 0xDE /r ; s:MMX, t:MMX, w:RW|R -PMAXUB ; Vx,Wx ; n/a ; 0x66 0x0F 0xDE /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PANDN ; Pq,Qq ; n/a ; NP 0x0F 0xDF /r ; s:MMX, t:LOGICAL, w:RW|R -PANDN ; Vx,Wx ; n/a ; 0x66 0x0F 0xDF /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 +ADDSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 +ADDSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2 +PSRLW ; Pq,Qq ; ; NP 0x0F 0xD1 /r ; s:MMX, t:MMX, w:RW|R +PSRLW ; Vx,Wx ; ; 0x66 0x0F 0xD1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRLD ; Pq,Qq ; ; NP 0x0F 0xD2 /r ; s:MMX, t:MMX, w:RW|R +PSRLD ; Vx,Wx ; ; 0x66 0x0F 0xD2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRLQ ; Pq,Qq ; ; NP 0x0F 0xD3 /r ; s:MMX, t:MMX, w:RW|R +PSRLQ ; Vx,Wx ; ; 0x66 0x0F 0xD3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDQ ; Pq,Qq ; ; NP 0x0F 0xD4 /r ; s:SSE2, t:MMX, w:RW|R, e:4 +PADDQ ; Vx,Wx ; ; 0x66 0x0F 0xD4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMULLW ; Pq,Qq ; ; NP 0x0F 0xD5 /r ; s:MMX, t:MMX, w:RW|R +PMULLW ; Vx,Wx ; ; 0x66 0x0F 0xD5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +MOVQ ; Wq,Vq ; ; 0x66 0x0F 0xD6 /r ; s:SSE2, t:DATAXFER, w:W|R, e:5 +MOVQ2DQ ; Vdq,Nq ; ; 0xF3 0x0F 0xD6 /r:reg ; s:SSE2, t:DATAXFER, w:W|R +MOVDQ2Q ; Pq,Uq ; ; 0xF2 0x0F 0xD6 /r:reg ; s:SSE2, t:DATAXFER, w:W|R +PMOVMSKB ; Gy,Nq ; ; NP 0x0F 0xD7 /r:reg ; s:SSE, t:MMX, w:W|R, e:7, a:D64 +PMOVMSKB ; Gy,Ux ; ; 0x66 0x0F 0xD7 /r:reg ; s:SSE2, t:SSE, w:W|R, e:7, a:D64 +PSUBUSB ; Pq,Qq ; ; NP 0x0F 0xD8 /r ; s:MMX, t:MMX, w:RW|R +PSUBUSB ; Vx,Wx ; ; 0x66 0x0F 0xD8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSUBUSW ; Pq,Qq ; ; NP 0x0F 0xD9 /r ; s:MMX, t:MMX, w:RW|R +PSUBUSW ; Vx,Wx ; ; 0x66 0x0F 0xD9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMINUB ; Pq,Qq ; ; NP 0x0F 0xDA /r ; s:MMX, t:MMX, w:RW|R +PMINUB ; Vx,Wx ; ; 0x66 0x0F 0xDA /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PAND ; Pq,Qq ; ; NP 0x0F 0xDB /r ; s:MMX, t:LOGICAL, w:RW|R +PAND ; Vx,Wx ; ; 0x66 0x0F 0xDB /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 +PADDUSB ; Pq,Qq ; ; NP 0x0F 0xDC /r ; s:MMX, t:MMX, w:RW|R +PADDUSB ; Vx,Wx ; ; 0x66 0x0F 0xDC /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDUSW ; Pq,Qq ; ; NP 0x0F 0xDD /r ; s:MMX, t:MMX, w:RW|R +PADDUSW ; Vx,Wx ; ; 0x66 0x0F 0xDD /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMAXUB ; Pq,Qq ; ; NP 0x0F 0xDE /r ; s:MMX, t:MMX, w:RW|R +PMAXUB ; Vx,Wx ; ; 0x66 0x0F 0xDE /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PANDN ; Pq,Qq ; ; NP 0x0F 0xDF /r ; s:MMX, t:LOGICAL, w:RW|R +PANDN ; Vx,Wx ; ; 0x66 0x0F 0xDF /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 # 0xE0 - 0xEF -PAVGB ; Pq,Qq ; n/a ; NP 0x0F 0xE0 /r ; s:MMX, t:MMX, w:RW|R -PAVGB ; Vx,Wx ; n/a ; 0x66 0x0F 0xE0 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRAW ; Pq,Qq ; n/a ; NP 0x0F 0xE1 /r ; s:MMX, t:MMX, w:RW|R -PSRAW ; Vx,Wx ; n/a ; 0x66 0x0F 0xE1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSRAD ; Pq,Qq ; n/a ; NP 0x0F 0xE2 /r ; s:MMX, t:MMX, w:RW|R -PSRAD ; Vx,Wx ; n/a ; 0x66 0x0F 0xE2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PAVGW ; Pq,Qq ; n/a ; NP 0x0F 0xE3 /r ; s:MMX, t:MMX, w:RW|R -PAVGW ; Vx,Wx ; n/a ; 0x66 0x0F 0xE3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMULHUW ; Pq,Qq ; n/a ; NP 0x0F 0xE4 /r ; s:MMX, t:MMX, w:RW|R -PMULHUW ; Vx,Wx ; n/a ; 0x66 0x0F 0xE4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMULHW ; Pq,Qq ; n/a ; NP 0x0F 0xE5 /r ; s:MMX, t:MMX, w:RW|R -PMULHW ; Vx,Wx ; n/a ; 0x66 0x0F 0xE5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -CVTTPD2DQ ; Vx,Wpd ; n/a ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -CVTDQ2PD ; Vx,Wq ; n/a ; 0xF3 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:5 -CVTPD2DQ ; Vx,Wpd ; n/a ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 -MOVNTQ ; Mq,Pq ; n/a ; NP 0x0F 0xE7 /r:mem ; s:MMX, t:DATAXFER, w:W|R -MOVNTDQ ; Mx,Vx ; n/a ; 0x66 0x0F 0xE7 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 -PSUBSB ; Pq,Qq ; n/a ; NP 0x0F 0xE8 /r ; s:MMX, t:MMX, w:RW|R -PSUBSB ; Vx,Wx ; n/a ; 0x66 0x0F 0xE8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSUBSW ; Pq,Qq ; n/a ; NP 0x0F 0xE9 /r ; s:MMX, t:MMX, w:RW|R -PSUBSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xE9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMINSW ; Pq,Qq ; n/a ; NP 0x0F 0xEA /r ; s:MMX, t:MMX, w:RW|R -PMINSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xEA /r ; s:SSE2, t:SSE, w:RW|R, e:4 -POR ; Pq,Qq ; n/a ; NP 0x0F 0xEB /r ; s:MMX, t:LOGICAL, w:RW|R -POR ; Vx,Wx ; n/a ; 0x66 0x0F 0xEB /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 -PADDSB ; Pq,Qq ; n/a ; NP 0x0F 0xEC /r ; s:MMX, t:MMX, w:RW|R -PADDSB ; Vx,Wx ; n/a ; 0x66 0x0F 0xEC /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDSW ; Pq,Qq ; n/a ; NP 0x0F 0xED /r ; s:MMX, t:MMX, w:RW|R -PADDSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xED /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMAXSW ; Pq,Qq ; n/a ; NP 0x0F 0xEE /r ; s:MMX, t:MMX, w:RW|R -PMAXSW ; Vx,Wx ; n/a ; 0x66 0x0F 0xEE /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PXOR ; Pq,Qq ; n/a ; NP 0x0F 0xEF /r ; s:MMX, t:LOGICAL, w:RW|R -PXOR ; Vx,Wx ; n/a ; 0x66 0x0F 0xEF /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 +PAVGB ; Pq,Qq ; ; NP 0x0F 0xE0 /r ; s:MMX, t:MMX, w:RW|R +PAVGB ; Vx,Wx ; ; 0x66 0x0F 0xE0 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRAW ; Pq,Qq ; ; NP 0x0F 0xE1 /r ; s:MMX, t:MMX, w:RW|R +PSRAW ; Vx,Wx ; ; 0x66 0x0F 0xE1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSRAD ; Pq,Qq ; ; NP 0x0F 0xE2 /r ; s:MMX, t:MMX, w:RW|R +PSRAD ; Vx,Wx ; ; 0x66 0x0F 0xE2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PAVGW ; Pq,Qq ; ; NP 0x0F 0xE3 /r ; s:MMX, t:MMX, w:RW|R +PAVGW ; Vx,Wx ; ; 0x66 0x0F 0xE3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMULHUW ; Pq,Qq ; ; NP 0x0F 0xE4 /r ; s:MMX, t:MMX, w:RW|R +PMULHUW ; Vx,Wx ; ; 0x66 0x0F 0xE4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMULHW ; Pq,Qq ; ; NP 0x0F 0xE5 /r ; s:MMX, t:MMX, w:RW|R +PMULHW ; Vx,Wx ; ; 0x66 0x0F 0xE5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +CVTTPD2DQ ; Vx,Wpd ; ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +CVTDQ2PD ; Vx,Wq ; ; 0xF3 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:5 +CVTPD2DQ ; Vx,Wpd ; ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2 +MOVNTQ ; Mq,Pq ; ; NP 0x0F 0xE7 /r:mem ; s:MMX, t:DATAXFER, w:W|R +MOVNTDQ ; Mx,Vx ; ; 0x66 0x0F 0xE7 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1 +PSUBSB ; Pq,Qq ; ; NP 0x0F 0xE8 /r ; s:MMX, t:MMX, w:RW|R +PSUBSB ; Vx,Wx ; ; 0x66 0x0F 0xE8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSUBSW ; Pq,Qq ; ; NP 0x0F 0xE9 /r ; s:MMX, t:MMX, w:RW|R +PSUBSW ; Vx,Wx ; ; 0x66 0x0F 0xE9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMINSW ; Pq,Qq ; ; NP 0x0F 0xEA /r ; s:MMX, t:MMX, w:RW|R +PMINSW ; Vx,Wx ; ; 0x66 0x0F 0xEA /r ; s:SSE2, t:SSE, w:RW|R, e:4 +POR ; Pq,Qq ; ; NP 0x0F 0xEB /r ; s:MMX, t:LOGICAL, w:RW|R +POR ; Vx,Wx ; ; 0x66 0x0F 0xEB /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 +PADDSB ; Pq,Qq ; ; NP 0x0F 0xEC /r ; s:MMX, t:MMX, w:RW|R +PADDSB ; Vx,Wx ; ; 0x66 0x0F 0xEC /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDSW ; Pq,Qq ; ; NP 0x0F 0xED /r ; s:MMX, t:MMX, w:RW|R +PADDSW ; Vx,Wx ; ; 0x66 0x0F 0xED /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMAXSW ; Pq,Qq ; ; NP 0x0F 0xEE /r ; s:MMX, t:MMX, w:RW|R +PMAXSW ; Vx,Wx ; ; 0x66 0x0F 0xEE /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PXOR ; Pq,Qq ; ; NP 0x0F 0xEF /r ; s:MMX, t:LOGICAL, w:RW|R +PXOR ; Vx,Wx ; ; 0x66 0x0F 0xEF /r ; s:SSE2, t:LOGICAL, w:RW|R, e:4 # 0xF0 - 0xFF -LDDQU ; Vx,Mx ; n/a ; 0xF2 0x0F 0xF0 /r:mem ; s:SSE3, t:SSE, w:W|R, e:4 -PSLLW ; Pq,Qq ; n/a ; NP 0x0F 0xF1 /r ; s:MMX, t:MMX, w:RW|R -PSLLW ; Vx,Wx ; n/a ; 0x66 0x0F 0xF1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSLLD ; Pq,Qq ; n/a ; NP 0x0F 0xF2 /r ; s:MMX, t:MMX, w:RW|R -PSLLD ; Vx,Wx ; n/a ; 0x66 0x0F 0xF2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSLLQ ; Pq,Qq ; n/a ; NP 0x0F 0xF3 /r ; s:MMX, t:MMX, w:RW|R -PSLLQ ; Vx,Wx ; n/a ; 0x66 0x0F 0xF3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMULUDQ ; Pq,Qq ; n/a ; NP 0x0F 0xF4 /r ; s:SSE2, t:MMX, w:RW|R, e:4 -PMULUDQ ; Vx,Wx ; n/a ; 0x66 0x0F 0xF4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PMADDWD ; Pq,Qq ; n/a ; NP 0x0F 0xF5 /r ; s:MMX, t:MMX, w:RW|R -PMADDWD ; Vx,Wx ; n/a ; 0x66 0x0F 0xF5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSADBW ; Pq,Qq ; n/a ; NP 0x0F 0xF6 /r ; s:MMX, t:MMX, w:RW|R -PSADBW ; Vx,Wx ; n/a ; 0x66 0x0F 0xF6 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +LDDQU ; Vx,Mx ; ; 0xF2 0x0F 0xF0 /r:mem ; s:SSE3, t:SSE, w:W|R, e:4 +PSLLW ; Pq,Qq ; ; NP 0x0F 0xF1 /r ; s:MMX, t:MMX, w:RW|R +PSLLW ; Vx,Wx ; ; 0x66 0x0F 0xF1 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSLLD ; Pq,Qq ; ; NP 0x0F 0xF2 /r ; s:MMX, t:MMX, w:RW|R +PSLLD ; Vx,Wx ; ; 0x66 0x0F 0xF2 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSLLQ ; Pq,Qq ; ; NP 0x0F 0xF3 /r ; s:MMX, t:MMX, w:RW|R +PSLLQ ; Vx,Wx ; ; 0x66 0x0F 0xF3 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMULUDQ ; Pq,Qq ; ; NP 0x0F 0xF4 /r ; s:SSE2, t:MMX, w:RW|R, e:4 +PMULUDQ ; Vx,Wx ; ; 0x66 0x0F 0xF4 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PMADDWD ; Pq,Qq ; ; NP 0x0F 0xF5 /r ; s:MMX, t:MMX, w:RW|R +PMADDWD ; Vx,Wx ; ; 0x66 0x0F 0xF5 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSADBW ; Pq,Qq ; ; NP 0x0F 0xF6 /r ; s:MMX, t:MMX, w:RW|R +PSADBW ; Vx,Wx ; ; 0x66 0x0F 0xF6 /r ; s:SSE2, t:SSE, w:RW|R, e:4 MASKMOVQ ; Pq,Nq ; pDIq ; NP 0x0F 0xF7 /r:reg ; s:MMX, t:DATAXFER, w:R|R|W MASKMOVDQU ; Vdq,Udq ; pDIdq ; 0x66 0x0F 0xF7 /r:reg ; s:SSE2, t:DATAXFER, w:R|R|W, e:4 -PSUBB ; Pq,Qq ; n/a ; NP 0x0F 0xF8 /r ; s:MMX, t:MMX, w:RW|R -PSUBB ; Vx,Wx ; n/a ; 0x66 0x0F 0xF8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSUBW ; Pq,Qq ; n/a ; NP 0x0F 0xF9 /r ; s:MMX, t:MMX, w:RW|R -PSUBW ; Vx,Wx ; n/a ; 0x66 0x0F 0xF9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSUBD ; Pq,Qq ; n/a ; NP 0x0F 0xFA /r ; s:MMX, t:MMX, w:RW|R -PSUBD ; Vx,Wx ; n/a ; 0x66 0x0F 0xFA /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PSUBQ ; Pq,Qq ; n/a ; NP 0x0F 0xFB /r ; s:MMX, t:MMX, w:RW|R -PSUBQ ; Vx,Wx ; n/a ; 0x66 0x0F 0xFB /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDB ; Pq,Qq ; n/a ; NP 0x0F 0xFC /r ; s:MMX, t:MMX, w:RW|R -PADDB ; Vx,Wx ; n/a ; 0x66 0x0F 0xFC /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDW ; Pq,Qq ; n/a ; NP 0x0F 0xFD /r ; s:MMX, t:MMX, w:RW|R -PADDW ; Vx,Wx ; n/a ; 0x66 0x0F 0xFD /r ; s:SSE2, t:SSE, w:RW|R, e:4 -PADDD ; Pq,Qq ; n/a ; NP 0x0F 0xFE /r ; s:MMX, t:MMX, w:RW|R -PADDD ; Vx,Wx ; n/a ; 0x66 0x0F 0xFE /r ; s:SSE2, t:SSE, w:RW|R, e:4 -UD0 ; Gd,Ed ; n/a ; 0x0F 0xFF /r ; s:UD, t:UD, w:R|R +PSUBB ; Pq,Qq ; ; NP 0x0F 0xF8 /r ; s:MMX, t:MMX, w:RW|R +PSUBB ; Vx,Wx ; ; 0x66 0x0F 0xF8 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSUBW ; Pq,Qq ; ; NP 0x0F 0xF9 /r ; s:MMX, t:MMX, w:RW|R +PSUBW ; Vx,Wx ; ; 0x66 0x0F 0xF9 /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSUBD ; Pq,Qq ; ; NP 0x0F 0xFA /r ; s:MMX, t:MMX, w:RW|R +PSUBD ; Vx,Wx ; ; 0x66 0x0F 0xFA /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PSUBQ ; Pq,Qq ; ; NP 0x0F 0xFB /r ; s:MMX, t:MMX, w:RW|R +PSUBQ ; Vx,Wx ; ; 0x66 0x0F 0xFB /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDB ; Pq,Qq ; ; NP 0x0F 0xFC /r ; s:MMX, t:MMX, w:RW|R +PADDB ; Vx,Wx ; ; 0x66 0x0F 0xFC /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDW ; Pq,Qq ; ; NP 0x0F 0xFD /r ; s:MMX, t:MMX, w:RW|R +PADDW ; Vx,Wx ; ; 0x66 0x0F 0xFD /r ; s:SSE2, t:SSE, w:RW|R, e:4 +PADDD ; Pq,Qq ; ; NP 0x0F 0xFE /r ; s:MMX, t:MMX, w:RW|R +PADDD ; Vx,Wx ; ; 0x66 0x0F 0xFE /r ; s:SSE2, t:SSE, w:RW|R, e:4 +UD0 ; Gd,Ed ; ; 0x0F 0xFF /r ; s:UD, t:UD, w:R|R diff --git a/isagenerator/instructions/table_legacy_2.dat b/isagenerator/instructions/table_legacy_2.dat new file mode 100644 index 0000000..a34033f --- /dev/null +++ b/isagenerator/instructions/table_legacy_2.dat @@ -0,0 +1,148 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +# 0x00 - 0x0F +PSHUFB ; Pq,Qq ; ; NP 0x0F 0x38 0x00 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PSHUFB ; Vx,Wx ; ; 0x66 0x0F 0x38 0x00 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHADDW ; Pq,Qq ; ; NP 0x0F 0x38 0x01 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHADDW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x01 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHADDD ; Pq,Qq ; ; NP 0x0F 0x38 0x02 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHADDD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x02 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHADDSW ; Pq,Qq ; ; NP 0x0F 0x38 0x03 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHADDSW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x03 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PMADDUBSW ; Pq,Qq ; ; NP 0x0F 0x38 0x04 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PMADDUBSW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x04 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHSUBW ; Pq,Qq ; ; NP 0x0F 0x38 0x05 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHSUBW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x05 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHSUBD ; Pq,Qq ; ; NP 0x0F 0x38 0x06 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHSUBD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x06 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PHSUBSW ; Pq,Qq ; ; NP 0x0F 0x38 0x07 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PHSUBSW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x07 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PSIGNB ; Pq,Qq ; ; NP 0x0F 0x38 0x08 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PSIGNB ; Vx,Wx ; ; 0x66 0x0F 0x38 0x08 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PSIGNW ; Pq,Qq ; ; NP 0x0F 0x38 0x09 /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PSIGNW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x09 /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PSIGND ; Pq,Qq ; ; NP 0x0F 0x38 0x0A /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PSIGND ; Vx,Wx ; ; 0x66 0x0F 0x38 0x0A /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 +PMULHRSW ; Pq,Qq ; ; NP 0x0F 0x38 0x0B /r ; s:SSSE3, t:MMX, w:RW|R , a:NOREX2 +PMULHRSW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x0B /r ; s:SSSE3, t:SSE, w:RW|R, e:4, a:NOREX2 + +# 0x10 - 0x1F +PBLENDVB ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x10 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +BLENDVPS ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x14 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +BLENDVPD ; Vdq,Wdq ; XMM0 ; 0x66 0x0F 0x38 0x15 /r ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +PTEST ; Vdq,Wdq ; Fv ; 0x66 0x0F 0x38 0x17 /r ; s:SSE4, t:SSE, w:R|R|W, f:CF=m|PF=0|AF=0|ZF=m|SF=0|OF=0, e:4, a:NOREX2 +PABSB ; Pq,Qq ; ; NP 0x0F 0x38 0x1C /r ; s:SSSE3, t:MMX, w:W|R , a:NOREX2 +PABSB ; Vx,Wx ; ; 0x66 0x0F 0x38 0x1C /r ; s:SSSE3, t:SSE, w:W|R, e:4, a:NOREX2 +PABSW ; Pq,Qq ; ; NP 0x0F 0x38 0x1D /r ; s:SSSE3, t:MMX, w:W|R , a:NOREX2 +PABSW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x1D /r ; s:SSSE3, t:SSE, w:W|R, e:4, a:NOREX2 +PABSD ; Pq,Qq ; ; NP 0x0F 0x38 0x1E /r ; s:SSSE3, t:MMX, w:W|R , a:NOREX2 +PABSD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x1E /r ; s:SSSE3, t:SSE, w:W|R, e:4, a:NOREX2 + +# 0x20 - 0x2F +PMOVSXBW ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x20 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVSXBD ; Vdq,Wd ; ; 0x66 0x0F 0x38 0x21 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVSXBQ ; Vdq,Ww ; ; 0x66 0x0F 0x38 0x22 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVSXWD ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x23 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVSXWQ ; Vdq,Wd ; ; 0x66 0x0F 0x38 0x24 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVSXDQ ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x25 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMULDQ ; Vx,Wx ; ; 0x66 0x0F 0x38 0x28 /r ; s:SSE4, t:SSE, w:RW|R, e:4, a:NOREX2 +PCMPEQQ ; Vx,Wx ; ; 0x66 0x0F 0x38 0x29 /r ; s:SSE4, t:SSE, w:RW|R, e:4, a:NOREX2 +MOVNTDQA ; Vx,Mx ; ; 0x66 0x0F 0x38 0x2A /r:mem ; s:SSE4, t:SSE, w:W|R, e:1 , a:NOREX2 +PACKUSDW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x2B /r ; s:SSE4, t:SSE, w:RW|R, e:4, a:NOREX2 + + +# 0x30 - 0x3F +PMOVZXBW ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x30 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVZXBD ; Vdq,Wd ; ; 0x66 0x0F 0x38 0x31 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVZXBQ ; Vdq,Ww ; ; 0x66 0x0F 0x38 0x32 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVZXWD ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x33 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVZXWQ ; Vdq,Wd ; ; 0x66 0x0F 0x38 0x34 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PMOVZXDQ ; Vdq,Wq ; ; 0x66 0x0F 0x38 0x35 /r ; s:SSE4, t:SSE, w:W|R, e:5 , a:NOREX2 +PCMPGTQ ; Vx,Wx ; ; 0x66 0x0F 0x38 0x37 /r ; s:SSE42, t:SSE, w:RW|R, e:4, a:NOREX2 +PMINSB ; Vx,Wx ; ; 0x66 0x0F 0x38 0x38 /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMINSD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x39 /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMINUW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3A /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMINUD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3B /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMAXSB ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3C /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMAXSD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3D /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMAXUW ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3E /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 +PMAXUD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x3F /r ; s:SSE4, t:SSE, w:RW|R, e:4 , a:NOREX2 + +# 0x40 - 0x4F +PMULLD ; Vx,Wx ; ; 0x66 0x0F 0x38 0x40 /r ; s:SSE4, t:SSE, w:RW|R, e:4, a:NOREX2 +PHMINPOSUW ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0x41 /r ; s:SSE4, t:SSE, w:W|R, e:4, a:NOREX2 + +# 0x50 - 0x5F + +# 0x60 - 0x6F + +# 0x70 - 0x7F + +# 0x80 - 0x8F +INVEPT ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x80 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL|NOREX2, m:VMXROOT +INVVPID ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x81 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL|NOREX2, m:VMXROOT +INVPCID ; Gy,Mdq ; ; 0x66 0x0F 0x38 0x82 /r:mem ; s:INVPCID, t:MISC, w:R|R, a:F64|NOREX2, m:KERNEL|NOV86 + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +SHA1NEXTE ; Vdq,Wdq ; ; NP 0x0F 0x38 0xC8 /r ; s:SHA, t:SHA, w:RW|R, e:4, a:NOREX2 +SHA1MSG1 ; Vdq,Wdq ; ; NP 0x0F 0x38 0xC9 /r ; s:SHA, t:SHA, w:RW|R, e:4, a:NOREX2 +SHA1MSG2 ; Vdq,Wdq ; ; NP 0x0F 0x38 0xCA /r ; s:SHA, t:SHA, w:RW|R, e:4, a:NOREX2 +SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; NP 0x0F 0x38 0xCB /r ; s:SHA, t:SHA, w:RW|R|R, e:4, a:NOREX2 +SHA256MSG1 ; Vdq,Wdq ; ; NP 0x0F 0x38 0xCC /r ; s:SHA, t:SHA, w:RW|R, e:4, a:NOREX2 +SHA256MSG2 ; Vdq,Wdq ; ; NP 0x0F 0x38 0xCD /r ; s:SHA, t:SHA, w:RW|R, e:4, a:NOREX2 +GF2P8MULB ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xCF /r ; s:GFNI, t:GFNI, w:RW|R, e:4, a:NOREX2 + +# 0xD0 - 0xDF +AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /0:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL, a:NOREX2 +AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /1:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL, a:NOREX2 +AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /2:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL, a:NOREX2 +AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; 0xF3 0x0F 0x38 0xD8 /3:mem ; s:KL, t:WIDE_KL, w:R|RW|W, f:AESKL, a:NOREX2 +AESIMC ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xDB /r ; s:AES, t:AES, w:W|R, e:4, a:NOREX2 +AESENC ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xDC /r ; s:AES, t:AES, w:RW|R, e:4, a:NOREX2 +AESENC128KL ; Vdq,M384 ; Fv ; 0xF3 0x0F 0x38 0xDC /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL, a:NOREX2 +LOADIWKEY ; Vdq,Udq ; EAX,XMM0,Fv ; 0xF3 0x0F 0x38 0xDC /r:reg ; s:KL, t:KL, w:R|R|R|R|W, f:AESKL, m:KERNEL, a:NOREX2 +AESENCLAST ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xDD /r ; s:AES, t:AES, w:RW|R, e:4, a:NOREX2 +AESDEC128KL ; Vdq,M384 ; Fv ; 0xF3 0x0F 0x38 0xDD /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL, a:NOREX2 +AESDEC ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xDE /r ; s:AES, t:AES, w:RW|R, e:4, a:NOREX2 +AESENC256KL ; Vdq,M512 ; Fv ; 0xF3 0x0F 0x38 0xDE /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL, a:NOREX2 +AESDECLAST ; Vdq,Wdq ; ; 0x66 0x0F 0x38 0xDF /r ; s:AES, t:AES, w:RW|R, e:4, a:NOREX2 +AESDEC256KL ; Vdq,M512 ; Fv ; 0xF3 0x0F 0x38 0xDF /r:mem ; s:KL, t:AESKL, w:RW|R|W, f:AESKL, a:NOREX2 + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF +MOVBE ; Gv,Mv ; ; NP 0x0F 0x38 0xF0 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:NOREX2 +MOVBE ; Gv,Mv ; ; 0x66 0x0F 0x38 0xF0 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:S66|NOREX2 +CRC32 ; Gy,Eb ; ; 0xF2 0x0F 0x38 0xF0 /r ; s:SSE42, t:SSE, w:RW|R, a:NOREX2 +MOVBE ; Mv,Gv ; ; NP 0x0F 0x38 0xF1 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:NOREX2 +MOVBE ; Mv,Gv ; ; 0x66 0x0F 0x38 0xF1 /r:mem ; s:MOVBE, t:DATAXFER, w:W|R, a:S66|NOREX2 +CRC32 ; Gy,Ev ; ; 0xF2 0x0F 0x38 0xF1 /r ; s:SSE42, t:SSE, w:RW|R, a:NOREX2 +WRUSSD ; My,Gy ; ; 0x66 0x0F 0x38 0xF5 /r:mem ; s:CET_SS, t:CET, c:WRUSS, a:SHS|NOREX2, w:W|R, m:KERNEL +WRUSSQ ; My,Gy ; ; rexw 0x66 0x0F 0x38 0xF5 /r:mem ; s:CET_SS, t:CET, c:WRUSS, a:SHS|NOREX2, w:W|R, m:KERNEL +WRSSD ; My,Gy ; ; NP 0x0F 0x38 0xF6 /r:mem ; s:CET_SS, t:CET, c:WRSS, a:SHS|NOREX2, w:W|R +WRSSQ ; My,Gy ; ; rexw NP 0x0F 0x38 0xF6 /r:mem ; s:CET_SS, t:CET, c:WRSS, a:SHS|NOREX2, w:W|R +ADCX ; Gy,Ey ; Fv ; 0x66 0x0F 0x38 0xF6 /r ; s:ADX, t:ARITH, w:RW|R|RW, f:CF=m, a:NOREX2 +ADOX ; Gy,Ey ; Fv ; 0xF3 0x0F 0x38 0xF6 /r ; s:ADX, t:ARITH, w:RW|R|RW, f:OF=m, a:NOREX2 +MOVDIR64B ; rMoq,Moq ; ; 0x66 0x0F 0x38 0xF8 /r:mem ; s:MOVDIR64B, t:MOVDIR64B, w:W|R, a:NOREX2 +ENQCMD ; rM?,Moq ; Fv ; 0xF2 0x0F 0x38 0xF8 /r:mem ; s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD, a:NOREX2 +ENQCMDS ; rM?,Moq ; Fv ; 0xF3 0x0F 0x38 0xF8 /r:mem ; s:ENQCMD, t:ENQCMD, w:W|R|W, f:ENQCMD, a:NOREX2 +URDMSR ; Rq,Gq ; MSR ; 0xF2 0x0F 0x38 0xF8 /r:reg ; s:USER_MSR, t:USER_MSR, w:W|R|R, m:O64 +UWRMSR ; Gq,Rq ; MSR ; 0xF3 0x0F 0x38 0xF8 /r:reg ; s:USER_MSR, t:USER_MSR, w:R|R|W, m:O64 +MOVDIRI ; My,Gy ; ; NP 0x0F 0x38 0xF9 /r:mem ; s:MOVDIRI, t:MOVDIRI, w:W|R, a:NOREX2 + +ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; 0xF3 0x0F 0x38 0xFA /r:reg ; s:KL, t:AESKL, w:W|R|R|W|W|W, f:ZERO, a:NOREX2 +ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; 0xF3 0x0F 0x38 0xFB /r:reg ; s:KL, t:AESKL, w:W|R|RW|W|W, f:ZERO, a:NOREX2 + +AADD ; My,Gy ; ; NP 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R, a:NOREX2 +AAND ; My,Gy ; ; 0x66 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R, a:NOREX2 +AOR ; My,Gy ; ; 0xF2 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R, a:NOREX2 +AXOR ; My,Gy ; ; 0xF3 0x0F 0x38 0xFC /r:mem ; s:RAOINT, t:RAOINT, w:RW|R, a:NOREX2 diff --git a/isagenerator/instructions/table_legacy_3.dat b/isagenerator/instructions/table_legacy_3.dat new file mode 100644 index 0000000..bfe97ca --- /dev/null +++ b/isagenerator/instructions/table_legacy_3.dat @@ -0,0 +1,74 @@ +# +# Copyright (c) 2020 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +# 0x00 - 0x0F +ROUNDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2 +ROUNDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2 +ROUNDSS ; Vss,Wss,Ib ; ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2 +ROUNDSD ; Vsd,Wsd,Ib ; ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2 +BLENDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0C /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +BLENDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0D /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +PBLENDW ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0E /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +PALIGNR ; Pq,Qq,Ib ; ; NP 0x0F 0x3A 0x0F /r ib ; s:SSSE3, t:MMX, w:RW|R|R, a:NOREX2 +PALIGNR ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0F /r ib ; s:SSSE3, t:SSE, w:RW|R|R, e:4, a:NOREX2 + +# 0x10 - 0x1F +# TODO: for PEXTRx, a smaller size is accessed, in fact. +PEXTRB ; Mb,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x14 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 +PEXTRB ; Ry,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x14 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64|NOREX2 +PEXTRW ; Mw,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x15 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 +PEXTRW ; Ry,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x15 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64|NOREX2 +PEXTRD ; Md,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x16 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 +PEXTRD ; Ry,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x16 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:D64|NOREX2 +PEXTRQ ; Mq,Vdq,Ib ; ; rexw 0x66 0x0F 0x3A 0x16 /r:mem ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 +PEXTRQ ; Ry,Vdq,Ib ; ; rexw 0x66 0x0F 0x3A 0x16 /r:reg ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 +EXTRACTPS ; Ed,Vdq,Ib ; ; 0x66 0x0F 0x3A 0x17 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:5, a:NOREX2 + +# 0x20 - 0x2F +PINSRB ; Vdq,Mb,Ib ; ; 0x66 0x0F 0x3A 0x20 /r:mem ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 +PINSRB ; Vdq,Ry,Ib ; ; 0x66 0x0F 0x3A 0x20 /r:reg ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 +INSERTPS ; Vdq,Md,Ib ; ; 0x66 0x0F 0x3A 0x21 /r:mem ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 +INSERTPS ; Vdq,Udq,Ib ; ; 0x66 0x0F 0x3A 0x21 /r:reg ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 +PINSRD ; Vdq,Ed,Ib ; ; 0x66 0x0F 0x3A 0x22 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 +PINSRQ ; Vdq,Eq,Ib ; ; rexw 0x66 0x0F 0x3A 0x22 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:5, a:NOREX2 + +# 0x30 - 0x3F + +# 0x40 - 0x4F +DPPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2 +DPPD ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2 +MPSADBW ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x42 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2 +PCLMULQDQ ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x44 /r ib ; s:PCLMULQDQ, t:PCLMULQDQ, w:RW|R|R, e:4, a:NOREX2 + +# 0x50 - 0x5F + +# 0x60 - 0x6F +PCMPESTRM ; Vdq,Wdq,Ib ; yAX,yDX,XMM0,Fv ; 0x66 0x0F 0x3A 0x60 /r ib ; s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4, a:NOREX2 +PCMPESTRI ; Vdq,Wdq,Ib ; yAX,yDX,yCX,Fv ; 0x66 0x0F 0x3A 0x61 /r ib ; s:SSE42, t:SSE, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4, a:NOREX2 +PCMPISTRM ; Vdq,Wdq,Ib ; XMM0,Fv ; 0x66 0x0F 0x3A 0x62 /r ib ; s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4, a:NOREX2 +PCMPISTRI ; Vdq,Wdq,Ib ; yCX,Fv ; 0x66 0x0F 0x3A 0x63 /r ib ; s:SSE42, t:SSE, w:R|R|R|W|W, f:PCMPSTR, e:4, a:NOREX2 + +# 0x70 - 0x7F + +# 0x80 - 0x8F + +# 0x90 - 0x9F + +# 0xA0 - 0xAF + +# 0xB0 - 0xBF + +# 0xC0 - 0xCF +SHA1RNDS4 ; Vdq,Wdq,Ib ; ; NP 0x0F 0x3A 0xCC /r ib ; s:SHA, t:SHA, w:RW|R|R, e:4, a:NOREX2 +GF2P8AFFINEQB ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0xCE /r ib ; s:GFNI, t:GFNI, w:RW|R|R, e:4, a:NOREX2 +GF2P8AFFINEINVQB ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0xCF /r ib ; s:GFNI, t:GFNI, w:RW|R|R, e:4, a:NOREX2 + +# 0xD0 - 0xDF +AESKEYGENASSIST ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4, a:NOREX2 + +# 0xE0 - 0xEF + +# 0xF0 - 0xFF +HRESET ; Ib ; EAX ; 0xF3 0x0F 0x3A 0xF0 /0xC0 ib ; s:HRESET, t:HRESET, w:N|R, m:KERNEL|NOV86|NOTSX, a:NOREX2 diff --git a/isagenerator/instructions/table_fpu.dat b/isagenerator/instructions/table_legacy_fpu.dat similarity index 86% rename from isagenerator/instructions/table_fpu.dat rename to isagenerator/instructions/table_legacy_fpu.dat index 90723a6..f72df40 100644 --- a/isagenerator/instructions/table_fpu.dat +++ b/isagenerator/instructions/table_legacy_fpu.dat @@ -30,34 +30,34 @@ FLDCW ; Mw ; X87CONTROL,X87STATUS ; 0xD9 /5:mem ; s FNSTENV ; Mfe ; X87STATUS ; 0xD9 /6:mem ; s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u FNSTCW ; Mw ; X87CONTROL,X87STATUS ; 0xD9 /7:mem ; s:X87, t:X87_ALU, w:W|R|W, u:C0=u|C1=u|C2=u|C3=u -FNOP ; n/a ; n/a ; 0xD9 /0xD0 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u -FCHS ; n/a ; X87STATUS ; 0xD9 /0xE0 ; s:X87, t:X87_ALU, w:W, u:C1=0 -FABS ; n/a ; X87STATUS ; 0xD9 /0xE1 ; s:X87, t:X87_ALU, w:W, u:C1=0 -FTST ; n/a ; X87STATUS ; 0xD9 /0xE4 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m -FXAM ; n/a ; X87STATUS ; 0xD9 /0xE5 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m -FLD1 ; n/a ; X87STATUS ; 0xD9 /0xE8 ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDL2T ; n/a ; X87STATUS ; 0xD9 /0xE9 ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDL2E ; n/a ; X87STATUS ; 0xD9 /0xEA ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDPI ; n/a ; X87STATUS ; 0xD9 /0xEB ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDLG2 ; n/a ; X87STATUS ; 0xD9 /0xEC ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDLN2 ; n/a ; X87STATUS ; 0xD9 /0xED ; s:X87, t:X87_ALU, w:W, u:C1=m -FLDZ ; n/a ; X87STATUS ; 0xD9 /0xEE ; s:X87, t:X87_ALU, w:W, u:C1=m -F2XM1 ; n/a ; X87STATUS ; 0xD9 /0xF0 ; s:X87, t:X87_ALU, w:W, u:C1=m -FYL2X ; n/a ; X87STATUS ; 0xD9 /0xF1 ; s:X87, t:X87_ALU, w:W, u:C1=m -FPTAN ; n/a ; X87STATUS ; 0xD9 /0xF2 ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m -FPATAN ; n/a ; X87STATUS ; 0xD9 /0xF3 ; s:X87, t:X87_ALU, w:W, u:C1=m -FXTRACT ; n/a ; X87STATUS ; 0xD9 /0xF4 ; s:X87, t:X87_ALU, w:W, u:C1=m -FPREM1 ; n/a ; X87STATUS ; 0xD9 /0xF5 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m -FDECSTP ; n/a ; X87STATUS ; 0xD9 /0xF6 ; s:X87, t:X87_ALU, w:W, u:C1=0 -FINCSTP ; n/a ; X87STATUS ; 0xD9 /0xF7 ; s:X87, t:X87_ALU, w:W, u:C1=0 -FPREM ; n/a ; X87STATUS ; 0xD9 /0xF8 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m -FYL2XP1 ; n/a ; X87STATUS ; 0xD9 /0xF9 ; s:X87, t:X87_ALU, w:W, u:C1=m -FSQRT ; n/a ; X87STATUS ; 0xD9 /0xFA ; s:X87, t:X87_ALU, w:W, u:C1=m -FSINCOS ; n/a ; X87STATUS ; 0xD9 /0xFB ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m -FRNDINT ; n/a ; X87STATUS ; 0xD9 /0xFC ; s:X87, t:X87_ALU, w:W, u:C1=m -FSCALE ; n/a ; X87STATUS ; 0xD9 /0xFD ; s:X87, t:X87_ALU, w:W, u:C1=m -FSIN ; n/a ; X87STATUS ; 0xD9 /0xFE ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m -FCOS ; n/a ; X87STATUS ; 0xD9 /0xFF ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FNOP ; ; ; 0xD9 /0xD0 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FCHS ; ; X87STATUS ; 0xD9 /0xE0 ; s:X87, t:X87_ALU, w:W, u:C1=0 +FABS ; ; X87STATUS ; 0xD9 /0xE1 ; s:X87, t:X87_ALU, w:W, u:C1=0 +FTST ; ; X87STATUS ; 0xD9 /0xE4 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m +FXAM ; ; X87STATUS ; 0xD9 /0xE5 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FLD1 ; ; X87STATUS ; 0xD9 /0xE8 ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDL2T ; ; X87STATUS ; 0xD9 /0xE9 ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDL2E ; ; X87STATUS ; 0xD9 /0xEA ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDPI ; ; X87STATUS ; 0xD9 /0xEB ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDLG2 ; ; X87STATUS ; 0xD9 /0xEC ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDLN2 ; ; X87STATUS ; 0xD9 /0xED ; s:X87, t:X87_ALU, w:W, u:C1=m +FLDZ ; ; X87STATUS ; 0xD9 /0xEE ; s:X87, t:X87_ALU, w:W, u:C1=m +F2XM1 ; ; X87STATUS ; 0xD9 /0xF0 ; s:X87, t:X87_ALU, w:W, u:C1=m +FYL2X ; ; X87STATUS ; 0xD9 /0xF1 ; s:X87, t:X87_ALU, w:W, u:C1=m +FPTAN ; ; X87STATUS ; 0xD9 /0xF2 ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FPATAN ; ; X87STATUS ; 0xD9 /0xF3 ; s:X87, t:X87_ALU, w:W, u:C1=m +FXTRACT ; ; X87STATUS ; 0xD9 /0xF4 ; s:X87, t:X87_ALU, w:W, u:C1=m +FPREM1 ; ; X87STATUS ; 0xD9 /0xF5 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FDECSTP ; ; X87STATUS ; 0xD9 /0xF6 ; s:X87, t:X87_ALU, w:W, u:C1=0 +FINCSTP ; ; X87STATUS ; 0xD9 /0xF7 ; s:X87, t:X87_ALU, w:W, u:C1=0 +FPREM ; ; X87STATUS ; 0xD9 /0xF8 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FYL2XP1 ; ; X87STATUS ; 0xD9 /0xF9 ; s:X87, t:X87_ALU, w:W, u:C1=m +FSQRT ; ; X87STATUS ; 0xD9 /0xFA ; s:X87, t:X87_ALU, w:W, u:C1=m +FSINCOS ; ; X87STATUS ; 0xD9 /0xFB ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FRNDINT ; ; X87STATUS ; 0xD9 /0xFC ; s:X87, t:X87_ALU, w:W, u:C1=m +FSCALE ; ; X87STATUS ; 0xD9 /0xFD ; s:X87, t:X87_ALU, w:W, u:C1=m +FSIN ; ; X87STATUS ; 0xD9 /0xFE ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m +FCOS ; ; X87STATUS ; 0xD9 /0xFF ; s:X87, t:X87_ALU, w:W, u:C1=m|C2=m FLD ; ST(0),ST(i) ; X87STATUS ; 0xD9 /0:reg ; s:X87, t:X87_ALU, w:W|R|W, u:C1=m FXCH ; ST(0),ST(i) ; X87STATUS ; 0xD9 /1:reg ; s:X87, t:X87_ALU, w:RW|RW|W, u:C1=0 FSTPNCE ; ST(i),ST(0) ; X87STATUS ; 0xD9 /3:reg ; s:X87, t:X87_ALU, w:W|R|W @@ -73,7 +73,7 @@ FIDIV ; ST(0),Md ; X87STATUS ; 0xDA /6:mem ; s FIDIVR ; ST(0),Md ; X87STATUS ; 0xDA /7:mem ; s:X87, t:X87_ALU, w:RW|R|W, u:C1=m -FUCOMPP ; n/a ; X87STATUS ; 0xDA /0xE9 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m +FUCOMPP ; ; X87STATUS ; 0xDA /0xE9 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=m|C2=m|C3=m FCMOVB ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDA /0:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m FCMOVE ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDA /1:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m FCMOVBE ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDA /2:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m @@ -87,11 +87,11 @@ FIST ; Md,ST(0) ; X87STATUS ; 0xDB /2:mem ; s FISTP ; Md,ST(0) ; X87STATUS ; 0xDB /3:mem ; s:X87, t:X87_ALU, w:W|R|W, u:C1=m FLD ; ST(0),Mft ; X87STATUS ; 0xDB /5:mem ; s:X87, t:X87_ALU, w:W|R|W, u:C1=m FSTP ; Mft,ST(0) ; X87STATUS ; 0xDB /7:mem ; s:X87, t:X87_ALU, w:W|R|W, u:C1=m -FNOP ; n/a ; n/a ; 0xDB /0xE0 ; s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u -FNDISI ; n/a ; n/a ; 0xDB /0xE1 ; s:X87, t:X87_ALU, w:W -FNCLEX ; n/a ; X87STATUS ; 0xDB /0xE2 ; s:X87, t:X87_ALU, w:W -FNINIT ; n/a ; X87CONTROL,X87TAG,X87STATUS ;0xDB /0xE3 ; s:X87, t:X87_ALU, w:W|W|W, u:C0=0|C1=0|C2=0|C3=0 -FNOP ; n/a ; n/a ; 0xDB /0xE4 ; s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u +FNOP ; ; ; 0xDB /0xE0 ; s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u +FNDISI ; ; ; 0xDB /0xE1 ; s:X87, t:X87_ALU, w:W +FNCLEX ; ; X87STATUS ; 0xDB /0xE2 ; s:X87, t:X87_ALU, w:W +FNINIT ; ; X87CONTROL,X87TAG,X87STATUS ;0xDB /0xE3 ; s:X87, t:X87_ALU, w:W|W|W, u:C0=0|C1=0|C2=0|C3=0 +FNOP ; ; ; 0xDB /0xE4 ; s:X87, t:X87_ALU, u:C0=u|C1=u|C2=u|C3=u FCMOVNB ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDB /0:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t, u:C1=m FCMOVNE ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDB /1:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:ZF=t, u:C1=m FCMOVNBE ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDB /2:reg ; s:X87, t:X87_ALU, w:CW|R|RW|W, f:CF=t|ZF=t, u:C1=m @@ -145,7 +145,7 @@ FISUBR ; ST(0),Mw ; X87STATUS ; 0xDE /5:mem ; s FIDIV ; ST(0),Mw ; X87STATUS ; 0xDE /6:mem ; s:X87, t:X87_ALU, w:RW|R|W, u:C1=m FIDIVR ; ST(0),Mw ; X87STATUS ; 0xDE /7:mem ; s:X87, t:X87_ALU, w:RW|R|W, u:C1=m -FCOMPP ; n/a ; X87STATUS ; 0xDE /0xD9 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m +FCOMPP ; ; X87STATUS ; 0xDE /0xD9 ; s:X87, t:X87_ALU, w:W, u:C0=m|C1=0|C2=m|C3=m FADDP ; ST(i),ST(0) ; X87STATUS ; 0xDE /0:reg ; s:X87, t:X87_ALU, w:RW|R|W, u:C1=m FMULP ; ST(i),ST(0) ; X87STATUS ; 0xDE /1:reg ; s:X87, t:X87_ALU, w:RW|R|W, u:C1=m FCOMP ; ST(0),ST(i) ; X87STATUS ; 0xDE /2:reg ; s:X87, t:X87_ALU, w:RW|R|W, u:C0=m|C1=0|C2=m|C3=m @@ -171,8 +171,8 @@ FXCH ; ST(0),ST(i) ; X87TAG ; 0xDF /1:reg ; s FSTP ; ST(i),ST(0) ; X87STATUS ; 0xDF /2:reg ; s:X87, t:X87_ALU, w:R|W|W, u:C1=m FSTP ; ST(i),ST(0) ; X87STATUS ; 0xDF /3:reg ; s:X87, t:X87_ALU, w:R|W|W, u:C1=m FNSTSW ; AX ; X87STATUS ; 0xDF /0xE0 ; s:X87, t:X87_ALU, w:W|W, u:C0=u|C1=u|C2=u|C3=u -FSTDW ; AX ; n/a ; 0xDF /0xE1 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u, m:NO64 -FSTSG ; AX ; n/a ; 0xDF /0xE2 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u +FSTDW ; AX ; ; 0xDF /0xE1 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u, m:NO64 +FSTSG ; AX ; ; 0xDF /0xE2 ; s:X87, t:X87_ALU, w:W, u:C0=u|C1=u|C2=u|C3=u FUCOMIP ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDF /5:reg ; s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m FCOMIP ; ST(0),ST(i) ; X87STATUS,Fv ; 0xDF /6:reg ; s:X87, t:X87_ALU, w:R|R|W|W, f:CF=m|PF=m|ZF=m|OF=0, u:C0=m|C1=0|C2=m|C3=m -FRINEAR ; n/a ; n/a ; 0xDF /0xFC ; s:X87, t:X87_ALU +FRINEAR ; ; ; 0xDF /0xFC ; s:X87, t:X87_ALU diff --git a/isagenerator/instructions/table_vex1.dat b/isagenerator/instructions/table_vex_1.dat similarity index 54% rename from isagenerator/instructions/table_vex1.dat rename to isagenerator/instructions/table_vex_1.dat index ee9009b..0e2f144 100644 --- a/isagenerator/instructions/table_vex1.dat +++ b/isagenerator/instructions/table_vex_1.dat @@ -6,50 +6,50 @@ # 0x00 - 0x0F # 0x10 - 0x1F -VMOVUPS ; Vx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x10 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 -VMOVUPD ; Vx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x10 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 -VMOVSS ; Vdq,Hdq,Uss ; n/a ; vex m:1 p:2 l:i w:i 0x10 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSS ; Vdq,Md ; n/a ; vex m:1 p:2 l:i w:i 0x10 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVSD ; Vdq,Hdq,Usd ; n/a ; vex m:1 p:3 l:i w:i 0x10 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSD ; Vdq,Mq ; n/a ; vex m:1 p:3 l:i w:i 0x10 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVUPS ; Wx,Vx ; n/a ; vex m:1 p:0 l:x w:i 0x11 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 -VMOVUPD ; Wx,Vx ; n/a ; vex m:1 p:1 l:x w:i 0x11 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 -VMOVSS ; Uss,Hss,Vss ; n/a ; vex m:1 p:2 l:i w:i 0x11 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSS ; Md,Vss ; n/a ; vex m:1 p:2 l:i w:i 0x11 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVSD ; Usd,Hsd,Vsd ; n/a ; vex m:1 p:3 l:i w:i 0x11 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSD ; Mq,Vsd ; n/a ; vex m:1 p:3 l:i w:i 0x11 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVLPS ; Vdq,Hdq,Mq ; n/a ; vex m:1 p:0 l:0 w:i 0x12 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVHLPS ; Vdq,Hdq,Udq ; n/a ; vex m:1 p:0 l:0 w:i 0x12 /r:reg ; s:AVX, t:AVX, w:W|R|R, e:7 -VMOVLPD ; Vdq,Hdq,Mq ; n/a ; vex m:1 p:1 l:0 w:i 0x12 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSLDUP ; Vx,Wx ; n/a ; vex m:1 p:2 l:x w:i 0x12 /r ; s:AVX, t:AVX, w:W|R, e:4 -VMOVDDUP ; Vdq,Wq ; n/a ; vex m:1 p:3 l:0 w:i 0x12 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVDDUP ; Vqq,Wqq ; n/a ; vex m:1 p:3 l:1 w:i 0x12 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVLPS ; Mq,Vdq ; n/a ; vex m:1 p:0 l:0 w:i 0x13 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVLPD ; Mq,Vdq ; n/a ; vex m:1 p:1 l:0 w:i 0x13 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VUNPCKLPS ; Vx,Hx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x14 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VUNPCKLPD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x14 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VUNPCKHPS ; Vx,Hx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x15 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VUNPCKHPD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x15 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VMOVHPS ; Vdq,Hdq,Mq ; n/a ; vex m:1 p:0 l:0 w:i 0x16 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVLHPS ; Vdq,Hdq,Udq ; n/a ; vex m:1 p:0 l:0 w:i 0x16 /r:reg ; s:AVX, t:AVX, w:W|R|R, e:7 -VMOVHPD ; Vdq,Hdq,Mq ; n/a ; vex m:1 p:1 l:0 w:i 0x16 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 -VMOVSHDUP ; Vx,Wx ; n/a ; vex m:1 p:2 l:x w:i 0x16 /r ; s:AVX, t:AVX, w:W|R, e:4 -VMOVHPS ; Mq,Vdq ; n/a ; vex m:1 p:0 l:0 w:i 0x17 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVHPD ; Mq,Vdq ; n/a ; vex m:1 p:1 l:0 w:i 0x17 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVUPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x10 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVUPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x10 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVSS ; Vdq,Hdq,Uss ; ; vex m:1 p:2 l:i w:i 0x10 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSS ; Vdq,Md ; ; vex m:1 p:2 l:i w:i 0x10 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVSD ; Vdq,Hdq,Usd ; ; vex m:1 p:3 l:i w:i 0x10 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSD ; Vdq,Mq ; ; vex m:1 p:3 l:i w:i 0x10 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVUPS ; Wx,Vx ; ; vex m:1 p:0 l:x w:i 0x11 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVUPD ; Wx,Vx ; ; vex m:1 p:1 l:x w:i 0x11 /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VMOVSS ; Uss,Hss,Vss ; ; vex m:1 p:2 l:i w:i 0x11 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSS ; Md,Vss ; ; vex m:1 p:2 l:i w:i 0x11 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVSD ; Usd,Hsd,Vsd ; ; vex m:1 p:3 l:i w:i 0x11 /r:reg ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSD ; Mq,Vsd ; ; vex m:1 p:3 l:i w:i 0x11 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVLPS ; Vdq,Hdq,Mq ; ; vex m:1 p:0 l:0 w:i 0x12 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVHLPS ; Vdq,Hdq,Udq ; ; vex m:1 p:0 l:0 w:i 0x12 /r:reg ; s:AVX, t:AVX, w:W|R|R, e:7 +VMOVLPD ; Vdq,Hdq,Mq ; ; vex m:1 p:1 l:0 w:i 0x12 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSLDUP ; Vx,Wx ; ; vex m:1 p:2 l:x w:i 0x12 /r ; s:AVX, t:AVX, w:W|R, e:4 +VMOVDDUP ; Vdq,Wq ; ; vex m:1 p:3 l:0 w:i 0x12 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVDDUP ; Vqq,Wqq ; ; vex m:1 p:3 l:1 w:i 0x12 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVLPS ; Mq,Vdq ; ; vex m:1 p:0 l:0 w:i 0x13 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVLPD ; Mq,Vdq ; ; vex m:1 p:1 l:0 w:i 0x13 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VUNPCKLPS ; Vx,Hx,Wx ; ; vex m:1 p:0 l:x w:i 0x14 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKLPD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x14 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKHPS ; Vx,Hx,Wx ; ; vex m:1 p:0 l:x w:i 0x15 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VUNPCKHPD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x15 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VMOVHPS ; Vdq,Hdq,Mq ; ; vex m:1 p:0 l:0 w:i 0x16 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVLHPS ; Vdq,Hdq,Udq ; ; vex m:1 p:0 l:0 w:i 0x16 /r:reg ; s:AVX, t:AVX, w:W|R|R, e:7 +VMOVHPD ; Vdq,Hdq,Mq ; ; vex m:1 p:1 l:0 w:i 0x16 /r:mem ; s:AVX, t:DATAXFER, w:W|R|R, e:5 +VMOVSHDUP ; Vx,Wx ; ; vex m:1 p:2 l:x w:i 0x16 /r ; s:AVX, t:AVX, w:W|R, e:4 +VMOVHPS ; Mq,Vdq ; ; vex m:1 p:0 l:0 w:i 0x17 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVHPD ; Mq,Vdq ; ; vex m:1 p:1 l:0 w:i 0x17 /r:mem ; s:AVX, t:DATAXFER, w:W|R, e:5 # 0x20 - 0x2F -VMOVAPS ; Vx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VMOVAPD ; Vx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VMOVAPS ; Wx,Vx ; n/a ; vex m:1 p:0 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VMOVAPD ; Wx,Vx ; n/a ; vex m:1 p:1 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VCVTSI2SS ; Vss,Hss,Ey ; n/a ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 -VCVTSI2SD ; Vsd,Hsd,Ey ; n/a ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 -VMOVNTPS ; Mx,Vx ; n/a ; vex m:1 p:0 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 -VMOVNTPD ; Mx,Vx ; n/a ; vex m:1 p:1 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 -VCVTTSS2SI ; Gy,Wss ; n/a ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTTSD2SI ; Gy,Wsd ; n/a ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTSS2SI ; Gy,Wss ; n/a ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 -VCVTSD2SI ; Gy,Wsd ; n/a ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 +VMOVAPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPS ; Wx,Vx ; ; vex m:1 p:0 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVAPD ; Wx,Vx ; ; vex m:1 p:1 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VCVTSI2SS ; Vss,Hss,Ey ; ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 +VCVTSI2SD ; Vsd,Hsd,Ey ; ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64 +VMOVNTPS ; Mx,Vx ; ; vex m:1 p:0 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 +VMOVNTPD ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1 +VCVTTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 +VCVTTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 +VCVTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 +VCVTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64 VUCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 VUCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 VCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3 @@ -59,172 +59,172 @@ VCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i # 0x40 - 0x4F # Note: ALL these instructions will zero-extend the result into the destination, up to the max length of the mask reg. -KANDW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x41 /r:reg ; s:AVX512F, t:KMASK, c:KAND, w:W|R|R, e:K20 -KANDB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x41 /r:reg ; s:AVX512DQ, t:KMASK, c:KAND, w:W|R|R, e:K20 -KANDQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x41 /r:reg ; s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 -KANDD ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x41 /r:reg ; s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 -KANDNW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x42 /r:reg ; s:AVX512F, t:KMASK, c:KANDN, w:W|R|R, e:K20 -KANDNB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x42 /r:reg ; s:AVX512DQ, t:KMASK, c:KANDN, w:W|R|R, e:K20 -KANDNQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x42 /r:reg ; s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 -KANDND ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x42 /r:reg ; s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 -KORW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x45 /r:reg ; s:AVX512F, t:KMASK, c:KOR, w:W|R|R, e:K20 -KORB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x45 /r:reg ; s:AVX512DQ, t:KMASK, c:KOR, w:W|R|R, e:K20 -KORQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x45 /r:reg ; s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 -KORD ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x45 /r:reg ; s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 -KXNORW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x46 /r:reg ; s:AVX512F, t:KMASK, c:KXNOR, w:W|R|R, e:K20 -KXNORB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x46 /r:reg ; s:AVX512DQ, t:KMASK, c:KXNOR, w:W|R|R, e:K20 -KXNORQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x46 /r:reg ; s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 -KXNORD ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x46 /r:reg ; s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 -KXORW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x47 /r:reg ; s:AVX512F, t:KMASK, c:KXOR, w:W|R|R, e:K20 -KXORB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x47 /r:reg ; s:AVX512DQ, t:KMASK, c:KXOR, w:W|R|R, e:K20 -KXORQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x47 /r:reg ; s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 -KXORD ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x47 /r:reg ; s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 -KADDW ; rKw,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x4A /r:reg ; s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 -KADDB ; rKb,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x4A /r:reg ; s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 -KADDQ ; rKq,vKq,mKq ; n/a ; vex m:1 p:0 l:1 w:1 0x4A /r:reg ; s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 -KADDD ; rKd,vKd,mKd ; n/a ; vex m:1 p:1 l:1 w:1 0x4A /r:reg ; s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 -KMOVW ; rKw,Mw ; n/a ; vex m:1 p:0 l:0 w:0 0x90 /r:mem ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVB ; rKb,Mb ; n/a ; vex m:1 p:1 l:0 w:0 0x90 /r:mem ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVQ ; rKq,Mq ; n/a ; vex m:1 p:0 l:0 w:1 0x90 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVD ; rKd,Md ; n/a ; vex m:1 p:1 l:0 w:1 0x90 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVW ; rKw,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x90 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVB ; rKb,mKb ; n/a ; vex m:1 p:1 l:0 w:0 0x90 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVQ ; rKq,mKq ; n/a ; vex m:1 p:0 l:0 w:1 0x90 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVD ; rKd,mKd ; n/a ; vex m:1 p:1 l:0 w:1 0x90 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVW ; Mw,rKw ; n/a ; vex m:1 p:0 l:0 w:0 0x91 /r:mem ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVB ; Mb,rKb ; n/a ; vex m:1 p:1 l:0 w:0 0x91 /r:mem ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVQ ; Mq,rKq ; n/a ; vex m:1 p:0 l:0 w:1 0x91 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVD ; Md,rKd ; n/a ; vex m:1 p:1 l:0 w:1 0x91 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 -KMOVW ; rKw,Ry ; n/a ; vex m:1 p:0 l:0 w:0 0x92 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVB ; rKb,Ry ; n/a ; vex m:1 p:1 l:0 w:0 0x92 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVQ ; rKq,Ry ; n/a ; vex m:1 p:3 l:0 w:1 0x92 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVD ; rKd,Ry ; n/a ; vex m:1 p:3 l:0 w:0 0x92 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVW ; Gy,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x93 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVB ; Gy,mKb ; n/a ; vex m:1 p:1 l:0 w:0 0x93 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVQ ; Gy,mKq ; n/a ; vex m:1 p:3 l:0 w:1 0x93 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMOVD ; Gy,mKd ; n/a ; vex m:1 p:3 l:0 w:0 0x93 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 -KMERGE2L1H ; rKw,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x48 /r:reg ; s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1H, w:W|R, e:K20 -KMERGE2L1L ; rKw,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x49 /r:reg ; s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1L, w:W|R, e:K20 -KUNPCKBW ; rKw,vKb,mKb ; n/a ; vex m:1 p:1 l:1 w:0 0x4B /r:reg ; s:AVX512F, t:KMASK, c:KUNPCKBW, w:W|R|R, e:K20 -KUNPCKWD ; rKd,vKw,mKw ; n/a ; vex m:1 p:0 l:1 w:0 0x4B /r:reg ; s:AVX512BW, t:KMASK, c:KUNPCKWD, w:W|R|R, e:K20 -KUNPCKDQ ; rKq,vKd,mKd ; n/a ; vex m:1 p:0 l:1 w:1 0x4B /r:reg ; s:AVX512BW, t:KMASK, c:KUNPCKDQ, w:W|R|R, e:K20 -KNOTW ; rKw,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x44 /r:reg ; s:AVX512F, t:KMASK, c:KNOT, w:W|R, e:K20 -KNOTB ; rKb,mKb ; n/a ; vex m:1 p:1 l:0 w:0 0x44 /r:reg ; s:AVX512DQ, t:KMASK, c:KNOT, w:W|R, e:K20 -KNOTQ ; rKq,mKq ; n/a ; vex m:1 p:0 l:0 w:1 0x44 /r:reg ; s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 -KNOTD ; rKd,mKd ; n/a ; vex m:1 p:1 l:0 w:1 0x44 /r:reg ; s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 +KANDW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x41 /r:reg ; s:AVX512F, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x41 /r:reg ; s:AVX512DQ, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x41 /r:reg ; s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDD ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x41 /r:reg ; s:AVX512BW, t:KMASK, c:KAND, w:W|R|R, e:K20 +KANDNW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x42 /r:reg ; s:AVX512F, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDNB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x42 /r:reg ; s:AVX512DQ, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDNQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x42 /r:reg ; s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KANDND ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x42 /r:reg ; s:AVX512BW, t:KMASK, c:KANDN, w:W|R|R, e:K20 +KORW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x45 /r:reg ; s:AVX512F, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x45 /r:reg ; s:AVX512DQ, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x45 /r:reg ; s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 +KORD ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x45 /r:reg ; s:AVX512BW, t:KMASK, c:KOR, w:W|R|R, e:K20 +KXNORW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x46 /r:reg ; s:AVX512F, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x46 /r:reg ; s:AVX512DQ, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x46 /r:reg ; s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXNORD ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x46 /r:reg ; s:AVX512BW, t:KMASK, c:KXNOR, w:W|R|R, e:K20 +KXORW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x47 /r:reg ; s:AVX512F, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x47 /r:reg ; s:AVX512DQ, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x47 /r:reg ; s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KXORD ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x47 /r:reg ; s:AVX512BW, t:KMASK, c:KXOR, w:W|R|R, e:K20 +KADDW ; rKw,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x4A /r:reg ; s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDB ; rKb,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x4A /r:reg ; s:AVX512DQ, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDQ ; rKq,vKq,mKq ; ; vex m:1 p:0 l:1 w:1 0x4A /r:reg ; s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 +KADDD ; rKd,vKd,mKd ; ; vex m:1 p:1 l:1 w:1 0x4A /r:reg ; s:AVX512BW, t:KMASK, c:KADD, w:W|R|R, e:K20 +KMOVW ; rKw,Mw ; ; vex m:1 p:0 l:0 w:0 0x90 /r:mem ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVB ; rKb,Mb ; ; vex m:1 p:1 l:0 w:0 0x90 /r:mem ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVQ ; rKq,Mq ; ; vex m:1 p:0 l:0 w:1 0x90 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVD ; rKd,Md ; ; vex m:1 p:1 l:0 w:1 0x90 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVW ; rKw,mKw ; ; vex m:1 p:0 l:0 w:0 0x90 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB ; rKb,mKb ; ; vex m:1 p:1 l:0 w:0 0x90 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ ; rKq,mKq ; ; vex m:1 p:0 l:0 w:1 0x90 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD ; rKd,mKd ; ; vex m:1 p:1 l:0 w:1 0x90 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVW ; Mw,rKw ; ; vex m:1 p:0 l:0 w:0 0x91 /r:mem ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVB ; Mb,rKb ; ; vex m:1 p:1 l:0 w:0 0x91 /r:mem ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVQ ; Mq,rKq ; ; vex m:1 p:0 l:0 w:1 0x91 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVD ; Md,rKd ; ; vex m:1 p:1 l:0 w:1 0x91 /r:mem ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K21 +KMOVW ; rKw,Ry ; ; vex m:1 p:0 l:0 w:0 0x92 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB ; rKb,Ry ; ; vex m:1 p:1 l:0 w:0 0x92 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ ; rKq,Ry ; ; vex m:1 p:3 l:0 w:1 0x92 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD ; rKd,Ry ; ; vex m:1 p:3 l:0 w:0 0x92 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVW ; Gy,mKw ; ; vex m:1 p:0 l:0 w:0 0x93 /r:reg ; s:AVX512F, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVB ; Gy,mKb ; ; vex m:1 p:1 l:0 w:0 0x93 /r:reg ; s:AVX512DQ, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVQ ; Gy,mKq ; ; vex m:1 p:3 l:0 w:1 0x93 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMOVD ; Gy,mKd ; ; vex m:1 p:3 l:0 w:0 0x93 /r:reg ; s:AVX512BW, t:KMASK, c:KMOV, w:W|R, e:K20 +KMERGE2L1H ; rKw,mKw ; ; vex m:1 p:0 l:0 w:0 0x48 /r:reg ; s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1H, w:W|R, e:K20 +KMERGE2L1L ; rKw,mKw ; ; vex m:1 p:0 l:0 w:0 0x49 /r:reg ; s:UNKNOWN, t:UNKNOWN, c:KMERGE2L1L, w:W|R, e:K20 +KUNPCKBW ; rKw,vKb,mKb ; ; vex m:1 p:1 l:1 w:0 0x4B /r:reg ; s:AVX512F, t:KMASK, c:KUNPCKBW, w:W|R|R, e:K20 +KUNPCKWD ; rKd,vKw,mKw ; ; vex m:1 p:0 l:1 w:0 0x4B /r:reg ; s:AVX512BW, t:KMASK, c:KUNPCKWD, w:W|R|R, e:K20 +KUNPCKDQ ; rKq,vKd,mKd ; ; vex m:1 p:0 l:1 w:1 0x4B /r:reg ; s:AVX512BW, t:KMASK, c:KUNPCKDQ, w:W|R|R, e:K20 +KNOTW ; rKw,mKw ; ; vex m:1 p:0 l:0 w:0 0x44 /r:reg ; s:AVX512F, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTB ; rKb,mKb ; ; vex m:1 p:1 l:0 w:0 0x44 /r:reg ; s:AVX512DQ, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTQ ; rKq,mKq ; ; vex m:1 p:0 l:0 w:1 0x44 /r:reg ; s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 +KNOTD ; rKd,mKd ; ; vex m:1 p:1 l:0 w:1 0x44 /r:reg ; s:AVX512BW, t:KMASK, c:KNOT, w:W|R, e:K20 KORTESTW ; rKw,mKw ; Fv ; vex m:1 p:0 l:0 w:0 0x98 /r:reg ; s:AVX512F, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 KORTESTB ; rKb,mKb ; Fv ; vex m:1 p:1 l:0 w:0 0x98 /r:reg ; s:AVX512DQ, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 KORTESTQ ; rKq,mKq ; Fv ; vex m:1 p:0 l:0 w:1 0x98 /r:reg ; s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 KORTESTD ; rKd,mKd ; Fv ; vex m:1 p:1 l:0 w:1 0x98 /r:reg ; s:AVX512BW, t:KMASK, c:KORTEST, w:R|R|W, f:KORTEST, e:K20 -KTESTW ; rKw,mKw ; n/a ; vex m:1 p:0 l:0 w:0 0x99 /r:reg ; s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 -KTESTB ; rKb,mKb ; n/a ; vex m:1 p:1 l:0 w:0 0x99 /r:reg ; s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 -KTESTQ ; rKq,mKq ; n/a ; vex m:1 p:0 l:0 w:1 0x99 /r:reg ; s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 -KTESTD ; rKd,mKd ; n/a ; vex m:1 p:1 l:0 w:1 0x99 /r:reg ; s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTW ; rKw,mKw ; ; vex m:1 p:0 l:0 w:0 0x99 /r:reg ; s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTB ; rKb,mKb ; ; vex m:1 p:1 l:0 w:0 0x99 /r:reg ; s:AVX512DQ, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTQ ; rKq,mKq ; ; vex m:1 p:0 l:0 w:1 0x99 /r:reg ; s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 +KTESTD ; rKd,mKd ; ; vex m:1 p:1 l:0 w:1 0x99 /r:reg ; s:AVX512BW, t:KMASK, c:KTEST, w:W|R, e:K20 # 0x50 - 0x5F -VMOVMSKPS ; Gy,Ux ; n/a ; vex m:1 p:0 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 -VMOVMSKPD ; Gy,Ux ; n/a ; vex m:1 p:1 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 -VSQRTPS ; Vx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 -VSQRTPD ; Vx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 -VSQRTSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 -VSQRTSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 -VRSQRTPS ; Vx,Wx ; n/a ; vex m:1 p:0 l:x w:i 0x52 /r ; s:AVX, t:AVX, w:W|R, e:4 -VRSQRTSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x52 /r ; s:AVX, t:AVX, w:W|R|R, e:5 -VRCPPS ; Vps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x53 /r ; s:AVX, t:AVX, w:W|R, e:4 -VRCPSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x53 /r ; s:AVX, t:AVX, w:W|R|R, e:5 -VANDPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x54 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VANDPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x54 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VANDNPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x55 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VANDNPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x55 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VORPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VORPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VXORPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VXORPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 -VADDPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMULSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VCVTPS2PD ; Vpd,Wq ; n/a ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPS2PD ; Vqq,Wdq ; n/a ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPD2PS ; Vdq,Wdq ; n/a ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPD2PS ; Vdq,Wqq ; n/a ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTSS2SD ; Vsd,Hx,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 -VCVTSD2SS ; Vss,Hx,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 -VCVTDQ2PS ; Vps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTPS2DQ ; Vps,Wps ; n/a ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTTPS2DQ ; Vps,Wps ; n/a ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VSUBPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VSUBSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMINSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VDIVSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXSS ; Vss,Hss,Wss ; n/a ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMAXSD ; Vsd,Hsd,Wsd ; n/a ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMOVMSKPS ; Gy,Ux ; ; vex m:1 p:0 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 +VMOVMSKPD ; Gy,Ux ; ; vex m:1 p:1 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 +VSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 +VSQRTPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2 +VSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 +VSQRTSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3 +VRSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x52 /r ; s:AVX, t:AVX, w:W|R, e:4 +VRSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x52 /r ; s:AVX, t:AVX, w:W|R|R, e:5 +VRCPPS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x53 /r ; s:AVX, t:AVX, w:W|R, e:4 +VRCPSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x53 /r ; s:AVX, t:AVX, w:W|R|R, e:5 +VANDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x54 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x54 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDNPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x55 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VANDNPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x55 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VXORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VXORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4 +VADDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMULPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMULPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMULSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMULSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VCVTPS2PD ; Vpd,Wq ; ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPS2PD ; Vqq,Wdq ; ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPD2PS ; Vdq,Wdq ; ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPD2PS ; Vdq,Wqq ; ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTSS2SD ; Vsd,Hx,Wss ; ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 +VCVTSD2SS ; Vss,Hx,Wsd ; ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3 +VCVTDQ2PS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTPS2DQ ; Vps,Wps ; ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTTPS2DQ ; Vps,Wps ; ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VSUBSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VSUBSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMINPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMINPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMINSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMINSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VDIVPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VDIVPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VDIVSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VDIVSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMAXPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMAXPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMAXSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMAXSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2 # 0x60 - 0x6F -VPUNPCKLBW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x60 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKLWD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x61 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKLDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x62 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPACKSSWB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x63 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPGTB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x64 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPGTW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x65 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPGTD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x66 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPACKUSWB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x67 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKHBW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x68 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKHWD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x69 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKHDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x6A /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPACKSSDW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x6B /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKLQDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x6C /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPUNPCKHQDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x6D /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VMOVD ; Vdq,Ey ; n/a ; vex m:1 p:1 l:0 w:0 0x6E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 -VMOVQ ; Vdq,Ey ; n/a ; vex m:1 p:1 l:0 w:1 0x6E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 -VMOVDQA ; Vx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x6F /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VMOVDQU ; Vx,Wx ; n/a ; vex m:1 p:2 l:x w:i 0x6F /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VPUNPCKLBW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x60 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLWD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x61 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x62 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPACKSSWB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x63 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x64 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x65 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPGTD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x66 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPACKUSWB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x67 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHBW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x68 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHWD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x69 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x6A /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPACKSSDW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x6B /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKLQDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x6C /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPUNPCKHQDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x6D /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VMOVD ; Vdq,Ey ; ; vex m:1 p:1 l:0 w:0 0x6E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 +VMOVQ ; Vdq,Ey ; ; vex m:1 p:1 l:0 w:1 0x6E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 +VMOVDQA ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x6F /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVDQU ; Vx,Wx ; ; vex m:1 p:2 l:x w:i 0x6F /r ; s:AVX, t:DATAXFER, w:W|R, e:4 # 0x70 - 0x7F -VPSHUFD ; Vx,Wx,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSHUFHW ; Vx,Wx,Ib ; n/a ; vex m:1 p:2 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSHUFLW ; Vx,Wx,Ib ; n/a ; vex m:1 p:3 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPEQB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x74 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPEQW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x75 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPEQD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0x76 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VZEROUPPER ; n/a ; BANK ; vex m:1 p:0 l:0 0x77 ; s:AVX, t:AVX, w:W, e:8 -VZEROALL ; n/a ; BANK ; vex m:1 p:0 l:1 0x77 ; s:AVX, t:AVX, w:W, e:8 -VHADDPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHADDPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHSUBPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VHSUBPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VMOVD ; Ey,Vd ; n/a ; vex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 -VMOVQ ; Ey,Vq ; n/a ; vex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 -VMOVQ ; Vdq,Wq ; n/a ; vex m:1 p:2 l:0 w:i 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5 -VMOVDQA ; Wx,Vx ; n/a ; vex m:1 p:1 l:x w:i 0x7F /r ; s:AVX, t:DATAXFER, w:W|R, e:1 -VMOVDQU ; Wx,Vx ; n/a ; vex m:1 p:2 l:x w:i 0x7F /r ; s:AVX, t:DATAXFER, w:W|R, e:4 -VPSRLW ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x71 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSRAW ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x71 /4:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSLLW ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x71 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSRLD ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x72 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSRAD ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x72 /4:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSLLD ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x72 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSRLQ ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x73 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSRLDQ ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x73 /3:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSLLQ ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x73 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 -VPSLLDQ ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i 0x73 /7:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSHUFD ; Vx,Wx,Ib ; ; vex m:1 p:1 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSHUFHW ; Vx,Wx,Ib ; ; vex m:1 p:2 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSHUFLW ; Vx,Wx,Ib ; ; vex m:1 p:3 l:x w:i 0x70 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x74 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x75 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x76 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VZEROUPPER ; ; BANK ; vex m:1 p:0 l:0 0x77 ; s:AVX, t:AVX, w:W, e:8 +VZEROALL ; ; BANK ; vex m:1 p:0 l:1 0x77 ; s:AVX, t:AVX, w:W, e:8 +VHADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VHADDPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VHSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VHSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VMOVD ; Ey,Vd ; ; vex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 +VMOVQ ; Ey,Vq ; ; vex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64 +VMOVQ ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5 +VMOVDQA ; Wx,Vx ; ; vex m:1 p:1 l:x w:i 0x7F /r ; s:AVX, t:DATAXFER, w:W|R, e:1 +VMOVDQU ; Wx,Vx ; ; vex m:1 p:2 l:x w:i 0x7F /r ; s:AVX, t:DATAXFER, w:W|R, e:4 +VPSRLW ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x71 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSRAW ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x71 /4:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLW ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x71 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLD ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x72 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSRAD ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x72 /4:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLD ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x72 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLQ ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x73 /2:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSRLDQ ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x73 /3:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLQ ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x73 /6:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 +VPSLLDQ ; Hx,Ux,Ib ; ; vex m:1 p:1 l:x w:i 0x73 /7:reg ib ; s:AVX, t:AVX, w:W|R|R, e:7 # 0x80 - 0x8F @@ -233,77 +233,77 @@ VPSLLDQ ; Hx,Ux,Ib ; n/a ; vex m:1 p:1 l:x w:i # 0xA0 - 0xAF VLDMXCSR ; Md ; MXCSR ; vex m:1 p:0 0xAE /2:mem ; s:AVX, t:AVX, w:R|W, e:5 VSTMXCSR ; Md ; MXCSR ; vex m:1 p:0 0xAE /3:mem ; s:AVX, t:AVX, w:W|R, e:5 -SPFLT ; Ry ; n/a ; vex m:1 p:3 0xAE /6:reg ; s:UNKNOWN, t:UNKNOWN, w:R -DELAY ; Ry ; n/a ; vex m:1 p:2 0xAE /6:reg ; s:UNKNOWN, t:UNKNOWN, w:R -CLEVICT0 ; M? ; n/a ; vex m:1 p:3 0xAE /7:mem ; s:UNKNOWN, t:UNKNOWN, w:N -CLEVICT1 ; M? ; n/a ; vex m:1 p:2 0xAE /7:mem ; s:UNKNOWN, t:UNKNOWN, w:N +SPFLT ; Ry ; ; vex m:1 p:3 0xAE /6:reg ; s:UNKNOWN, t:UNKNOWN, w:R +DELAY ; Ry ; ; vex m:1 p:2 0xAE /6:reg ; s:UNKNOWN, t:UNKNOWN, w:R +CLEVICT0 ; M? ; ; vex m:1 p:3 0xAE /7:mem ; s:UNKNOWN, t:UNKNOWN, w:N +CLEVICT1 ; M? ; ; vex m:1 p:2 0xAE /7:mem ; s:UNKNOWN, t:UNKNOWN, w:N # 0xB0 - 0xBF # 0xC0 - 0xCF -VCMPPS ; Vss,Hss,Wss,Ib ; n/a ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPPD ; Vpd,Hpd,Wpd,Ib ; n/a ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPSS ; Vss,Hss,Wss,Ib ; n/a ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VCMPSD ; Vsd,Hsd,Wsd,Ib ; n/a ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VPINSRW ; Vdq,Hdq,Mw,Ib ; n/a ; vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VPINSRW ; Vdq,Hdq,Rd,Ib ; n/a ; vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VPEXTRW ; Gy,Udq,Ib ; n/a ; vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 -VSHUFPS ; Vps,Hps,Wps,Ib ; n/a ; vex m:1 p:0 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VSHUFPD ; Vpd,Hpd,Wpd,Ib ; n/a ; vex m:1 p:1 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VCMPPS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPSS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VCMPSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VPINSRW ; Vdq,Hdq,Mw,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRW ; Vdq,Hdq,Rd,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VPEXTRW ; Gy,Udq,Ib ; ; vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 +VSHUFPS ; Vps,Hps,Wps,Ib ; ; vex m:1 p:0 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VSHUFPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 # 0xD0 - 0xDF -VADDSUBPD ; Vpd,Hpd,Wpd ; n/a ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VADDSUBPS ; Vps,Hps,Wps ; n/a ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 -VPSRLW ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSRLD ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xD2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSRLQ ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xD3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xD4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMULLW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VMOVQ ; Wq,Vdq ; n/a ; vex m:1 p:1 l:0 w:i 0xD6 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 -VPMOVMSKB ; Gy,Ux ; n/a ; vex m:1 p:1 l:x w:i 0xD7 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 -VPSUBUSB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSUBUSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINUB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDA /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPAND ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDB /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 -VPADDUSB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDC /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDUSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDD /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXUB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDE /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPANDN ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xDF /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 +VADDSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VADDSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2 +VPSRLW ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSRLD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSRLQ ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xD4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMULLW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VMOVQ ; Wq,Vdq ; ; vex m:1 p:1 l:0 w:i 0xD6 /r ; s:AVX, t:DATAXFER, w:W|R, e:5 +VPMOVMSKB ; Gy,Ux ; ; vex m:1 p:1 l:x w:i 0xD7 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64 +VPSUBUSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBUSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDA /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPAND ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDB /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 +VPADDUSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDC /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDUSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDD /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDE /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPANDN ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xDF /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 # 0xE0 - 0xEF -VPAVGB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE0 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSRAW ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xE1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSRAD ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xE2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPAVGW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMULHUW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMULHW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VCVTTPD2DQ ; Vdq,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VCVTDQ2PD ; Vdq,Wq ; n/a ; vex m:1 p:2 l:0 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 -VCVTDQ2PD ; Vqq,Wdq ; n/a ; vex m:1 p:2 l:1 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 -VCVTPD2DQ ; Vdq,Wx ; n/a ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 -VMOVNTDQ ; Mx,Vx ; n/a ; vex m:1 p:1 l:x w:i 0xE7 /r:mem ; s:AVX, t:AVX, w:W|R, e:1 -VPSUBSB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSUBSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xEA /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPOR ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xEB /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 -VPADDSB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xEC /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xED /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXSW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xEE /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPXOR ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xEF /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 +VPAVGB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE0 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSRAW ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xE1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSRAD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xE2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPAVGW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHUW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VCVTTPD2DQ ; Vdq,Wx ; ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VCVTDQ2PD ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 +VCVTDQ2PD ; Vqq,Wdq ; ; vex m:1 p:2 l:1 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5 +VCVTPD2DQ ; Vdq,Wx ; ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2 +VMOVNTDQ ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0xE7 /r:mem ; s:AVX, t:AVX, w:W|R, e:1 +VPSUBSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xEA /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPOR ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xEB /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 +VPADDSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xEC /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xED /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xEE /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPXOR ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xEF /r ; s:AVX, t:LOGICAL, w:W|R|R, e:4 # 0xF0 - 0xFF -VLDDQU ; Vx,Mx ; n/a ; vex m:1 p:3 l:x w:i 0xF0 /r:mem ; s:AVX, t:AVX, w:W|R, e:4 -VPSLLW ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xF1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSLLD ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xF2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSLLQ ; Vx,Hx,Wdq ; n/a ; vex m:1 p:1 l:x w:i 0xF3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMULUDQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xF4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMADDWD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xF5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSADBW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xF6 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VLDDQU ; Vx,Mx ; ; vex m:1 p:3 l:x w:i 0xF0 /r:mem ; s:AVX, t:AVX, w:W|R, e:4 +VPSLLW ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xF1 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSLLD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xF2 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSLLQ ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xF3 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMULUDQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xF4 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMADDWD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xF5 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSADBW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xF6 /r ; s:AVX, t:AVX, w:W|R|R, e:4 VMASKMOVDQU ; Vdq,Udq ; pDIdq ; vex m:1 p:1 l:0 w:i 0xF7 /r:reg ; s:AVX, t:AVX, w:R|R|W, e:4 -VPSUBB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xF8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSUBW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xF9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSUBD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xFA /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSUBQ ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xFB /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDB ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xFC /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDW ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xFD /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPADDD ; Vx,Hx,Wx ; n/a ; vex m:1 p:1 l:x w:i 0xFE /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xF8 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xF9 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xFA /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSUBQ ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xFB /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xFC /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xFD /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPADDD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xFE /r ; s:AVX, t:AVX, w:W|R|R, e:4 diff --git a/isagenerator/instructions/table_vex2.dat b/isagenerator/instructions/table_vex_2.dat similarity index 58% rename from isagenerator/instructions/table_vex2.dat rename to isagenerator/instructions/table_vex_2.dat index 3bf4071..ec7eebe 100644 --- a/isagenerator/instructions/table_vex2.dat +++ b/isagenerator/instructions/table_vex_2.dat @@ -4,242 +4,242 @@ # # 0x00 - 0x0F -VPSHUFB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x00 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHADDW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x01 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHADDD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x02 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHADDSW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x03 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMADDUBSW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x04 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHSUBW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x05 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHSUBD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x06 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHSUBSW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x07 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSIGNB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x08 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSIGNW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x09 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPSIGND ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x0A /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMULHRSW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x0B /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPERMILPS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x0C /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPERMILPD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x0D /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSHUFB ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x00 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x01 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x02 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHADDSW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x03 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMADDUBSW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x04 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x05 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x06 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHSUBSW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x07 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGNB ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x08 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGNW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x09 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPSIGND ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x0A /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMULHRSW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x0B /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x0C /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x0D /r ; s:AVX, t:AVX, w:W|R|R, e:4 VTESTPS ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0 0x0E /r ; s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4 VTESTPD ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0 0x0F /r ; s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4 # 0x10 - 0x1F -VCVTPH2PS ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 -VCVTPH2PS ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 -VPERMPS ; Vqq,Hqq,Wqq ; n/a ; vex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VCVTPH2PS ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 +VCVTPH2PS ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11 +VPERMPS ; Vqq,Hqq,Wqq ; ; vex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 VPTEST ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:i 0x17 /r ; s:AVX, t:LOGICAL, w:R|R|W, f:VPTEST, e:4 -VBROADCASTSS ; Vx,Wss ; n/a ; vex m:2 p:1 l:x w:0 0x18 /r ; s:AVX, t:BROADCAST, w:W|R, e:6 -VBROADCASTSD ; Vqq,Wsd ; n/a ; vex m:2 p:1 l:x w:0 0x19 /r ; s:AVX, t:BROADCAST, w:W|R, e:6 -VBROADCASTF128 ; Vqq,Mdq ; n/a ; vex m:2 p:1 l:1 w:0 0x1A /r:mem ; s:AVX, t:BROADCAST, w:W|R, e:6 -VPABSB ; Vx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x1C /r ; s:AVX, t:AVX, w:W|R, e:4 -VPABSW ; Vx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x1D /r ; s:AVX, t:AVX, w:W|R, e:4 -VPABSD ; Vx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x1E /r ; s:AVX, t:AVX, w:W|R, e:4 +VBROADCASTSS ; Vx,Wss ; ; vex m:2 p:1 l:x w:0 0x18 /r ; s:AVX, t:BROADCAST, w:W|R, e:6 +VBROADCASTSD ; Vqq,Wsd ; ; vex m:2 p:1 l:x w:0 0x19 /r ; s:AVX, t:BROADCAST, w:W|R, e:6 +VBROADCASTF128 ; Vqq,Mdq ; ; vex m:2 p:1 l:1 w:0 0x1A /r:mem ; s:AVX, t:BROADCAST, w:W|R, e:6 +VPABSB ; Vx,Wx ; ; vex m:2 p:1 l:x w:i 0x1C /r ; s:AVX, t:AVX, w:W|R, e:4 +VPABSW ; Vx,Wx ; ; vex m:2 p:1 l:x w:i 0x1D /r ; s:AVX, t:AVX, w:W|R, e:4 +VPABSD ; Vx,Wx ; ; vex m:2 p:1 l:x w:i 0x1E /r ; s:AVX, t:AVX, w:W|R, e:4 # 0x20 - 0x2F -VPMOVSXBW ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x20 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXBW ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x20 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVSXBD ; Vdq,Wd ; n/a ; vex m:2 p:1 l:0 w:i 0x21 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXBD ; Vqq,Wq ; n/a ; vex m:2 p:1 l:1 w:i 0x21 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVSXBQ ; Vdq,Ww ; n/a ; vex m:2 p:1 l:0 w:i 0x22 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXBQ ; Vqq,Wd ; n/a ; vex m:2 p:1 l:1 w:i 0x22 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVSXWD ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x23 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXWD ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x23 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVSXWQ ; Vdq,Wd ; n/a ; vex m:2 p:1 l:0 w:i 0x24 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXWQ ; Vqq,Wq ; n/a ; vex m:2 p:1 l:1 w:i 0x24 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVSXDQ ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x25 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVSXDQ ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x25 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMULDQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x28 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPCMPEQQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x29 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VMOVNTDQA ; Vx,Mx ; n/a ; vex m:2 p:1 l:x w:i 0x2A /r:mem ; s:AVX, t:AVX, w:W|R, e:1 -VPACKUSDW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x2B /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VMASKMOVPS ; Vx,Hx,Mx ; n/a ; vex m:2 p:1 l:x w:0 0x2C /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 -VMASKMOVPD ; Vx,Hx,Mx ; n/a ; vex m:2 p:1 l:x w:0 0x2D /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 -VMASKMOVPS ; Mx,Hx,Vx ; n/a ; vex m:2 p:1 l:x w:0 0x2E /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 -VMASKMOVPD ; Mx,Hx,Vx ; n/a ; vex m:2 p:1 l:x w:0 0x2F /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 +VPMOVSXBW ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x20 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBW ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x20 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXBD ; Vdq,Wd ; ; vex m:2 p:1 l:0 w:i 0x21 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBD ; Vqq,Wq ; ; vex m:2 p:1 l:1 w:i 0x21 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXBQ ; Vdq,Ww ; ; vex m:2 p:1 l:0 w:i 0x22 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXBQ ; Vqq,Wd ; ; vex m:2 p:1 l:1 w:i 0x22 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXWD ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x23 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXWD ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x23 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXWQ ; Vdq,Wd ; ; vex m:2 p:1 l:0 w:i 0x24 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXWQ ; Vqq,Wq ; ; vex m:2 p:1 l:1 w:i 0x24 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVSXDQ ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x25 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVSXDQ ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x25 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMULDQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x28 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPCMPEQQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x29 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VMOVNTDQA ; Vx,Mx ; ; vex m:2 p:1 l:x w:i 0x2A /r:mem ; s:AVX, t:AVX, w:W|R, e:1 +VPACKUSDW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x2B /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VMASKMOVPS ; Vx,Hx,Mx ; ; vex m:2 p:1 l:x w:0 0x2C /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPD ; Vx,Hx,Mx ; ; vex m:2 p:1 l:x w:0 0x2D /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPS ; Mx,Hx,Vx ; ; vex m:2 p:1 l:x w:0 0x2E /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 +VMASKMOVPD ; Mx,Hx,Vx ; ; vex m:2 p:1 l:x w:0 0x2F /r:mem ; s:AVX, t:AVX, w:W|R|R, e:6 # 0x30 - 0x3F -VPMOVZXBW ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x30 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXBW ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x30 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVZXBD ; Vdq,Wd ; n/a ; vex m:2 p:1 l:0 w:i 0x31 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXBD ; Vqq,Wq ; n/a ; vex m:2 p:1 l:1 w:i 0x31 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVZXBQ ; Vdq,Ww ; n/a ; vex m:2 p:1 l:0 w:i 0x32 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXBQ ; Vqq,Wd ; n/a ; vex m:2 p:1 l:1 w:i 0x32 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVZXWD ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x33 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXWD ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x33 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVZXWQ ; Vdq,Wd ; n/a ; vex m:2 p:1 l:0 w:i 0x34 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXWQ ; Vqq,Wq ; n/a ; vex m:2 p:1 l:1 w:i 0x34 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPMOVZXDQ ; Vdq,Wq ; n/a ; vex m:2 p:1 l:0 w:i 0x35 /r ; s:AVX, t:AVX, w:W|R, e:5 -VPMOVZXDQ ; Vqq,Wdq ; n/a ; vex m:2 p:1 l:1 w:i 0x35 /r ; s:AVX2, t:AVX2, w:W|R, e:5 -VPERMD ; Vqq,Hqq,Wqq ; n/a ; vex m:2 p:1 l:1 w:0 0x36 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPCMPGTQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x37 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINSB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x38 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x39 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINUW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3A /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMINUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3B /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXSB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3C /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3D /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXUW ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3E /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPMAXUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x3F /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMOVZXBW ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x30 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBW ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x30 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXBD ; Vdq,Wd ; ; vex m:2 p:1 l:0 w:i 0x31 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBD ; Vqq,Wq ; ; vex m:2 p:1 l:1 w:i 0x31 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXBQ ; Vdq,Ww ; ; vex m:2 p:1 l:0 w:i 0x32 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXBQ ; Vqq,Wd ; ; vex m:2 p:1 l:1 w:i 0x32 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXWD ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x33 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXWD ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x33 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXWQ ; Vdq,Wd ; ; vex m:2 p:1 l:0 w:i 0x34 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXWQ ; Vqq,Wq ; ; vex m:2 p:1 l:1 w:i 0x34 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPMOVZXDQ ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:i 0x35 /r ; s:AVX, t:AVX, w:W|R, e:5 +VPMOVZXDQ ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:i 0x35 /r ; s:AVX2, t:AVX2, w:W|R, e:5 +VPERMD ; Vqq,Hqq,Wqq ; ; vex m:2 p:1 l:1 w:0 0x36 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPCMPGTQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x37 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSB ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x38 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINSD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x39 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3A /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMINUD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3B /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSB ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3C /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXSD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3D /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUW ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3E /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPMAXUD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x3F /r ; s:AVX, t:AVX, w:W|R|R, e:4 # 0x40 - 0x4F -VPMULLD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0x40 /r ; s:AVX, t:AVX, w:W|R|R, e:4 -VPHMINPOSUW ; Vdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:i 0x41 /r ; s:AVX, t:AVX, w:W|R, e:4 -VPSRLVD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x45 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPSRLVQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x45 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPSRAVD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x46 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPSLLVD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPSLLVQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPMULLD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0x40 /r ; s:AVX, t:AVX, w:W|R|R, e:4 +VPHMINPOSUW ; Vdq,Wdq ; ; vex m:2 p:1 l:0 w:i 0x41 /r ; s:AVX, t:AVX, w:W|R, e:4 +VPSRLVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x45 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSRLVQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x45 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSRAVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x46 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSLLVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPSLLVQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4 -LDTILECFG ; Moq ; n/a ; vex m:2 p:0 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1 -STTILECFG ; Moq ; n/a ; vex m:2 p:1 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2 -TILELOADD ; rTt,Mt ; n/a ; vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 -TILESTORED ; Mt,rTt ; n/a ; vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 -TILELOADDT1 ; rTt,Mt ; n/a ; vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 -TILERELEASE ; n/a ; n/a ; vex m:2 p:0 l:0 w:0 0x49 /0xC0 ; s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6 -TILEZERO ; rTt ; n/a ; vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0 ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 +LDTILECFG ; Moq ; ; vex m:2 p:0 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1 +STTILECFG ; Moq ; ; vex m:2 p:1 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2 +TILELOADD ; rTt,Mt ; ; vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILESTORED ; Mt,rTt ; ; vex m:2 p:2 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILELOADDT1 ; rTt,Mt ; ; vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3 +TILERELEASE ; ; ; vex m:2 p:0 l:0 w:0 0x49 /0xC0 ; s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6 +TILEZERO ; rTt ; ; vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0 ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5 # 0x50 - 0x5F -VPDPBUUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPBUSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x50 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 -VPDPBSUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPBSSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:3 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPBUUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPBUSDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x51 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 -VPDPBSUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPBSSDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:3 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 -VPDPWSSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x52 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 -VPDPWSSDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x53 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBUUD ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBUSD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x50 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBSUD ; Vx,Hx,Wx ; ; vex m:2 p:2 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBSSD ; Vx,Hx,Wx ; ; vex m:2 p:3 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBUUDS ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBUSDS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x51 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPBSUDS ; Vx,Hx,Wx ; ; vex m:2 p:2 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPBSSDS ; Vx,Hx,Wx ; ; vex m:2 p:3 l:x w:0 0x51 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4 +VPDPWSSD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x52 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 +VPDPWSSDS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x53 /r ; s:AVXVNNI, t:AVXVNNI, w:RW|R|R, e:4 -VPBROADCASTD ; Vx,Wd ; n/a ; vex m:2 p:1 l:x w:0 0x58 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 -VPBROADCASTQ ; Vx,Wq ; n/a ; vex m:2 p:1 l:x w:0 0x59 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 -VBROADCASTI128 ; Vqq,Mdq ; n/a ; vex m:2 p:1 l:1 w:0 0x5A /r:mem ; s:AVX2, t:BROADCAST, w:W|R, e:6 +VPBROADCASTD ; Vx,Wd ; ; vex m:2 p:1 l:x w:0 0x58 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 +VPBROADCASTQ ; Vx,Wq ; ; vex m:2 p:1 l:x w:0 0x59 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 +VBROADCASTI128 ; Vqq,Mdq ; ; vex m:2 p:1 l:1 w:0 0x5A /r:mem ; s:AVX2, t:BROADCAST, w:W|R, e:6 -TDPBF16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:2 l:0 w:0 0x5C /r:reg ; s:AMXBF16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TDPFP16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:3 l:0 w:0 0x5C /r:reg ; s:AMXFP16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TDPBUUD ; rTt,mTt,vTt ; n/a ; vex m:2 p:0 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TDPBUSD ; rTt,mTt,vTt ; n/a ; vex m:2 p:1 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TDPBSUD ; rTt,mTt,vTt ; n/a ; vex m:2 p:2 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TDPBSSD ; rTt,mTt,vTt ; n/a ; vex m:2 p:3 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBF16PS ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x5C /r:reg ; s:AMXBF16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x5C /r:reg ; s:AMXFP16, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBUUD ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBUSD ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBSUD ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TDPBSSD ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 # 0x60 - 0x6F -TCMMRLFP16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:0 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 -TCMMIMFP16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:1 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TCMMRLFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 +TCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4 # 0x70 - 0x7F -VCVTNEPS2BF16 ; Vx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0x72 /r ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 -VPBROADCASTB ; Vx,Wb ; n/a ; vex m:2 p:1 l:x w:0 0x78 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 -VPBROADCASTW ; Vx,Ww ; n/a ; vex m:2 p:1 l:x w:0 0x79 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 +VCVTNEPS2BF16 ; Vx,Wx ; ; vex m:2 p:2 l:x w:0 0x72 /r ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VPBROADCASTB ; Vx,Wb ; ; vex m:2 p:1 l:x w:0 0x78 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 +VPBROADCASTW ; Vx,Ww ; ; vex m:2 p:1 l:x w:0 0x79 /r ; s:AVX2, t:BROADCAST, w:W|R, e:6 # 0x80 - 0x8F -VPMASKMOVD ; Vx,Hx,Mx ; n/a ; vex m:2 p:1 l:x w:0 0x8C /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 -VPMASKMOVQ ; Vx,Hx,Mx ; n/a ; vex m:2 p:1 l:x w:1 0x8C /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 -VPMASKMOVD ; Mx,Hx,Vx ; n/a ; vex m:2 p:1 l:x w:0 0x8E /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 -VPMASKMOVQ ; Mx,Hx,Vx ; n/a ; vex m:2 p:1 l:x w:1 0x8E /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVD ; Vx,Hx,Mx ; ; vex m:2 p:1 l:x w:0 0x8C /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVQ ; Vx,Hx,Mx ; ; vex m:2 p:1 l:x w:1 0x8C /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVD ; Mx,Hx,Vx ; ; vex m:2 p:1 l:x w:0 0x8E /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 +VPMASKMOVQ ; Mx,Hx,Vx ; ; vex m:2 p:1 l:x w:1 0x8E /r:mem ; s:AVX2, t:AVX2, w:W|R|R, e:6 # 0x90 - 0x9F -VPGATHERDD ; Vx,Mvm32n,Hx ; n/a ; vex m:2 p:1 l:x w:0 0x90 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VPGATHERDQ ; Vx,Mvm32h,Hx ; n/a ; vex m:2 p:1 l:x w:1 0x90 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VPGATHERQD ; Vdq,Mvm64n,Hdq ; n/a ; vex m:2 p:1 l:x w:0 0x91 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VPGATHERQQ ; Vx,Mvm64n,Hx ; n/a ; vex m:2 p:1 l:x w:1 0x91 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VGATHERDPS ; Vx,Mvm32n,Hx ; n/a ; vex m:2 p:1 l:x w:0 0x92 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VGATHERDPD ; Vx,Mvm32h,Hx ; n/a ; vex m:2 p:1 l:x w:1 0x92 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VGATHERQPS ; Vdq,Mvm64n,Hdq ; n/a ; vex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VGATHERQPD ; Vx,Mvm64n,Hx ; n/a ; vex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERDD ; Vx,Mvm32n,Hx ; ; vex m:2 p:1 l:x w:0 0x90 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERDQ ; Vx,Mvm32h,Hx ; ; vex m:2 p:1 l:x w:1 0x90 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERQD ; Vdq,Mvm64n,Hdq ; ; vex m:2 p:1 l:x w:0 0x91 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VPGATHERQQ ; Vx,Mvm64n,Hx ; ; vex m:2 p:1 l:x w:1 0x91 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERDPS ; Vx,Mvm32n,Hx ; ; vex m:2 p:1 l:x w:0 0x92 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERDPD ; Vx,Mvm32h,Hx ; ; vex m:2 p:1 l:x w:1 0x92 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERQPS ; Vdq,Mvm64n,Hdq ; ; vex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 +VGATHERQPD ; Vx,Mvm64n,Hx ; ; vex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12 -VFMADDSUB132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD132SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD132SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB132SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB132SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD132SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD132SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB132PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB132PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB132SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB132SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 # 0xA0 - 0xAF -VFMADDSUB213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD213SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD213SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB213SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB213SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD213SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD213SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB213PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB213PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB213SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB213SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 # 0xB0 - 0xBF -VCVTNEOPH2PS ; Vx,Mx ; n/a ; vex m:2 p:0 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 -VCVTNEEPH2PS ; Vx,Mx ; n/a ; vex m:2 p:1 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 -VCVTNEEBF162PS ; Vx,Mx ; n/a ; vex m:2 p:2 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 -VCVTNEOBF162PS ; Vx,Mx ; n/a ; vex m:2 p:3 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 -VBCSTNESH2PS ; Vx,Mw ; n/a ; vex m:2 p:1 l:x w:0 0xB1 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 -VBCSTNEBF162PS ; Vx,Mw ; n/a ; vex m:2 p:2 l:x w:0 0xB1 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 +VCVTNEOPH2PS ; Vx,Mx ; ; vex m:2 p:0 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEEPH2PS ; Vx,Mx ; ; vex m:2 p:1 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEEBF162PS ; Vx,Mx ; ; vex m:2 p:2 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VCVTNEOBF162PS ; Vx,Mx ; ; vex m:2 p:3 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4 +VBCSTNESH2PS ; Vx,Mw ; ; vex m:2 p:1 l:x w:0 0xB1 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 +VBCSTNEBF162PS ; Vx,Mw ; ; vex m:2 p:2 l:x w:0 0xB1 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:5 -VPMADD52LUQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xB4 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 -VPMADD52HUQ ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xB5 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 +VPMADD52LUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB4 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 +VPMADD52HUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB5 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4 -VFMADDSUB231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADDSUB231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUBADD231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMADD231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMADD231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFMSUB231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFMSUB231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMADD231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMADD231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB231PS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB231PD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 -VFNMSUB231SS ; Vdq,Hdq,Wss ; n/a ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VFNMSUB231SD ; Vdq,Hdq,Wsd ; n/a ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADDSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADDSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUBADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2 +VFNMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 +VFNMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3 -VSHA512RNDS2 ; Vqq,Hqq,Udq ; n/a ; vex m:2 p:3 l:1 w:0 0xCB /r:reg ; s:SHA512, t:SHA512, w:RW|R|R, e:6 -VSHA512MSG1 ; Vqq,Udq ; n/a ; vex m:2 p:3 l:1 w:0 0xCC /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6 -VSHA512MSG2 ; Vqq,Uqq ; n/a ; vex m:2 p:3 l:1 w:0 0xCD /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6 -VGF2P8MULB ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, w:W|R|R +VSHA512RNDS2 ; Vqq,Hqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCB /r:reg ; s:SHA512, t:SHA512, w:RW|R|R, e:6 +VSHA512MSG1 ; Vqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCC /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6 +VSHA512MSG2 ; Vqq,Uqq ; ; vex m:2 p:3 l:1 w:0 0xCD /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6 +VGF2P8MULB ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, w:W|R|R -VPDPWUUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VPDPWUSD ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VPDPWSUD ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VPDPWUUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:0 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VPDPWUSDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VPDPWSUDS ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWUUD ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWUSD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWSUD ; Vx,Hx,Wx ; ; vex m:2 p:2 l:x w:0 0xD2 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWUUDS ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWUSDS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 +VPDPWSUDS ; Vx,Hx,Wx ; ; vex m:2 p:2 l:x w:0 0xD3 /r ; s:AVXVNNIINT16, t:AVXVNNIINT16, w:RW|R|R, e:4 -VSM3MSG1 ; Vdq,Hdq,Wdq ; n/a ; vex m:2 p:0 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4 -VSM3MSG2 ; Vdq,Hdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4 -VSM4KEY4 ; Vx,Hx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6 -VSM4RNDS4 ; Vx,Hx,Wx ; n/a ; vex m:2 p:3 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6 -VAESIMC ; Vdq,Wdq ; n/a ; vex m:2 p:1 l:0 w:i 0xDB /r ; s:AES, t:AES, w:W|R, e:4 -VAESENC ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDC /r ; s:AES, t:AES, w:W|R|R, e:4 -VAESENCLAST ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDD /r ; s:AES, t:AES, w:W|R|R, e:4 -VAESDEC ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDE /r ; s:AES, t:AES, w:W|R|R, e:4 -VAESDECLAST ; Vx,Hx,Wx ; n/a ; vex m:2 p:1 l:x w:i 0xDF /r ; s:AES, t:AES, w:W|R|R, e:4 +VSM3MSG1 ; Vdq,Hdq,Wdq ; ; vex m:2 p:0 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4 +VSM3MSG2 ; Vdq,Hdq,Wdq ; ; vex m:2 p:1 l:0 w:0 0xDA /r ; s:SM3, t:SM3, w:RW|R|R, e:4 +VSM4KEY4 ; Vx,Hx,Wx ; ; vex m:2 p:2 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6 +VSM4RNDS4 ; Vx,Hx,Wx ; ; vex m:2 p:3 l:x w:0 0xDA /r ; s:SM4, t:SM4, w:W|R|R, e:6 +VAESIMC ; Vdq,Wdq ; ; vex m:2 p:1 l:0 w:i 0xDB /r ; s:AES, t:AES, w:W|R, e:4 +VAESENC ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0xDC /r ; s:AES, t:AES, w:W|R|R, e:4 +VAESENCLAST ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0xDD /r ; s:AES, t:AES, w:W|R|R, e:4 +VAESDEC ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0xDE /r ; s:AES, t:AES, w:W|R|R, e:4 +VAESDECLAST ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:i 0xDF /r ; s:AES, t:AES, w:W|R|R, e:4 # 0xE0 - 0xEF CMPOXADD ; My,Gy,By ; Fv ; vex m:2 p:1 l:0 w:x 0xE0 /r:mem ; s:CMPCCXADD, t:CMPCCXADD, w:RW|RW|R|W, a:COND, f:ARITH, e:14 @@ -265,10 +265,10 @@ BLSR ; By,Ey ; Fv ; vex m:2 p:0 l:0 w:x BLSMSK ; By,Ey ; Fv ; vex m:2 p:0 l:0 w:x 0xF3 /2 ; s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=0|SF=m|OF=0, e:13 BLSI ; By,Ey ; Fv ; vex m:2 p:0 l:0 w:x 0xF3 /3 ; s:BMI1, t:BMI1, w:W|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 BZHI ; Gy,Ey,By ; Fv ; vex m:2 p:0 l:0 w:x 0xF5 /r ; s:BMI2, t:BMI2, w:W|R|R|W, f:CF=m|PF=u|AF=u|ZF=m|SF=m|OF=0, e:13 -PEXT ; Gy,By,Ey ; n/a ; vex m:2 p:2 l:0 w:x 0xF5 /r ; s:BMI2, t:BMI2, w:W|R|R|W, e:13 -PDEP ; Gy,By,Ey ; n/a ; vex m:2 p:3 l:0 w:x 0xF5 /r ; s:BMI2, t:BMI2, w:W|R|R|W, e:13 +PEXT ; Gy,By,Ey ; ; vex m:2 p:2 l:0 w:x 0xF5 /r ; s:BMI2, t:BMI2, w:W|R|R|W, e:13 +PDEP ; Gy,By,Ey ; ; vex m:2 p:3 l:0 w:x 0xF5 /r ; s:BMI2, t:BMI2, w:W|R|R|W, e:13 MULX ; Gy,By,Ey ; yDX ; vex m:2 p:3 l:0 w:x 0xF6 /r ; s:BMI2, t:BMI2, w:W|W|R|R, e:13 BEXTR ; Gy,Ey,By ; Fv ; vex m:2 p:0 l:0 w:x 0xF7 /r ; s:BMI1, t:BMI1, w:W|R|R|W, f:CF=0|PF=u|AF=u|ZF=m|SF=u|OF=0, e:13 -SHLX ; Gy,Ey,By ; n/a ; vex m:2 p:1 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 -SARX ; Gy,Ey,By ; n/a ; vex m:2 p:2 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 -SHRX ; Gy,Ey,By ; n/a ; vex m:2 p:3 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 +SHLX ; Gy,Ey,By ; ; vex m:2 p:1 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 +SARX ; Gy,Ey,By ; ; vex m:2 p:2 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 +SHRX ; Gy,Ey,By ; ; vex m:2 p:3 l:0 w:x 0xF7 /r ; s:BMI2, t:BMI2, w:W|R|R, e:13 diff --git a/isagenerator/instructions/table_vex3.dat b/isagenerator/instructions/table_vex_3.dat similarity index 53% rename from isagenerator/instructions/table_vex3.dat rename to isagenerator/instructions/table_vex_3.dat index 8cb6b5d..87af2a1 100644 --- a/isagenerator/instructions/table_vex3.dat +++ b/isagenerator/instructions/table_vex_3.dat @@ -4,128 +4,128 @@ # # 0x00 - 0x0F -VPERMQ ; Vqq,Wqq,Ib ; n/a ; vex m:3 p:1 l:1 w:1 0x00 /r ib ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPERMPD ; Vqq,Wqq,Ib ; n/a ; vex m:3 p:1 l:1 w:1 0x01 /r ib ; s:AVX2, t:AVX2, w:W|R|R, e:4 -VPBLENDD ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:0 0x02 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:4 -VPERMILPS ; Vx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 -VPERMILPD ; Vx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:0 0x05 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 -VPERM2F128 ; Vqq,Hqq,Wqq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x06 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VROUNDPS ; Vx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 -VROUNDPD ; Vx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 -VROUNDSS ; Vss,Hss,Wss,Ib ; n/a ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VROUNDSD ; Vsd,Hsd,Wsd,Ib ; n/a ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 -VBLENDPS ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x0C /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VBLENDPD ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x0D /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VPBLENDW ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x0E /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VPALIGNR ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VPERMQ ; Vqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:1 0x00 /r ib ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPERMPD ; Vqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:1 0x01 /r ib ; s:AVX2, t:AVX2, w:W|R|R, e:4 +VPBLENDD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x02 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:4 +VPERMILPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 +VPERMILPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x05 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4 +VPERM2F128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x06 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VROUNDPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 +VROUNDPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2 +VROUNDSS ; Vss,Hss,Wss,Ib ; ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VROUNDSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3 +VBLENDPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0C /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VBLENDPD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0D /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VPBLENDW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0E /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VPALIGNR ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 # 0x10 - 0x1F -VPEXTRB ; Mb,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x14 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 -VPEXTRB ; Ry,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x14 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 -VPEXTRW ; Mw,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x15 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 -VPEXTRW ; Ry,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x15 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 -VPEXTRD ; Md,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x16 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 -VPEXTRD ; Ry,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x16 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64|D64 -VPEXTRQ ; Mq,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x16 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 -VPEXTRQ ; Ry,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x16 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 -VEXTRACTPS ; Md,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x17 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 -VEXTRACTPS ; Ry,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5 -VINSERTF128 ; Vqq,Hqq,Wdq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x18 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:6 -VEXTRACTF128 ; Wdq,Vqq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x19 /r ib ; s:AVX, t:AVX, w:W|R|R, e:6 -VCVTPS2PH ; Wq,Vdq,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 -VCVTPS2PH ; Wdq,Vqq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 +VPEXTRB ; Mb,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x14 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRB ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x14 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 +VPEXTRW ; Mw,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x15 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 +VPEXTRW ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x15 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64 +VPEXTRD ; Md,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x16 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VPEXTRD ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x16 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64|D64 +VPEXTRQ ; Mq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:1 0x16 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VPEXTRQ ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:1 0x16 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64 +VEXTRACTPS ; Md,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x17 /r:mem ib ; s:AVX, t:AVX, w:W|R|R, e:5 +VEXTRACTPS ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5 +VINSERTF128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0 0x18 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:6 +VEXTRACTF128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x19 /r ib ; s:AVX, t:AVX, w:W|R|R, e:6 +VCVTPS2PH ; Wq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 +VCVTPS2PH ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11 # 0x20 - 0x2F -VPINSRB ; Vdq,Hdq,Mb,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VPINSRB ; Vdq,Hdq,Rd,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x20 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VINSERTPS ; Vdq,Hdq,Md,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x21 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VINSERTPS ; Vdq,Hdq,Udq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x21 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 -VPINSRD ; Vdq,Hdq,Ey,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x22 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64 -VPINSRQ ; Vdq,Hdq,Ey,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x22 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64 +VPINSRB ; Vdq,Hdq,Mb,Ib ; ; vex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRB ; Vdq,Hdq,Rd,Ib ; ; vex m:3 p:1 l:0 w:i 0x20 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VINSERTPS ; Vdq,Hdq,Md,Ib ; ; vex m:3 p:1 l:0 w:i 0x21 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VINSERTPS ; Vdq,Hdq,Udq,Ib ; ; vex m:3 p:1 l:0 w:i 0x21 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5 +VPINSRD ; Vdq,Hdq,Ey,Ib ; ; vex m:3 p:1 l:0 w:0 0x22 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64 +VPINSRQ ; Vdq,Hdq,Ey,Ib ; ; vex m:3 p:1 l:0 w:1 0x22 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64 # 0x30 - 0x3F -KSHIFTRW ; rKw,mKw,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x30 /r:reg ib ; s:AVX512F, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 -KSHIFTRB ; rKb,mKb,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x30 /r:reg ib ; s:AVX512DQ, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 -KSHIFTRQ ; rKq,mKq,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x31 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 -KSHIFTRD ; rKd,mKd,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x31 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 -KSHIFTLW ; rKw,mKw,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x32 /r:reg ib ; s:AVX512F, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 -KSHIFTLB ; rKb,mKb,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x32 /r:reg ib ; s:AVX512DQ, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 -KSHIFTLQ ; rKq,mKq,Ib ; n/a ; vex m:3 p:1 l:0 w:1 0x33 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 -KSHIFTLD ; rKd,mKd,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0x33 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 -VINSERTI128 ; Vqq,Hqq,Wdq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x38 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 -VEXTRACTI128 ; Wdq,Vqq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x39 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 +KSHIFTRW ; rKw,mKw,Ib ; ; vex m:3 p:1 l:0 w:1 0x30 /r:reg ib ; s:AVX512F, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRB ; rKb,mKb,Ib ; ; vex m:3 p:1 l:0 w:0 0x30 /r:reg ib ; s:AVX512DQ, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRQ ; rKq,mKq,Ib ; ; vex m:3 p:1 l:0 w:1 0x31 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTRD ; rKd,mKd,Ib ; ; vex m:3 p:1 l:0 w:0 0x31 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20 +KSHIFTLW ; rKw,mKw,Ib ; ; vex m:3 p:1 l:0 w:1 0x32 /r:reg ib ; s:AVX512F, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLB ; rKb,mKb,Ib ; ; vex m:3 p:1 l:0 w:0 0x32 /r:reg ib ; s:AVX512DQ, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLQ ; rKq,mKq,Ib ; ; vex m:3 p:1 l:0 w:1 0x33 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +KSHIFTLD ; rKd,mKd,Ib ; ; vex m:3 p:1 l:0 w:0 0x33 /r:reg ib ; s:AVX512BW, t:KMASK, c:KSHIFTL, w:W|R|R, e:K20 +VINSERTI128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0 0x38 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 +VEXTRACTI128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x39 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 # 0x40 - 0x4F -VDPPS ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 -VDPPD ; Vdq,Hdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 -VMPSADBW ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x42 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VPCLMULQDQ ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4 -VPERM2I128 ; Vqq,Hqq,Wqq,Ib ; n/a ; vex m:3 p:1 l:1 w:0 0x46 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 -VPERMIL2PS ; Vx,Hx,Wx,Lx,m2zIb ; n/a ; vex m:3 p:1 l:x w:0 0x48 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 -VPERMIL2PS ; Vx,Hx,Lx,Wx,m2zIb ; n/a ; vex m:3 p:1 l:x w:1 0x48 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 -VPERMIL2PD ; Vx,Hx,Wx,Lx,m2zIb ; n/a ; vex m:3 p:1 l:x w:0 0x49 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 -VPERMIL2PD ; Vx,Hx,Lx,Wx,m2zIb ; n/a ; vex m:3 p:1 l:x w:1 0x49 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 -VBLENDVPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x4A /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VBLENDVPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x4B /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 -VPBLENDVB ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x4C /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VDPPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 +VDPPD ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2 +VMPSADBW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x42 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VPCLMULQDQ ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4 +VPERM2I128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x46 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6 +VPERMIL2PS ; Vx,Hx,Wx,Lx,m2zIb ; ; vex m:3 p:1 l:x w:0 0x48 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMIL2PS ; Vx,Hx,Lx,Wx,m2zIb ; ; vex m:3 p:1 l:x w:1 0x48 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMIL2PD ; Vx,Hx,Wx,Lx,m2zIb ; ; vex m:3 p:1 l:x w:0 0x49 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VPERMIL2PD ; Vx,Hx,Lx,Wx,m2zIb ; ; vex m:3 p:1 l:x w:1 0x49 /r is4 ; s:XOP, t:XOP, w:W|R|R|R|R, e:4 +VBLENDVPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x4A /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VBLENDVPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x4B /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 +VPBLENDVB ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x4C /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4 # 0x50 - 0x5F -VFMADDSUBPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSUBPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBADDPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R # 0x60 - 0x6F VPCMPESTRM ; Vdq,Wdq,Ib ; yAX,yDX,XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x60 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 VPCMPESTRI ; Vdq,Wdq,Ib ; yAX,yDX,yCX,Fv ; vex m:3 p:1 l:0 w:i 0x61 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4 VPCMPISTRM ; Vdq,Wdq,Ib ; XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x62 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 VPCMPISTRI ; Vdq,Wdq,Ib ; yCX,Fv ; vex m:3 p:1 l:0 w:i 0x63 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4 -VFMADDPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSS ; Vdq,Hdq,Wss,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSS ; Vdq,Hdq,Ldq,Wss ; n/a ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; n/a ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; n/a ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; n/a ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R # 0x70 - 0x7F -VFNMADDPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; n/a ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; n/a ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPS ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPS ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPD ; Vx,Hx,Wx,Lx ; n/a ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBPD ; Vx,Hx,Lx,Wx ; n/a ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; n/a ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; n/a ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R -VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; n/a ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R +VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R # 0xC0 - 0xCF -VGF2P8AFFINEQB ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4 -VGF2P8AFFINEINVQB ; Vx,Hx,Wx,Ib ; n/a ; vex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4 +VGF2P8AFFINEQB ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4 +VGF2P8AFFINEINVQB ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4 # 0xD0 - 0xDF -VSM3RNDS2 ; Vdq,Hdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:0 0xDE /r ib ; s:SM3, t:SM3, w:RW|R|R|R, e:4 -VAESKEYGENASSIST ; Vdq,Wdq,Ib ; n/a ; vex m:3 p:1 l:0 w:i 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4 +VSM3RNDS2 ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:0 0xDE /r ib ; s:SM3, t:SM3, w:RW|R|R|R, e:4 +VAESKEYGENASSIST ; Vdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0xDF /r ib ; s:AES, t:AES, w:W|R|R, e:4 # 0xF0 - 0xFF -RORX ; Gy,Ey,Ib ; n/a ; vex m:3 p:3 l:0 w:x 0xF0 /r ib ; s:BMI2, t:BMI2, w:W|R|R, e:13 +RORX ; Gy,Ey,Ib ; ; vex m:3 p:3 l:0 w:x 0xF0 /r ib ; s:BMI2, t:BMI2, w:W|R|R, e:13 \ No newline at end of file diff --git a/isagenerator/instructions/table_vex_7.dat b/isagenerator/instructions/table_vex_7.dat new file mode 100644 index 0000000..982346a --- /dev/null +++ b/isagenerator/instructions/table_vex_7.dat @@ -0,0 +1,7 @@ +# +# Copyright (c) 2024 Bitdefender +# SPDX-License-Identifier: Apache-2.0 +# + +UWRMSR ; Id,Rq ; MSR ; vex m:7 p:2 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:R|R|W, m:O64 +URDMSR ; Rq,Id ; MSR ; vex m:7 p:3 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:W|R|R, m:O64 \ No newline at end of file diff --git a/isagenerator/instructions/table_xop.dat b/isagenerator/instructions/table_xop.dat index e971a19..46406e7 100644 --- a/isagenerator/instructions/table_xop.dat +++ b/isagenerator/instructions/table_xop.dat @@ -22,46 +22,46 @@ # 0x70 - 0x7F # 0x80 - 0x8F -VPMACSSWW ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x85 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSSWD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x86 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSSDQL ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x87 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSSDD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x8E /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSSDQH ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x8F /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSSWW ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x85 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSSWD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x86 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSSDQL ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x87 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSSDD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x8E /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSSDQH ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x8F /r is4 ; s:XOP, t:XOP, w:W|R|R|R # 0x90 - 0x9F -VPMACSWW ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x95 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSWD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x96 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSDQL ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x97 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSDD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x9E /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMACSDQH ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0x9F /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSWW ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x95 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSWD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x96 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSDQL ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x97 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSDD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x9E /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMACSDQH ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0x9F /r is4 ; s:XOP, t:XOP, w:W|R|R|R # 0xA0 - 0xAF -VPCMOV ; Vx,Hx,Wx,Lx ; n/a ; xop m:8 w:0 0xA2 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPCMOV ; Vx,Hx,Lx,Wx ; n/a ; xop m:8 w:1 0xA2 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPPERM ; Vx,Hx,Wx,Lx ; n/a ; xop m:8 w:0 0xA3 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPPERM ; Vx,Hx,Lx,Wx ; n/a ; xop m:8 w:1 0xA3 /r is4 ; s:XOP, t:XOP, w:W|R|R|R -VPMADCSSWD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0xA6 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPCMOV ; Vx,Hx,Wx,Lx ; ; xop m:8 w:0 0xA2 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPCMOV ; Vx,Hx,Lx,Wx ; ; xop m:8 w:1 0xA2 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPPERM ; Vx,Hx,Wx,Lx ; ; xop m:8 w:0 0xA3 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPPERM ; Vx,Hx,Lx,Wx ; ; xop m:8 w:1 0xA3 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMADCSSWD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0xA6 /r is4 ; s:XOP, t:XOP, w:W|R|R|R # 0xB0 - 0xBF -VPMADCSWD ; Vdq,Hdq,Wdq,Ldq ; n/a ; xop m:8 0xB6 /r is4 ; s:XOP, t:XOP, w:W|R|R|R +VPMADCSWD ; Vdq,Hdq,Wdq,Ldq ; ; xop m:8 0xB6 /r is4 ; s:XOP, t:XOP, w:W|R|R|R # 0xC0 - 0xCF -VPROTB ; Vdq,Wdq,Ib ; n/a ; xop m:8 0xC0 /r ib ; s:XOP, t:XOP, w:W|R|R -VPROTW ; Vdq,Wdq,Ib ; n/a ; xop m:8 0xC1 /r ib ; s:XOP, t:XOP, w:W|R|R -VPROTD ; Vdq,Wdq,Ib ; n/a ; xop m:8 0xC2 /r ib ; s:XOP, t:XOP, w:W|R|R -VPROTQ ; Vdq,Wdq,Ib ; n/a ; xop m:8 0xC3 /r ib ; s:XOP, t:XOP, w:W|R|R -VPCOMB ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xCC /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMW ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xCD /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMD ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xCE /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMQ ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xCF /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPROTB ; Vdq,Wdq,Ib ; ; xop m:8 0xC0 /r ib ; s:XOP, t:XOP, w:W|R|R +VPROTW ; Vdq,Wdq,Ib ; ; xop m:8 0xC1 /r ib ; s:XOP, t:XOP, w:W|R|R +VPROTD ; Vdq,Wdq,Ib ; ; xop m:8 0xC2 /r ib ; s:XOP, t:XOP, w:W|R|R +VPROTQ ; Vdq,Wdq,Ib ; ; xop m:8 0xC3 /r ib ; s:XOP, t:XOP, w:W|R|R +VPCOMB ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xCC /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMW ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xCD /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMD ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xCE /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMQ ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xCF /r ib ; s:XOP, t:XOP, w:W|R|R|R # 0xD0 - 0xDF # 0xE0 - 0xEF -VPCOMUB ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xEC /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMUW ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xED /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMUD ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xEE /r ib ; s:XOP, t:XOP, w:W|R|R|R -VPCOMUQ ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xEF /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMUB ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xEC /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMUW ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xED /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMUD ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xEE /r ib ; s:XOP, t:XOP, w:W|R|R|R +VPCOMUQ ; Vdq,Hdq,Wdq,Ib ; ; xop m:8 0xEF /r ib ; s:XOP, t:XOP, w:W|R|R|R # 0xF0 - 0xFF @@ -70,19 +70,19 @@ VPCOMUQ ; Vdq,Hdq,Wdq,Ib ; n/a ; xop m:8 0xEF /r ib # XOP.mmmmm = 9 # 0x00 - 0x0F -BLCFILL ; By,Ey ; n/a ; xop m:9 0x01 /1 ; s:TBM, t:BITBYTE, w:RW|R -BLSFILL ; By,Ey ; n/a ; xop m:9 0x01 /2 ; s:TBM, t:BITBYTE, w:RW|R -BLCS ; By,Ey ; n/a ; xop m:9 0x01 /3 ; s:TBM, t:BITBYTE, w:RW|R -TZMSK ; By,Ey ; n/a ; xop m:9 0x01 /4 ; s:TBM, t:BITBYTE, w:RW|R -BLCIC ; By,Ey ; n/a ; xop m:9 0x01 /5 ; s:TBM, t:BITBYTE, w:RW|R -BLSIC ; By,Ey ; n/a ; xop m:9 0x01 /6 ; s:TBM, t:BITBYTE, w:RW|R -T1MSKC ; By,Ey ; n/a ; xop m:9 0x01 /7 ; s:TBM, t:BITBYTE, w:RW|R -BLCMSK ; By,Ey ; n/a ; xop m:9 0x02 /1 ; s:TBM, t:BITBYTE, w:RW|R -BLCI ; By,Ey ; n/a ; xop m:9 0x02 /6 ; s:TBM, t:BITBYTE, w:RW|R +BLCFILL ; By,Ey ; ; xop m:9 0x01 /1 ; s:TBM, t:BITBYTE, w:RW|R +BLSFILL ; By,Ey ; ; xop m:9 0x01 /2 ; s:TBM, t:BITBYTE, w:RW|R +BLCS ; By,Ey ; ; xop m:9 0x01 /3 ; s:TBM, t:BITBYTE, w:RW|R +TZMSK ; By,Ey ; ; xop m:9 0x01 /4 ; s:TBM, t:BITBYTE, w:RW|R +BLCIC ; By,Ey ; ; xop m:9 0x01 /5 ; s:TBM, t:BITBYTE, w:RW|R +BLSIC ; By,Ey ; ; xop m:9 0x01 /6 ; s:TBM, t:BITBYTE, w:RW|R +T1MSKC ; By,Ey ; ; xop m:9 0x01 /7 ; s:TBM, t:BITBYTE, w:RW|R +BLCMSK ; By,Ey ; ; xop m:9 0x02 /1 ; s:TBM, t:BITBYTE, w:RW|R +BLCI ; By,Ey ; ; xop m:9 0x02 /6 ; s:TBM, t:BITBYTE, w:RW|R # 0x10 - 0x1F -LLWPCB ; Ry ; n/a ; xop m:9 0x12 /0:reg ; s:LWP, t:LWP, w:R -SLWPCB ; Ry ; n/a ; xop m:9 0x12 /1:reg ; s:LWP, t:LWP, w:R +LLWPCB ; Ry ; ; xop m:9 0x12 /0:reg ; s:LWP, t:LWP, w:R +SLWPCB ; Ry ; ; xop m:9 0x12 /1:reg ; s:LWP, t:LWP, w:R # 0x20 - 0x2F @@ -97,61 +97,61 @@ SLWPCB ; Ry ; n/a ; xop m:9 0x12 /1:reg # 0x70 - 0x7F # 0x80 - 0x8F -VFRCZPS ; Vx,Wx ; n/a ; xop m:9 0x80 /r ; s:XOP, t:XOP, w:W|R -VFRCZPD ; Vx,Wx ; n/a ; xop m:9 0x81 /r ; s:XOP, t:XOP, w:W|R -VFRCZSS ; Vdq,Wss ; n/a ; xop m:9 0x82 /r ; s:XOP, t:XOP, w:W|R -VFRCZSD ; Vdq,Wsd ; n/a ; xop m:9 0x83 /r ; s:XOP, t:XOP, w:W|R -VPSHAB ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x98 /r ; s:XOP, t:XOP, w:W|R|R -VPSHAB ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x98 /r ; s:XOP, t:XOP, w:W|R|R -VPSHAW ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x99 /r ; s:XOP, t:XOP, w:W|R|R -VPSHAW ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x99 /r ; s:XOP, t:XOP, w:W|R|R -VPSHAD ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x9A /r ; s:XOP, t:XOP, w:W|R|R -VPSHAD ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x9A /r ; s:XOP, t:XOP, w:W|R|R -VPSHAQ ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x9B /r ; s:XOP, t:XOP, w:W|R|R -VPSHAQ ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x9B /r ; s:XOP, t:XOP, w:W|R|R +VFRCZPS ; Vx,Wx ; ; xop m:9 0x80 /r ; s:XOP, t:XOP, w:W|R +VFRCZPD ; Vx,Wx ; ; xop m:9 0x81 /r ; s:XOP, t:XOP, w:W|R +VFRCZSS ; Vdq,Wss ; ; xop m:9 0x82 /r ; s:XOP, t:XOP, w:W|R +VFRCZSD ; Vdq,Wsd ; ; xop m:9 0x83 /r ; s:XOP, t:XOP, w:W|R +VPSHAB ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x98 /r ; s:XOP, t:XOP, w:W|R|R +VPSHAB ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x98 /r ; s:XOP, t:XOP, w:W|R|R +VPSHAW ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x99 /r ; s:XOP, t:XOP, w:W|R|R +VPSHAW ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x99 /r ; s:XOP, t:XOP, w:W|R|R +VPSHAD ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x9A /r ; s:XOP, t:XOP, w:W|R|R +VPSHAD ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x9A /r ; s:XOP, t:XOP, w:W|R|R +VPSHAQ ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x9B /r ; s:XOP, t:XOP, w:W|R|R +VPSHAQ ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x9B /r ; s:XOP, t:XOP, w:W|R|R # 0x90 - 0x9F -VPROTB ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x90 /r ; s:XOP, t:XOP, w:W|R|R -VPROTB ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x90 /r ; s:XOP, t:XOP, w:W|R|R -VPROTW ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x91 /r ; s:XOP, t:XOP, w:W|R|R -VPROTW ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x91 /r ; s:XOP, t:XOP, w:W|R|R -VPROTD ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x92 /r ; s:XOP, t:XOP, w:W|R|R -VPROTD ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x92 /r ; s:XOP, t:XOP, w:W|R|R -VPROTQ ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x93 /r ; s:XOP, t:XOP, w:W|R|R -VPROTQ ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x93 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLB ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x94 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLB ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x94 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLW ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x95 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLB ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x95 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLD ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x96 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLB ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x96 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLQ ; Vdq,Wdq,Hdq ; n/a ; xop m:9 w:0 0x97 /r ; s:XOP, t:XOP, w:W|R|R -VPSHLQ ; Vdq,Hdq,Wdq ; n/a ; xop m:9 w:1 0x97 /r ; s:XOP, t:XOP, w:W|R|R +VPROTB ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x90 /r ; s:XOP, t:XOP, w:W|R|R +VPROTB ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x90 /r ; s:XOP, t:XOP, w:W|R|R +VPROTW ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x91 /r ; s:XOP, t:XOP, w:W|R|R +VPROTW ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x91 /r ; s:XOP, t:XOP, w:W|R|R +VPROTD ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x92 /r ; s:XOP, t:XOP, w:W|R|R +VPROTD ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x92 /r ; s:XOP, t:XOP, w:W|R|R +VPROTQ ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x93 /r ; s:XOP, t:XOP, w:W|R|R +VPROTQ ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x93 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLB ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x94 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLB ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x94 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLW ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x95 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLB ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x95 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLD ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x96 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLB ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x96 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLQ ; Vdq,Wdq,Hdq ; ; xop m:9 w:0 0x97 /r ; s:XOP, t:XOP, w:W|R|R +VPSHLQ ; Vdq,Hdq,Wdq ; ; xop m:9 w:1 0x97 /r ; s:XOP, t:XOP, w:W|R|R # 0xA0 - 0xAF # 0xB0 - 0xBF # 0xC0 - 0xCF -VPHADDBW ; Vdq,Wdq ; n/a ; xop m:9 0xC1 /r ; s:XOP, t:XOP, w:W|R -VPHADDBD ; Vdq,Wdq ; n/a ; xop m:9 0xC2 /r ; s:XOP, t:XOP, w:W|R -VPHADDBQ ; Vdq,Wdq ; n/a ; xop m:9 0xC3 /r ; s:XOP, t:XOP, w:W|R -VPHADDWD ; Vdq,Wdq ; n/a ; xop m:9 0xC6 /r ; s:XOP, t:XOP, w:W|R -VPHADDWQ ; Vdq,Wdq ; n/a ; xop m:9 0xC7 /r ; s:XOP, t:XOP, w:W|R -VPHADDDQ ; Vdq,Wdq ; n/a ; xop m:9 0xCB /r ; s:XOP, t:XOP, w:W|R +VPHADDBW ; Vdq,Wdq ; ; xop m:9 0xC1 /r ; s:XOP, t:XOP, w:W|R +VPHADDBD ; Vdq,Wdq ; ; xop m:9 0xC2 /r ; s:XOP, t:XOP, w:W|R +VPHADDBQ ; Vdq,Wdq ; ; xop m:9 0xC3 /r ; s:XOP, t:XOP, w:W|R +VPHADDWD ; Vdq,Wdq ; ; xop m:9 0xC6 /r ; s:XOP, t:XOP, w:W|R +VPHADDWQ ; Vdq,Wdq ; ; xop m:9 0xC7 /r ; s:XOP, t:XOP, w:W|R +VPHADDDQ ; Vdq,Wdq ; ; xop m:9 0xCB /r ; s:XOP, t:XOP, w:W|R # 0xD0 - 0xDF -VPHADDUBW ; Vdq,Wdq ; n/a ; xop m:9 0xD1 /r ; s:XOP, t:XOP, w:W|R -VPHADDUBD ; Vdq,Wdq ; n/a ; xop m:9 0xD2 /r ; s:XOP, t:XOP, w:W|R -VPHADDUBQ ; Vdq,Wdq ; n/a ; xop m:9 0xD3 /r ; s:XOP, t:XOP, w:W|R -VPHADDUWD ; Vdq,Wdq ; n/a ; xop m:9 0xD6 /r ; s:XOP, t:XOP, w:W|R -VPHADDUWQ ; Vdq,Wdq ; n/a ; xop m:9 0xD7 /r ; s:XOP, t:XOP, w:W|R -VPHADDUDQ ; Vdq,Wdq ; n/a ; xop m:9 0xDB /r ; s:XOP, t:XOP, w:W|R +VPHADDUBW ; Vdq,Wdq ; ; xop m:9 0xD1 /r ; s:XOP, t:XOP, w:W|R +VPHADDUBD ; Vdq,Wdq ; ; xop m:9 0xD2 /r ; s:XOP, t:XOP, w:W|R +VPHADDUBQ ; Vdq,Wdq ; ; xop m:9 0xD3 /r ; s:XOP, t:XOP, w:W|R +VPHADDUWD ; Vdq,Wdq ; ; xop m:9 0xD6 /r ; s:XOP, t:XOP, w:W|R +VPHADDUWQ ; Vdq,Wdq ; ; xop m:9 0xD7 /r ; s:XOP, t:XOP, w:W|R +VPHADDUDQ ; Vdq,Wdq ; ; xop m:9 0xDB /r ; s:XOP, t:XOP, w:W|R # 0xE0 - 0xEF -VPHSUBBW ; Vdq,Wdq ; n/a ; xop m:9 0xE1 /r ; s:XOP, t:XOP, w:W|R -VPHSUBWD ; Vdq,Wdq ; n/a ; xop m:9 0xE2 /r ; s:XOP, t:XOP, w:W|R -VPHSUBDQ ; Vdq,Wdq ; n/a ; xop m:9 0xE3 /r ; s:XOP, t:XOP, w:W|R +VPHSUBBW ; Vdq,Wdq ; ; xop m:9 0xE1 /r ; s:XOP, t:XOP, w:W|R +VPHSUBWD ; Vdq,Wdq ; ; xop m:9 0xE2 /r ; s:XOP, t:XOP, w:W|R +VPHSUBDQ ; Vdq,Wdq ; ; xop m:9 0xE3 /r ; s:XOP, t:XOP, w:W|R # 0xF0 - 0xFF @@ -161,9 +161,9 @@ VPHSUBDQ ; Vdq,Wdq ; n/a ; xop m:9 0xE3 /r # 0x00 - 0x0F # 0x10 - 0x1F -BEXTR ; Gy,Ey,Id ; n/a ; xop m:A 0x10 /r id ; s:TBM, t:BITBYTE, w:RW|R|R -LWPINS ; By,Ed,Id ; n/a ; xop m:A 0x12 /0 id ; s:LWP, t:LWP, w:RW|R|R -LWPVAL ; By,Ed,Id ; n/a ; xop m:A 0x12 /1 id ; s:LWP, t:LWP, w:RW|R|R +BEXTR ; Gy,Ey,Id ; ; xop m:A 0x10 /r id ; s:TBM, t:BITBYTE, w:RW|R|R +LWPINS ; By,Ed,Id ; ; xop m:A 0x12 /0 id ; s:LWP, t:LWP, w:RW|R|R +LWPVAL ; By,Ed,Id ; ; xop m:A 0x12 /1 id ; s:LWP, t:LWP, w:RW|R|R # 0x20 - 0x2F diff --git a/isagenerator/isagenerator.vcxproj b/isagenerator/isagenerator.vcxproj index 766a83b..514d081 100644 --- a/isagenerator/isagenerator.vcxproj +++ b/isagenerator/isagenerator.vcxproj @@ -30,6 +30,7 @@ {0E9D2957-34FA-40EE-B4B2-0D008D2FE317} isagenerator 10.0.18362.0 + isagenerator_x86 @@ -199,30 +200,30 @@ + - - - - + + + + + - - - - - - - - - - + + + + + + + + + + + - - - diff --git a/isagenerator/isagenerator.vcxproj.filters b/isagenerator/isagenerator.vcxproj.filters index cf88055..b6bbb8e 100644 --- a/isagenerator/isagenerator.vcxproj.filters +++ b/isagenerator/isagenerator.vcxproj.filters @@ -16,14 +16,23 @@ {8eaf791a-1023-446d-b655-528b2e53c283} + + {bd1ad80f-3298-4629-b5f8-82534060f84d} + + + {889c4ba1-29f0-474b-a5f6-4e927dbb45c6} + + + {6e4531e2-861d-4a6e-955b-384333e3e3e6} + + + {50d53c2f-9192-4b67-955a-56dc137a364b} + + + {b2f84880-170b-4fb3-b8c0-408dc88f9598} + - - Source Files - - - Source Files - data @@ -33,58 +42,68 @@ data - - data + + Source Files - - data + + Source Files - - data + + data\table legacy - - data + + data\table legacy + + + data\table legacy + + + data\table legacy + + + data\table legacy - data - - - data - - - data - - - data - - - data - - - data - - - data - - - data - - - data + data\table 3dnow - data + data\table xop - - data + + data\table vex - - data + + data\table vex + + + data\table vex + + + data\table evex + + + data\table evex + + + data\table evex + + + data\table evex + + + data\table evex + + + data\table evex + + + Source Files + + + data\table vex + + + data\table evex - - - - data - \ No newline at end of file diff --git a/prepare_fuzzing_image.sh b/prepare_fuzzing_image.sh new file mode 100644 index 0000000..f03e76f --- /dev/null +++ b/prepare_fuzzing_image.sh @@ -0,0 +1,15 @@ +#!/bin/bash +set -e + +img="bddfuzz" +out="bddfuzz.tar" + +rm -rf "${out}" + +podman build -t ${img} -f Dockerfile.fuzzing . +podman save -o ${out} ${img} + +echo "Done! Copy ${out} to the fuzzing machine and load it with 'podman load -i ${out}'" +echo "You probably want to run it like this: " +echo "'podman run --cap-add=SYS_PTRACE -it -v /host/share/:/bddfuzz/share ${img} /bin/bash'" +echo "All fuzzers are present in the image, you must start one of them"